数字鉴相器——用VHDL语言实现

相关主题
  1. 1、下载文档前请自行甄别文档内容的完整性,平台不提供额外的编辑、内容补充、找答案等附加服务。
  2. 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
  3. 3、如文档侵犯您的权益,请联系客服反馈,我们会尽快为您处理(人工客服工作时间:9:00-18:30)。

数字鉴相器——用VHDL语言实现.txt27信念的力量在于即使身处逆境,亦能帮助你鼓起前进的船帆;信念的魅力在于即使遇到险运,亦能召唤你鼓起生活的勇气;信念的伟大在于即使遭遇不幸,亦能促使你保持崇高的心灵。LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY multiplier IS
PORT(clk: IN STD_LOGIC;
reset: IN STD_LOGIC;
input1: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
input2: IN SIGNED(7 DOWNTO 0);
output: OUT SIGNED(7 DOWNTO 0)
);
END multiplier;
ARCHITECTURE behavior OF multiplier IS
SIGNAL out_temp: SIGNED(15 DOWNTO 0);
SIGNAL input1_buf:SIGNED(15 DOWNTO 0);
SIGNAL part0,part1,part2,part3,part4,part5,part6,part7:SIGNED(15 DOWNTO 0);
BEGIN
PROCESS(clk,reset)
BEGIN
IF(reset='1') THEN
out_temp<=(others=>'0');
output<=(others=>'0');
part0<=(others=>'0');
part1<=(others=>'0');
part2<=(others=>'0');
part3<=(others=>'0');
part4<=(others=>'0');
part5<=(others=>'0');
part6<=(others=>'0');
part7<=(others=>'0');
ELSIF rising_edge(CLK) THEN
input1_buf<=input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&input1(7)&input1(7)

&input1(7)&SIGNED(input1);
IF(input2(0)='1') THEN
part0<=-(input1_buf);
ELSE
part0<=(others=>'0');
END IF;
IF(input2(1)='1') THEN
IF(input2(0)='0') THEN
part1<=-(input1_buf);
ELSE
part1<=(others=>'0');
END IF;
ELSE
IF(input2(0)='1') THEN
part1<=input1_buf;
ELSE
part1<=(others=>'0');
END IF;
END IF;
IF(input2(2)='1') THEN
IF(input2(1)='0') THEN
part2<=-(input1_buf);
ELSE
part2<="0000000000000000";
END IF;
ELSE
IF (input2(1)='1') THEN
part2<=input1_buf;
ELSE
part2<="0000000000000000";
END IF;
END IF;
IF(input2(3)='1') THEN
IF(input2(2)='0') THEN
part3<=-(input1_buf);
ELSE
part3<="0000000000000000";
END IF;
ELSE
IF (input2(2)='1') THEN
part3<=input1_buf;
ELSE
part3<="0000000000000000";
END IF;
END IF;
IF(input2(4)='1') THEN
IF(input2(3)='0') THEN
part4<=-(input1_buf);
ELSE
part4<="0000000000000000";
END IF;
ELSE
IF (input2(3)='1') THEN
part4<=input1_buf;
ELSE
part4<="0000000000000000";
END IF;
END IF;
IF(input2(5)='1') THEN
IF(input2(4)='0') THEN
part5<=-(input1_buf);
ELSE
part5<="0000000000000000";
END IF;
ELSE
IF (input2(4)='1') THEN
part5<=input1_buf;
ELSE
part5<="0000000000000000";
END IF;
END IF;
IF(input2(6)='1') THEN
IF(input2(5)='0') THEN
part6<=-(input1_buf);
ELSE
part6<="0000000000000000";
END IF;
ELSE
IF (input2(5)='1') THEN
part6<=input1_buf;
ELSE
part6<="0000000000000000";
END IF;
END IF;
IF(input2(7)='1') THEN
IF(input2(6)='0') THEN
part7<=-(input

1_buf);
ELSE
part7<="0000000000000000";
END IF;
ELSE
IF (input2(6)='1') THEN
part7<=input1_buf;
ELSE
part7<="0000000000000000";
END IF;
END IF;
out_temp<=part0+(part1(14 DOWNTO 0)&'0')+(part2(13 DOWNTO 0)&"00")+
(part3(12 DOWNTO 0)&"000")+(part4(11 DOWNTO 0)&"0000")+
(part5(10 DOWNTO 0)&"00000")+(part6(9 DOWNTO 0)&"000000")+
(part7(8 DOWNTO 0)&"0000000");
output<=out_temp(15 DOWNTO 8);
END IF;
END PROCESS;
END behavior;

相关文档
最新文档