74LVTH162245
VISION AT697 EVB User's Manual
8 VISION AT697 EVB User's Manual
4.4 PLL, SKEW配置
CPU内部时钟,可以使用bypass或PLL SKEW可以调整, 线路如下:
缺省设定是全off
© 2009 上海创景计算机系统有限公司
4.5 其他
还有一些CPU的管脚培植如下:
CPU 配置
9
nBRDY一直是下拉的 如果使用PLL,并且PLL lock后, D5就会亮
EDAC配置
4.4
PLL, SKEW配置
4.5
其他
第5章 Power
第6章 Clock
第7章 Buffer
第8章 SDRAM
第9章 RS232
第10章 LED
第11章 Key
第12章 CPCI
第13章 DSU
第14章 扩展接口
第15章 CPLD
© 2009 上海创景计算机系统有限公司 Nhomakorabea目录
I
1 2 4 5 5 6 7 8 9 11 13 15 16 17 18 20 21 22 24 26
• 四个IO用于按键，可接到Interrupt
© 2009 上海创景计算机系统有限公司
功能介绍
3
• CPCI接口，CPCI 工作于33Mhz, 32Bits。支持Host, Satellite • 可外接CPU Clock, PCI Clock • 丰富的外接扩展接口，可通过CPCI P4, P5，也可通过SAMTEK QSH-QTH接
这SEL8_40Bits在CPLD中进行了译码:
//config 8 / 40 bits operation
always @(posedge clk)
74LVCH162245A(总线隔离,U20 U21 U22)
查询74LVC162245A供应商SSOP48:plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1TSSOP48:plastic thin shrink small outline package; 48 leads; body width 6.1mm SOT362-1NOTESDefinitionsShort-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook.Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.DisclaimersLife support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.Philips Semiconductors811 East Arques AvenueP.O. Box 3409Sunnyvale, California 94088–3409Telephone 800-234-7381© Copyright Philips Electronics North America Corporation 1998All rights reserved. Printed in U.S.A.print code Date of release: 05-96。
74LVT162245MTDX中文资料
© 2005 Fairchild Semiconductor Corporation DS012446January 1999Revised June 200574LVT162245 • 74LVTH162245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25: Series Resistors in A Port Outputs74LVT162245 • 74LVTH162245Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25: Series Resistors in A Port OutputsGeneral DescriptionThe LVT162245 and LVTH162245 contains sixteen non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. Each byte has separate control inputs which can be shorted together for full 16-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state.The LVT162245 and LVTH162245 are designed with equivalent 25: series resistance in both the HIGH and LOW states on the A Port outputs. This design reduces line noise in applications such as memory address drivers,clock drivers, and bus transceivers/transmitters.The LVTH162245 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.These non-inverting transceivers are designed for low volt-age (3.3V) V CC applications, but with the capability to pro-vide a TTL interface to a 5V environment. The LVT162245and LVTH162245 are fabricated with an advanced BiCMOS technology to achieve high speed operation simi-lar to 5V ABT while maintaining a low power dissipation.Featuress Input and output interface capability to systems at 5V V CC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH162245),also available without bushold feature (74LVT162245).s Live insertion/extraction permitteds Power Up/Down high impedance provides glitch-free bus loading s A Port outputs include equivalent series resistance of 25: making external termination resistors unnecessary and reducing overshoot and undershoot s A Port outputs source/sink r 12 mA.B Port outputs source/sink 32 mA/ 64 mA s Functionally compatible with the 74 series 162245s Latch-up performance exceeds 500 mA s ESD performance:Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000Vs Also packaged in plastic Fine Pitch Ball Grid Array (FBGA)Ordering Code:Note 1: Ordering code “G” indicates Trays.Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.Order Number Package Number Package Description74LVT162245G (Note 1)(Note 2)BGA54A (Preliminary)54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 74LVT162245MEA (Note 2)MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LVT162245MTD (Note 2)MTD4848-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 74LVTH162245G (Note 1)(Note 2)BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 74LVTH162245MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TUBE]74LVTH162245MEX MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TAPE and REEL]74LVTH162245MTD MTD4848-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TUBE]74LVTH162245MTXMTD4848-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL] 274L V T 162245 • 74L V T H 162245Logic SymbolConnection DiagramsPin Assignments for SSOP and TSSOPPin Assignment for FBGA(Top Thru View)Pin DescriptionsFBGA Pin AssignmentsTruth TablesH HIGH Voltage LevelL LOW Voltage Level X ImmaterialZ High ImpedancePin Names DescriptionOE n Output Enable Input (Active LOW)T/R n Transmit/Receive Input A 0–A 15Side A Inputs/3-STATE Outputs B 0–B 15Side B Inputs/3-STATE Outputs NCNo Connect123456A B 0NC T/R 1OE 1NC A 0B B 2B 1NC NC A 1A 2C B 4B 3V CC V CC A 3A 4D B 6B 5GND GND A 5A 6E B 8B 7GND GND A 7A 8F B 10B 9GND GND A 9A 10G B 12B 11V CC V CC A 11A 12H B 14B 13NC NC A 13A 14JB 15NCT/R 2OE 2NCA 15Inputs OutputsOE 1T/R 1L L Bus B 0–B 7 Data to Bus A 0–A 7L H Bus A 0–A 7 Data to Bus B 0–B 7HXHIGH-Z State on A 0–A 7, B 0–B 7Inputs OutputsOE 2T/R 2L L Bus B 8–B 15 Data to Bus A 8–A 15L H Bus A 8–A 15 Data to Bus B 8–B 15HXHIGH-Z State on A 8–A 15, B 8–B 1574LVT162245 • 74LVTH162245Functional DescriptionThe LVT162245 and LVTH162245 contain sixteen non-inverting bidirectional buffers with 3-STATE outputs. The device is byte controlled with each byte functioning identi-cally, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation.Logic DiagramsPlease note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 474L V T 162245 • 74L V T H 162245Absolute Maximum Ratings (Note 3)Recommended Operating ConditionsNote 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 4: I O Absolute Maximum Rating must be observed.DC Electrical CharacteristicsSymbol ParameterValueConditionsUnits V CC Supply Voltage 0.5 to 4.6V V I DC Input Voltage 0.5 to 7.0VV O Output Voltage 0.5 to 7.0Output in 3-STATEV 0.5 to 7.0Output in HIGH or LOW State (Note 4)I IK DC Input Diode Current 50V I GND mA I OK DC Output Diode Current 50V O GND mA I O DC Output Current64V O ! V CC Output at HIGH State mA 128V O ! V CCOutput at LOW StateI CC DC Supply Current per Supply Pin r 64mA I GND DC Ground Current per Ground Pin r 128mAT STGStorage Temperature65 to 150q CSymbol ParameterMin Max Units V CC Supply Voltage 2.7 3.6V V I Input Voltage5.5V I OH HIGH-Level Output Current B Port 32mA A Port 12I OL LOW-Level Output Current B Port 64mAA Port12T AFree Air Operating Temperature40 85q C 't/'VInput Edge Rate, V IN 0.8V –2.0V, V CC 3.0V10ns/VSymbol ParameterV CC T A 40q C to 85q C Units Conditions(V)MinMax V IK Input Clamp Diode Voltage 2.7 1.2V I I 18 mA V IH Input HIGH Voltage 2.7–3.6 2.0V V O d 0.1V or V IL Input LOW Voltage 2.7–3.60.8V V O t V CC 0.1V V OHOutput HIGH VoltageA Port 3.0 2.0V I OH 12 mA 2.7–3.6V CC 0.2V I OH 100 P A B Port2.7 2.4V I OH 8 mA3.0 2.0I OH 32 mA V OLOutput LOW VoltageA Port3.00.8V I OL 12 mA 2.70.2VI OL 100 P A B Port2.70.5VI OL 24 mA 3.00.4I OL 16 mA 3.00.5I OL 32 mA 3.00.55I OL 64 mA I I(HOLD)Bushold Input Minimum Drive3.075P A V I 0.8V (Note 5) 75V I 2.0V I I(OD)Bushold Input Over-Drive 3.0500P A (Note 6)(Note 5)Current to Change State 500(Note 7)I IInput Current3.610P AV I 5.5V Control Pins 3.6r 1V I 0V or V CC Data Pins3.6 5V I 0V 1V I V CCI OFFPower Off Leakage Current 0r 100P A 0V d V I or V O d 5.5V74LVT162245 • 74LVTH162245DC Electrical Characteristics (Continued)Note 5: Applies to Bushold versions only (74LVTH162245).Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than V CC or GND.Dynamic Switching Characteristics (Note 9)Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested.Note 10: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. Output under test held LOW.Symbol ParameterV CC T A 40q C to 85q C Units Conditions(V)MinMax I PU/PD Power Up/Down 0–1.5V r 100P A V O 0.5V to 3.0V 3-STATE CurrentV I GND to V CC I OZL 3-STATE Output Leakage Current 3.6 5P A V O 0.5V I OZL 3-STATE Output Leakage Current 3.6 5P A V O 0.0V (Note 5)I OZH 3-STATE Output Leakage Current 3.65P A V O 3.0V I OZH 3-STATE Output Leakage Current3.65P A V O 3.6V (Note 5)I OZH 3-STATE Output Leakage Current 3.610P A V CC V O d 5.5V I CCH Power Supply Current 3.60.19mA Outputs HIGH I CCL Power Supply Current 3.65mA Outputs LOW I CCZ Power Supply Current 3.60.19mA Outputs Disabled I CCZ Power Supply Current3.60.19mA V CC d V O d 5.5V,Outputs Disabled 'I CCIncrease in Power Supply Current 3.60.2mAOne Input at V CC 0.6V (Note 8)Other Inputs at V CC or GNDSymbol ParameterV CC T A 25q C Units Conditions (V)MinTyp MaxC L 50 pF, R L 500:V OLP Quiet Output Maximum Dynamic V OL 3.30.8V (Note 10)V OLVQuiet Output Minimum Dynamic V OL3.30.8V(Note 10) 674L V T 162245 • 74L V T H 162245AC Electrical CharacteristicsNote 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t OSHL ) or LOW-to-HIGH (t OSLH ).Capacitance (Note 12)Note 12: Capacitance is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012.SymbolParameterT A 40q C to 85q CUnitsC L 50 pF, R L 500:V CC 3.3V r 0.3V V CC 2.7V MinMax MinMax t PLH Propagation Delay Data to A Port Output1.0 4.0 1.0 4.6ns t PHL 1.0 3.7 1.0 4.1t PLH Propagation Delay Data to B Port Output 1.0 3.5 1.0 3.9ns t PHL 1.0 3.5 1.0 3.9t PZH Output Enable Time for A Port Output 1.0 5.3 1.0 6.3ns t PZL 1.0 5.6 1.07.2t PZH Output Enable Time for B Port Output 1.0 4.6 1.0 5.4ns t PZL 1.0 5.3 1.0 6.9t PHZ Output Disable Time for A Port Output 1.5 5.6 1.5 6.3ns t PLZ 1.5 5.5 1.5 5.5t PHZ Output Disable Time for B Port Output 1.5 5.4 1.5 6.1ns t PLZ 1.55.1 1.55.4t OSHL A Port Output to Output Skew 1.0 1.0ns t OSLH (Note 11)t OSHL B Port Output to Output Skew 1.01.0ns t OSLH(Note 11)Symbol ParameterConditionsTypical Units C IN Input Capacitance V CC 0V, V I 0V or V CC 4pF C I/OInput/Output CapacitanceV CC 3.0V, V O 0V or V CC8pF74LVT162245 • 74LVTH162245Physical Dimensionsinches (millimeters) unless otherwise noted54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm WidePackage Number BGA54A 874L V T 162245 • 74L V T H 162245Physical Dimensions inches (millimeters) unless otherwise noted (Continued)48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" WidePackage Number MS48A974LVT162245 • 74LVTH162245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25: Series Resistors in A Port OutputsPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm WidePackage Number MTD48Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user.2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。
SNJ54LVTH162245WD中文资料
PACKAGING INFORMATIONOrderable Device Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball FinishMSL Peak Temp (3)5962-9678001QXA ACTIVE CFP WD 481TBD Call TI Level-NC-NC-NC 5962-9678001VXA ACTIVE CFP WD 481TBDCall TI Level-NC-NC-NC 74LVTH162245DGGRG4ACTIVE TSSOP DGG 482000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM 74LVTH162245DLRG4ACTIVE SSOP DL 481000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM 74LVTH162245GRDR ACTIVE LFBGA GRD 541000TBDSNPB Level-1-240C-UNLIM 74LVTH162245GRE4ACTIVE TSSOP DGG 482000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM 74LVTH162245ZQLR ACTIVE VFBGA ZQL 561000Green (RoHS &no Sb/Br)SNAGCU Level-1-260C-UNLIM 74LVTH162245ZRDR ACTIVE LFBGA ZRD 541000Green (RoHS &no Sb/Br)SNAGCU Level-1-260C-UNLIM SN74LVTH162245DGGR ACTIVE TSSOP DGG 482000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LVTH162245DL ACTIVE SSOP DL 4825Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LVTH162245DLG4ACTIVE SSOP DL 4825Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LVTH162245DLR ACTIVE SSOP DL 481000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LVTH162245KR ACTIVE VFBGA GQL 561000TBD SNPB Level-1-240C-UNLIM SNJ54LVTH162245WDACTIVECFPWD481TBDCall TILevel-NC-NC-NC(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in anew design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS)or Green (RoHS &no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.PACKAGE OPTION ADDENDUM4-Oct-2005Addendum-Page 1元器件交易网元器件交易网元器件交易网IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvements, and other changes to its products and services at any time and to discontinueany product or service without notice. Customers should obtain the latest relevant information before placingorders and should verify that such information is current and complete. All products are sold subject to TI’s termsand conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. T esting and other quality control techniques are used to the extent TIdeems necessary to support this warranty. Except where mandated by government requirements, testing of allparameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers are responsible fortheir products and applications using TI components. T o minimize the risks associated with customer productsand applications, customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or processin which TI products or services are used. Information published by TI regarding third-party products or servicesdoes not constitute a license from TI to use such products or services or a warranty or endorsement thereof.Use of such information may require a license from a third party under the patents or other intellectual propertyof the third party, or a license from TI under the patents or other intellectual property of TI.Reproduction of information in TI data books or data sheets is permissible only if reproduction is withoutalteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproductionof this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable forsuch altered documentation.Resale of TI products or services with statements different from or beyond the parameters stated by TI for thatproduct or service voids all express and any implied warranties for the associated TI product or service andis an unfair and deceptive business practice. TI is not responsible or liable for any such statements.Following are URLs where you can obtain information on other Texas Instruments products and applicationsolutions:Products ApplicationsAmplifiers Audio /audioData Converters Automotive /automotiveDSP Broadband /broadbandInterface Digital Control /digitalcontrolLogic Military /militaryPower Mgmt Optical Networking /opticalnetworkMicrocontrollers Security /securityTelephony /telephonyVideo & Imaging /videoWireless /wirelessMailing Address:Texas InstrumentsPost Office Box 655303 Dallas, Texas 75265Copyright 2005, Texas Instruments Incorporated。
逻辑器件74LVCH16245A与74LVC16245A的差异
逻辑器件74LVCH16245A与74LVC16245A的差异 前段时间公司⼀款⽣产了很久的产品出现⼀个很奇怪的问题，先放上等效图说明：1. INPUT左边是⼀个连接器，相当于直接到地的⼀个开关，所以这⾥⽤⼀个SW1替代2. 设备在上电后，SW1处于断开状态，所以INPUT为⾼，这时TO_MCU检测为⾼；当SW1按下时，NPUT为低，此时TO_MCU为低 遇到的问题是，SW1按下时，TO_MCU为低，再将SW1断开，INPUT为⾼，但是这时TO_MCU还是为低，这是个很奇怪的现象，后⾯发现是芯⽚信号⽤错了，本来是⽤74LVC16245A的，结果⽤成了74LVC H16245A，就是多了这个H结果就是不⼀样，后⾯将INPUT上拉电阻R1更换为4.7K后正常，那么这两个型号有什么差异呢，初⼀看都是⼀样的，只有些细微的差异。
如下截取⾃74LVCH16245A Datasheet从以上信息可知1. 输⼊脚在没有驱动的情况下，其输⼊端也会保持⼀个有效的逻辑状态，即要么是0，要么是1，总之是⼀个确定的逻辑状态。
2. 逻辑状态的转变，输⼊电流必须⼤于500uA，否则输⼊端会⼀直保持上⼀个逻辑状态。
再来分析为什么把R1从10K变为4.7K就可以了1. R1 = 10K时，I = 3.3 / 10K==>330uA2. R1 = 4.7K时，I =3.3 /4.7K==>702uA从上⾯两点来看，R1 = 10K时，⼩于500uA，所以输⼊的状态⼀直保持上⼀个逻辑电平；R1 = 4.7K时，才会进⾏状态转换，这时就可以跟74LVC16245A⼀样了，这就是多了⼀个H多出的内容，有点类似锁存的味道；在输⼊⽐较多的情况，需要留意其电流的消耗，因为每个输⼊脚都要提供⼤于500uA的电流，如果数量⼀多，就不得不好考虑其电流的消耗了，如如果16个PIN全部⽤上，都在同⼀时刻切换的话，这时候16*0.5mA=8mA。
74LVT2245D-T中文资料
19 OE 18 B0 17 B1 16 B2 15 B3 14 B4 13 B5 12 B6 11 B7 mna817
19
G3
3 EN1 (BA)
1
3 EN2 (AB)
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mna818
Fig 2. IEC logic symbol
SOT339-1
plastic thin shrink small outline package; 20 leads; SOT360-1 body width 4.4 mm
plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
74LVTH2245PW −40 °C to +85 °C TSSOP20
Description
Version
plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
plastic shrink small outline package; 20 leads; body width 5.3 mm
The 74LVT2245; 74LVTH2245 is designed with 30 Ω series resistance in both the HIGH-state and LOW-state of the output. This design reduces line noise in applications such as memory address drivers, clock drivers and bus transceivers and transmitters.
LVTH162245总线驱动芯片
PACKAGING INFORMATIONOrderable Device Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)CLVTH162245IDGGREP ACTIVE TSSOP DGG 482000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM CLVTH162245MDLREPACTIVE SSOP DL 481000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM V62/04709-01XE ACTIVE TSSOP DGG 482000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM V62/04709-02YEACTIVESSOPDL481000Green (RoHS &no Sb/Br)CU NIPDAULevel-1-260C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1)lead-based flip-chip solder bumps used between the die and package,or 2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free (RoHS compatible)as defined above.Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has takenand continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.OTHER QUALIFIED VERSIONS OF SN74LVTH162245-EP :•Catalog:SN74LVTH162245•Military:SN54LVTH162245NOTE:Qualified Version Definitions:•Catalog-TI's standard catalog product •Military -QML certified for Military and Defense ApplicationsPACKAGE OPTION ADDENDUM18-Sep-2008TAPE AND REEL INFORMATION*All dimensions are nominalDevicePackage Type Package Drawing Pins SPQReel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant CLVTH162245IDGGREP TSSOP DGG 482000330.024.48.615.8 1.812.024.0Q1CLVTH162245MDLREPSSOPDL481000330.032.411.3516.23.116.032.0Q1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) CLVTH162245IDGGREP TSSOP DGG482000346.0346.041.0 CLVTH162245MDLREP SSOP DL481000346.0346.049.0IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by government requirements,testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design.Customers are responsible for their products and applications using TI components.To minimize the risks associated with customer products and applications,customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license,either express or implied,is granted under any TI patent right,copyright,mask work right, or other TI intellectual property right relating to any combination,machine,or process in which TI products or services are rmation published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement e of such information may require a license from a third party under the patents or other intellectual property of the third party,or a license from TI under the patents or other intellectual property of TI.Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties,conditions,limitations,and notices.Reproduction of this information with alteration is an unfair and deceptive business practice.TI is not responsible or liable for such altered rmation of third parties may be subject to additional restrictions.Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice.TI is not responsible or liable for any such statements.TI products are not authorized for use in safety-critical applications(such as life support)where a failure of the TI product would reasonably be expected to cause severe personal injury or death,unless officers of the parties have executed an agreement specifically governing such use.Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications,and acknowledge and agree that they are solely responsible for all legal,regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications,notwithstanding any applications-related information or support that may be provided by TI.Further,Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications.TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or"enhanced plastic."Only products designated by TI as military-grade meet military specifications.Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk,and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS16949requirements.Buyers acknowledge and agree that,if they use any non-designated products in automotive applications,TI will not be responsible for any failure to meet such requirements.Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAmplifiers AudioData Converters AutomotiveDSP BroadbandClocks and Timers Digital ControlInterface MedicalLogic MilitaryPower Mgmt Optical NetworkingMicrocontrollers SecurityRFID TelephonyRF/IF and ZigBee®Solutions Video&ImagingWirelessMailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2008,Texas Instruments Incorporated。
YL2440
YL2440优点(以下是其它开发板所没有的):1,双网卡(10M CS8900Q3, 100M DM9000都有) 2,高速IDE接口(配上LINUX,WCE驱动的)3,标准VGA接口4,CF卡接口5,CAN总线接口6,130万象素的摄像头接口7,IRDA红外线数据通讯口8,双系统,LINUX2.6和WinCE5.0注意: 本页仅出售YL2440开发板的光盘若需YL2440开发板,本店另有套件出售,详见:/, 那儿将附送YL2440开发板的光盘. 合作愉快. DVD光盘内的主要资料如下:.With.Platform.Builder ( PB5.0) Microsoft eMbedded Visual C++ 4.0Linux 2.6 全套开发包及源代码WinCE 5.0 全套开发包及源代码YL2440开以板原理图BIOS源码(ADS编译)裸板(无系统)测试程席源码.下面是驱动详细见绍:YL2440开发板简介YL2440 开发板采用SAMSUNG S3C2440A微处理器设计，核心板采用DIMM－200连接器与底板相连接，并且兼容我公司出品的YL2410核心板。
该板可流畅进行MP3编解码和 QVGA，可接130万像素摄像头。
尤适用于开发GPS导航,各种监控设备，网络应用产品等。
YL2440开发板硬件资源:中央处理器◆ CPU: 三星S3C2440A，主频400MHz；外部存储器◆内存：64M字节；◆ NOR Flash：2M字节（SST39VF1601）；◆ NAND Flash：64M字节（K9F1208，用户可自己更换为16M、32M或128M的NandFlash）串口◆两个五线异步串行口，波特率高达115200bps；◆一个九线异步串行口，采用ST16C550扩展出来的，波特率高达1.5Mbps；网络接口◆一个10M网口，采用CS8900Q3，带联接和传输指示灯；◆一个100M网口，采用DM9000，带联接和传输指示灯；USB接口◆一个USB1.1 HOST接口；◆一个USB1.1 Device接口；红外通讯口◆一个IRDA红外线数据通讯口；CAN总线接口◆一个CAN总线接口，全面支持CAN2.0A和CAN2.0B协议；音频接口◆采用IIS接口芯片UDA1341，一路立体声音频输出接口可接耳机或音箱；◆支持录音，板子自带驻机体话筒可直接录音，另有一路话筒输入接口可接麦克风；存储接口◆一个SD卡接口，可接1GB SD卡；◆一个CF卡接口（3.3V，接口信号均加了74LVTH162245驱动），工作在TrueIDE模式；◆一个IDE接口(接口信号均加了74LVTH162245驱动)，可直接挂接硬盘；LCD和触摸屏接口◆板上集成了4线电阻式触摸屏接口的相关电路；◆一个50芯LCD接口引出了LCD控制器的全部信号，并且这些信号引脚都加了74LVTH162245驱动，所以LCD输出更加稳定可靠；◆标准配置为256K色240x320/3.5英寸TFT液晶屏，带触摸屏◆支持黑白、4级灰度、16级灰度、256色、4096色STN液晶屏，尺寸从3.5寸到12.1寸，屏幕分辨率可达到1024×768象素；◆板上引出一个5V电源输出接口，可为大尺寸TFT液晶屏的5V CCFL背光模块供电；摄像头接口◆板上自带一个130万象素的摄像头，可直接摄像并在液晶屏上显示，并有一个2毫米间距双排插座用作摄像头扩展，用户可使用这个扩展口连接其他型号摄像头；VGA接口◆一个标准VGA接口，可直接连接各种VGA接口的CRT显示器或液晶显示器，带对比度微调电位器；时钟源◆内部实时时钟（带有后备锂电池）；复位电路◆一个复位按键，并采用专用复位芯片进行复位，稳定可靠；调试及下载接口◆一个20芯Multi－ICE标准JTAG接口，支持SDT2.51,ADS1.2等调试；电源接口◆ 5V电源供电，带电源开关和指示灯；其他◆八个小按键，四个高亮LED；◆一个蜂鸣器（带使能控制的短路块）；◆一个可调电阻接到ADC引脚上用来验证模数转换；◆一个50芯2毫米间距双排标准连接器用作扩展口，引出了地址线、数据线、读写、片选、中断、IO口、ADC、5V和3.3V电源、地等用户扩展可能用到的信号；；操作系统◆支持Linux2.6.12◆支持WinCE5.0用户光盘上提供的开发工具和源代码：1) ADS1.20安装程序(评估版)；2) 使用SUPERJTAG并支持ADS1.20的JTAG调试软件ARMJTAGDEBUGFINAL；3) 烧写FLASH的工具软件SJF2410（这个工具支持2410/2440，包含NT/2000/XP解决方案）；4) 串口工具软件sscom32.exe、dnw.exe、tftp.exe；5) 64K色（RGB565）图片字模软件；6) USB Device接口驱动程序；7) BIOS源代码（ADS1.20的项目文件）；8) 测试程序(ADS1.20的项目文件，包含全部源代码)，包括如下测试：RTC 实时时钟测试、按键测试（中断测试）、蜂鸣器测试、SD卡读写测试、音频录音放音测试、蜂鸣器测试（PWM测试）、ADC模数转换器测试、IIS音频播放 wav音乐测试、IIS音频录音测试、IrDA红外测试和、触摸屏测试、3.5寸夏普TFT液晶屏测试、CAN总线测试、VGA测试、摄像头测试等等；9) Linux for S3c2440内核源码包以及编译工具，含CS8900和DM9000的EHTNENET端口驱动，UART驱动USB HOST & DEVICE驱动；10) 核心板和底板电路原理图（OrCAD格式）11) 元件封装库和PCB尺寸结构图；12) 开发板使用手册（pdf格式）；13) 开发板上所用到的主要芯片手册、资料；14) ADS使用、DNW串口使用和超级终端配置的一些多媒体演示；4500元的 YL2440 套件包括:1) 一块已测试好的YL2440开发板（包括YL2440核心板与底板）2) 可选购配件LCD：CT35T CT64T CT80T CT104T (配有触摸笔)3) YL2440用户光盘4) 一个SUPER JTAG调试头（带20芯排线）, 可选购仿真器：ARMstep-P/ ARMstep-U/ ARM-tracerII5) 一条25P（公对母）并口线6) 一条9线交叉串口线7) 一条交叉网线8) 一条USB线9) 一条触摸笔10) 一个130万象素的摄像头11) 一个5V/2A直流电源12) 一个精美包装盒YL2440开发平台技术规格。
AV162344DL资料
元器件交易网SSOP56:plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1TSSOP56:plastic thin shrink small outline package; 56 leads; body width 6.1mm SOT364-1NOTES 1998 Jun 3011DefinitionsShort-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook.Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.DisclaimersLife support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.Philips Semiconductors811 East Arques AvenueP.O. Box 3409Sunnyvale, California 94088–3409Telephone 800-234-7381© Copyright Philips Electronics North America Corporation 1998All rights reserved. Printed in U.S.A.print code Date of release: 05-96。
IDT74FCT162245ET中文资料
MILITARY AND COMMERCIAL TEMPERATURE RANGESAUGUST 1996The 16-bit transceivers are built using advanced dual metal CMOS technology. These high-speed, low-power transceiv-ers are ideal for synchronous communication between two busses (A and B). The Direction and Output Enable controls operate these devices as either two independent 8-bit trans-ceivers or one 16-bit transceiver. The direction control pin (xDIR) controls the direction of data flow. The output enable pin (x OE ) overrides the direction control and disables both ports. All inputs are designed with hysteresis for improved noise margin.The FCT16245T are ideally suited for driving high-capaci-tance loads and low-impedance backplanes. The output buff-ers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers.The FCT162245T have balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot, and controlled output fall times– reducing the need for external series terminating resistors. The FCT162245T are plug-in replacements for the FCT16245T and ABT16245 for on-board interface applications.The FCT166245T are suited for very low noise, point-to-point driving where there is a single receiver, or a light lumpedThe IDT logo is a registered trademark of Integrated Device Technology, Inc.FUNCTIONAL BLOCK DIAGRAM1 DIR1OE1A 11A 21A 31A 41A 51A 61A 71A 81B 11B 21B 31B 41B 51B 61B 71B 82545 drw 022 DIR22A 12A 22A 32A 42A 52A 62A 72A 82B 12B 22B 32B 42B 52B 62B 72B 82545 drw 01•Common features:–0.5 MICRON CMOS Technology–High-speed, low-power CMOS replacement for ABT functions–Typical t SK (o) (Output Skew) < 250ps–Low input and output leakage ≤ 1µA (max.)–ESD > 2000V per MIL-STD-883, Method 3015;> 200V using machine model (C = 200pF, R = 0)–Packages include 25 mil pitch SSOP, 19.6 mil pitchTSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack –Extended commercial range of -40°C to +85°C •Features for FCT16245T/AT/CT/ET:–High drive outputs (-32mA I OH , 64mA I OL )–Power off disable outputs permit “live insertion”–Typical V OLP (Output Ground Bounce) < 1.0V at V CC = 5V, T A = 25°C•Features for FCT162245T/AT/CT/ET:–Balanced Output Drivers:±24mA (commercial),±16mA (military)–Reduced system switching noise–Typical V OLP (Output Ground Bounce) < 0.6V at V CC = 5V,T A = 25°C1DIR 1B 1GND1B 3V CCGND2B 2GNDV CCGND1B 21B 41B 51B 61B 71B 82B 12B 32B 42B 52B 72B 82B 62DIR1A 11A 2GND1A 31A 4V CC1A 51A 61A 71A 82A 12A 22A 32A 4V CC2A 52A 72A 82A 6GNDGNDGND21OE 2545 drw 04CERPACK TOP VIEWFEATURES: (Cont'd.)DESCRIPTION: (Cont'd.)•Features for FCT166245T/AT/CT:–Light Drive A Port:±8mA (commercial),±6mA (military)–High Drive B Port:+64mA, –32mA (commercial),+48mA, –24mA (military)–Minimal system switching noise–Typical V OLP (Output Ground Bounce) < 0.25V at V CC = 5V,T A = 25°C (A Port Switching)•Features for FCT162H245T/AT/CT/ET:–Bus Hold retains last active bus state during 3-state –Eliminates the need for external pull up resistorsload (<100pF). The buffers are designed to limit the output current to levels which will avoid noise and ringing on the signal lines without using external series terminating resis-tors. These parts have a ±8mA driver on the "A" Port and a +64/–32mA driver on the "B" Port, making them ideal for interfacing noisy system busses to noise sensitive interfaces.The FCT162H245T have "Bus Hold" which retains the input's last state whenever the input goes to high impedance.This prevents "floating" inputs and eliminates the need for pull-up/down resistors.PIN CONFIGURATIONS1DIR 1B 1GND1B 3V CCGND2B 2GNDV CCGND1B 21B 41B 51B 61B 71B 82B 12B 32B 42B 52B 72B 82B 62DIR1A 11A 2GND1A 31A 4V CC1A 51A 61A 71A 82A 12A 22A 32A 4V CC2A 52A 72A 82A 6GNDGNDGND212545 drw 03SSOP/TSSOP/TVSOP TOP VIEW1. This parameter is measured at characterization but not tested.(1)2545 tbl 02CAPACITANCE (T A = +25°C, f = 1.0MHz)(1)1.H = HIGH Voltage LevelL = LOW Voltage Level X = Don't CareZ = High Impedance2545 tbl 01NOTES:1.On FCT162H245T these pins have “Bus Hold”. All other pins are standard inputs, outputs or I/Os.2.On FCT166245T this is the ±8mA Port.3.On FCT166245T this is the +64/–32mA Port.1.Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.2.All device terminals except FCT162XXXT and FCT166XXXT (A-Port)Output and I/O terminals.3.Output and I/O terminals for FCT162XXXT and FCT166XXXT (A-Port).ADC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (STANDARD PARTS)Following Conditions Apply Unless Otherwise Specified:NOTES:1.For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.2.Typical values are at Vcc = 5.0V, +25°C ambient.3.Not more than one output should be tested at one time. Duration of the test should not exceed one second.4.Duration of the condition can not exceed one second.5.The test limit for this parameter is ± 5µA at T A = –55°C.DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE (BUS HOLD) Following Conditions Apply Unless Otherwise Specified:A CC A CCNOTES:1.For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.2.Typical values are at Vcc = 5.0V, +25°C ambient.3.Not more than one output should be tested at one time. Duration of the test should not exceed one second.4.Pins with Bus Hold are identified in the pin description.5.The test limit for this parameter is ± 5µA at T A = –55°C.6.Does not include Bus Hold I/O pins.1.For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.2.Typical values are at V CC = 5.0V, +25°C ambient.3.Per TTL driven input (V IN = 3.4V). All other inputs at V CC or GND.4.This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.5.Values for these conditions are examples of the I CC formula. These limits are guaranteed but not tested.6.I C = I QUIESCENT + I INPUTS + I DYNAMICI C = I CC + ∆I CC D H N T + I CCD (f CP N CP/2 + f i N i)I CC = Quiescent Current (I CCL, I CCH and I CCZ)∆I CC = Power Supply Current for a TTL High Input (V IN = 3.4V)D H = Duty Cycle for TTL Inputs HighN T = Number of TTL Inputs at D HI CCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)f CP = Clock Frequency for Register Devices (Zero for Non-Register Devices)N CP = Number of Clock Inputs at f CPf i = Input FrequencyN i = Number of Inputs at f iNOTES:1.See test circuit and waveforms.2.Minimum limits are guaranteed but not tested on Propagation Delays.3.Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.4.This parameter is guaranteed but not tested.5.Including parts with Bus Hold.ANOTES:1.See test circuit and waveforms.2.Minimum limits are guaranteed but not tested on Propagation Delays.3.Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.4.This parameter is guaranteed but not tested.C L =Load capacitance: includes jig and probe capacitance.R T =Termination resistance: should be equal to Z OUT of the PulseGenerator.7.0V3V 1.5V 0V3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V DATA INPUTPRESET CLEAR ETC.1.5V1.5V3V 1.5V 0V 1.5V V OH OUTPUT3V 1.5V 0VV OL 3V 1.5V0V 3.5V 0VV OLENABLEDISABLEV OHPRESET CLEARCLOCK ENABLEETC.PROPAGATION DELAYSET-UP, HOLD AND RELEASE TIMES PULSE WIDTHSWITCH POSITIONTEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTSNOTES:1.Diagram shown for input Control Enable-LOW and input Control Disable-HIGH2.Pulse Generator for All Pulses: Rate ≤ 1.0MHz; t F ≤ 2.5ns; t R ≤ 2.5ns2545 drw 092545 drw 052545 drw 062545 drw 082545 drw 07ENABLE AND DISABLE TIMESORDERING INFORMATION2545 drw 10IDT XXXXXX X X BlankB PV PA PF E 245T 245AT 245CT 245ET CommercialMIL-STD-883, Class BShrink Small Outline Package (SO48-1)Thin Shrink Small Outline Package (SO48-2)Thin Very Small Outline Package (SO48-3)CERPACK (E48-1)Non-Inverting 16-Bit Bidirectional Transceiver5474–55°C to +125°C –40°C to +85°CFCTBlank H Standard Bus Hold1616216616-Bit High Drive16-Bit Balanced Drive 16-Bit Light Drive X X。
74LVC245AD原版数据手册.pdf-EasyDatasheet
NXP Semiconductors
74LVC245A; 74LVCH245A
Octal bus transceiver; 3-state
3. Ordering information
Table 1. Ordering information Package Temperature range Name 74LVC245AD 74LVCH245AD 74LVC245ADB 74LVCH245ADB 74LVC245APW 74LVCH245APW 74LVC245ABQ 74LVCH245ABQ 74LVC245ABX 74LVCH245ABX 40 C to +125 C DHXQFN20 40 C to +125 C DHVQFN20 40 C to +125 C TSSOP20 40 C to +125 C SSOP20 40 C to +125 C SO20 Description plastic small outline package; 20 leads; body width 7.5 mm plastic shrink small outline package; 20 leads; body width 5.3 mm Version SOT163-1 SOT339-1 Type number
74LVC_LVCH245A
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Product data sheet
Rev. 8 — 28 June 2013
基于UART Ip核实现嵌入式微处理器扩展多串口电路的设计
基于ＵＡＲＴＩｐ核实现嵌入式微处理器扩展多串口电路的设计作者：方明林建中来源：《硅谷》2009年第05期[摘要]给出利用FPGA上实现的UART IP核，实现在微处理器S3C2440A总线上动态扩展多串口电路，论述基于发送和接收FIFO下的UART接口模块设计以及各主要功能模块实现。
另外，给出节省中断资源的用于实现串口动态扩展的电路。
最后，给出WINCE5.0下多串口设备驱动程序的实现框架。
[关键词]UART S3C2440A WINCE 5.0中图分类号：TP3文献标识码：A文章编号：16717597（2009）0310015－03一、引言由于基于FPGA/CPLD实现的电路在灵活性，体积，成本方面都有其优势。
本文从实际应用的角度出发，为了满足高速数据传输要求，利用FPGA实现了分别拥有512字节的发送和接收FIFO的UART接口模块，并采用接口电路动态扩展UART，以实现微处理器S3C2440A上实现扩展多串口的目的，在最少改动电路下满足要求高速传输的多串口场合。
同时，本文还给出了在嵌入式操作系统WINCE5.0下的多串口驱动实现过程。
二、硬件电路总体设计硬件电路实现如图（1）所示，主要有微处理器S3C2440A，两片缓冲器74LVTH162245分别用于地址总线/片选和数据总线的缓冲，以及一块FPGA模块组成。
微处理器是三星32bit ARM920T内核的S3C2440A，其主频在400MHZ，最高可达533MHZ，可扩展外部存器，具有丰富的I2C，SPI，CAN，以太网，USB等控制接口，还可通过总线扩展其他接口电路，应用层面非常广泛。
而FPGA模块的功能是使用VHDL实现了UART IP核以及多串口扩展控制电路，该控制电路通过产生多个串口的片选以及通过微处理器的1个GPIO口作为中断使能信号来高效管理多个串口中断共用一个中断的有效方法来实现多串口的扩展，通过这不仅节约了中断资源，同时，也保证了多个串口中断的无漏检测和服务。
SN74CBT16214CDGGR,SN74CBT16214CDGGR,74CBT16214CDGGRE4,74CBT16214CDGGRG4, 规格书,Datasheet 资料
PACKAGING INFORMATIONOrderable Device Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)74CBT16214CDGGRE4ACTIVE TSSOP DGG 562000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM 74CBT16214CDGGRG4ACTIVE TSSOP DGG 562000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74CBT16214CDGGR ACTIVE TSSOP DGG 562000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74CBT16214CDL ACTIVE SSOP DL 5620Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74CBT16214CDLG4ACTIVE SSOP DL 5620Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74CBT16214CDLR ACTIVE SSOP DL 561000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74CBT16214CDLRG4ACTIVESSOPDL561000Green (RoHS &no Sb/Br)CU NIPDAULevel-1-260C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1)lead-based flip-chip solder bumps used between the die and package,or 2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free (RoHS compatible)as defined above.Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and freeof Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.PACKAGE OPTION ADDENDUM27-Sep-2007TAPE AND REEL INFORMATION*All dimensions are nominalDevicePackage Type Package Drawing Pins SPQReel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant SN74CBT16214CDGGR TSSOP DGG 562000330.024.48.615.6 1.812.024.0Q1SN74CBT16214CDLRSSOPDL561000330.032.411.3518.673.116.032.0Q1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) SN74CBT16214CDGGR TSSOP DGG562000346.0346.041.0 SN74CBT16214CDLR SSOP DL561000346.0346.049.0IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by government requirements,testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design.Customers are responsible for their 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74LVCH162245的作用
关于
74LVCH162245
的作用
近来在S3C2410平台做TFT液晶，发现很多电路都使用了74LVCH162245作为总线连接期间，也有一些IDE硬盘的连接也使用了他，上网查询了一下，具体作用应该有如下三个：
1. 电平转换，这是说的最多的一个，也是最不确定的一个作用。
不知道有没有！
2. 总线隔离，我觉得这是最主要的作用。
一个高速的总线（50M以上）到处乱跑的话，其后果的很可怕的。
使用它可以有效减少EMI，同时也不会由于一个外设的损坏而导致整个总线的瘫痪。
3. 增强总线的驱动能力。
目前了解的作用应该就是以上三点。
希望大家赐教！。
sn74alvc164245
FEATURESNOTE: New and improved versions of the SN74ALVC164245are available. The new part numbers are SN74LVC16T245 andSN74LVCH16T245 and should be considered for new designs.DESCRIPTION/ORDERING INFORMATIONDGG OR DL PACKAGE(TOP VIEW)1234567891011121314151617181920212223244847464544434241403938373635343332313029282726251DIR1B11B2GND1B31B4(3.3 V, 5 V) V CCB1B51B6GND1B71B82B12B2GND2B32B4(3.3 V, 5 V) V CCB2B52B6GND2B72B82DIR1OE1A11A2GND1A31A4V CCA (2.5 V, 3.3 V)1A51A6GND1A71A82A12A2GND2A32A4V CCA (2.5 V, 3.3 V)2A52A6GND2A72A82OESN74ALVC16424516-BIT2.5-V TO3.3-V/3.3-V TO5-V LEVEL-SHIFTING TRANSCEIVERWITH3-STATE OUTPUTSSCAS416P–MARCH1994–REVISED NOVEMBER2005•Member of the Texas Instruments Widebus™Family•Max t pd of5.8ns at3.3V•±24-mA Output Drive at3.3V•Control Inputs V IH/V IL Levels Are Referencedto V CCA Voltage•Latch-Up Performance Exceeds250mA PerJESD17This16-bit(dual-octal)noninverting bus transceivercontains two separate supply rails.B port has V CCB,which is set to operate at3.3V and5V.A port hasV CCA,which is set to operate at2.5V and3.3V.Thisallows for translation from a 2.5-V to a 3.3-Venvironment,and vice versa,or from a3.3-V to a5-Venvironment,and vice versa.The SN74ALVC164245is designed for asynchronouscommunication between data buses.The controlcircuitry(1DIR,2DIR,1OE,and2OE)is powered byV CCA.To ensure the high-impedance state during power upor power down,the output-enable(OE)input shouldbe tied to V CC through a pullup resistor;the minimumvalue of the resistor is determined by thecurrent-sinking capability of the driver.ORDERING INFORMATIONT A PACKAGE(1)ORDERABLE PART NUMBER TOP-SIDE MARKINGFBGA–GRD74ALVC164245GRDRTape and reel VC4245FBGA–ZRD(Pb-free)74ALVC164245ZRDRTube of25SN74ALVC164245DLSSOP–DL SN74ALVC164245DLR ALVC164245Reel of100074ALVC164245DLRG4–40°C to85°C SN74ALVC164245DGGRReel of200074ALVC164245DGGRG4TSSOP–DGG ALVC164245SN74ALVC164245DGGTReel of25074ALVC164245DGGTE4VFBGA–GQL SN74ALVC164245KRReel of1000VC4245VFBGA–ZQL(Pb-free)74ALVC164245ZQLR(1)Package drawings,standard packing quantities,thermal data,symbolization,and PCB design guidelines are available at/sc/package.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Widebus is a trademark of Texas Instruments.PRODUCTION DATA information is current as of publication date.Copyright©1994–2005,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.DESCRIPTION/ORDERING INFORMATION (CONTINUED)GQL OR ZQL PACKAGE (TOP VIEW)J H G F E D C B A 213465KGRD OR ZRD PACKAGE(TOP VIEW)JH G F E D C B A 213465SN74ALVC16424516-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTSSCAS416P–MARCH 1994–REVISED NOVEMBER 2005The logic levels of the direction-control (DIR)input and the output-enable (OE)input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode.The device transmits data from the A bus to the B bus when the B-port outputs are activated,and from the B bus to the A bus when the A-port outputs are activated.The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess I CC and I CCZ .TERMINAL ASSIGNMENTS (1)(56-Ball GQL/ZQL Package)123456A 1DIR NC NC NC NC 1OE B 1B21B1GND GND 1A11A2C 1B41B3V CCB V CCA 1A31A4D 1B61B5GNDGND1A51A6E 1B81B71A71A8F 2B12B22A22A1G 2B32B4GND GND 2A42A3H 2B52B6V CCB V CCA 2A62A5J 2B72B8GND GND 2A82A7K2DIRNCNCNCNC2OE(1)NC –No internal connectionTERMINAL ASSIGNMENTS (1)(54-Ball GRD/ZRD Package)123456A 1B1NC 1DIR 1OE NC 1A1B 1B31B2NC NC 1A21A3C 1B51B4V CCB V CCA 1A41A5D 1B71B6GND GND 1A61A7E 2B11B8GND GND 1A82A1F 2B32B2GND GND 2A22A3G 2B52B4V CCB V CCA 2A42A5H 2B72B6NC NC 2A62A7J 2B8NC2DIR2OENC2A8(1)NC –No internal connectionFUNCTION TABLE (1)(EACH 8-BIT SECTION)CONTROL INPUTS OUTPUT CIRCUITS OPERATION OE DIR A PORT B PORT L L Enabled Hi-Z B data to A bus L H Hi-Z Enabled A data to B busH XHi-ZHi-ZIsolation(1)Input circuits of the data I/Os always are active.2To Seven Other Channels 1DIR1A11B11OETo Seven Other Channels2DIR2A12B12OEAbsolute Maximum Ratings (1)SN74ALVC16424516-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVERWITH 3-STATE OUTPUTSSCAS416P–MARCH 1994–REVISED NOVEMBER 2005LOGIC DIAGRAM (POSITIVE LOGIC)over operating free-air temperature range for V CCB at 5V and V CCA at 3.3V (unless otherwise noted)MINMAX UNIT V CCA –0.5 4.6V CCSupply voltage rangeVV CCB–0.56Except I/O ports (2)–0.56V I Input voltage range I/O port A (3)–0.5V CCA +0.5V I/O port B (2)–0.5V CCB +0.5I IK Input clamp current V I <0–50mA I OK Output clamp current V O <0–50mA I OContinuous output current±50mA Continuous current through each V CC or GND±100mA DGG package70DL package 63θJAPackage thermal impedance (4)°C/W GQL/ZQL package 42GRD/ZRD package36T stg Storage temperature range–65150°C (1)Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)This value is limited to 6V maximum.(3)This value is limited to 4.6V maximum.(4)The package thermal impedance is calculated in accordance with JESD 51-7.3Recommended Operating Conditions (1)Recommended Operating Conditions (1)SN74ALVC16424516-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTSSCAS416P–MARCH 1994–REVISED NOVEMBER 2005for V CCB at 3.3V and 5VMINMAX UNIT V CCB Supply voltage 3 5.5V V IH High-level input voltage 2V V CCB =3V to 3.6V 0.7V IL Low-level input voltage V V CCB =4.5V to 5.5V0.8V IB Input voltage 0V CCB V V OB Output voltage0V CCB V I OH High-level output current –24mA I OL Low-level output current 24mA ∆t/∆v Input transition rise or fall rate 10ns/V T A Operating free-air temperature–4085°C(1)All unused inputs of the device must be held at V CC or GND to ensure proper device operation.Refer to the TI application report,Implications of Slow or Floating CMOS Inputs ,literature number SCBA004.for V CCA at 2.5V and 3.3VMINMAX UNIT V CCA Supply voltage 2.3 3.6V V CCA =2.3V to 2.7V 1.7V IH High-level input voltage V V CCA =3V to 3.6V 2V CCA =2.3V to 2.7V 0.7V IL Low-level input voltage V V CCA =3V to 3.6V0.8V IA Input voltage 0V CCA V V OA Output voltage0V CCA V V CCA =2.3V –18I OH High-level output current mA V CCA =3V –24V CCA =2.3V 18I OL Low-level output current mA V CCA =3V24∆t/∆v Input transition rise or fall rate 10ns/V T A Operating free-air temperature–4085°C(1)All unused inputs of the device must be held at V CC or GND to ensure proper device operation.Refer to the TI application report,Implications of Slow or Floating CMOS Inputs ,literature number SCBA004.4Electrical Characteristics Electrical CharacteristicsSN74ALVC164245 16-BIT2.5-V TO3.3-V/3.3-V TO5-V LEVEL-SHIFTING TRANSCEIVERWITH3-STATE OUTPUTSSCAS416P–MARCH1994–REVISED NOVEMBER2005over recommended operating free-air temperature range for VCCA =2.7V to3.6V and VCCB=4.5V to5.5V(unlessotherwise noted)PARAMETER TEST CONDITIONS V CCA V CCB MIN TYP(1)MAX UNITI OH=–100µA 2.7V to3.6V V CC–0.22.7V 2.2B to A I OH=–12mA3V 2.4I OH=–24mA3V2V OH V4.5V 4.3I OH=–100µA5.5V 5.3A to B4.5V 3.7I OH=–24mA5.5V 4.7I OL=100µA 2.7V to3.6V0.2B to A I OL=12mA 2.7V0.4V OL I OL=24mA3V0.55VI OL=100µA 4.5V to5.5V0.2A to BI OL=24mA 4.5V to5.5V0.55I I Control inputs V I=V CCA/V CCB or GND 3.6V 5.5V±5µAI OZ(2)A or B port V O=V CCA/V CCB or GND 3.6V 5.5V±10µAI CC V I=V CCA/V CCB or GND,I O=0 3.6V 5.5V40µAOne input at V CCA/V CCB–0.6V,∆I CC(3)3V to3.6V 4.5V to5.5V750µA Other inputs at V CCA/V CCB or GNDC i Control inputs V I=V CCA/V CCB or GND 3.3V5V 6.5pFC io A or B port V O=V CCA/V CCB or GND 3.3V 3.3V8.5pF(1)Typical values are measured at V CCA=3.3V and V CCB=5V,T A=25°C.(2)For I/O ports,the parameter I OZ includes the input leakage current.(3)This is the increase in supply current for each input that is at one of the specified TTL voltage levels,rather than at0or the associatedV CC.over recommended operating free-air temperature range for VCCA =2.3V to2.7V and VCCB=3V to3.6V(unless otherwisenoted)PARAMETER TEST CONDITIONS V CCA V CCB MIN MAX UNITI OH=–100µA 2.3V to2.7V3V to3.6V V CCA–0.2B to A I OH=–8mA 2.3V3V to3.6V 1.7V OH I OH=–12mA 2.7V3V to3.6V 1.8VI OH=–100µA 2.3V to2.7V3V to3.6V V CCB–0.2A to BI OH=–18mA 2.3V to2.7V3V 2.2I OL=100µA 2.3V to2.7V3V to3.6V0.2B to AI OL=12mA 2.3V3V to3.6V0.6V OL VI OL=100µA 2.3V to2.7V3V to3.6V0.2A to BI OL=18mA 2.3V3V0.55I I Control inputs V I=V CCA/V CCB or GND 2.3V to2.7V3V to3.6V±5µAI OZ(1)A or B port V O=V CCA/V CCB or GND 2.3V to2.7V3V to3.6V±10µAI CC V I=V CCA/V CCB or GND,I O=0 2.3V to2.7V3V to3.6V20µAOne input at V CCA/V CCB–0.6V,∆I CC(2) 2.3V to2.7V3V to3.6V750µA Other inputs at V CCA/V CCB or GND(1)For I/O ports,the parameter I OZ includes the input leakage current.(2)This is the increase in supply current for each input that is at one of the specified TTL voltage levels,rather than at0or the associatedV CC.5Switching CharacteristicsOperating CharacteristicsSN74ALVC16424516-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTSSCAS416P–MARCH 1994–REVISED NOVEMBER 2005over recommended operating free-air temperature range (unless otherwise noted)(see Figure 1through Figure 4)V CCB =3.3V V CCB =5V ±0.5V ±0.3V FROM TO PARAMETERV CCA =2.5V V CCA =3.3V UNIT(INPUT)(OUTPUT)V CCA =2.7V ±0.2V ±0.3V MINMAX MINMAX MIN MAX A B 7.6 5.91 5.8t pd ns B A 7.6 6.7 1.2 5.8t en OE B 11.59.318.9ns t dis OE B 10.59.2 2.19.5ns t en OE A 12.310.229.1ns t disOEA9.392.98.6ns T A =25°CV CCB =3.3VV CCB =5V PARAMETERTEST CONDITIONSV CCA =2.5VV CCA =3.3VUNITTYPTYP Outputs enabled (B)5556C L =50pF,f =10MHz Outputs disabled (B)276C pdPower dissipation capacitancepF Outputs enabled (A)11856C L =50pF,f =10MHzOutputs disabled (A)5866POWER-UP CONSIDERATIONS(1)SN74ALVC16424516-BIT2.5-V TO3.3-V/3.3-V TO5-V LEVEL-SHIFTING TRANSCEIVERWITH3-STATE OUTPUTSSCAS416P–MARCH1994–REVISED NOVEMBER2005TI level-translation devices offer an opportunity for successful mixed-voltage signal design.A proper power-up sequence always should be followed to avoid excessive supply current,bus contention,oscillations,or other anomalies caused by improperly biased device pins.Take these precautions to guard against such power-up problems:1.Connect ground before any supply voltage is applied.2.Power up the control side of the device(V CCA for all four of these devices).3.Tie OE to V CCA with a pullup resistor so that it ramps with V CCA.4.Depending on the direction of the data path,DIR can be high or low.If DIR high is needed(A data to B bus),ramp it with V CCA.Otherwise,keep DIR low.(1)Refer to the TI application report,Texas Instruments Voltage-Level-Translation Devices,literature number SCEA021.7PARAMETER MEASUREMENT INFORMATION V OHB V OLBC L LOAD CIRCUITCCB = 6 VOpenOutput Control (low-level enabling)Output Waveform 1S1 at 6 V (see Note B)Output Waveform 2S1 at GND (see Note B)0 V0 VV CCAV CCBVOLTAGE WAVEFORMS PROPAGATION DELAY TIMESVOLTAGE WAVEFORMS ENABLE AND DISABLE TIMESt pd t PLZ /t PZL t PHZ /t PZHOpen V CCB = 6 V GNDTEST S1NOTES: A.C L includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, Z O = 50 Ω, t r ≤2 ns, t f ≤2 ns.D.The outputs are measured one at a time, with one transition per measurement.E.t PLZ and t PHZ are the same as t dis .F.t PZL and t PZH are the same as t en .G.t PLH and t PHL are the same as t pd .SN74ALVC16424516-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTSSCAS416P–MARCH 1994–REVISED NOVEMBER 2005V CCA =2.5V ±0.2V to V CCB =3.3V ±0.3VFigure 1.Load Circuit and Voltage Waveforms8PARAMETER MEASUREMENT INFORMATIONV OHAV OLA From Output Under TestC L LOAD CIRCUITOpen Output Control (low-level enabling)Output Waveform 1S1 at 2 × V CCA (see Note B)Output Waveform 2S1 at GND (see Note B)0 V0 V2.7 VVOLTAGE WAVEFORMS ENABLE AND DISABLE TIMESt pd t PLZ /t PZL t PHZ /t PZHOpen 2 × V CCA GNDTEST S1NOTES: A.C L includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, Z O = 50 Ω, t r ≤2 ns, t f ≤2 ns.D.The outputs are measured one at a time, with one transition per measurement.E.t PLZ and t PHZ are the same as t dis .F.t PZL and t PZH are the same as t en .G.t PLH and t PHL are the same as t pd .InputOutputVOLTAGE WAVEFORMS PROPAGATION DELAY TIMES× V CCAV CCASN74ALVC16424516-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVERWITH 3-STATE OUTPUTSSCAS416P–MARCH 1994–REVISED NOVEMBER 2005V CCB =3.3V ±0.3V to V CCA =2.5V ±0.2VFigure 2.Load Circuit and Voltage Waveforms9PARAMETER MEASUREMENT INFORMATIONV OH V OLC L LOAD CIRCUITV CCBOpenOutput Control (low-level enabling)Output Waveform 1S1 at 2 V CCB(see Note B)Output Waveform 2S1 at GND (see Note B)0 V0 V2.7 V≈V CCBVOLTAGE WAVEFORMS PROPAGATION DELAY TIMESVOLTAGE WAVEFORMS ENABLE AND DISABLE TIMESt pd t PLZ /t PZL t PHZ /t PZHOpen 2 V CCB GNDTEST S1NOTES: A.C L includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 Ω, t r ≤ 2.5 ns, t f ≤ 2.5 ns.D.The outputs are measured one at a time, with one transition per measurement.E.t PLZ and t PHZ are the same as t dis .F.t PZL and t PZH are the same as t en .G.t PLH and t PHL are the same as t pd .SN74ALVC16424516-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTSSCAS416P–MARCH 1994–REVISED NOVEMBER 2005V CCA =3.3V ±0.3V to V CCB =5V ±0.5VFigure 3.Load Circuit and Voltage Waveforms10 PARAMETER MEASUREMENT INFORMATION V OHA V OLAC L LOAD CIRCUIT = 6 VOpenOutput Control(low-levelenabling)Output Waveform 1S1 at 6 V (see Note B)Output Waveform 2S1 at GND (see Note B)0 V 0 V 3 V ≈3 V VOLTAGE WAVEFORMSPROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES t pd t PLZ /t PZL t PHZ /t PZH Open V CCA = 6 V GND TEST S1NOTES: A.C L includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 Ω, t r ≤ 2.5 ns, t f ≤ 2.5 ns.D.The outputs are measured one at a time, with one transition per measurement.E.t PLZ and t PHZ are the same as t dis .F.t PZL and t PZH are the same as t en .G.t PLH and t PHL are the same as t pd .SN74ALVC16424516-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS SCAS416P–MARCH 1994–REVISED NOVEMBER 2005V CCB =5V ±0.5V to V CCA =2.7V and 3.3V ±0.3VFigure 4.Load Circuit and Voltage WaveformsPACKAGING INFORMATIONAddendum-Page 1(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check /productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.OTHER QUALIFIED VERSIONS OF SN74ALVC164245 :•Enhanced Product: SN74ALVC164245-EPNOTE: Qualified Version Definitions:•Enhanced Product - Supports Defense, Aerospace and Medical ApplicationsAddendum-Page 2TAPE AND REELINFORMATION *All dimensions are nominal Device Package Type Package DrawingPinsSPQ Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant 74ALVC164245ZQLR BGA MICROSTAR JUNIORZQL 561000330.016.4 4.87.3 1.58.016.0Q174ALVC164245ZRDR BGA MICROSTAR JUNIORZRD 541000330.016.4 5.88.3 1.558.016.0Q1SN74ALVC164245DGGR TSSOP DGG 482000330.024.48.615.8 1.812.024.0Q1SN74ALVC164245DLR SSOP DL 481000330.032.411.3516.2 3.116.032.0Q1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm)ZQL561000336.6336.628.6 74ALVC164245ZQLR BGA MICROSTARJUNIORZRD541000336.6336.628.6 74ALVC164245ZRDR BGA MICROSTARJUNIORSN74ALVC164245DGGR TSSOP DGG482000367.0367.045.0SN74ALVC164245DLR SSOP DL481000367.0367.055.0IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,enhancements,improvements and other changes to its semiconductor products and services per JESD46,latest issue,and to discontinue any product or service per JESD48,latest issue.Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All semiconductor products(also referred to herein as“components”)are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its components to the specifications applicable at the time of sale,in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by applicable law,testing of all parameters of each component is not necessarily performed.TI assumes no liability for applications assistance or the design of Buyers’products.Buyers are responsible for their products and applications using TI components.To minimize the risks associated with Buyers’products and applications,Buyers should provide adequate design and operating safeguards.TI does not warrant or represent that any license,either express or implied,is granted under any patent right,copyright,mask work right,or other intellectual property right relating to any combination,machine,or process in which TI components or services are rmation published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement e of such information may require a license from a third party under the patents or other intellectual property of the third party,or a license from TI under the patents or other intellectual property of TI.Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties,conditions,limitations,and notices.TI is not responsible or liable for such altered rmation of third parties may be subject to additional restrictions.Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. 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74LVTH16245中文资料
The LVT16245 and LVTH16245 contain sixteen non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. Each byte has separate control inputs which can be shorted together for full 16-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state. The LVTH16245 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These non-inverting transceivers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT16245 and LVTH16245 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation.
74VCX164245中文资料
元器件交易网
74VCX164245
Connection Diagram
Truth Tables
Inputs
OE1
T/R1
L
L
L
General Description
The VCX164245 is a dual supply, 16-bit translating transceiver that is designed for 2 way asynchronous communication between busses at different supply voltages by providing true signal translation. The supply rails consist of VCCB, which is the higher potential rail operating at 2.3 to 3.6V and VCCA, which is the lower potential rail operating at 1.65 to 2.7V. (VCCA must be less than or equal to VCCB for proper device operation.) This dual supply design allows for translation from 1.8V to 2.5V busses to busses at a higher potential, up to 3.3V.
The 74VCX164245 is suitable for mixed voltage applications such as notebook computers using a 1.8V CPU and 3.3V peripheral components. It is fabricated with an Advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
74LVCH32245AEC-T资料
74LVCH32245A32-bit bus transceiver with direction pin; 5 V tolerant; 3-stateRev. 03 — 20 August 2007Product data sheet1.General descriptionThe74LVCH32245A is a32-bit transceiver featuring non-inverting3-state bus compatibleoutputs in both send and receive directions.The device features four output enable(nOE)inputs for easy cascading and four send/receive (nDIR) inputs for direction control.Pin nOE controls the outputs so that the buses are effectively isolated.Inputs can be driven from either 3.3 V or5V devices. When disabled, up to 5.5 V can beapplied to the outputs. These features allow the use of these devices in mixed3.3V and5V applications.T o ensure the high-impedance state during power-up or power-down, pin nOE should betied to V CC through a pull-up resistor; the minimum value of the resistor is determined bythe current-sinking capability of the driver.Bus hold on data inputs eliminates the need for external pull-up resistors to hold unusedinputs.2.FeaturesI5V tolerant inputs/outputs for interfacing with 5V logicI Wide supply voltage range from 1.2 V to3.6VI CMOS low power consumptionI MULTIBYTE flow-through standard pin-out architectureI Low inductance multiple power and ground pins for minimum noise and groundbounceI Direct interface with TTL levelsI Inputs accept voltages up to 5.5 VI High-impedance when V CC=0VI All data inputs have bus holdI Complies with JEDEC standard JESD8-B / JESD36I ESD protection:N HBM EIA/JESD22-A114-B exceeds 2000VN MM EIA/JESD22-A115-A exceeds 200VI Specified from−40°C to+85°CI Packaged in plastic fine-pitch ball grid array package3.Ordering informationTable 1.Ordering informationType number PackageTemperature range Name Description Version 74LVCH32245AEC−40°C to+85°C LFBGA96plastic low profile fine-pitch ball grid array package;SOT536-196balls; body 13.5×5.5×1.05mm4.Functional diagramFig 1.Logic symbolA5A31DIRA2A41B01B11B21B31B41B51B61B7A6A1B5B2B6B1C5C2C6C1D5D2D61A01A11A21A31A41A51A61A7D11OEE5H32DIRE2H42B02B12B22B32B42B52B62B7E6E1F5F2F6F1G5G2G6G1H6H1H52A02A12A22A32A42A52A62A7H22OEJ5J33DIRJ2J43B03B13B23B33B43B53B63B7J6J1K5K2K6K1L5L2L6L1M5M2M63A03A13A23A33A43A53A63A7M13OEN5T34DIRN2T44B04B14B24B34B44B54B64B7N6N1P5P2P6P1R5R2R6R1T6T1T54A04A14A24A34A44A54A64A7T24OEmna4765.Pinning information5.1Pinning5.2Pin descriptionFig 2.Bus hold circuitmna473V CCdata inputto internal circuitFig 3.Pin configurationmna4751A11A31A51A72A12A32A52A63A13A33A53A74A14A34A54A61A01A21A41A62A02A22A42A73A03A23A43A64A04A24A44A71B01B21B41B62B02B22B42B73B03B23B43B64B04B24B44B71B11B31B51B72B12B32B52B63B13B33B53B74B14B34B54B61OE 2OE 3OE GND GND GND GND 4OE V CC V CC GND GND GND GND V CC V CC 1DIR 6521432DIR 3DIR GND GND GND GND 4DIR V CC V CC GND GND GND GND V CC V CC AHJBDEGTCFKMNRLPTable 2.Pin descriptionPin name BallDescription nDIR (n = 1 to 4)A3, H3, J3, T3direction controlnOE (n = 1 to 4)A4, H4, J4, T4output enable input (active LOW)1A[0:7]A5, A6, B5, B6, C5, C6, D5, D6input or output 1B[0:7]A2, A1, B2, B1, C2, C1, D2, D1input or output 2A[0:7]E5, E6, F5, F6, G5, G6, H6, H5input or output 2B[0:7]E2, E1, F2, F1, G2, G1, H1, H2input or output 3A[0:7]J5, J6, K5, K6, L5, L6, M5, M6input or output 3B[0:7]J2, J1, K2, K1, L2, L1, M2, M1input or output 4A[0:7]N5, N6, P5, P6, R5, R6, T6, T5input or output 4B[0:7]N2, N1, P2, P1, R2, R1, T1, T2input or outputGND B3,B4,D3,D4,E3,E4,G3,G4,K3,K4,M3, M4, N3, N4, R3, R4ground (0 V)V CCC3, C4, F3, F4, L3, L4, P3, P4supply voltage6.Functional description[1]H =HIGH voltage level; L =LOW voltage level; X =don’t care; Z = high-impedance OFF-state7.Limiting values[1]The minimum input voltage ratings may be exceeded if the input current ratings are observed.[2]The output voltage ratings may be exceeded if the output current ratings are observed.[3]All supply and ground pins connected externally to one voltage source.[4]Above 70°C the value of P tot derates linearly with 1.8mW/K.8.Recommended operating conditionsTable 3.Function selection [1]Input OutputnOE nDIR nAn nBn L L A = B inputs L H inputs B = A HXZZTable 4.Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).Symbol Parameter Conditions Min Max Unit V CC supply voltage −0.5+6.5V I IK input clamping current V I <0V−50-mA V I input voltage[1]−0.5+6.5V I OK output clamping current V O >V CC or V O <0V -±50mA V O output voltage output HIGH or LOW state [2]−0.5V CC +0.5V output 3-state [2]−0.5+6.5V I O output current V O =0V to V CC-±50mA I CC supply current [3]-200mA I GND ground current [3]−200-mA T stg storage temperature −65+150°C P tottotal power dissipationT amb =−40°C to +85°C[4]-1000mWTable 5.Recommended operating conditions Symbol Parameter ConditionsMin Typ Max Unit V CC supply voltage for maximum speed performance 2.7- 3.6V for low-voltage applications1.2--V V I input voltage 0- 5.5V V O output voltage output HIGH or LOW state 0-V CC V output 3-state 0- 5.5V T amb ambient temperature in free air−40-+85°C ∆t/∆Vinput transition rise and fall rateV CC = 1.2 V to 2.7 V --20ns/V V CC = 2.7 V to 3.6 V --10ns/V9.Static characteristics[1]All typical values are measured at V CC = 3.3 V (unless stated otherwise) and T amb =25°C.[2]The bus hold circuit is switched off when V I >V CC allowing 5.5V on the input terminal.[3]For I/O ports the parameter I OZ includes the input leakage current.[4]Valid for data inputs only. Note that control inputs do not have a bus hold circuit.[5]The specified sustaining current at the data input holds the input below the specified V I level.[6]The specified overdrive current at the data input forces the data input to the opposite input state.Table 6.Static characteristicsAt recommended operating conditions. Voltages are referenced to GND (ground = 0 V).Symbol ParameterConditionsV CC (V)Min Typ [1]Max Unit T amb =−40°C to +85°CV IH HIGH-level input voltage 1.2V CC --V 2.7 to 3.6 2.0--V V IL LOW-level input voltage 1.2--GND V 2.7 to 3.6--0.8V V OHHIGH-level output voltageV I =V IH or V IL I O =−100µA 2.7 to 3.6V CC −0.2V CC -V I O =−12mA 2.7V CC −0.5--V I O =−18mA 3.0V CC −0.6--V I O =−24mA3.0V CC −0.8--V V OLLOW-level output voltageV I =V IH or V IL I O =100µA 2.7 to 3.6-GND 0.20V I O =12mA 2.7--0.40V I O =24mA3.0--0.55V I I input leakage current V I =5.5V or GND 3.6[2]-±0.1±5µA I OZ OFF-state output current V I =V IH or V IL ;V O =5.5V or GND 3.6[2][3]-±0.1±5µA I OFF power-off leakage current V I or V O =5.5V0.0-±0.1±10µA I CC supply currentV I =V CC or GND; I O =0A 3.6-0.140µA ∆I CC additional supply current per input pin;V I =V CC −0.6V; I O =0A 2.7 to 3.6-5500µA C I input capacitance V I =GND to V CC 0 to 3.6- 5.0-pF C I/O input/output capacitance V I =GND to V CC 0 to 3.6-10-pF I BHL bus hold LOW current V I =0.8V 3.0[4][5]75--µA I BHH bus hold HIGH current V I =2.0V3.0[4][5]−75--µA I BHLO bus hold LOW overdrive current3.6[4][6]500--µA I BHHObus hold HIGH overdrive current3.6[4][6]−500--µA10.Dynamic characteristics[1]Typical values are measured at T amb =25°C and V CC = 1.2 V , 2.7 V , and 3.3 V respectively.[2]t pd is the same as t PLH and t PHL .t en is the same as t PZL and t PZH .t dis is the same as t PLZ and t PHZ .[3]Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.[4]C PD is used to determine the dynamic power dissipation (P D in µW).P D =C PD ×V CC 2×f i ×N +Σ(C L ×V CC 2×f o )where:f i = input frequency in MHz; f o =output frequency in MHz C L =output load capacitance in pF V CC =supply voltage in Volts N =number of inputs switchingΣ(C L ×V CC 2×f o )=sum of the outputs.11.WaveformsTable 7.Dynamic characteristicsVoltages are referenced to GND (ground =0V). For test circuit see Figure 6.Symbol Parameter ConditionsV CC (V)Min Typ [1]Max Unit T amb =−40°C to +85°C t pdpropagation delaynAn to nBn;nBn to nAn; see Figure 41.2[2]-13.0-ns 2.7 1.0 2.7 4.7ns 3.0 to 3.61.02.2 4.5ns t enenable timenOE to nAn, nBn: see Figure 51.2[2]-15.0-ns2.7 1.53.6 6.7ns 3.0 to 3.61.02.8 5.5ns t disdisable timenOE to nAn, nBn; see Figure 51.2[2]-11.0-ns2.7 1.53.4 6.6ns 3.0 to 3.61.53.2 5.6ns t sk(o)output skew time 3.0 to 3.6[3]-- 1.0ns C PDpower dissipation capacitanceper buffer; V I =GND to V CC3.3[4]-30-pFV M =1.5V at V CC ≥2.7V .V M =0.5×V CC at V CC <2.7V .V OL and V OH are typical output voltage levels that occur with the output load.Fig 4.The input (nAn, nBn) to output (nBn, nAn) propagation delaysmna477nAn, nBn inputnBn, nAn outputt PHLt PLHGNDV IV MV MV OHV OLV M =1.5V at V CC ≥2.7V .V M =0.5×V CC at V CC <2.7V .V X = V OL + 0.3 V at V CC ≥2.7V;V X = V OL + 0.15 V at V CC <2.7V .V Y = V OH − 0.3 V at V CC ≥2.7V;V Y = V OH − 0.15 V at V CC < 2.7V .V OL and V OH are typical output voltage levels that occur with the output load.Fig 5.3-state enable and disable times.mna362t PLZt PHZoutputs disabledoutputs enabledV YV Xoutputs enabledoutput LOW-to-OFF OFF-to-LOWoutput HIGH-to-OFF OFF-to-HIGHnOE inputV IV OLV OHV CCV MGNDGNDt PZLt PZH V MV MTest data is given in T able 8.Definitions for test circuit:R L = Load resistance.C L = Load capacitance including jig and probe capacitance.R T = Termination resistance should be equal to output impedance Z o of the pulse generator.V EXT = External voltage for measuring switching times.Fig 6.Load circuitry for switching times V M V Mt Wt W10 %90 %0 VV IV I negative pulsepositive pulse0 VV MV M90 %10 %t ft r t rt f 001aae331V EXTV CCV I V ODUTC LR TR LR LGTable 8.Test dataSupply voltageInput Load V EXT V It r , t f C L R L t PLH , t PHL t PLZ , t PZL t PHZ , t PZH 1.2V V CC ≤ 2 ns 50pF 500Ωopen 2× V CC GND 2.7V 2.7V ≤ 2.5ns 50pF 500Ωopen 2× V CC GND 3.0V to 3.6V2.7V≤ 2.5ns50pF500Ωopen2× V CCGND12.Package outlineFig 7.Package outline SOT536-1 (LFBGA96)0.8A 1b A 2UNIT D y e REFERENCESOUTLINE VERSION EUROPEAN PROJECTIONISSUE DATE 00-03-0403-02-05IECJEDECJEITAmm1.50.410.311.20.95.65.4y 113.613.40.510.410.10.2e 14e 212DIMENSIONS (mm are the original dimensions) SOT536-1E 0.15v 0.1w 0510 mmscaleSOT536-1LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm A max.AA 2A 1detail Xe eXD EAB C D E F H G J K L M P N R T 246135B Ae 2e 1ball A1index areaball A1index areayy 1Cb CA C CB∅ v M ∅ w M 1/2 e1/2 e13.Abbreviations14.Revision historyTable 9.AbbreviationsAcronym Description DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine ModelTTLT ransistor-Transistor LogicTable 10.Revision historyDocument ID Release date Data sheet status Change notice Supersedes 74LVCH32245A_320070820Product data sheet-74LVCH32245A_2Modifications:•The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors.•Legal texts have been adapted to the new company name where appropriate.•Error in Table 2 “Pin description” corrected.•Quick Reference Data section rmation (C PD ,C I ,C I/O )moved from it to Table 6and Table 7.•Some parameter symbols and descriptions have been updated to comply with NXP guidelines.74LVCH32245A_220040511Product specification -74LVC_LVCH32245A_174LVC_LVCH32245A_119990901---15.Legal information15.1Data sheet status[1]Please consult the most recently issued document before initiating or completing a design.[2]The term ‘short data sheet’ is explained in section “Definitions”.[3]The product status of device(s)described in this document may have changed since this document was published and may differ in case of multiple devices.The latest product status information is available on the Internet at URL .15.2DefinitionsDraft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness ofinformation included herein and shall have no liability for the consequences of use of such information.Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s)and title.A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.15.3DisclaimersGeneral —Information in this document is believed to be accurate andreliable.However,NXP Semiconductors does not give any representations or warranties,expressed or implied,as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including withoutlimitation specifications and product descriptions, at any time and without notice.This document supersedes and replaces all information supplied prior to the publication hereof.Suitability for use —NXP Semiconductors products are not designed,authorized or warranted to be suitable for use in medical, military, aircraft,space or life support equipment, nor in applications where failure ormalfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage.NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.Limiting values —Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134)may cause permanent damage to the device.Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in theCharacteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability.Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale,as published at /profile/terms , including those pertaining to warranty,intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail.No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant,conveyance or implication of any license under any copyrights,patents or other industrial or intellectual property rights.15.4TrademarksNotice:All referenced brands,product names,service names and trademarks are the property of their respective owners.16.Contact informationFor additional information, please visit:For sales office addresses, send an email to:salesaddresses@Document status [1][2]Product status [3]DefinitionObjective [short] data sheet Development This document contains data from the objective specification for product development.Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.Product [short] data sheetProductionThis document contains the product specification.17.Contents1General description. . . . . . . . . . . . . . . . . . . . . . 12Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Ordering information. . . . . . . . . . . . . . . . . . . . . 24Functional diagram . . . . . . . . . . . . . . . . . . . . . . 35Pinning information. . . . . . . . . . . . . . . . . . . . . . 45.1Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45.2Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 46Functional description . . . . . . . . . . . . . . . . . . . 57Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 58Recommended operating conditions. . . . . . . . 59Static characteristics. . . . . . . . . . . . . . . . . . . . . 610Dynamic characteristics . . . . . . . . . . . . . . . . . . 711Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712Package outline . . . . . . . . . . . . . . . . . . . . . . . . 1013Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 1114Revision history. . . . . . . . . . . . . . . . . . . . . . . . 1115Legal information. . . . . . . . . . . . . . . . . . . . . . . 1215.1Data sheet status . . . . . . . . . . . . . . . . . . . . . . 1215.2Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215.3Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 1215.4T rademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 1216Contact information. . . . . . . . . . . . . . . . . . . . . 1217Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.© NXP B.V.2007.All rights reserved.For more information, please visit: For sales office addresses, please send an email to: salesaddresses@Date of release: 20 August 2007。
74LV165中文资料
元器件交易网DIP16:plastic dual in-line package; 16 leads (300 mil)SOT38-4SO16:plastic small outline package; 16 leads; body width 3.9 mm SOT109-1SSOP16:plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1TSSOP16:plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1NOTESPhilips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.This data sheet contains preliminary data, and supplementary data will be published at a later date. PhilipsSemiconductors reserves the right to make changes at any time without notice in order to improve designand supply the best possible product.Philips Semiconductors811 East Arques AvenueP .O. Box 3409Sunnyvale, California 94088–3409Telephone 800-234-7381DEFINITIONSData Sheet IdentificationProduct Status Definition Objective Specification Preliminary Specification Product Specification Formative or in Design Preproduction Product Full ProductionThis data sheet contains the design target or goal specifications for product development. Specificationsmay change in any manner without notice.This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changesat any time without notice, in order to improve design and supply the best possible product.© Copyright Philips Electronics North America Corporation 1998All rights reserved. Printed in U.S.A.print codeDate of release: 05-96。
SN74LV1T04 单电源电源反转CMOS逻辑级转换器说明书
NC A GND V CC Y12345ProductFolderSample &BuyTechnical Documents Tools &SoftwareSupport &CommunitySN74LV1T04SCLS738B –SEPTEMBER 2013–REVISED FEBRUARY 2014SN74LV1T04Single Power Supply Inverter Gate CMOS Logic Level Shifter1Features2Applications•Single-Supply Voltage Translator at •Industrial controllers 5.0/3.3/2.5/1.8V V CC•Telecom•Operating Range of 1.8V to 5.5V •Portable applications •Up Translation•Servers– 1.2V (1)to 1.8V at 1.8V V CC •PC and notebooks – 1.5V (1)to 2.5V at 2.5V V CC •Automotive– 1.8V (1)to 3.3V at 3.3V V CC 3Description– 3.3V to 5.0V at 5.0V V CC SN74LV1T04is a low voltage CMOS gate logic that •Down Translationoperates at a wider voltage range for industrial,– 3.3V to 1.8V at 1.8V V CC portable,telecom,and automotive applications.The – 3.3V to 2.5V at 2.5V V CC output level is referenced to the supply voltage and is able to support 1.8V/2.5V/3.3V/5V CMOS levels.– 5.0V to 3.3V at 3.3V V CCThe input is designed with a lower threshold circuit to •Logic Output is Referenced to V CC match 1.8V input logic at V CC =3.3V and can be used •Output Drivein 1.8V to 3.3V level up translation.In addition,the –8mA Output Drive at 5V 5V tolerant input pins enable down translation (e.g.–7mA Output Drive at 3.3V 3.3V to 2.5V output at V CC =2.5V).The wide V CC range of 1.8V to 5.5V allows generation of desired –3mA Output Drive at 1.8Voutput levels to connect to controllers or processors.•Characterized up to 50MHz at 3.3V V CC The SN74LV1T04is designed with current-drive •5V Tolerance on Input Pinscapability of 8mA to reduce line reflections,•–40°C to 125°C Operating Temperature Range overshoot,and undershoot caused by high-drive •Pb-Free Packages Available:SC-70(DCK)outputs.–2×2.1×0.65mm (Height 1.1mm)Device Information•Latch-Up Performance Exceeds 250mA ORDER NUMBER PACKAGE BODY SIZE Per JESD 17SN74LV1T04DBVR SOT-23(5)2,90mm x 1,60mm •ESD Performance Tested Per JESD 22SN74LV1T04DCKRSC70(5)2,00mm x 1,25mm–2000-V Human-Body Model (A114-B,Class II)DCK or DBV PACKAGE–200-V Machine Model (A115-A)(TOP VIEW)–1000-V Charged-Device Model (C101)•Supports Standard Logic Pinouts•CMOS Output B Compatible with AUP1G and LVC1G Families(1)Refer to the V IH /V IL and output drive for lower V CC condition.SN74LV1T04SCLS738B–SEPTEMBER2013–REVISED Table of Contents4.6Operating Characteristics (7)1Features (1)5Parameter Measurement Information (8)2Applications (1)5.1More Product Selection (8)3Description (1)6Device and Documentation Support (9)4Revision History (2)6.1Trademarks (9)4.1Typical Design Examples (5)6.2Electrostatic Discharge Caution (9)4.2Absolute Maximum Ratings (5)6.3Glossary (9)4.3Recommended Operating Conditions (6)7Mechanical,Packaging,and Orderable4.4Electrical Characteristics (6)Information (9)4.5Switching Characteristics (7)4Revision HistoryNOTE:Page numbers for previous revisions may differ from page numbers in the current version.Changes from Original(September2013)to Revision A Page •Updated V CC values for V IH parameter in the ELECTRICAL CHARACTERISTICS table (6)Changes from Revision A(September2013)to Revision B Page •Updated document formatting (1)2Submit Documentation Feedback Copyright©2013–2014,Texas Instruments IncorporatedProduct Folder Links:SN74LV1T04AY24SN74LV1T04SCLS738B –SEPTEMBER 2013–REVISED FEBRUARY 2014Function TableINPUTOUTPUT (Lower Level Input)(V CC CMOS)A Y H L LHSUPPLY V CC =3.3VAYV IH (min)=1.35V V OH (min)=2.9V V IL (max)=0.8VV OL (max)=0.2V Figure 1.Logic Diagram (NAND Gate)Figure 2.Excellent Signal Integrity (1.8V to 3.3V at 3.3V V CC )Copyright ©2013–2014,Texas Instruments Incorporated Submit Documentation Feedback3Product Folder Links:SN74LV1T04SN74LV1T04SCLS738B–SEPTEMBER2013–REVISED Figure3.Excellent Signal Integrity(3.3V to3.3V at3.3V V CC)Figure4.Excellent Signal Integrity(3.3V to1.8V at1.8V V CC)4Submit Documentation Feedback Copyright©2013–2014,Texas Instruments IncorporatedProduct Folder Links:SN74LV1T04VIH minmin= 0.8V= 2.4Vmax= 0.4VVIH= 2.0VVIL= 0.8VVIH= 0.99VVIL= 0.55V5.0V3.3VSystemVcc = 5.0VLV1Txx Logic 5.0VSystemVcc = 1.8V5.0V, 3.3V2.5V, 1.8V1.5V, 1.2VSystemLV1Txx Logic 1.8VSystemSN74LV1T04 SCLS738B–SEPTEMBER2013–REVISED FEBRUARY2014 4.1Typical Design ExamplesFigure5.Switching Thresholds for1.8-V to3.3-V Translation4.2Absolute Maximum Ratings(1)over operating free-air temperature range(unless otherwise noted)MIN MAX UNIT V CC Supply voltage range–0.57.0VV I Input voltage range(2)–0.57.0V Voltage range applied to any output in the high-impedance or power-off state(2)–0.5 4.6VV OVoltage range applied to any output in the high or low state(2)–0.5V CC+0.5VI IK Input clamp current V I<0–20mAI OK Output clamp current V O<0or V O>V CC±20mAI O Continuous output current±25mAContinuous current through VCC or GND±50mADBV package206θJA Package thermal impedance(3)DCK package252°C/W T stg Storage temperature range–65150°C (1)Stresses beyond those listed under"absolute maximum ratings"may cause permanent damage to the device.These are stress ratingsonly,and functional operation of the device at these or any other conditions beyond those indicated under"recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3)The package thermal impedance is calculated in accordance with JESD51-7.Copyright©2013–2014,Texas Instruments Incorporated Submit Documentation Feedback5Product Folder Links:SN74LV1T04SN74LV1T04SCLS738B–SEPTEMBER2013–REVISED 4.3Recommended Operating Conditions(1)over operating free-air temperature range(unless otherwise noted)MIN MAX UNITV CC Supply voltage 1.6 5.5VV I Input voltage0 5.5VV O Output voltage0V CC VV CC=1.8V–3V CC=2.5V–5I OH High-level output current mAV CC=3.3V–7V CC=5.0V–8V CC=1.8V3V CC=2.5V5I OL Low-level output current mAV CC=3.3V7V CC=5.0V8V CC=1.8V20Δt/ΔInput transition rise or fall rate V CC=3.3V or2.5V20ns/VvV CC=5.0V20T A Operating free-air temperature–40125°C (1)All unused inputs of the device must be held at V CC or GND to ensure proper device operation.Refer to the TI application report,Implications of Slow or Floating CMOS Inputs,literature number SCBA004.4.4Electrical Characteristicsover recommended operating free-air temperature range(unless otherwise noted)T A=25°C T A=–40°C to125°C PARAMETER TEST CONDITIONS V CC UNITMIN TYP MAX MIN MAXV CC=1.65V to1.8V0.94 1.0V CC=2.0V 1.02 1.03V CC=2.25V to2.5V 1.135 1.18V CC=2.75V 1.21 1.23 High-level inputV IH V voltage V=3V to3.3V 1.35 1.37CCV CC=3.6V 1.47 1.48V CC=4.5V to5.0V 2.02 2.03V CC=5.5V 2.1 2.11V CC=1.65V to2.0V0.580.55V CC=2.25V to2.75V0.750.71 Low-level inputV IL V voltage V=3V to3.6V0.80.65CCV CC=4.5V to5.5V0.80.8I OH=–20µA 1.65V to5.5V V CC–0.1V CC–0.1V1.65V 1.28 1.21I OH=–2.0mA V1.8V 1.5 1.45I OH=–2.3mA222.3V VI OH=–3mA2 1.93I OH=–3mA 2.5V 2.25 2.15VV OHI OH=–3.0mA 2.78 2.73.0VI OH=–5.5mA 2.6 2.49VI OH=–5.5mA 3.3V 2.9 2.8I OH=–4mA 4.2 4.14.5VI OH=–8mA 4.1 3.95VI OH=–8mA 5.0V 4.6 4.56Submit Documentation Feedback Copyright©2013–2014,Texas Instruments IncorporatedProduct Folder Links:SN74LV1T04SN74LV1T04 SCLS738B–SEPTEMBER2013–REVISED FEBRUARY2014Electrical Characteristics(continued)over recommended operating free-air temperature range(unless otherwise noted)T A=25°C T A=–40°C to125°C PARAMETER TEST CONDITIONS V CC UNITMIN TYP MAX MIN MAXI OL=20µA 1.65V to5.5V0.10.1I OL=1.9mA 1.65V0.20.25I OH=2.3mA0.10.152.3VI OH=3mA0.150.2V OLI OL=3mA0.10.153.0VI OL=5.5mA0.20.252VI OL=4mA0.150.24.5VI OL=8mA0.30.35I I A input V I=0V or V CC0V,1.8V,2.5V,3.3V,5.5V0.12±1μA5.0V1103.3V110V I=0V or V CC,I CCμAI O=0;open on loading 2.5V1101.8V110One input at0.3V or3.4V,Other inputs at0or V CC, 5.5V 1.35 1.5mAI O=0ΔI CCOne input at0.3V or1.1VOther inputs at0or V CC, 1.8V1010μAI O=0C i V I=V CC or GND 3.3V210210pFC o V O=V CC or GND 3.3V 2.5 2.5pF4.5Switching Characteristicsover recommended operating free-air temperature range(unless otherwise noted)(see Figure7)T A=25°C T A=–65°C to125°CFROM TO FREQUENCYPARAMETER V CC C L UNIT (INPUT)(OUTPUT)(TYP)MIN TYP MAX MIN TYP MAX15pF45455.0V ns30pF 5.57.0 5.57.0DC to50MHz15pF 4.855 5.53.3V ns30pF5 5.5 5.5 6.5 t pd Any In Y15pF6 6.577.5DC to25MHz 2.5V ns30pF 6.57.57.58.515pF10.5111112DC to15MHz 1.8V ns30pF121312144.6Operating CharacteristicsT A=25°CPARAMETER TEST CONDITIONS V CC TYP UNIT1.8V±0.15V102.5V±0.2V10C pd Power dissipation capacitance f=1MHz and10MHz pF3.3V±0.3V105.5V±0.5V10Copyright©2013–2014,Texas Instruments Incorporated Submit Documentation Feedback7Product Folder Links:SN74LV1T04From Output Under TestLOAD CIRCUIT1 M ΩVOLTAGE WAVEFORMS PROPAGATION DELAY TIMESINVERTING AND NONINVERTING OUTPUTSV OHV OHV OLV OLV I0 VInputOutputOutputNOTES: A.C L includes probe and jig capacitance.B.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 Ω, slew rate ≥ 1 V/ns.C.The outputs are measured one at a time, with one transition per measurement.D.t PLH and t PHL are the same as t pd .V CC = 2.5 V ± 0.2 V V CC = 3.3 V ± 0.3 V C L V MI V MO5, 10, 15, 30 pFV I /2V CC /25, 10, 15, 30 pFV I /2V CC /2SN74LV1T04SCLS738B –SEPTEMBER 2013–REVISED FEBRUARY 20145Parameter Measurement InformationFigure 6.Load Circuit and Voltage Waveforms5.1More Product SelectionDEVICE PACKAGE DESCRIPTIONSN74LV1T00DCK,DBV 2-Input Positive-NAND Gate SN74LV1T02DCK,DBV 2-Input Positive-NOR Gate SN74LV1T04DCK,DBV Inverter GateSN74LV1T08DCK,DBV 2-Input Positive-AND GateSN74LV1T17DCK,DBV Single Buffer Gate with 3-state Output SN74LV1T14DCK,DBV Single Schmitt-Trigger Inverter Gate SN74LV1T32DCK,DBV 2-Input Positive-OR GateSN74LV1T50DCK,DBV Single Buffer Gate with 3-state Output SN74LV1T86DCK,DBV Single 2-Input Exclusive-Or Gate SN74LV1T125DCK,DBV Single Buffer Gate with 3-state Output SN74LV1T126DCK,DBV Single Buffer Gate with 3-state OutputSN74LV4T125RGY,PWQuadruple Bus Buffer Gate With 3-State Outputs8Submit Documentation FeedbackCopyright ©2013–2014,Texas Instruments IncorporatedProduct Folder Links:SN74LV1T04SN74LV1T04 SCLS738B–SEPTEMBER2013–REVISED FEBRUARY20146Device and Documentation Support6.1TrademarksAll trademarks are the property of their respective owners.6.2Electrostatic Discharge CautionThese devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.6.3GlossarySLYZ022—TI Glossary.This glossary lists and explains terms,acronyms and definitions.7Mechanical,Packaging,and Orderable InformationThe following packaging information and addendum reflect the most current data available for the designated devices.This data is subject to change without notice and revision of this document.Copyright©2013–2014,Texas Instruments Incorporated Submit Documentation Feedback9Product Folder Links:SN74LV1T04PACKAGE OPTION ADDENDUM4-Apr-2019Addendum-Page 1PACKAGING INFORMATION(1)The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.(2)RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.(3)MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.(4)There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.(5)Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.(6)Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andPACKAGE OPTION ADDENDUM 4-Apr-2019Addendum-Page 2continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.TAPE AND REELINFORMATION *All dimensionsare nominal Device Package Type Package DrawingPinsSPQ Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant SN74LV1T04DBVR SOT-23DBV 53000180.08.4 3.23 3.17 1.37 4.08.0Q3SN74LV1T04DBVR SOT-23DBV 53000178.09.2 3.3 3.23 1.55 4.08.0Q3SN74LV1T04DBVR SOT-23DBV 53000178.09.0 3.3 3.2 1.4 4.08.0Q3SN74LV1T04DBVRG4SOT-23DBV 53000178.09.2 3.3 3.23 1.55 4.08.0Q3SN74LV1T04DCKR SC70DCK 53000178.09.0 2.4 2.5 1.2 4.08.0Q3SN74LV1T04DCKR SC70DCK 53000180.08.4 2.47 2.3 1.25 4.08.0Q3SN74LV1T04DCKR SC70DCK 53000178.09.2 2.4 2.4 1.22 4.08.0Q3SN74LV1T04DCKRG4SC70DCK 53000178.09.2 2.4 2.4 1.22 15-Dec-2018*All dimensionsare nominal DevicePackage Type Package Drawing Pins SPQ Length (mm)Width (mm)Height (mm)SN74LV1T04DBVRSOT-23DBV 53000202.0201.028.0SN74LV1T04DBVRSOT-23DBV 53000180.0180.018.0SN74LV1T04DBVRSOT-23DBV 53000180.0180.018.0SN74LV1T04DBVRG4SOT-23DBV 53000180.0180.018.0SN74LV1T04DCKRSC70DCK 53000180.0180.018.0SN74LV1T04DCKRSC70DCK 53000202.0201.028.0SN74LV1T04DCKRSC70DCK 53000180.0180.018.0SN74LV1T04DCKRG4SC70DCK 53000180.0180.018.0 15-Dec-2018PACKAGE OUTLINESOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTORNOTES:1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.2. This drawing is subject to change without notice.3. Refernce JEDEC MO-178.4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall notexceed 0.15 mm per side.EXAMPLE BOARD LAYOUTSOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTORNOTES: (continued)5. Publication IPC-7351 may have alternate designs.6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.EXAMPLE STENCIL DESIGNSOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTORNOTES: (continued)7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.8. Board assembly site may have different recommendations for stencil design.IMPORTANT NOTICE AND DISCLAIMERTI PROVIDES TECHNICAL AND RELIABILITY DATA(INCLUDING DATASHEETS),DESIGN RESOURCES(INCLUDING REFERENCE DESIGNS),APPLICATION OR OTHER DESIGN ADVICE,WEB TOOLS,SAFETY INFORMATION,AND OTHER RESOURCES“AS IS”AND WITH ALL FAULTS,AND DISCLAIMS ALL WARRANTIES,EXPRESS AND IMPLIED,INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY,FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for skilled developers designing with TI products.You are solely responsible for(1)selecting the appropriate TI products for your application,(2)designing,validating and testing your application,and(3)ensuring your application meets applicable standards,and any other safety,security,or other requirements.These resources are subject to change without notice.TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource.Other reproduction and display of these resources is prohibited.No license is granted to any other TI intellectual property right or to any third party intellectual property right.TI disclaims responsibility for,and you will fully indemnify TI and its representatives against,any claims, damages,costs,losses,and liabilities arising out of your use of these resources.TI’s products are provided subject to TI’s Terms of Sale(/legal/termsofsale.html)or other applicable terms available either on or provided in conjunction with such TI products.TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.Mailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2019,Texas Instruments Incorporated。
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74LVT162245 • 74LVTH162245
Absolute Maximum Ratings(Note 3)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 4) VI GND VO GND VO ! VCC VO ! VCC Output at HIGH State Output at LOW State V mA mA mA mA mA
(Top Thru View)
2
74LVT162245 • 74LVTH162245
Functional Description
The LVT162245 and LVTH162245 contain sixteen noninverting bidirectional buffers with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation.
Inputs OE2 L L H T/R2 L H X Outputs Bus B8–B15 Data to Bus A8–A15 Bus A8–A15 Data to Bus B8–B15 HIGH-Z State on A8–A15, B8–B15
H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance
FBGA Pin Assignments
1 A B C D E F G H J B0 B2 B4 B6 B8 B10 B12 B14 B15 2 NC B1 B3 B5 B7 B9 B11 B13 NC 3 T/R1 NC VCC GND GND GND VCC NC T/R2 4 OE1 NC VCC GND GND GND VCC NC OE2 5 NC A1 A3 A5 A7 A9 A11 A13 NC 6 A0 A2 A4 A6 A8 A10 A12 A14 A15
Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000V
s Also packaged in plastic Fine Pitch Ball Grid Array (FBGA)
Ordering Code:
Order Number 74LVT162245G (Note 1)(Note 2) 74LVT162245MEA (Note 2) 74LVT162245MTD (Note 2) 74LVTH162245G (Note 1)(Note 2) 74LVTH162245MEA 74LVTH162245MEX 74LVTH162245MTD 74LVTH162245MTX Package Number BGA54A (Preliminary) MS48A MTD48 BGA54A MS48A MS48A MTD48 MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TUBE] 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide [TAPE and REEL] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TUBE] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL]
74LVT162245 • 74LVTH162245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25: Series Resistors in A Port Outputs
General Description
The LVT162245 and LVTH162245 contains sixteen noninverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. Each byte has separate control inputs which can be shorted together for full 16-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state. The LVT162245 and LVTH162245 are designed with equivalent 25: series resistance in both the HIGH and LOW states on the A Port outputs. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. The LVTH162245 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These non-inverting transceivers are designed for low voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT162245 and LVTH162245 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation.
Note 1: Ordering code “G” indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Features
s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pullup resistors to hold unused inputs (74LVTH162245), also available without bushold feature (74LVT162245). s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s A Port outputs include equivalent series resistance of 25: making external termination resistors unnecessary and reducing overshoot and undershoot s A Port outputs source/sink r12 mA. B Port outputs source/sink 32 mA/64 mA s Functionally compatible with the 74 series 162245 s Latch-up performance exceeds 500 mA s ESD performance: