串行EEPROM AT24CXX芯片资料

合集下载

数据存储AT24Cxx及其应用

AT24CXX电气特性
AT24CXX电气特性
ቤተ መጻሕፍቲ ባይዱ 100KHz参数分析
• f=100KHz=0.1MHz • t=1/0.1us=5us(一个高电平持续的时间+一个低电平持续的时间) • scl的高低电平持续时间各为3us • scl为高电平时，sda数据线电平不能变化（否则就是开始信号或停止信号）；scl为低电平时，sda数据线电平才能变化（即此时给sda赋需要发送的值）。
I2C总线的信号类型
• 开始信号：SCL为高电平时，SDA由高电平向低电平跳变，开始传送数据。 • 结束信号：SCL为高电平时，SDA由低电平向高电平跳变，结束传送数据。
I2C总线的信号类型
• 位的传输 SDA 线上的数据必须在时钟的高电平周期保持稳定，数据线的高或低电平状态只有在SCL 线的时钟信号是低电平时才能改变。
SDA SDA
存储器
SCL
SCL
SDA SCL
SDA
SDA
SCL
SCL
A/D
LED
SCL
SCL
Vcc
I2C （I2C、 IIC ）总线概述
R1 R2
单片机键盘 D/A
SDA
SDA
SDA SDA
存储器
SCL
SCL
SDA SCL
SDA
SDA
SCL
SCL
A/D
LED
• 其中，I2C总线的SCL和SDA端口（开漏极，线与）在使用时必须连接上拉电阻。I2C总线的传输速率可以支持100khz和 400khz两种，对于100khz的速率一般采用10k欧姆的上拉电阻，对于400khz的速率一般采用2k欧姆的上拉电阻。

AT24cxx协议

AT24C02是由ATMEL公司提供的，IIC总线串行EEPROM(electronic eraser programmer read only memory)，其容量为2kbit（256B），工作电压在2.7v"5.5v 之间，生产工艺是CMOS。

一般数字芯片都在左下角和右上角为GND,VCC。

容量的计算方法:AT24Cxx :01"1024 容量= xx * 1kbit。

写入过程：AT24C系列EEPROM芯片的固定部分为1010，A2，A1，A0引脚接高低电平后得到确定的3位编码，形成7位编码即为该器件的地址码。

单片机进行写操作时，首先发送该器件的7位地址码和写方向位”0”(共8位，即一个字节),发送完后释放SDA线并在SCL线上产生第9个时钟信号。

被选中的存储器器件在确认是自己的地址后，在SDA线上产生一个应答信号作为响应，单片机收到应答后就可以传送数据了。

传送数据时，单片机首先发送一个字节的被写入存储器的首地址，收到存储器器件的应答后，单片机就逐个发送数据字节，但每发送一个字节后都要等待应答。

AT24C系列片内地址在接收到每一个数据字节地址后自动加1，在芯片的“一次装载字节数”限度内，只需输入首地址。

装载字节数超过芯片的“一次装载字节数”时，数据地址将“上卷”，前面的数据将被覆盖。

字节写:页写：读入过程:单片机先发送该器件的7位地址码和写方向位“0”（“伪写”），发送完后释放SDA线并在SCL线上产生第9个时钟信号。

被选中的存储器器件在确认是自己的地址后，在SDA线上产生一个应答信号作为回应。

然后，再发一个字节的要读出器件的存储区的首地址，收到应答后，单片机要重复一次起始信号并发出器件地址和读方向位（“1”），收到器件应答后就可以读出数据字节，每读出一个字节，单片机都要回复应答信号。

当最后一个字节数据读完后，单片机应返回以“非应答”（高电平），并发出终止信号以结束读出操作。

串行i2c总线e2prom at24cxxx的应用.

9.串行I2C总线E2PROM AT24CXXX的应用这一篇介绍I2C存储器的使用。

主要是介绍AT24CXX系列器件，它分为两类，主要是通过被存储容量地址来分的，一类是AT24C02－AT24C16，它的存储容量从256字节到2048字节。

另一类是AT24C32－AT24C1024，容量从4K－128K。

（理论上好像可以达到最高512K字节容量，但现在网上最高也就能看到AT24C1024也就是128K字节容量）原理：I2C总线是一种用于IC器件之间连接的二线制总线。

它通过SDA（串行数据线）及SCL（串行时钟线)两根线在连到总线上的器件之间传送信息，并根据地址识别每个器件：不管是单片机、存储器、LCD驱动器还是键盘接口。

I2C总线接口电路结构如图所示。

SDA和SCL均为双向I/O线，通过上拉电阻接正电源。

当总线空闲时，两根线都是高电平。

连接总线的器件的输出级必须是集电极或漏极开路，以具有线“与”功能。

I2C总线的数据传送速率在标准工作方式下为100kbit/s，在快速方式下，最高传送速率可达400kbit/s。

在I2C总线技术规范中，开始和结束信号（也称启动和停止信号）的定义如图所示。

当时钟线SCL为高电平时，数据线SDA由高电平跳变为低电平定义为“开始”信号；当SCL 线为高电平时，SDA线发生低电平到高电平的跳变为“结束”信号。

开始和结束信号都是由主器件产生。

在开始信号以后，总线即被认为处于忙状态；在结束信号以后的一段时间内，总线被认为是空闲的。

I2C总线的数据传送格式是：在I2C总线开始信号后，送出的第一个字节数据是用来选择从器件地址的，其中4－7位为器件码，如1010就是代表串行E2PROM器件。

1－3位为存储器的片选地址或存储器内的块地址码，如何区分？后面再做详细说明，第8位为方向位(R/W)。

方向位为“0”表示发送，即主器件把信息写到所选择的从器件；方向位为“1”表示主器件将从从器件读信息。

存储芯片24C02中文资料.doc

LTH 二线制串行EEPROM—AT24C01/02/04/08/16概述与特点♦AT24C01/02/04/08/16是低工作电压的1K/2K/4K/8K/16K位串行电可擦除只读存储器，内部组织为128/256/512/1024/2048个字节，每个字节8位，该芯片被广泛应用于低电压及低功耗的工商业领域。

主要特性♦工作电压：1.8V〜5 5V♦输入/输岀引脚兼容5V♦应用在内部结构：128x8(1K)# 256x8(2K), 512x8(4K)r 1024x8(8K), 2048x8(16K)♦二线串行接口♦输入引脚经施密特触发器滤波抑制噪声♦双向数据传输协议♦兼容400KHz (1. 8V, 2. 5V r 2. 7V, 3. 6V )♦支持硬件写保护♦高可靠性：读写次数:1,000,000次-数据保存:100年极限额定参数工作温度-55°C 〜+125°C 存储温度-65°C 〜+150°C 任何引脚的对地电压-1.0V 〜+7.0V站大工作电压 6.25V直流输出电流 5.0 mATSOT23-5LSCLGNDSDA引脚定义ETlrTIrT] VCC节主：如果外加条件超过“极限额定参数”的额定值，将会对芯片造成永久杵的破坏。

这些仪是外加条件的极限额定参数，本说明书屮止常工作条件卞的功能和忤能参数并不适用于这些极限条件或其它任何超过本说明书标明的止常工作条件外的情况。

长时间处于极限条件卜，将影响器件引脚名称引脚功能A0-A2廉件地址输入SDA半厅数据输入输出SCL串行时钟输入WP写保护VCC电源封装类型Y 译码引脚说明串行时钟值号引N (SCL ):在SCL 输入时钟信号的上升沿将数据洪入EEPROM 器件，井在时钟的下降沿将数据读出。

串行数据输入/输出引脚(SDA)： SDA 引脚可实现双向串行数据传输。

该引脚为开漏输出，可与其它多个开漏输出器件或开集电极器件线或连接。

AT24Cxx中文数据手册

AT24C01A/02/04/08A/16A提供1024/2048/4096/8192/16384个连续的可擦除的位，以及由每8位组成一个字节的可编程只读存储器（EEPROM），其分别提供128/256/512/1024/2048个字节。

该设备适用在许多低功耗和低电压操作的工业和商业应用中。

1引脚描述1.1串行时钟(SCL)SCL输入用于正向输出边缘时钟信号到每个EEPROM设备，以及每个设备输出的反向边缘时钟数据。

1.2串行数据(SDA)SDA引脚是用于串行数据双向传输。

该引脚为开漏输出，同时可以与其他开漏极或集电极开路器件进行线或。

1.3设备/页地址(A2,A1,A0)对于AT24C01A和AT24C02，A2、A1和A0引脚是配置器件的硬件地址输入。

一根总线上可以连接多达八个1K / 2K的设备（器件寻址部分详细讨论了器件寻址）。

AT24C04使用A2和A1引脚作为硬件地址输入，在一根总线上有4个4K 的设备可用来寻址。

A0引脚没有连接。

AT24C08A只使用A2引脚作为硬件地址输入，在一根总线上有2个8K 的设备可用来寻址。

A0和A1引脚没有连接。

AT24C16A不使用设备地址引脚，这限制了一根总线上只能挂一个设备。

A0、A1和A2引脚没有连接。

1.4写保护(WP)AT24C01A / 02 / 04 / 08A/ 16A有一个写保护引脚，提供硬件数据保护。

写保护引脚允许正常读/写操作时连接到GND。

当写保护引脚连接到VCC，写保护功能启用和操作如下表所示。

2设备操作2.1时钟和数据转换SDA引脚通常情况下拉高。

SDA引脚上的数据只能在SCL低时间段内更改，而启动条件或停止条件在SCL为高时进行。

2.2启动条件在任何其他指令之前，SDA由高变为低，且SCL为高。

2.3停止条件SDA由低变为高，且SCL为高。

在读取序列之后，执行停止命令后EEPROM进入备用电源模式。

2.4应答所有地址和数据字都是从EEPROM串行发送和接收8位字节。

EEPROM---AT24Cxx应用介绍

EEPROM---AT24Cxx应⽤介绍结论：1、读写AT24CXX芯⽚，根据容量有多种⽅式：⼀、容量为AT24C01~AT24C16，⾸先发送设备地址（8位地址），再发送数据地址（8位地址），再发送或者接受数据。

⼆、AT24C32/AT24C64~AT24C512，⾸先发送设备地址（8位地址），再发送⾼位数据地址，再发送地位数据地址，再发送或者接受数据。

三、容量AT24C1024的芯⽚,是把容量⼀和容量⼆的⽅法结合，设备地址中要⽤⼀位作为数据地址位，存储地址长度是17位。

2、它的设备地址根据容量不同有区别： 1）、AT24C01~AT24C16：这⼀类⼜分为两类，分别为AT24C01/AT24C02和AT24C04~AT24C16;他们的设备地址为⾼7位，低1位⽤来作为读写标⽰位，1为读，0为写。

*1*、AT24C01/AT24C02。

AT24C01/AT24C02的A0、A1、A2引脚作为7位设备地址的低三位，⾼4为固定为1010B，低三位A0、A1、A2确定了AT24CXX的设备地址，所以⼀根I2C线上最⼤可以接8个AT24CXX，地址为1010000B~1010111B。

*2*、AT24C04~AT24C16的 A0、A1、A2只使⽤⼀部分，不⽤的悬空或者接地（数据⼿册中写的是悬空不接）。

举例：AT24C04只⽤A2、A1引脚作为设备地址，另外⼀位A0不⽤悬空，发送地址中对应的这位（A0）⽤来写⼊页寻址的页⾯号,⼀根I2C线上最⼤可以接4个，地址为101000xB~101011xB 2）、AT24C32/AT24C64:和AT24C01/AT24C02⼀样，区别是，发送数据地址变成16位。

注意事项：对AT24C32来说，WP置⾼，则只有四分之⼀受保护，即0x0C00－0x0FFF。

也就是说保护区为1KBytes。

对于低地址的四分之三，则不保护。

所以，如果数据较多时，可以有选择地存储。

AT24C1024介绍

AT24C1024介绍AT24C10242 线串⾏EEPROM特性低电压操作：2.7（Vcc=2.7V to 5.5V）内部组织：131,072*8 位=1M2 线串⾏接⼝施密特触发器，噪声抑制滤波输⼊双向数据传输协议时钟速率：400kHz(2.7V)和1MHz(5V) 硬件写保护引脚和软件数据保护256 字节页写模式(允许部分页⾯写⼊)随机和顺序读写模式⾃定义写周期(5ms)⾼可靠性：耐久⼒：写周期/页100,000 次数据保留：40 年8 引脚PDIP，8 引脚有铅SOIC 封装，8 引脚⽆铅阵列和8 引脚球状dBGA 封装描述AT24C1024 提供1,048,567 位的串⾏可电擦除和可编程只读存储器（EEPROM），它的每8 位组成⼀个字节，共131,072 个字节。

该设备的级联功能允许多达2 个设备共亨同⼀条2- 线总线。

该设备适合⽤于许多⼯业和商业，应⽤必要的低功耗和低电压的操作。

该器件可提供节省空间的8 引脚PDIP，8 引脚有铅SOIC 封装，8 引脚⽆铅阵列和8 引脚球状dBGA 封装。

另外，这⼀系列产品允许在2.7V（2.7V~5.5V）下⼯作。

绝对最⼤额定值：⼯作温度：-55~+125存储温度：-65~+150任何引脚的对地电压：-1.0V~+7.0V最⼤⼯作电压：6.25V 直流输出电流：5.0mA注意：强制⾼出“绝对最⼤额定值”可能导致设备的永久损坏。

设备的压⼒等级和功能操作只有在这些或超出本规范所标明的其他任何条件下是不允许的。

长时间⼯作在绝对最⼤额定值的条件下可能影响设备的可靠性。

引脚描述：串⾏时钟（SCL）：SCL 的输⼊是在时钟的上升沿数据进⼊每个EEPROM 设备和下降沿数据输出每个设备。

串⾏数据（SDA）：SDA 引脚是双向串⾏数据传输的。

这个引脚是漏极输出的，可以与其它的漏极开路或集电极开路的设备线或。

器件/ 页地址（A1 ）：A1 引脚是设备的输⼊地址，它能够通过导线与不兼容的设备AT24C128/256/512 连接。

AT24C

1Features•Low-voltage and Standard-voltage Operation –2.7 (V CC = 2.7V to 5.5V)–1.8 (V CC = 1.8V to 5.5V)•Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K),1024 x 8 (8K) or 2048 x 8 (16K)•Two-wire Serial Interface•Schmitt Trigger, Filtered Inputs for Noise Suppression •Bidirectional Data Transfer Protocol•100 kHz (1.8V) and 400 kHz (2.7V, 5V) Compatibility •Write Protect Pin for Hardware Data Protection•8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes •Partial Page Writes Allowed•Self-timed Write Cycle (5 ms max)•High-reliability–Endurance: 1 Million Write Cycles –Data Retention: 100 Years •Automotive Devices Available•8-lead JEDEC PDIP , 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 5-lead SOT23, 8-lead TSSOP and 8-ball dBGA2 Packages•Die Sales: Wafer Form, Waffle Pack and Bumped WafersDescriptionThe AT24C01A/02/04/08A/16A provides 1024/2048/4096/8192/16384 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT24C01A/02/04/08A/16A is available in space-saving 8-lead PDIP ,8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 5-lead SOT23(AT24C01A/AT24C02/AT24C04), 8-lead TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions. Table 1. Pin ConfigurationPin Name Function A0 - A2Address Inputs SDA Serial Data SCL Serial Clock Input WP Write Protect NC No Connect GND Ground VCCPower Supply8-lead SOIC 8-lead PDIP8-lead Ultra Thin Mini-MAP(MLP 2x3)Bottom View 5-lead SOT238-ball dBGA2Bottom View 8-lead TSSOP2AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Figure 1. Block DiagramAbsolute Maximum RatingsOperating Temperature..................................–55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage Temperature.....................................–65°C to +150°C Voltage on Any Pinwith Respect to Ground....................................–1.0V to +7.0V Maximum Operating Voltage..........................................6.25V DC Output Current........................................................5.0 mA3AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Pin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the AT24C01A and the AT24C02. As many as eight 1K/2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section).The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a single bus system. The A0 pin is a no connect and can be connected to ground.The AT24C08A only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are no connects and can be connected to ground.The AT24C16A does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1 and A2 pins are no connects and can be connected to ground.WRITE PROTECT (WP): The AT24C01A/02/04/08A/16A has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal Read/Write operations when connected to ground (GND). When the Write Protect pin is connected to V CC , the write protection feature is enabled and operates as shown in Table 2.Table 2. Write ProtectMemory OrganizationAT24C01A, 1K SERIAL EEPROM: Internally organized with 16 pages of 8 bytes each,the 1K requires a 7-bit data word address for random word addressing.AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each,the 2K requires an 8-bit data word address for random word addressing.AT24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each,the 4K requires a 9-bit data word address for random word addressing.AT24C08A, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data word address for random word addressing. AT24C16A, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit data word address for random word addressing.WP Pin Status Part of the Array Protected24C01A 24C0224C0424C08A 24C16A At V CC Full (1K) ArrayFull (2K) ArrayFull (4K) ArrayFull (8K) ArrayFull (16K) ArrayAt GNDNormal Read/Write Operations4AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Note:1.This parameter is characterized and is not 100% tested.Note:1.V IL min and V IH max are reference only and are not tested.Table 3. Pin Capacitance (1)Applicable over recommended operating range from T A = 25°C, f = 1.0 MHz, V CC = +1.8VSymbol Test ConditionMax Units Conditions C I/O Input/Output Capacitance (SDA)8pF V I/O = 0V C IN Input Capacitance (A 0, A 1, A 2, SCL)6pFV IN = 0VTable 4. DC CharacteristicsApplicable over recommended operating range from: T AI = –40°C to +85°C, V CC = +1.8V to +5.5V, V CC =+1.8V to +5.5V (unless otherwise noted)Symbol Parameter Test ConditionMin TypMax Units V CC1Supply Voltage 1.8 5.5V V CC2Supply Voltage 2.7 5.5V V CC3Supply Voltage4.55.5V I CC Supply Current V CC = 5.0V READ at 100 kHz 0.4 1.0mA I CC Supply Current V CC = 5.0V WRITE at 100 kHz 2.0 3.0mA I SB1Standby Current V CC = 1.8V V IN = V CC or V SS 0.6 3.0µA I SB2Standby Current V CC = 2.5V V IN = V CC or V SS 1.4 4.0µA I SB3Standby Current V CC = 2.7V V IN = V CC or V SS 1.6 4.0µA I SB4Standby Current V CC = 5.0V V IN = V CC or V SS 8.018.0µA I LI Input Leakage Current V IN = V CC or V SS 0.10 3.0µA I LO Output Leakage Current V OUT = V CC or V SS0.05 3.0µA V IL Input Low Level (1)–0.6V CC x 0.3V V IH Input High Level (1)V CC x 0.7V CC + 0.5V V OL2Output Low Level V CC = 3.0V I OL = 2.1 mA 0.4V V OL1Output Low Level V CC = 1.8VI OL = 0.15 mA 0.2V5AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Note:1.This parameter is characterized.Table 5. AC CharacteristicsApplicable over recommended operating range from T AI = –40°C to +85°C, V CC = +1.8V to +5.5V, V CC = +2.7V to +5.5V,CL = 1 TTL Gate and 100pF (unless otherwise noted)Symbol Parameter1.8-volt2.7, 5.0-volt Units MinMax MinMax f SCL Clock Frequency, SCL 100400kHz t LOW Clock Pulse Width Low 4.7 1.2µs t HIGH Clock Pulse Width High 4.00.6µs t I Noise Suppression Time (1)10050ns t AA Clock Low to Data Out Valid 0.1 4.50.10.9µs t BUF Time the bus must be free before a new transmission can start (1) 4.7 1.2µs t HD.STA Start Hold Time 4.00.6µs t SU.STA Start Setup Time 4.70.6µs t HD.DAT Data In Hold Time 00µs t SU.DAT Data In Setup Time 200100ns t R Inputs Rise Time (1) 1.00.3µs t F Inputs Fall Time (1)300300ns t SU.STO Stop Setup Time 4.70.6µs t DH Data Out Hold Time 10050ns t WRWrite Cycle Time 55ms Endurance (1) 5.0V, 25°C, Byte Mode1M 1MWrite Cycles6AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-nal device. Data on the SDA pin may change only during SCL low time periods (see Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 5 on page 8).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 5 on page 8).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.STANDBY MODE: The AT24C01A/02/04/08A/16A features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps:1.Clock up to 9 cycles.2.Look for SDA high in each cycle while SCL is high.3.Create a start condition.7AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Bus TimingFigure 2. SCL: Serial Clock, SDA: Serial Data I/O ®Write Cycle TimingFigure 3. SCL: Serial Clock, SDA: Serial Data I/ONote:1.The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.Figure 4.Data Validity8AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Figure 5. Start and Stop DefinitionFigure 6.Output Acknowledge9AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Device AddressingThe 1K, 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 7).The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all the EEPROM devices.The next 3 bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM.These 3 bits must compare to their corresponding hard-wired input pins.The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corre-sponding hard-wired input pins. The A0 pin is no connect.The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect.The 16K does not use any device address bits but instead the 3 bits are used for mem-ory page addressing. These page addressing bits on the 4K, 8K and 16K devices should be considered the most significant bits of the data word address which follows.The A0, A1 and A2 pins are no connect.The eighth bit of the device address is the read/write operation select bit. A read opera-tion is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a standby state.Write OperationsBYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condi-tion. At this time the EEPROM enters an internally timed write cycle, t WR , to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 8 on page 11).PAGE WRITE: The 1K/2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and 16K devices are capable of 16-byte page writes.A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (1K/2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 9 on page 11).The data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address,internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (1K/2K) or sixteen (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word address will “roll over” and previ-ous data will be overwritten.10AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue.ReadOperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations:current address read, random address read and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page.The address “roll over” during write is from the last byte of the current page to the first byte of the same page.Once the device address with the read/write select bit set to one is clocked in and acknowl-edged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condi-tion (see Figure 10 on page 12).RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition.The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a fol-lowing stop condition (see Figure 11 on page 12).SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-dom address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will con-tinue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (see Figure 12 on page 12).11AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Figure 7. Device AddressFigure 8. Byte WriteFigure 9. Page Write(* = DON’T CARE bit for 1K)12AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Figure 10. Current Address ReadFigure 11. Random Read(* = DON’T CARE bit for 1K)Figure 12.Sequential Read13AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Notes:1.This device is not recommended for new design. Please refer to AT24C01B datasheet. For2.7V devices used in the 4.5V to5.5V range, please refer to performance values in the AC and DC characteristics table.2.“U” designates Green Package + RoHS compliant.3.“H” designates Green Package + RoHS compliant, with NiPdAu Lead Finish.4.Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Pleasecontact Serial EEPROM Marketing.AT24C01A Ordering Information (1)Ordering CodePackage Operation RangeAT24C01A-10PU-2.7(2)AT24C01A-10PU-1.8(2)AT24C01A-10SU-2.7(2)AT24C01A-10SU-1.8(2)AT24C01A-10TU-2.7(2)AT24C01A-10TU-1.8(2)AT24C01A-10TSU-1.8(2)AT24C01AU3-10UU-1.8(2)AT24C01AY1-10YU-1.8(2) (Not recommended for new design)AT24C01AY6-10YH-1.8(3)8P38P38S18S18A28A25TS18U318Y18Y6Lead-free/Halogen-free/Industrial Temperature (–40°C to 85°C)AT24C01A-W1.8-11(4)Die SaleIndustrial Temperature (–40°C to 85°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8A28-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)8Y68-lead, 2.00 x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP , Dual No Lead Package (DFN), (MLP 2x3 mm)5TS15-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)8U3-18-ball, die Ball Grid Away Package (dBGA2)Options–2.7Low-voltage (2.7V to 5.5V)–1.8Low-voltage (1.8V to 5.5V)14AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Notes:1.This device is not recommended for new design. Please refer to AT24C02B datasheet. For2.7V devices used in the 4.5V to5.5V range, please refer to performance values in the AC and DC characteristics table.2.“U” designates Green Package + RoHS compliant.3.Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please contactSerial EEPROM Marketing.AT24C02 Ordering Information (1)Ordering Code Package Operation RangeAT24C02-10PU-2.7(2)AT24C02-10PU-1.8(2)AT24C02N-10SU-2.7(2)AT24C02N-10SU-1.8(2)AT24C02-10TU-2.7(2)AT24C02-10TU-1.8(2)AT24C02Y1-10YU-1.8(2)AT24C02-10TSU-1.8(2)AT24C02U3-10UU-1.8(2)8P38P38S18S18A28A28Y15TS18U3-1Lead-free/Halogen-free/Industrial Temperature (–40°C to 85°C)AT24C02-W2.7-11(3)Die SaleIndustrial Temperature (–40°C to 85°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8A28-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)5TS15-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)8U3-18-ball, die Ball Grid Away Package (dBGA2)Options–2.7Low-voltage (2.7V to 5.5V)–1.8Low-voltage (1.8V to 5.5V)15AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Notes:1.For2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.2.“U” designates Green Package + RoHS compliant.3.“H” designates Green Package + RoHS compliant, with NiPdAu Lead Finish.4.Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing.AT24C04 Ordering Information (1)Ordering CodePackage Operation RangeAT24C04-10PU-2.7(2)AT24C04-10PU-1.8(2)AT24C04N-10SU-2.7(2)AT24C04N-10SU-1.8(2)AT24C04-10TU-2.7(2)AT24C04-10TU-1.8(2)AT24C04Y1-10YU-1.8(2) (Not recommended for new design)AT24C04Y6-10YH-1.8(3)AT24C04-10TSU-1.8(2)AT24C04U3-10UU-1.8(2)8P38P38S18S18A28A28Y18Y65TS18U3-1Lead-free/Halogen-free/Industrial Temperature (–40°C to 85°C)AT24C04-W1.8-11(4)Die SaleIndustrial Temperature (–40°C to 85°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8A28-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)8Y68-lead, 2.00 x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP , Dual No Lead Package (DFN), (MLP 2x3 mm)5TS15-lead, 2.90 mm x 1.60 mm Body, Plastic Thin Shrink Small Outline Package (SOT23)8U3-18-ball, die Ball Grid Away Package (dBGA2)Options–2.7Low-voltage (2.7V to 5.5V)–1.8Low-voltage (1.8V to 5.5V)16AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Notes:1.For2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.2.“U” designates Green Package + RoHS compliant.3.“H” designates Green Package + RoHS compliant, with NiPdAu Lead Finish.4.Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing.AT24C08A Ordering Information (1)Ordering CodePackage Operation RangeAT24C08A-10PU-2.7(2)AT24C08A-10PU-1.8(2)AT24C08AN-10SU-2.7(2)AT24C08AN-10SU-1.8(2)AT24C08A-10TU-2.7(2)AT24C08A-10TU-1.8(2)AT24C08AY1-10YU-1.8(2) (Not recommended for new design)AT24C08AY6-10YH-1.8(3)AT24C08AU2-10UU-1.8(28P38P38S18S18A28A28Y18Y68U2-1Lead-free/Halogen-free/Industrial Temperature (−40°C to 85°C)AT24C08A-W1.8-11(4)Die SaleIndustrial Temperature (–40°C to 85°C)Package Type8P38-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8A28-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)8Y68-lead, 2.00 x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP , Dual No Lead Package (DFN), (MLP 2x3 mm)8U2-18-ball, die Ball Grid Array Package (dBGA2)Options−2.7Low Voltage (2.7V to 5.5V)−1.8Low Voltage (1.8V to 5.5V)17AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Notes:1.This device is not recommended for new design. Please refer to AT24C16B datasheet. For2.7V devices used in the 4.5V to5.5V range, please refer to performance values in the AC and DC characteristics table.2.“U” designates Green Package + RoHS compliant.3.“H” designates Green Package + RoHS compliant, with NiPdAu Lead Finish.4.Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Pleasecontact Serial EEPROM Marketing.AT24C16A Ordering Information (1)Ordering CodePackage Operation RangeAT24C16A-10PU-2.7(2)AT24C16A-10PU-1.8(2)AT24C16AN-10SU-2.7(2)AT24C16AN-10SU-1.8(2)AT24C16A-10TU-2.7(2)AT24C16A-10TU-1.8(2)AT24C16AY1-10YU-1.8(2) (Not recommended for new design)AT24C16AY6-10YH-1.8(3)AT24C16AU2-10UU-1.8(2)8P38P38S18S18A28A28Y18Y68U2-1Lead-free/Halogen-free/Industrial Temperature (−40°C to 85°C)AT24C16A-W1.8-11(3)Die SaleIndustrial Temperature (−40°C to 85°C)Package Type8P38-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8A28-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)8Y68-lead, 2.00 x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP , Dual No Lead Package (DFN), (MLP 2x3 mm)8U2-18-ball, die Ball Grid Array Package (dBGA2)Options−2.7Low Voltage (2.7V to 5.5V)−1.8Low Voltage (1.8V to 5.5V)18AT24C01A/02/04/08A/16A0180Z–SEEPR–11/06Packaging Information8P3 – PDIP19AT24C01A/02/04/08A/16A0180Z–SEEPR–11/068S1 – JEDEC SOIC20AT24C01A/02/04/08A/16A0180Z–SEEPR–11/068A2 – TSSOP21AT24C01A/02/04/08A/16A0180Z–SEEPR–11/068Y1 – MAP22AT24C01A/02/04/08A/16A0180Z–SEEPR–11/068Y6 − Mini-MAP (MLP 2x3 mm)23AT24C01A/02/04/08A/16A0180Z–SEEPR–11/065TS1 – SOT2324AT24C01A/02/04/08A/16A0180Z–SEEPR–11/068U2 – dBGA225AT24C01A/02/04/08A/16A0180Z–SEEPR–11/068U3-1 – dBGA20180Z–SEEPR–11/06Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise,to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.Atmel CorporationAtmel Operations2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 487-2600Regional HeadquartersEuropeAtmel SarlRoute des Arsenaux 41Case Postale 80CH-1705 Fribourg SwitzerlandTel: (41) 26-426-5555Fax: (41) 26-426-5500AsiaRoom 1219Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong KongTel: (852) 2721-9778Fax: (852) 2722-1369Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Memory2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314Microcontrollers2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314La Chantrerie BP 7060244306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18Fax: (33) 2-40-18-19-60ASIC/ASSP/Smart CardsZone Industrielle13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00Fax: (33) 4-42-53-60-011150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300Fax: 1(719) 540-1759Scottish Enterprise Technology Park Maxwell BuildingEast Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000Fax: (44) 1355-242-743RF/AutomotiveTheresienstrasse 2Postfach 353574025 Heilbronn, Germany Tel: (49) 71-31-67-0Fax: (49) 71-31-67-23401150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300Fax: 1(719) 540-1759Biometrics/Imaging/Hi-Rel MPU/High Speed Converters/RF DatacomAvenue de Rochepleine BP 12338521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00Fax: (33) 4-76-58-34-80Literature Requests/literature© 2006 Atmel Corporation. All rights reserved. Atmel ®, logo and combinations thereof, Everywhere You Are ® and others, are registered trade-marks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.。

(完整word版)AT24Cxx中文数据手册

AT24C01A/02/04/08A/16A提供1024/2048/4096/8192/16384个连续的可擦除的位,以及由每8位组成一个字节的可编程只读存储器（EEPROM）,其分别提供128/256/512/1024/2048个字节.该设备适用在许多低功耗和低电压操作的工业和商业应用中。

1引脚描述1.1串行时钟（SCL）SCL输入用于正向输出边缘时钟信号到每个EEPROM设备，以及每个设备输出的反向边缘时钟数据。

1.2串行数据(SDA)SDA引脚是用于串行数据双向传输。

该引脚为开漏输出，同时可以与其他开漏极或集电极开路器件进行线或.1.3设备/页地址（A2,A1，A0）对于AT24C01A和AT24C02,A2、A1和A0引脚是配置器件的硬件地址输入。

一根总线上可以连接多达八个1K / 2K的设备（器件寻址部分详细讨论了器件寻址）.AT24C04使用A2和A1引脚作为硬件地址输入，在一根总线上有4个4K 的设备可用来寻址。

A0引脚没有连接。

AT24C08A只使用A2引脚作为硬件地址输入,在一根总线上有2个8K 的设备可用来寻址.A0和A1引脚没有连接。

AT24C16A不使用设备地址引脚,这限制了一根总线上只能挂一个设备。

A0、A1和A2引脚没有连接。

1.4写保护(WP）AT24C01A / 02 / 04 / 08A/ 16A有一个写保护引脚，提供硬件数据保护。

写保护引脚允许正常读/写操作时连接到GND。

当写保护引脚连接到VCC,写保护功能启用和操作如下表所示.2设备操作2.1时钟和数据转换SDA引脚通常情况下拉高.SDA引脚上的数据只能在SCL低时间段内更改,而启动条件或停止条件在SCL 为高时进行。

2.2启动条件在任何其他指令之前，SDA由高变为低，且SCL为高。

2.3停止条件SDA由低变为高，且SCL为高。

在读取序列之后,执行停止命令后EEPROM进入备用电源模式.2.4应答所有地址和数据字都是从EEPROM串行发送和接收8位字节。

AT24C1024B 1024K EEPROM 产品说明书

Features•Low-voltage Operation–1.8V(V CC=1.8V to3.6V)–2.5V(V CC=2.5V to5.5V)•Internally Organized131,072x8•Two-wire Serial Interface•Schmitt Triggers,Filtered Inputs for Noise Suppression•Bidirectional Data Transfer Protocol•400kHz(1.8V)and1MHz(5V,2.5V)Clock Rate•Write Protect Pin for Hardware and Software Data Protection•256-byte Page Write Mode(Partial Page Writes Allowed)•Random and Sequential Read Modes•Self-timed Write Cycle(5ms Typical)•High Reliability–Endurance:1,000,000Write Cycles/Page–Data Retention:40Years•8-lead PDIP,8-lead JEDEC SOIC,8-lead EIAJ SOIC,8-lead TSSOP,8-lead Ultra Thin Small Array(SAP),and8-ball dBGA2Packages•Die Sales:Wafer Form,Tape and Reel and Bumped DieDescriptionThe AT24C1024B provides1,048,576bits of serial electrically erasable and program-mable read only memory(EEPROM)organized as131,072words of8bits each.The device’s cascadable feature allows up to four devices to share a common two-wire bus.The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential.The devices are available in space-saving8-lead PDIP,8-lead JEDEC SOIC,8-lead EIAJ SOIC,8-lead TSSOP, 8-ball dBGA2and8-lead Ultra Thin SAP packages.In addition,the entire family is available in1.8V(1.8V to3.6V)and2.5V(2.5V to5.5V)versions.8-lead PDIP12348765NCA1A2GNDVCCWPSCLSDA8-lead TSSOP12348765VCCWPSCLSDANCA1A2GND8-lead SOIC12348765NCA1A2GNDVCCWPSCLSDA8-lead Ultra-Thin SAPBottom ViewVCCWPSCLSDANCA1A2GND123487658-lead dBGA2Bottom ViewVCCWPSCLSDANCA1A2GND1234876525194F–SEEPR–1/08AT24C1024B1.Absolute Maximum Ratings**NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings”may cause permanent dam-age to the device.This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied.Exposure to absolute maximum rating conditions for extended periods may affect device reliability.35194F–SEEPR–1/08AT24C1024BFigure 1-1.Block Diagram2.Pin DescriptionSERIAL CLOCK (SCL):The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA):The SDA pin is bi-directional for serial data transfer.This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.DEVICE/ADDRESSES (A1/A2):The A1,A2pin is a device address input that can be hardwired or left not connected for hardware compatibility with other AT24Cxx devices.When the A1,A2pins are hardwired,as many as four 1024K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section).If the A1/A2pins are left floating,the A1/A2pin will be internally pulled down to GND if the capacitive coupling to the circuit board V CC plane is <3pF.If coupling is >3pF,Atmel recommends connecting the A1/A2pin to GND.WRITE PROTECT (WP):The write protect input,when connected to GND,allows normal write operations.When WP is connected high to V CC ,all write operations to the memory are inhibited.If the pin is left floating,the WP pin will be internally pulled down to GND if the capacitive cou-pling to the circuit board V CC plane is <3pF.If coupling is >3pF,Atmel recommends connecting the pin to GND.Switching WP to V CC prior to a write operation creates a software write-protectfunction.VCC GND WP SCL SDAA 2A 1A 045194F–SEEPR–1/08AT24C1024B3.Memory OrganizationAT24C1024B,1024K SERIAL EEPROM:The 1024K is internally organized as 512pages of 256bytes each.Random word addressing requires a 17-bit data word address.IL IH Table 3-1.Pin Capacitance (1)Table 3-2.DC CharacteristicsTable 3-3.AC Characteristics (Industrial Temperature)Applicable over recommended operating range from T AI =-40︒C to +85︒C,V CC =+1.8V to +3.6V,CL =100pF (unless oth-55194F–SEEPR–1/08AT24C1024B2.AC measurement conditions:R L (connects to V CC ):1.3k Ω(2.5V,5V),10k Ω(1.8V)Input pulse voltages:0.3V CC to 0.7V CC Input rise and fall times:≤50nsInput and output timing reference voltages:0.5V CC4.Device OperationCLOCK and DATA TRANSITIONS:The SDA pin is normally pulled high with an external device.Data on the SDA pin may change only during SCL low time periods (see Figure 4-4on page 7).Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION:A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 4-5on page 8).Table 3-3.AC Characteristics (Industrial Temperature)Applicable over recommended operating range from T AI =-40︒C to +85︒C,V CC =+1.8V to +3.6V,CL =100pF (unless oth-65194F–SEEPR–1/08AT24C1024BSTOP CONDITION:A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence,the Stop command will place the EEPROM in a standby power mode (see Fig-ure 4-5on page 8).ACKNOWLEDGE:All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.The EEPROM sends a zero during the ninth clock cycle to acknowl-edge that it has received each word.STANDBY MODE:The AT24C1024B features a low-power standby mode which is enabled:a)upon power-up and b)after the receipt of the stop bit and the completion of any internal operations.SOFTWARE RESET:After an interruption in protocol,power loss or system reset,any 2-wire part can be protocol reset by following these steps:(a)Create a start bit condition,(b)clock 9cycles,(c)create another start bit followed by stop bit condition as shown below.The device is ready for next communication after above steps have been completed.Figure 4-1.Software ResetFigure 4-2.Bus Timing (SCL:Serial Clock,SDA:Serial Data I/O ®)SCLSDASCLSDA INSDA OUT75194F–SEEPR–1/08AT24C1024BFigure 4-3.Write Cycle Timing (SCL:Serial Clock,SDA:Serial Data I/O)Note:1.The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.Figure 4-4.DataValiditySTOP CONDITIONSTART CONDITIONSCLSDASDASCLDAT A STABLEDAT A STABLEDAT A CHANGE85194F–SEEPR–1/08AT24C1024BFigure 4-5.Start and Stop DefinitionFigure 4-6.Output Acknowledge5.Device AddressingThe 1024K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 7-1on page 11).The device address word con-sists of a mandatory one,zero sequence for the first four most significant bits as shown.This is common to all two-wire EEPROM devices.The 1024K uses the two device address bit,A1,A2,to allow up to four devices on the same bus.These A1,A2bits must compare to the corresponding hardwired input pins.The A1,A2pin uses an internal proprietary circuit that biases it to a logic low condition if the pin is allowed to float.The seventh bit (P 0)of the device address is a memory page address bit.This memory page address bit is the most significant bit of the data word address that follows.The eighth bit of the device address is the read/write operation select bit.A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address,the EEPROM will output a zero.If a compare is not made,the device will return to astandby state.SDASCLSTART STOPSCLDAT A INDAT A OUTSTART ACKNOWLEDGE98195194F–SEEPR–1/08AT24C1024BDATA SECURITY:The AT24C1024B has a hardware data protection scheme that allows the user to write-protect the entire memory when the WP pin is at V CC .6.Write OperationsBYTE WRITE:To select a data word in the 1024K memory requires a 17-bit word address.The word address field consists of the P 0bit of the device address,then the most significant word address followed by the least significant word address (see Figure 7-2on page 11)A write operation requires the P 0bit and two 8-bit data word addresses following the device address word and acknowledgment.Upon receipt of this address,the EEPROM will again respond with a zero and then clock in the first 8-bit data word.Following receipt of the 8-bit data word,the EEPROM will output a zero.The addressing device,such as a microcontroller,then must terminate the write sequence with a stop condition.At this time the EEPROM enters an internally timed write cycle,T WR ,to the nonvolatile memory.All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 7-2on page 11).PAGE WRITE:The 1024K EEPROM is capable of 256-byte page writes.A page write is initiated the same way as a byte write,but the microcontroller does not send a stop condition after the first data word is clocked in.Instead,after the EEPROM acknowledges receipt of the first data word,the microcontroller can transmit up to 255more data words.The EEPROM will respond with a zero after each data word received.The microcontroller must ter-minate the page write sequence with a stop condition (see Figure 7-3on page 11).The data word address lower 8bits are internally incremented following the receipt of each data word.The higher data word address bits are not incremented,retaining the memory page row location.When the word address,internally generated,reaches the page boundary,the follow-ing byte is placed at the beginning of the same page.If more than 256data words are transmitted to the EEPROM,the data word address will “roll over”and previous data will be overwritten.The address “rollover”during write is from the last byte of the current page to the first byte of the same page.ACKNOWLEDGE POLLING:Once the internally timed write cycle has started and the EEPROM inputs are disabled,acknowledge polling can be initiated.This involves sending a start condition followed by the device address word.The read/write bit is representative of the operation desired.Only if the internal write cycle has completed will the EEPROM respond with a zero,allowing the read or write sequence to continue.7.Read OperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one.There are three read operations:current address read,random address read and sequential read.CURRENT ADDRESS READ:The internal data word address counter maintains the last address accessed during the last read or write operation,incremented by one.This address stays valid between operations as long as the chip power is maintained.The address “rollover”during read is from the last byte of the last memory page,to the first byte of the first page.105194F–SEEPR–1/08AT24C1024BOnce the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM,the current address data word is serially clocked out.The microcontroller does not respond with an input zero but does generate a following stop condition (see Figure 7-4on page 11).RANDOM READ:A random read requires a “dummy”byte write sequence to load in the data word address.Once the device address word and data word address are clocked in and acknowledged by the EEPROM,the microcontroller must generate another start condition.The microcontroller now initiates a current address read by sending a device address with the read/write select bit high.The EEPROM acknowledges the device address and serially clocks out the data word.The microcontroller does not respond with a zero but does generate a follow-ing stop condition (see Figure 7-5on page 12).SEQUENTIAL READ:Sequential reads are initiated by either a current address read or a ran-dom address read.After the microcontroller receives a data word,it responds with an acknowledge.As long as the EEPROM receives an acknowledge,it will continue to increment the data word address and serially clock out sequential data words.When the memory address limit is reached,the data word address will “roll over”and the sequential read will continue.The sequential read operation is terminated when the microcontroller does not respond with a zero,but does generate a following stop condition (see Figure 7-6on page 12).115194F–SEEPR–1/08AT24C1024BFigure 7-1.Device AddressFigure 7-2.Byte WriteFigure 7-3.Page WriteFigure 7-4.Current AddressReadSIGNIFICANTMOSTSIGNIFICANTLEAST125194F–SEEPR–1/08AT24C1024BFigure 7-5.Random ReadFigure 7-6.Sequential Read135194F–SEEPR–1/08AT24C1024BNotes: 1.“-B”denotes bulk2.“-T”denotes tape and reel.SOIC =4K per reel.TSSOP and dBGA2=5K per reel.SAP =3K per reel.EIAJ =2K per reel.3.Available in tape and reel and wafer form;order as SL788for inkless wafer form.Bumped die available upon request.Pleasecontact Serial Interface Marketing.Ordering Information145194F–SEEPR–1/08AT24C1024B8.Part marking scheme8.18-SOIC(1.8V)8.28-SOIC(2.5V)TOP MARKSeal YearY = SEAL YEARWW = SEAL WEEK | Seal Week6: 2006 0: 2010 02 = Week 2 | | |7: 2007 1: 2011 04 = Week 4 |---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: : A T M L H Y W W 9: 2009 3: 2013:: : :::: :: |---|---|---|---|---|---|---|---| 50 = Week 50 2 G B 152 = Week 52|---|---|---|---|---|---|---|---| * Lot NumberLot Number to Use ALL Characters in Marking |---|---|---|---|---|---|---|---| |BOTTOM MARKPin 1 Indicator (Dot)No Bottom MarkTOP MARKSeal YearY = SEAL YEARWW = SEAL WEEK | Seal Week6: 2006 0: 2010 02 = Week 2 | | |7: 2007 1: 2011 04 = Week 4 |---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: : A T M L H Y W W 9: 2009 3: 2013:: : :::: :: |---|---|---|---|---|---|---|---| 50 = Week 50 2 G B 252 = Week 52|---|---|---|---|---|---|---|---| * Lot NumberLot Number to Use ALL Characters in Marking |---|---|---|---|---|---|---|---| |BOTTOM MARKPin 1 Indicator (Dot)No Bottom Mark155194F–SEEPR–1/08AT24C1024B8.38-TSSOP(1.8V)8.48-TSSOP(2.5V)TOP MARKPin 1 Indicator (Dot)Y = SEAL YEAR WW = SEAL WEEK |6: 2006 0: 2010 02 = Week 2 |---|---|---|---| 7: 2007 1: 2011 04 = Week 4 * H Y W W 8: 2008 2: 2012 :: : :::: : |---|---|---|---|---| 9: 2009 3: 2013:: : :::: :: 2 G B 1 50 = Week 50 |---|---|---|---|---| 52 = Week 52BOTTOM MARK|---|---|---|---|---|---|---| P H|---|---|---|---|---|---|---| A A A A A A A |---|---|---|---|---|---|---| <- Pin 1 IndicatorTOP MARKPin 1 Indicator (Dot)Y = SEAL YEAR WW = SEAL WEEK |6: 2006 0: 2010 02 = Week 2 |---|---|---|---| 7: 2007 1: 2011 04 = Week 4 * H Y W W 8: 2008 2: 2012 :: : :::: : |---|---|---|---|---| 9: 2009 3: 2013:: : :::: :: 2 G B 2 50 = Week 50 |---|---|---|---|---| 52 = Week 52BOTTOM MARK|---|---|---|---|---|---|---| P H|---|---|---|---|---|---|---| A A A A A A A |---|---|---|---|---|---|---| <- Pin 1 Indicator165194F–SEEPR–1/08AT24C1024B8.58-PDIP(1.8V)8.68-PDIP(2.5V)8.78-Ultra Thin SAP (1.8V)TOP MARKSeal YearY = SEAL YEARWW = SEAL WEEK | Seal Week6: 2006 0: 2010 02 = Week 2 | | |7: 2007 1: 2011 04 = Week 4 |---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: : A T M L U Y W W 9: 2009 3: 2013:: : :::: :: |---|---|---|---|---|---|---|---| 50 = Week 50 2 G B 152 = Week 52|---|---|---|---|---|---|---|---| * Lot NumberLot Number to Use ALL Characters in Marking |---|---|---|---|---|---|---|---| |BOTTOM MARKPin 1 Indicator (Dot)No Bottom MarkTOP MARKSeal YearY = SEAL YEARWW = SEAL WEEK | Seal Week6: 2006 0: 2010 02 = Week 2 | | |7: 2007 1: 2011 04 = Week 4 |---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: : A T M L U Y W W 9: 2009 3: 2013:: : :::: :: |---|---|---|---|---|---|---|---| 50 = Week 50 2 G B 252 = Week 52|---|---|---|---|---|---|---|---| * Lot NumberLot Number to Use ALL Characters in Marking |---|---|---|---|---|---|---|---| |BOTTOM MARKPin 1 Indicator (Dot)No Bottom MarkTOP MARKSeal Year| Seal Week Y = SEAL YEARWW = SEAL WEEK | | |6: 2006 0: 2010 02 = Week 2 |---|---|---|---|---|---|---|---| 7: 2007 1: 2011 04 = Week 4 A T M L H Y W W 8: 2008 2: 2012 :: : :::: : |---|---|---|---|---|---|---|---| 9: 2009 3: 2013:: : :::: :: 2 G B 150 = Week 50 |---|---|---|---|---|---|---|---| 52 = Week 52Lot Number|---|---|---|---|---|---|---|---| * |Pin 1 Indicator (Dot)175194F–SEEPR–1/08AT24C1024B8.88-Ultra Thin SAP (2.5V)8.9dBGA2TOP MARKSeal Year| Seal Week Y = SEAL YEARWW = SEAL WEEK | | |6: 2006 0: 2010 02 = Week 2 |---|---|---|---|---|---|---|---| 7: 2007 1: 2011 04 = Week 4 A T M L H Y W W 8: 2008 2: 2012 :: : :::: : |---|---|---|---|---|---|---|---| 9: 2009 3: 2013:: : :::: :: 2 G B 250 = Week 50 |---|---|---|---|---|---|---|---| 52 = Week 52Lot Number|---|---|---|---|---|---|---|---| * |Pin 1 Indicator (Dot)TOP MARKLINE 1-------> 2GBU LINE 2-------> PYMTC|<-- Pin 1 This CornerP = COUNTRY OF ORIGINY = ONE DIGIT YEAR CODE 4: 2004 7: 20075: 2005 8: 20086: 2006 9: 2009M = SEAL MONTH (USE ALPHA DESIGNATOR A-L) A = JANUARY B = FEBRUARY " " """"""" J = OCTOBER K = NOVEMBER L = DECEMBERTC = TRACE CODE (ATMEL LOT NUMBERS TO CORRESPONDWITH ATK TRACE CODE LOG BOOK)185194F–SEEPR–1/08AT24C1024B9.Packaging Information 8P3–PDIP195194F–SEEPR–1/08AT24C1024B8S1-JEDEC SOIC205194F–SEEPR–1/08AT24C1024B8S2–EIAJ SOICAT24C1024B 8A2-TSSOP2122AT24C1024B8U4-1-dBGA2AT24C1024B 8Y7–SAP2324AT24C1024B10.Revision HistoryHeadquarters InternationalAtmel Corporation 2325Orchard Parkway San Jose,CA95131 USATel:1(408)441-0311 Fax:1(408)487-2600Atmel AsiaRoom1219Chinachem Golden Plaza77Mody Road TsimshatsuiEast KowloonHong KongTel:(852)2721-9778Fax:(852)2722-1369Atmel EuropeLe Krebs8,Rue Jean-Pierre TimbaudBP30978054Saint-Quentin-en-Yvelines CedexFranceTel:(33)1-30-60-70-00Fax:(33)1-30-60-71-11Atmel Japan9F,Tonetsu Shinkawa Bldg.1-24-8ShinkawaChuo-ku,Tokyo104-0033JapanTel:(81)3-3523-3551Fax:(81)3-3523-7581Product ContactWeb SiteTechnical Support******************Sales Contact/contactsLiterature Requests/literatureDisclaimer:The information in this document is provided in connection with Atmel products.No license,express or implied,by estoppel or otherwise,to any intellectual property right is granted by this document or in connection with the sale of Atmel products.EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-TIONS OF SALE LOCATED ON ATMEL’S WEB SITE,ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS,IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING,BUT NOT LIMITED TO,THE IMPLIED WARRANTY OF MERCHANTABILITY,FITNESS FOR A PARTICULAR PURPOSE,OR NON-INFRINGEMENT.IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,INDIRECT,CONSEQUENTIAL,PUNITIVE,SPECIAL OR INCIDEN-TAL DAMAGES(INCLUDING,WITHOUT LIMITATION,DAMAGES FOR LOSS OF PROFITS,BUSINESS INTERRUPTION,OR LOSS OF INFORMATION)ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT,EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice.Atmel does not make any commitment to update the information contained herein.Unless specifically provided otherwise,Atmel products are not suitable for,and shall not be used in,automotive applications.Atmel’s products are not intended,authorized,or warranted for use as components in applications intended to support or sustain life.©2008Atmel Corporation.All rights reserved.Atmel®,logo and combinations thereof,are registered trademarks or trademarks of Atmel Cor-poration or its subsidiaries.Other terms and product names may be trademarks of others.。

IIC接口EEPROM的控制

I 2C 接口EEPROM 的控制AT24Cxx 是Atmel 公司生产的串行电可擦的可编程存储器EEPROM ，它采用8引脚双排直插式封装，具有结构紧凑、存储容量大等特点，可以在I 2C 总线上并接4片该芯片，特别适用于具有大容量数据存储要求的数据采集系统。

本设计以AT24C512为例，介绍该芯片的工作原理和与单片机的软硬件接口。

一．AT24C512简要介绍AT24C512是Atmel 公司生产的64KByte 串行电可擦的可编程存储器，内部有512页，每一页为128Byte ，任一单元的地址为16位，地址范围为0000~0FFFFH 。

它采用8引脚封装，具有结构紧凑、存储容量大等特点，可以在I 2C 总线上并接4片芯片，特别适用于具有大容量数据存储要求的数据采集系统。

因此在测控系统中被大量采用。

1、AT24C512的主要特性具有如下3种工作电压:5.0 (VCC = 4.5V to 5.5V)。

2.7 (VCC = 2.7V to 5.5V)。

1.8 (VCC = 1.8V to 3.6V)。

存储容量为65,536Byte 即512Kbit( 64Kx 8bit)。

与100kHz 、400kHz 、1MHz I 2C 总线兼容。

ESD 保护电压>4kV 。

数据可保存40年。

CMOS 低功耗技术，最大写入电流为3mA 。

采用施密特触发，可抑制输入噪声。

符合双向数据传送协议。

具有硬件写保护和软件数据保护功能。

具有128Byte 页写入缓存器。

自动定时的写周期。

具有8引脚DIP 及20引脚SOIC 封装等多种。

2、管脚说明AT24C512的管脚如图所示各引脚的功能如下：A0、A1：地址选择输入端。

在串行总线结构中，如需连接4个AT24C512芯片，则可用A0、A1来区分各芯片。

A0、A1悬空时为0。

SDA ：双向串行数据输入输出口。

用于存储器与单片机之间的数据交换。

SCL ：串行时钟输入。

24CXX

3： VCC <2.5V，频率为 400 kHz。
4： MSOP 型封装 24XX128 和 24XX256 器件的引脚 A0 和 A1 没有连接。
5： P = 8-PDIP，SN = 8-SOIC （150 mil JEDEC），ST = 8-TSSOP，OT = 5 或 6-SOT23，MC = 2x3mm DFN， MS = 8-MSOP， SM = 8-SOIC （200 mil EIAJ），MF = 5x6mm DFN， ST14 = 14-TSSOP。
1.8-5.5V 2.5-5.5V 1.8-5.5V
400 kHz (2)
400 kHz 1 MHz(3)
64 字节
整个阵列
A0, A1, A2(4)
I
P, SN, SM, ST, MS, MF,
I, E ST14
I
256 千位器件
24AA256
1.8-5.5V 400 kHz (2)
24LC256 24FC256
2005 Microchip Technology Inc.
DS21930A_CN 第 3 页
24AAXX/24LCXX/24FCXX
2.0 电气特性
绝对最大额定值 (†)
VCC.............................................................................................................................................................................6.5V 相对于 Vss 的所有输入和输出 ............................................................................................................ -0.6V 到 VCC +1.0V 存储温度 ................................................................................................................................................. -65°C 到 +150°C 环境温度（使用电源时）........................................................................................................................ -40°C 到 +125°C 所有引脚静电保护 ....................................................................................................................................................................≥ 4 kV

串行E~2PROM-AT24CXX的原理及应用

- 42 -●新特器件应用《国外电子元器件》1997 年第 8 期 1997 年 8 月串行 E 2P RO M A T24CXX 的原理及应用孔令成王华摘要 : 本文分析了美国爱特梅尔 (A TM EL ) 公司生产的最新二线式串行 CMO SE 2PROM 芯片 A T24C01/ 02/ 04/ 08/ 16 的内部结构、性能特点、读写时序 ,并说明了使用方法。

关键词 : E 2PROM 串行读写地址数据如图 1 所示 ,各管脚功能如表 1 所示 ,内部结1 、引言串行 E 2PROM 芯片 A T24C01/ 02/ 04/ 08/ 16 是美国爱特梅尔 (A TM EL ) 公司最新生产的二线式串行 IC 卡芯片 , 小巧 , 可靠性高 ,具有保护性能 ,速度快 ,安全稳定 ,因此在设计 IC 卡等领域中得到了广泛的应用。

2 、A T24CXX 性能特点A T24CXX 系列芯片主要有 A T24C01 ,A T24C02 , A T24C04 , A T24C08 , A T24C16 等型号 ,其区别主要是容量不同 ,分别为 1k , 2k , 4k , 8k 和 16k 比特。

其内部组合分别为128 ×8 位、256 ×8 位、512 ×8 位、1024 ×8 位和 2048 ×8 位 ,并允许部分页面写入功能。

并有多种工作电压可供不同用户选择。

它采用低功耗、高速度和高密度 CMO S 工艺 , 可擦写 10 万次以上 , 数据保存 100 年有效 , 为双线串行接口。

存储在芯片中的数据 , 可通过软件的方法利用各种加密算法进行处理 , 从而确保其安全性。

芯片引脚和外形封装形式表 1 管脚功能表管脚功能构框图如图 2 所示。

A T24CXX 中 8 脚封装有双列直插塑封和表面封装两种形式 , 14 引脚只有表面封装一种形式。

24LCXX eeprom

一功能介绍1、能页操作，每页可达128字节。

2、具有的功能地址线，允许8个器件挂在同一总线上。

高达4MBit的地址空间（64k x8=512bit | 512bit x 8 = 4Mbit)3、在512k范围内，可随机读和顺序读。

4、板级供电电压范围1.7V to 5.5V。

二引脚描述引脚名功能A0 芯片选择（用户可配置）A1 芯片选择（用户可配置）A2 芯片选择（用户可配置）NC 未连接VSS 地SDA 串行数据SCL 串行时钟WP 写保护输入VCC 电源2.0 A0，A1 AND A2 芯片地址输入⏹芯片地址引脚允许8个芯片挂在同一条总线上。

当引脚的逻辑电平与芯片内部相应的设备地址相同时，芯片使能。

⏹芯片引脚的输入使能时VCC 和VSS⏹在大多数的应用中，地址线是被硬件拉高和拉低的。

在那些引脚受microcontroller 和可编程器件控制的应用中，在访问该EEPROM芯片之前，EEPROM的引脚要先拉高或拉低。

2.1 Serial Data (SDA)⏹该双向引脚是用来传输数据和地址的。

该引脚是内部开漏，所以SDA引脚要接一个上拉电阻到VCC( 典型的是10kohm/100khz, 2kohm/400Khz,1Mhz).⏹在数据传输中，SDA只有在SCL线为低时才发生改变。

在SCL线为高时SDA发生改变则被认为是开始或停止。

2.2 Serial Clock (SCL)数据同步时钟2.3 Write-Protect(WP) 写保护⏹该引脚只能连接VCC 或者VSS。

⏹当连接VCC时，允许对芯片写操作，当连接VSS，对芯片写操作禁止。

该引脚对芯片读操作没有任何影响。

三功能描述⏹24XX512支持双向2线制总线和数据传输协议。

在总线数据发送数据的成为发送方，接收数据的为接收方。

⏹当24XX512为从设备时，串行时钟（SCL）由主设备产生，来控制总线的访问和产生开始和结束条件。

⏹主设备和从设备都可以作为接收方和发送方，但是只有主设备才能决定处于那种模式。

STM32驱动AT24CXX系列芯片

AT24Cxx系列EEPROM是由美国Mcrochip公司出品，1-512K位的支持I2C总线数据传送协议的串行CMOS E2PROM，可用电擦除，可编程自定时写周期（包括自动擦除时间不超过10ms，典型时间为5ms）的。

串行E2PROM一般具有两种写入方式，一种是字节写入方式，还有另一种页写入方式。

允许在一个写周期内同时对1个字节到一页的若干字节的编程写入，1页的大小取决于芯片内页寄存器的大小。

其中，AT24C01具有8字节数据的页面写能力，AT24C02/04/08/16具有16字节数据的页面写能力，AT24C32/64具有32字节数据的页面写能力AT24CXX的驱动是基于IIC的,在基本的IIC上加入了一些通讯协议,具体如下1.随机写主器件发送起始命令和从器件地址信息(R/W 位置0)给从器件，主器件在收到从器件产生应答信号后，主器件发送 1 个8 位字节地址写入AT24C01/02/04/08/16 的地址指针，对于AT24C31/64/128/256 来说，所不同的是主器件发送两个8 位地址字写入AT24C32/64/128/256 的地址指针。

主器件在收到从器件的另一个应答信号后，再发送数据到被寻址的存储单元。

AT24Cxx 再次应答，并在主器件产生停止信号后开始内部数据的擦写，在内部擦写过程中，AT24Cxx 不再应答主器件的任何请求2.页写。

在页写模式下，AT24C01/02/04/08/16/32/64/128/256可一次写入8 /16/16/16/16/32/32/64/64 个字节数据。

页写操作的启动和字节写一样，不同的是在于传送了一字节数据后并不产生停止信号。

安特尔AT24C32D 32K Serial EEPROM数据手册说明书

AT24C32DI2C-Compatible (2-Wire) Serial EEPROM32-Kbit (4,096 x 8)DATASHEET Features●Low-voltage and Standard-voltage OperationV CC = 1.7V to 5.5V●Internally Organized as 4,096 x 8 (32K)●I2C-compatible (2-Wire) Serial Interface●Schmitt Trigger, Filtered Inputs for Noise Suppression●Bidirectional Data Transfer Protocol●400kHz (1.7V) and 1MHz (2.5V, 2.7V, 5.0V) Compatibility●Write Protect Pin for Hardware Protection●32-byte Page Write ModePartial Page Writes Allowed●Self-timed Write cycle (5ms Max)●High ReliabilityEndurance: 1,000,000 Write CyclesData Retention: 100 Years●Lead-free/Halogen-free devices Available●Green Package Options (Pb/Halide-free/RoHS Compliant)8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 8-pad XDFN, 5-leadSOT23, 5-ball WLCSP, and 8-ball VFBGA packages●Die Sale Options: Wafer Form, Waffle Pack, and Bumped Wafers DescriptionThe Atmel® AT24C32D provides 32,768 bits of Serial Electrically Erasable and Programmable Read-Only Memory (EEPROM) organized as 4,096 words of 8 bits each. The device’s cascading feature allows up to eight devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 8-pad XDFN, 5-lead SOT23, 5-ball WLCSP, and 8-ball VFBGA packages. In addition, this device operates from 1.7V to 5.5V.AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_12201621.Pin Configurations and PinoutsTable 1-1.Pin Configuration Note:When using the 5-lead SOT-23 or the 5-ball WLCSP , the software bits A2, A1, and A0 must be set to Logic 0 to properly communicate with the device.2.Absolute Maximum Ratings*8-pad UDFN/XDFNV CC WP SCL SDAA 0A 1A 2GND123487658-ball VFBGABottom View8-lead SOIC8-lead TSSOPTop View12348765A 0A 1A 2GNDV CC WP SCL SDATop View Top ViewA 0A 1A 2GND V CC WP SCL SDA87651234SCL GND SDA123545-lead SOT23WPV CC* Note: Drawings are not to scale5-ball WLCSPBall Side View(1)A 0A 1A 2GNDV CC WP SCL SDA12348765(1)Operating Temperature . . . . . . . . . . .-55°C to +125°C Storage Temperature . . . . . . . . . . . . -65°C to + 150°C Voltage on any pinwith respect to ground . . . . . . . . . . . . . . .-1.0 V +7.0V Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V DC Output Current. . . . . . . . . . . . . . . . . . . . . . .5.0mA*Notice:Stresses beyond those listed under “AbsoluteMaximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions forextended periods may affect device reliability.3AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_1220163.Block Diagram4.Pin DescriptionsSerial Clock (SCL): The SCL input is used to positive-edge clock data into each EEPROM device and negative-edge clock data out of each device.Serial Data (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.Device Addresses (A 2, A 1, A 0): The A 2, A 1, and A 0 pins are device address inputs that are hard wired (directly to GND or to V CC ) for compatibility with other Atmel AT24C devices. When the pins are hard wired, as many as eight 32K devices may be addressed on a single bus system. (Device addressing is discussed in detail in Section 7., “Device Addressing” on page 9). A device is selected when a corresponding hardware and software match is true. If these pins are left floating, the A 2, A 1, and A 0 pins will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends using 10k Ω or less.Write Protect (WP): The Write Protect input, when connected to GND, allows normal write operations. When WP is connected directly to V CC , all Write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND; however, due to capacitive coupling that may appear during customerapplications, Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using 10k Ω or less.Table 4-1.Write ProtectV CC GND WP SCL SDAA 2A 1A 0AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_12201645.Memory OrganizationAT24C32D, 32K Serial EEPROM : The 32K is internally organized as 128 pages of 32-bytes each. Random word addressing requires a 12-bit data word address.5.1Pin CapacitanceTable 5-1.Pin Capacitance (1)Note:1.This parameter is characterized and is not 100% tested.5.2DC CharacteristicsTable 5-2.DC CharacteristicsNote:1.V IL min and V IH max are reference only and are not tested.Applicable over recommended operating range from: T A = 25°C, f = 1.0MHz, V CC = 5.5V.Applicable over recommended operating range from: T AI = -40°C to +85°C, V CC = 1.7V to 5.5V (unless otherwise noted).5AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_1220165.3AC CharacteristicsTable 5-3.AC Characteristics (Industrial Temperature)Notes:1.This parameter is ensured by characterization and is not 100% tested.2.AC measurement conditions:●R L (connects to V CC ): 1.3k Ω (2.5V, 5.5V), 10k Ω (1.7V)●Input pulse voltages: 0.3V CC to 0.7V CC ●Input rise and fall times: ≤ 50ns ●Input and output timing reference voltages: 0.5 x V CCApplicable over recommended operating range from: T AI = -40°C to +85°C, V CC = 1.7V to 5.5V, CL = 100pF (unless otherwise noted). Test conditions are listed in Note 2.AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_12201666.Device OperationClock and Data Transitions: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods. Data changes during SCL high periods will indicate a Start or Stop condition as defined below.Figure 6-1.Data ValidityStart Condition : A high-to-low transition of SDA with SCL high is a Start condition that must precede every command.Stop Condition: A low-to-high transition of SDA with SCL high is a Stop condition. After a Read sequence, the Stop condition will place the EEPROM in a standby power mode.Figure 6-2.Start Condition and Stop Condition DefinitionSDASCLData ChangeData StableData StableSDASCLStart Condition Stop Condition7AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_122016Acknowledge: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The receiving device sends a zero during the ninth clock cycle to acknowledge that it has received each word. This zero response is referred to as an Acknowledge.Figure 6-3.Output AcknowledgeStandby Mode: AT24C32D features a low-power standby mode that is enabled upon power-up and after the receipt of the Stop condition and the completion of any internal operations.Software Reset : After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset by following these steps:1.Create a Start condition (if possible).2.Clock nine cycles.3.Create another Start condition followed by Stop condition as shown below.The device should be ready for the next communication after above steps have been completed. In the event that the device is still non-responsive or remains active on the SDA bus, a power cycle must be used to reset the device.Figure 6-4.Software ResetSCLData InData OutStart ConditionAcknowledge981SCLSDAAT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_1220168Figure 6-5.Bus TimingFigure 6-6.Write Cycle TimingNote: 1.The Write cycle time t WR is the time from a valid Stop condition of a Write sequence to the end ofthe internal Clear/Write cycle.SCLSDA InSDA OutSCLSDAStop ConditionStart Condition9AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_1220167.Device AddressingThe 32K EEPROM requires an 8-bit device address word following a Start condition to enable the chip for a Read or Write operation. The device address word consists of a mandatory ‘1010’ sequence for the first four most significant bits which is known as the device type identifier. These four bits are bit 7, bit 6, bit 5, and bit 4 as seen in Figure 7-1. This is common to all 2-wire Serial EEPROM devices.The next three bits are the A2, A1, and A0 hardware address select bits which allow as many as eight devices on the same bus. These bits must compare to their corresponding hard wired input pins, A 2, A 1, and A 0. The A 2, A 1, and A 0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.When utilizing the 5-ball WLCSP or the 5-lead SOT-23 packages, the A 2, A 1, and A 0 pins are not available. The A 2, A 1, and A 0 pins are internally pulled to ground and thus the A2, A1, and A0 device address bits must always be set to a Logic 0 to communicate with the device. This condition is depicted in Figure 7-1 below.The eighth bit of the device address is the Read/write operation select bit. A Read operation is initiated if this bit is a Logic 1, and a Write operation is initiated if this bit is a Logic 0.Upon a successful comparison of the device address, the EEPROM will output a zero during the following clock cycle. If a compare is not made, the device will not acknowledge and will instead return to a standby state.Figure 7-1.Device AddressingData Security: The AT24C32D has a hardware data protection scheme that allows the user to write protect the whole memory when the WP pin is at V CC .AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_122016108.Write OperationsByte Write : A Write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device, such as a microcontroller, must then terminate the write sequence with a Stop condition. At this time, the EEPROM enters an internally-timed Write cycle, t WR , to the nonvolatile memory (See Figure 6-6). All inputs are disabled during this Write cycle and the EEPROM will not respond until the Write is complete.Figure 8-1.Byte WriteNote:* = Don’t care bit.Page Write: The 32K EEPROM is capable of 32-byte Page Writes.A Page Write is initiated the same way as a Byte Write, but the microcontroller does not send a Stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 31 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the Page Write sequence with a Stop condition.The data word address lower five bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 32 data words are transmitted to the EEPROM, the data word address will roll-over and the previously loaded data will be altered. The address roll-over during Write is from the last byte of the current page to the first byte of the same page.Figure 8-2.Page WriteNote:* = Don’t care bit.Acknowledge Polling : Once the internally-timed Write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a Start condition followed by the device address word. The Read/Write bit is representative of the operation desired. Only if the internal Write cycle has completed will the EEPROM respond with a zero, allowing the Read or Write sequence to continue.S T A R TW R I T ES T O PDevice Address FirstWord Address Second Word AddressDataSDA LineM S BA C KR /W A C KA C KA CKSDA LineS T A W R I BK/W KKKKS T9.Read OperationsRead operations are initiated the same way as Write operations with the exception that the Read/Write select bit in the device address word is set to one. There are three Read operations:●Current Address Read ●Random Address Read ●Sequential ReadCurrent Address Read : The internal data word address counter maintains the last address accessed during the last Read or Write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address roll-over during read is from the last byte of the last memory page, to the first byte of the first page.Once the device address with the Read/Write select bit set to one is clocked in and acknowledged by theEEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an zero but does generate a Stop condition.Figure 9-1.Current Address ReadRandom Read: A Random Read requires a dummy Byte Write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another Start condition. The microcontroller now initiates a Current Address Read by sending a device address with the Read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a Stop condition.Figure 9-2.Random ReadNote:* = Don’t care bit.SDA LineS T A R TDevice AddressR E A DS T O PM S BA C KR /W N O A C KDataSDA LINES T A R TS T A R TR E A DW R I T ES T O PDevice Address Second Word Address Device AddressFirst Word Address Data (n)M S BA C KA C KAC KL S B A C KN O A C KR /W Dummy WriteR /W12Sequential Read: Sequential Reads are initiated by either a Current Address Read or a Random Address Read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address maximum address is reached, the data word address will roll-over and the Sequential Read will continue from the beginning of the array. The Sequential Read operation is terminated when the microcontroller does not respond with a zero but does generate a Stop condition.Figure 9-3.Sequential ReadNote:* = Don’t care bit.SDA LINESTARTSTARTREADWRITESTOP DeviceAddressSecond WordAddressDeviceAddressFirst WordAddressData (n + 1)Data (n + 2)Data (n + x)Data (n)MSBACKACKACKLSBACKACKACKACKNOACKR/WDummy Write. . .. . .R/AT24C32D [DATASHEET]10.Ordering Code DetailAtmel DesignatorProduct FamilyDevice DensityDevice RevisionShipping Carrier OptionOperating VoltagePackage Option32 = 32K24C = Standard I 2C-compatibleSerial EEPROMB = Bulk (Tubes)T = Tape and Reel, Standard Quantity Option E = Tape and Reel, Expanded Quantity OptionM = 1.7V to 5.5VSS = JEDEC SOIC X = TSSOP MA = UDFN ME = XDFN ST = SOT23U = 5-ball, 3x3 Grid Array, WLCSP C = VFBG A WWU = Wafer UnsawnWDT = Die in Tape and ReelPackage Device Grade or Wafer/Die ThicknessH = Green, NiPdAu Lead Finish, Industrial Temperature Range (-40°C to +85°C)U = Green, Matte Sn Lead Finish or SnAgCu Solder Ball Finish, Industrial Temperature Range (-40°C to +85°C)11= 11mil Wafer ThicknessA T 24C 32D -S S H M -TAT24C32D [DATASHEET]1411.Part MarkingsNotes: 1.WLCSP Package: CAUTION: Exposure to ultraviolet (UV) light can degrade the data stored in the EEPROM cells. Therefore, customers who use a WLCSP product must ensure that exposure to ultraviolet lightdoes not occur.2.Contact Atmel Sales for Wafer sales.13.18S1 — 8-lead JEDEC SOICAT24C32D [DATASHEET]1613.28X — 8-lead TSSOP13.38MA2 — 8-pad UDFNAT24C32D [DATASHEET] 1813.48ME1 — 8-pad XDFNAT24C32D [DATASHEET]2013.55TS1 — 5-lead SOT2321AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_12201613.65U-3 — 5-ball, WLCSPAT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_1220162213.78U2-1 — 8-ball VFBGA23AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_12201614.Revision HistoryX X X X X XAtmel Corporation1600 Technology Drive, San Jose, CA 95110 USAT: (+1)(408) 441.0311F: (+1)(408) 436.4200|© 2015 Atmel Corporation. / Rev.: Atmel-8866D-SEEPROM-AT24C32D-Datasheet_122016.Atmel ®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities ®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others.DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended,authorized, or warranted for use as components in applications intended to support or sustain life.SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any applications where the failure of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without an Atmel officer's specific written consent. Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapons systems.Atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by Atmel as military-grade. Atmel products are not designed nor intended for use in automotive applications unless specifically designated by Atmel as automotive-grade.。

串行E2PROM--24C××读写器电路

串行E2PROM--24C××读写器电路近日在做一个项目的过程中，要对大量的串行E2PROM AT24C系列进行读写。

起初欲设计一块简单的读写板，由单片机对E2PROM存储器写入，苦于时间紧，任务急，没有采用这种方法。

于是我想到了In te rnet网，何不上网找一找呢?我搜索了大量的国内外有关单片机以及嵌入式控制方面的网站，功夫不负有心人，终于在一个很不起眼的网站上找到了一个27k的小程序24cxx.exe，是专门写A T24C系列串行存储器的，附有一份电路图（见图2）。

充其量花5元钱，而且利用PC机打印口直接供电，不用外接电源。

我赶紧把程序下载到我的硬盘中，随后按电路图焊了一个简单的接口板，装上一片AT24C16，再将其插入我的笔记本电脑的打印口，启动程序，哇！真是帅呆了，写、擦、比、存、调、校等，要怎么操作就怎么操作，简直像是专门为我定做的。

当然，我是不敢自己一个人独享的，于是便凑成了本文。

好与大家共同分享。

这款程序不大，功能却不逊色于某些大型软件，界面也很简，稍加熟悉便会使用。

1 界面的左上角是软件的名称及版本号：24C×× PROGRAMMER VER1.0；2 界面的右上角是被写芯片的名称和类型：Mfr:ATMEL Type:AT24C01A（缺省值）。

3 中间大范围的部分是代码编辑缓冲区，可以将芯片中的内容先读入到该编辑区，重新编辑后再写回到芯片中去。

也可以将缓冲区中的内容以二进制文件的形式存放到硬盘上，或将硬盘上的二进制文件调入缓冲区，再写入到芯片中去。

4 中间靠右侧是弹出式菜单条，可用上下箭头选取菜单，再按回车键执行。

也可以按加亮的大写字母所代表的键进行相应的操作。

5 左下部是代码保存的二进制文件名输入区File Name。

6 中下部是芯片的起始地址Start Addr和结束地址End Addr。

7 右下部是缓冲区代码的校验和Check Sum。

AT24Cxx系列EEPROM应用笔记

-1-
PDF 文件使用 "pdfFactory Pro" 试用版本创建
AT24Cxx 系列 EEPROM 应用笔记
•100 kHz (1.8V, 2.5V, 2.7V) ， 400 kHz (5V)兼容 • 写保护管脚 • 32-Byte页写模式 • 可编程自定时写周期（包括自动擦除时间不超过10ms，典型时间为5ms） • 高可靠性
-5-
PDF 文件使用 "pdfFactory Pro" 试用版本创建
AT24Cxx 系列 EEPROM 应用笔记
图 8 字节写时序图
6.2. 页写
如图（图 9）所示为 AT24Cxx 页写时序图。在页写模式下，AT24C01/02/04/08/16/32/64/128/256 可一次写入 8 /16/16/16/16/32/32/64/64 个字节数据。页写操作的启动和字节写一样，不同的是在于传送了一字节数据后并不产生停止信号。主器件被允许发送 P （ AT24C01 ： P=7 ； AT24C02/04/08/16： P=15；AT24C32/64：P=31；AT24C128/256：P=63）个额外的字节。每发送一个字节数据后 AT24Cxx 产生一个应答位, 且内部低位地址加 1，高位保持不变。如果在发送停止信号之前主器件发送超过 P+1 个字节，地址计数器将自动翻转，先前写入的数据被覆盖。接收到 P+1 字节数据和主器件发送的停止信号后，AT24Cxx 启动内部写周期将数据写到数据区。所有接收的数据在一个写周期内写入 AT24Cxx。
AT24Cxx 系列 EEPROM 是由美国 Mcrochip 公司出品，1-512K 位的支持 I2C 总线数据传送协议的串行 CMOS E2PROM，可用电擦除，可编程自定时写周期（包括自动擦除时间不超过 10ms，典型时间为 5ms）的。串行 E2PROM 一般具有两种写入方式，一种是字节写入方式，还有另一种页写入方式。允许在一个写周期内同时对 1 个字节到一页的若干字节的编程写入，1 页的大小取决于芯片内页寄存器的大小。其中，AT24C01 具有 8 字节数据的页面写能力，AT24C02/04/08/16 具有 16 字节数据的页面写能力，AT24C32/64 具有 32 字节数据的页面写能力。