CMOS模拟电路设计问题解答

Solutions – Day 11.) (a.) The length and widths of M1 is 2µm and 10µm and of M2 is 2µm and 20µm.Therefore,C gd 1 = 220×10−12·10x10-6C gd 1 = 2.2fF C gd 2 = 220 × 10−12·20x10-6C gd 1 = 4.4fFNext, we must find the area and perimeter of each drain.AD1 = 60µm 2 & PD1 = 32µmAD2 = 120µm 2 & PD1 = 52µm C bd 1 = CJ·AD1 1+ 2.5V 2|φF |MJ + CJSW·PD11+ 2.5V 2|φF |MJSW = 770x10-6·60x10-12 1+ 2.5V 0.80.5 + 380x10-12·32x10-6 1+ 2.5V 0.80.38 C bd 1 = 22.75fF + 7.10fF =29.84fFC bd 2 = CJ·AD2 1+ 2.5V 2|φF |MJ + CJSW·PD2 1+ 2.5V 2|φF |MJSW = 560x10-6·120x10-12 1+ 2.5V 0.70.5 + 350x10-12·52x10-61+ 2.5V 0.70.35 C bd 2 =31.43fF +10.69fF =42.12fF(b.) Assume that the equivalent bulk resistance for the sources is found by the area defined by the rectangle between the edge of the polysilicon and the closest edge of the contacts. This assumption ignores the fact that current at the edges of the rectangle will not be the same as that in the middle. For M1, this rectangle is 2µm by 10µm and for M2 this rectangle is 2µm by 20µm. Therefore,R S 1 ≈ 35Ω/sq.x(2µm/10µm) + 4Ω/2 = 7Ω + 2Ω = 9 ΩandR S 2 ≈ 80Ω/sq.x(2µm/20µm) + 4Ω/4 = 8Ω + 1Ω = 9Ω2.) A simple first-order filter shown is to be built with a polysilicon resistor and a MOS capacitor. The polysilicon resistor has a sheet resistance of 50Ω/sq. ± 30% and is 5µmwide. The MOS capacitor is 2fF/µm 2 ± 10%. The -3dBfrequency of the lowpass filter is 1MHz. (a.) Choose the size of the resistor (the number of squares, N ) to minimize the total area of the filter including both the resistor and the capacitor.Find the area of the resistor and the capacitor in µm 2 and their values. (b.) Using the worst-case tolerance of the resistor and capacitor, find the maximum and minimum -3dB frequencies.Solution (a.)Value of R = 50Ω/sq.x N sq. = 50N ΩValue of C = 2fF/µm 2x A C µm 2 = 2A C fF Area of C = A CArea of R = A R = 25µm 2x N = 25N µm 2Total Area = A T = (25N + A C ) µm 2We know that the RC product is given asRC = 12πx106 = (50N )(2A C x10-15) = NA C x10-13∴ A C =12πx10-7NThus,A T = 25N +12πx10-7N →dA T dN = 25 - 12πx10-7N 2 = 0∴ N⇒A R = 252x25µm 2 = 6308µm 2 and A C =6308µm 2Also, R poly = R = 252x50 Ω = 12.6k Ω and C MOS = 6308µm 2 x2fF/µm 2 = 12.6pF (b.)Maximum -3dB frequency = 12π(0.7)(12.6k Ω)(0.9)(12.6pF) = 1.6MHzMinimum -3dB frequency = 12π(1.3)(12.6k Ω)(1.1)(12.6pF)= 0.7MHzR v inSolutions – Day 21.) A transmission gate is shown. If V DD = 2V, what is the highest possible large signal ON resistance of the transmissiongate. Ignore the bulk effects and assume that v DS ≈ 0V.SolutionR NMOS = 1K N (W 1/L 1)(V GS1-V TN ) = 106110(2-V AB-0.7)= 106110(1.3-VAB )⇒ G NMOS = 110(1.3-V AB )µSR PMOS = 1K P (W 2/L 2)(V SG2-|V TP |) = 10650(V AB -0.7) ⇒ G PMOS = 50(V AB -0.7)µSFirst, plot the sum of the conductances to graphically locate the minimum value of switchconductance.0.20.40.60.8 1.01.82.00V ABD2S1We note that the minimum value of switch conductance occurs at V AB = 1.3V. This corresponds to 30µS. Inverting this value gives the maximum switch resistance which is 33.3k Ω.Therefore, the maximum ON resistance occurs at 1.3V and is 33.3k Ω.R ON (max) = 33.3k Ω at V AB = 1.3V2.) (a.) If all W/Ls are 100µm/1µm, find the value of V GG that will give a minimum value of V MIN .(b.) Find the small signal values of R in , R out , and i out /i in .Solution :(a.) V GG = V GS 4 + V DS 1(sat) = V TN + 2·V DS (sat)V MIN = 2(0.135) = 0.27V(b.) R out ≈ g m4r ds 4r ds2 and i out /i in ≈ 1 Small signal model for R in calculation:v in = (i in - g m 3v gs 3)r ds 3 + (i in - g m 1v gs 1)r ds 1v gs 1 = v in and v gs 3 = -v s 3 = -(i in -g m 1v gs 1)r ds 1= -(i in -g m 1v in )r ds 1∴ v in = [i in r ds 3 + g m 3r ds 1r ds 3 - g m 1g m 3r ds 1r ds 3] + [i in r ds 1 - g m 1r ds 1v in ]or v in [1 + g m 1g m 3r ds 1r ds 3 + g m 1r ds 1] = i in [r ds 1 + r ds 3 + g m 3r ds 3]∴R in = v i n iin = r ds 1 + r ds 3 + r g m 3r ds 31 + g m 1g m 3r ds 1r ds 3 + g m 1r ds 1 ≈ 1g m 1g m 1g m 4, r ds 1 = r ds 2 = r ds 3 = r ds 4 = 0.25M Ω.∴ R i n ≈ 1gm 1= 11.48mS = 674ΩR out ≈ 250k Ω(1.48mS)250k Ω = 92.5M Ωand i outi in= 1Day 3 - SolutionsProblem 1A MOS cascode amplifier is shown below.Assume all transistors are saturated and the K N ’ =110µA/V 2, V T = 0.7V, and λN = 0.04V -1. The value of V GG 1 gives a dc bias current in both transistors of 100µA. (a.) Find the value of V GG 2 which gives a minimum output voltage (same as V MIN (out) for current sinks). What isthe value of miminum output voltage? (b.) Find the small-signal output resistance, R out . (c.) Find the small-signal voltage gain, v out /v in .Solution (a.) V ON∴ V GS = V ON + V T = 0.4264+0.7 = 1.1264V ⇒ V GG 2 = 2V O N +V T = 1.553VAlso V MIN = 2V ON = 2·0.4264 = 0.8528V (b.) R out = 20k Ω||g m 2r ds g mr ds = 1100µA·0.04 = 0.25M Ω∴ R out = 20k Ω||29.3M Ω ≈ 20k Ω(c.) The small signal voltage gain can be expressed asv outv in= -g m R out = -(469µS)(0.02M Ω) = -9.38V/Vv outV GG 2Problem 2A push-pull follower is shown which uses an NPN BJT and a p-channel MOSFET. In this problem, ignore the bulk effect, the channel length modulation, and the Early voltage. The parameters for the NPN BJT are βF = 100,I s = 10fA and V t = 25.9mV. The model parameters for the PMOS are K P ’ = 50µA/V 2 and V TP = -0.7V. (a.)Find the value of the dc batteries, V 1 and V 2, which will cause 100µA to flow in Q1 and M2 when the dc value of v IN = 0VDC. (b.) Find the small-signal input resistance,output resistance (not including R L ) and voltage gain when the dc value of v IN = 0VDC.Solution(a.) V 1= V BE 1 = V t ln i C I s = 0.0259ln100µA 10fA = 0.5964V → V 1=0.5964VV 2= V SG 2V TP → V 2=0.9V (b.) Small-signal model (simplified):g m 1 = I C 1V t = 100µA25.9mV = 3.86mSr π1 = 1+βFg m 1= 26.159k Ωg m 2R in :in π1in in + g m 1v π+ g m 2 v gs 2)R L = r π1i in + (i in + g m1r π1i in + g m 2 r π1i in )R LR in = v ini in= r π1 + R L + g m 1r π1R L + g m 2 r π1R L = r π1 + R L (1+βF ) + g m 2 r π1R L∴ R in = 26.159k Ω + 101·100Ω + 1·26.159k Ω ·0.1 = 38.875k Ω R in = 38.875k Ω R out : R out = 1gm 1 || 1g m 2= 13.86mS+1mS = 205.8Ω R out = 205.8Ωv out v in : v out v in = v out i in i in v in = R L (1+βF )+g m 2r π1R L r π1+R L (1+βF )+g m 2r π1RL= 12.71638.875 = 0.3271v outv in = 0.3271V/V=Ωv INDay 4 - SolutionsProblem 1A two-stage, BiCMOS op amp is shown.For the PMOS transistors, the modelparameters are K P ’=50µA/V 2, V TP = -0.7V and λP = 0.05V -1. For the NPN BJTs, the model parameters are βF = 100, V CE (sat) =0.2V, V A = 25V, V t = 26mV, I s = 10fA andn =1. (a.) Identify which input is positiveand which input is negative. (b.) Find the numerical values of differential voltage gain magnitude, |A v (0)|, GB (in Hertz), the slew rate, SR , and the location of the RHP zero.(c.) Find the numerical value of the maximum and minimum input commonmode voltages.Solution(a.) The plus and minus signs on the schematic show which input is positive and negative.(b.) The differential voltage gain, A v (0), is given as A v (0) = g m 1g ds 2+g o 4+g π6 ·g m 6g ds 7+g o 6g m 1 = g m 2r ds 2 =1λP I D = 2025µA= 0.8M Ω, r o 4 = V A I C = 25V 25µA = 1M Ω, g m 6 = I C V t = 100µA 26mV = 3846µS r π6 = βFg m 6 = 26k Ω,r ds 7 = 1λP I D= 20100µA = 0.2M Ω and r o 6 = V A I C = 25V100µA = 0.25M Ω∴|A v (0)| = [158.1(0.8||1||0.026)][3846(0.2||0.25)]= 3.888·427.36 =1,659.6V/V GB = g m 1C c = 158.1µS5pF = 31.62x106 rads/sec → GB = 5.0325MHzSR = 50µA 5pF = 10V/µsRHP zero = g m 6C c = 3.846mS5pF = 769.24x10 6 r ads/sec . (122MHz)(c.) The maximum input common mode voltage is given as v icm + = V CC -V DS5(sat) - V SG 1∴v icm + =0.0367V v icm - = -1.5 + V BE 3 - V T 1 = -1.5 + V t ln25µA 10fA - 0.7 = -2.2 + 0.5626 =-1.6374V50S01E2P1Problem2A CMOS circuit used as an output buffer for an OTA is shown. Find the value of the small signal output resistance, R out ,and from this value estimate the -3dB bandwidth if a 50pF capacitor is attached to the output. What is the maximum and minimum output voltage if a 1k Ω resistor is attached to the output? What is thequiescent power dissipation of this circuit? Use the following model parameters: K N ’=110µA/V 2, K P ’ =50µA/V 2, V TN = -V TP = 0.7V, λN =0.04V -1 and λP = 0.05V -1.Solution Use feedback concepts to calculate the output resistance, R out .R out = R o1-LGwhere R o is the output resistance with the feedback open and LG is the loop gain.R o = 1g ds 6+g ds 7 = 1(λN +λP )I 6 = 1060.09·500= 22.22k ΩThe loop gain is,LG = v out ’v out = - 12 g m 2g m 6g m 4 + g m 1g m 9g m 7 Rog m 1 = g m 2g m 3 = g m 4g m 6g m 7∴LG = v out ’v out= - 12-331.67·2236223.6 + -331.67·3316.7331.67 = -73.68V/V R out = R o 1-LG = 22.22k Ω1+73.68 = 294.5 Ωf -3dB = 12π·R out ·50pF = 12π·294.5·50pF= 10.81MHzTo get the maximum swing, we must check two limits. First, the saturation voltages of M6and M7.V ds 6and V ds 7Second, the maximum current available to the 1k Ω resistor is ±1mA which means that theoutput swing can only be ±1V. Therefore, maximum/minimum output = ±1V .P diss = 6V(650µA) = 3.9mWSS S01E2S3Day 5 - SolutionsProblem 1A comparator consists of an amplifier cascaded with a latch as shown below. The amplifier has a voltage gain of 10V/V and f -3dB = 100MHz and the latch has a time constant of 10ns.The maximum and minimum voltage swings of the amplifier and latch are V OH and V OL .When should the latch be enabled after the application of a step input to the amplifier of 0.05(V OH -V OL ) to get minimum overall propagation time delay? What is the value of the minimum propagation time delay? It may useful to recall that the propagation time delay ofthe latch is given as t p = τL lnV OH -V OL 2vil where v il is the latch input (∆V i of the text).v inSolutionThe solution is based on the figure shown.We note that,v oa (t ) = 10[1-e -ω-3dB t ]0.05(V OH -V OL ).If we define the input voltage to the latch as,v il = x ·(V OH -V OL )then we can solve for t 1 and t 2 as follows:x ·(V OH -V OL ) = 10[1-e -ω-3dB t 1]0.05(V OH -V OL ) → x = 0.5[1-e -ω-3dB t 1]This gives,t 1 = 1ω-3dB ln11-2x From the propagation time delay of the latch we get,t 2 = τL lnV OH -V OL 2v il = τL ln12x∴t p = t 1 + t 2 = 1ω-3dB ln 11-2x + τL ln12x → dt p dx = 0 gives x = π1+2π= 0.4313t 1 = 10ns 2π ln (1+2π) = 1.592ns·1.9856 = 3.16ns and t 2 = 10ns ln1+2π2π =1.477ns ∴t p = t 1 + t 2 = 3.16ns+1.477ns =4.637ns V OHV OLx (V OH -VProblem 2A 4-bit, binary-weighted, resistor DAC is shown. (a.) Assume that GB = ∞ and find the minimum differential gain,A vd (0), required for the DAC to have an INL of ±0.5LSB . (b.) If the differential gain is very large, find the conversion time of this DAC if GB = 1MHz.Solution(a.) First we need to find v out (ideal)and v out (actual) for the worst case condition which is when all switches are closed (closed loop gain is highest). v out (ideal) = -R EQR V REFandv out (actual) = -AR R +R EQ 1+ AR EQ R +R EQ V REF where R EQ = R 12 + 14 + 18 + 116 = 32R30 Now, v out (actual) - v out (ideal) ≤ V REF32 ⇒-ARR +R EQ 1+ AR EQ R +R EQV REF + R EQ R V REF ≤ V REF32 Which simplifies to,32RR EQ –1 ≤ AR EQ R +R EQ⇒A ≥ R +R EQ R EQ32RR EQ -1 A ≥15R +16R 16R 32R 32R 30 -1 = 311629 = 56.2V/V(b.) In this case, v out (ideal) = -3032V REF and v out (actual) = -3032 [1- e -t ωH ]V REF where ωH = GB·R EQ R +R EQ= 2πx10+6(32/30)1+ (32/30) = (32/31)πx10+6 rads/sec.Now, v out (actual) - v out (ideal) ≤ V REF 32 ⇒ -3032 [1- e -T ωH ]V REF + 3032V REF ≤ V REF 32which becomes,30 e -ωH T = 1⇒T = 1ωH ln (30) = 3132π ln (30) µs∴T = 1.0488µsV REF。