Common-mode currents and EMI in non-isolated power supplies

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共模电感英语

共模电感英语Common mode inductors, also known as common mode chokes, are essential components used in a wide range of electronic devices like power supplies, filters, and amplifiers. These inductors help to suppress electromagnetic interference (EMI) and noise by filtering the common mode signals.Step 1: Understanding the Basics of Common Mode InductorsA common mode inductor consists of two coils wound on a core that has a high magnetic permeability. These two coils are positioned next to each other and are connected in parallel. The input currents flow through both coils in the same direction, providing a high impedance to any common mode noise. While the differential mode currents pass through only one of the coils, providing a low impedance path.Step 2: Advantages of Using Common Mode InductorsCommon mode inductors offer several advantages, including:- EMI Suppression: One of the primary benefits of using common mode inductors is that they help to suppress electromagnetic interference (EMI). This is especially important in applications involving sensitive electronic equipment.- Noise Reduction: Common mode inductors also filter out noise, providing a much cleaner power supply to sensitive applications.- High Reliability: Common mode inductors are highly reliable and can operate even in harsh and demandingenvironments.Step 3: Applications of Common Mode InductorsCommon mode inductors are commonly used in a variety of electronic applications, including:- Power Supplies: Common mode inductors are used in power supplies to suppress EMI and provide a clean and reliable power supply.- Filters: They are also used in RF bandpass filters, band-reject filters, and other types of filters.- Audio Amplifiers: Common mode inductors can help to reduce noise in audio amplifiers.Step 4: ConclusionOverall, common mode inductors are an essential component in electronics design, helping to suppress EMI, reduce noise, and provide clean and reliable power. With their high reliability and versatility, they are a must-have electronic component for a variety of applications.。

压敏电阻的应用实例

压敏电阻的应用实例English Answer.1. Overvoltage Protection.In electronic circuits, overvoltage protection is critical to prevent damage to sensitive components. A surge suppressor is commonly used for this purpose, and it shunts excess voltage to ground.Transient voltage suppression (TVS) diodes and metal oxide varistors (MOVs) are two types of surge suppressors. However, they have different characteristics.TVS diodes are semiconductor devices that conduct in the reverse direction when the voltage exceeds a certain threshold. They offer fast response times and low capacitance, making them suitable for protecting against high-energy transients.MOVs, on the other hand, are ceramic-based devicesthat exhibit non-linear resistance. They have a higher voltage threshold than TVS diodes but offer better surge current handling capability.2. EMI/RFI Suppression.Electromagnetic interference (EMI) and radio frequency interference (RFI) can cause signal distortion, noise, and performance degradation in electronic systems.Ferrites and common-mode chokes are commonly used to suppress EMI and RFI.Ferrites are magnetic materials that exhibit high permeability at high frequencies. They can be used to create inductors that suppress unwanted high-frequency signals.Common-mode chokes are transformers with a specific winding configuration that blocks common-mode noise while allowing differential signals to pass through.3. Voltage Regulation.Voltage regulators are used to maintain a stable voltage level in electronic circuits. Varistors can be used as voltage regulators due to their non-linear resistance特性.When the voltage rises above a certain threshold, the varistor's resistance decreases, allowing more current to flow and thus regulating the output voltage.Varistors offer a simple and cost-effective solution for voltage regulation in applications where precise voltage control is not required.4. Load Protection.Inrush current can damage sensitive electronic components during startup. NTC thermistors can be used to limit the inrush current.NTC thermistors have a high resistance when cold, which limits the current flow during startup. As the thermistor heats up, its resistance decreases, allowing more current to pass through.This characteristic makes NTC thermistors ideal for protecting loads from excessive inrush current.5. Signal Conditioning.Voltage-dependent resistors (VDRs) can be used in signal conditioning circuits to vary the resistance based on the applied voltage.VDRs are typically used as voltage dividers or attenuators. By varying the applied voltage, the output voltage can be adjusted to the desired level.Chinese Answer.1. 过压保护。

反激式开关电源外文翻译

Measurement of the Source Impedance of Conducted Emission Using Mode Separable LISN: Conducted Emission of a Switching Power SupplyJUNICHI MIY ASHITA,1 MASAYUKI MITSUZAW A,1 TOSHIYUKI KARUBE,1KIYOHITO Y AMASAW A,2 and TOSHIRO SA TO21Precision Technology Research Institute of Nagano Prefecture, Japan2Shinshu University, JapanSUMMARYIn the procedure for reducing conducted emissions, it is helpful to know the noise source impedance. This paper presents a method of measuring noise source complex impedances of common and differential mode separately. We propose a line impedance stabilization network (LISN) to measure common and differential mode noise separately without changing LISN impedances of each mode. With this LISN, conducted emissions of each mode are measured inserting appropriate impedances at the equipment under test (EUT) terminal of the LISN. Noise source complex impedances of switching power supply are well calculated from measured results. © 2002 Scripta Technica, Electr Eng Jpn, 139(2): 72 78, 2002; DOI 10.1002/eej.1154Key words:Conducted emission; noise terminal voltage; noise source impedance; line impedance stabiliza-tion network (LISN); EMI.1. IntroductionSwitching power supplies are employed widely in various devices. High-speed on/off operation is accompa-nied by harmonic noise that may cause electromagnetic interference (EMI) with communication devices and other equipment. To prevent the interference, methods of meas-urement and limit values have been set for conducted noise (~30 MHz) and radiated noise (30 to 1000 MHz). Much time and effort are required to contain the noise within the limit values; hence, the efficiency of noise removal tech-niques is an urgent social problem. Understanding of the mechanism behind noise generation and propagation is necessary in order to develop efficient measures. In particu-lar, the propagation of conducted noise must be investi-gated.Modeling and analysis of equivalent circuits have been carried out in order to investigate conducted noise caused by switching [1, 2]. However, the stray capacitance and other circuit parameters of each device must be known in order to develop an equivalent circuit, which is not practicable in the field of noise removal. On the other hand, noise filters and other noise-removal devices do not actually provide the expected effect [3, 4], which is explained by the difference between the static characteristics measured at an impedance of 50 Ω, and the actual impedance. Thus, it is necessary to know the noise source impedance in order to analyze the conducted noise.Regulations on the measurement of noise terminal voltage [5] suggest using LISN; in particular, the vector sum (absolute voltage) of two propagation modes, namely, common mode and differential mode, is measured in terms of the frequency spectrum. Such a measurement, however, does not provide phase data, and propagation modes cannot be separated; therefore, the noise source impedance cannot be derived easily. There are publications dealing with the calculation of the noise source impedance; for example, common mode is only considered as the principal mode, and the absolute value of the noise source impedance for the common mode is found from the ground wire current and ungrounded voltage [6], or mode-separated measure-ment is performed by discrimination between grounded and ungrounded devices [7]. However, measurement of the ground wire current is impossible in the case of domestic single-phase two-line devices. The complex impedance can be found using an impedance analyzer in the nonoperating state, but its value may be different for the operating state. Thus, there is no simple and accurate method of measuring source noise impedance as a complex impedance.© 2002 Scripta TechnicaElectrical Engineering in Japan, V ol. 139, No. 2, 2002Translated from Denki Gakkai Ronbunshi, V ol. 120-D, No. 11, November 2000, pp. 1376 1381The authors assumed that the noise source impedance could be found easily using only a spectrum analyzer, provided that the noise could be measured separately for each mode, and the LISN impedance could be varied. For this purpose, a LISN with a balun transformer was devel-oped to ensure noise measurement, with the common mode and differential mode strictly separated. An appropriate known impedance is inserted at the EUT (equipment under test) terminals, and the noise source impedance is found from the variation of the noise level. This method was used to measure the conducted noise of a switching power sup-ply, and it was confirmed that the noise source impedance could be measured as a complex impedance independently for each mode. Thus, significant information for noiseremoval and propagation mode analysis was acquired.This paper presents a new method of measuring the noise source impedance of conducted emission using mode-separable LISN.2. Separate Measurement for Common Mode andDifferential ModeThe conventional single-phase LISN circuit for measurement of the noise terminal voltage is shown in Fig.1. The power supply is provided with high impedance by a 50-µH reactor, and a meter with an input impedance of 50Ω is connected between one line and the ground via a high-pass capacitor, and another line is terminated by 50 Ω. Thus, the LISN impedance as seen at the EUT is 100 Ω in the differential mode, and 25 Ω in the common mode. The measured value is the vector sum of both modes, and the noise must be found separately in order to find the noise source impedance for each mode. There is LISN with Y-to-delta switching to provide mode separation [8], but its impedance is 150 Ω, giving rise to a problem of data compatibility with 50-Ω LISN. Thus, a new mode-separa-ble LISN was developed as shown in Fig.2. The circuit is identical to that in Fig. 1 from the power supply through the high-pass capacitor. Switching of the connection pattern ensures measurement with one line of the balun transformer terminated by 50 Ω, and another line connected to the meter.In Fig. 2, the secondary side of the 2:1 balun trans-former is terminated by 50 Ω, while the primary side has 200 Ω; in the differential mode, the impedance (line-to-line) is 100 Ω since 200 Ω at the high-pass capacitor is connected in parallel. With the switch set at D, the meter is connected to the secondary side of the balun transformer. The voltage is one-half that of the line-to-line voltage, and measurement is performed in the standard way.The common mode current flows from both sides of the balun transformer via the middle tap to the 50-Ω termi-nal. The currents in the windings are antiphase, and no voltage is generated at the secondary side. Therefore, the impedance of the primary side is the terminal resistance of the tap. Since this impedance is connected in parallel to 50Ω (two 100 Ω in parallel) at the high-pass capacitor, the impedance between the common line and ground is 25 Ω. With the switch set at C, the meter is connected to the middle tap of the balun transformer, and the common-mode voltage is the line-to-ground voltage.3. Measurement of Noise Source Impedance3.1 Measurement circuit and calculationThough the propagation routes are different in the two modes, propagation from the noise source to the LISN can be represented in a simplified way as shown in Fig. 3. In the initial measurement, the load impedance Z L is the LISN impedance. Z L can be varied by inserting a knownimpedance at the EUT terminals. Consider three load im-Fig. 1. Standard 50-Ω/50-µH LISN.Fig. 2.Mode-separable LISN.Fig. 3. Schematic circuit of noise propagation.pedances, namely, LISN only and LISN with two different impedances inserted, Z L 1(R 1 + jX 1), Z L 2(R 2 + jX 2), andZ L 3(R 3+ jX 3). Using the values I 1, I 2, I 3 (scalars) measured in the three cases, Z 0(R 0 + jX 0) is found. Since V 0 = |Z L | × I ,the following expressions can be derived:From the above,Here a , b , and c are as follows:Substituting Eq. (2) into Eq. (1), the following quadratic equation for R 0 is obtained:Thus, R 0 and X 0 have two solutions each. The series of frequency points with positive R 0 is taken as the noise source impedance.3.2 Method of measurementAn impedance is inserted at the EUT terminals in order to measure the noise source impedance in the LISN as seen at the EUT. As shown in Fig. 4, the impedance is inserted so as to vary only the impedance in the mode under consideration, thus preventing an influence on the imped-ance in the other mode. In the diagram, V m is the voltage at the meter connected to the LISN, while the input impedance of the meter (50 Ω) is represented by the parallel resistance.Since parameters of both the LISN and the inserted imped-ance are known, the noise current I can be calculated from V m . Now Z 0 is calculated for each mode from the measured data obtained while varying Z L , by using Eqs. (2) and (3).With the differential mode shown in Fig. 4(a), CR is inserted between the two lines, thus varying the load im-pedance Z L . In the differential mode, Z 0 is assumed to be a low impedance, and hence the inserted impedance exerts a significant effect on the measured value. For this reason, 1Ω/0.47 µF and 0 Ω/0.1 µF were inserted, which are rather small compared to the LISN impedance.The measurement of the common mode shown in Fig.4(b) employs common-mode chokes that basically have no impedance in the differential mode. The common-mode chokes are provided with a secondary winding (ratio 1:1),so that the impedance at the secondary side can be varied.In the common mode, Z 0 is assumed to have a particularly high impedance in the low-frequency band. For this reason,5.1 k Ω and 100 pF were used as the secondary load for the common-mode choke to obtain a high inserted impedance.The measured data for the inserted impedance in the case of resistive and capacitive loads are presented in Fig. 5. The impedance of the common-mode choke includes its own inductance and the secondary load. In the case of a capaci-tive load, the resonance point is around 200 kHz; at higher frequencies, the impedance becomes capacitive.A single-phase two-line switching power supply (an ac adapter for a PC with an input of ac 100 V , a rated power of 45 W, and PWM switching at 73 kHz) was used as the EUT, and the rated load resistance was connected at the dcside. Filters were used for both the common and differential(1)modes, except for the case in which one common-mode choke was removed, in order to obtain the high noise level required for analysis. Both the EUT and the loads had conventional commercial ratings, and were placed 40 cm above a metal ground plate; the power cord was fixed.4. Measurement Results and Discussion The results of conventional measurement as well as common-mode and differential-mode measurement for the LISN without inserted impedance are shown in Fig. 6. The measurements were performed in the range of 150 kHz through 30 MHz, divided into three bands, using a spectrum analyzer with frequency linear sweep. Time-variable data were measured at their highest levels using the Max Hold function of the spectrum analyzer, and only the peak values were employed for calculation of Z 0. For this purpose, the values measured in every frequency band were subjected to the FFT, and all harmonics higher than the fundamental frequency were removed. The data were smoothed, and about 10 peak points were detected in every frequency band. In addition, only those peaks that were stronger than the meter s background noise by at least 6 dB were consid-ered.The results in Figs. 6(b) and 6(c) pertain to the LISN only; the level would vary with inserted impedance. The noise source impedance for both modes calculated from the measured data (using triple measurement) is given in Figs.7 and 9, respectively. The bold and dashed lines pertain to data acquired with the impedance analyzer at the EUT power plug, with the EUT not in operation. With the differ-ential mode, there were no high-frequency components, as shown in Fig. 6(b), and hence the impedance is calculated only for significant low-frequency peaks.The noise source impedance in differential mode can be represented schematically as in Fig. 8. The noise sourceimpedance is equal to the impedance between the LISNFig. 5.Inserted impedance in common mode.Fig. 6. Measured results of standard, differential-mode,and common-mode.Fig. 7. Noise source impedance for differential mode.terminals when the noise source is short-circuited. With switching power supplies, filtering is usually performed by a capacitor of 0.1 to 1 µF inserted between the lines. Since the impedance of the power cord is small in the measured frequency range, one may assume that the impedance as seen at the LISN is low, and that the phase changes from capacitive toward inductive as with the measured static characteristics. However, in the case of the given EUT, a nonlinear resistor was inserted between the power cord and the filter as shown in Fig. 8, and hence the impedance is rather high in the nonoperating state. In addition, there are rectifying diodes on the propagation route, but they do not conduct at the measurement voltage of the impedance ana-lyzer. The noise levels show considerable variation at 120Hz, which corresponds to the on/off frequency of the recti-fying diodes; however, only the peak values are measured and then used for calculation, and hence the impedance obtained by the proposed method is considered to pertain to the conductive state. For this reason, the results do not agree well with static characteristics. Thus, the impedance in the operating state cannot be measured in the differential mode.On the other hand, the measured data for |Z 0| in common mode agree well with the static characteristics, as shown in Fig. 9. The phase, too, exhibits a similar variation,although the scatter is rather large. The resistive part of three load impedances and Z 0 may be presented in a simplified way as in Fig. 10. From Eq. (1), the following is true for R 2,R 3, and Z 0:The distance ratio from Z 0 to R 3 and R 2 on the R X plane that satisfies this equation is I 2:I 3, which corresponds to a circle with radius r as in Eq. (4), with the center lying on the line R 3R 2:Similar circles for R 1 and R 2 are also shown in the diagram.When Z 0 and the load impedances lie on one line, the twocircles have a common point. Equation (4) indicates that if I 3 increases slightly, the outer circle becomes bigger, and the two circles do not adjoin. On the other hand, when the outer circle becomes smaller, the two circles intersect at two points, and X 0 varies more strongly than R 0. In practice, the difference in noise level due to the inserted impedance may drop below 1 dB at some frequencies, so that the solution for Z 0 becomes unavailable because of the scatter, or the phase scatters too much. The measurement accuracy is governed by the difference in noise level, and thus the inserted impedance should have a large enough variation compared to the measurement scatter; in addition, there should be a phase difference so that the two circles are not aligned, as in Fig. 10.Figures 7 and 9 pertain to one of the solutions of Eq.(3) with larger R 0. Here R 0 is not necessarily positive and the other solution is not necessarily negative. The two solutions may be basically discriminated from the fre-quency response and other characteristics, but other inser-tion data are employed for the sake of accuracy.Fig. 8. Equivalent circuit of differential-mode noisesource impedance.(4)Fig. 9.Noise source impedance for common mode.Fig. 10. Load impedances and Z 0 on R X plane.Figure 11 compares the measured data and calculated data for the variation of noise level due to insertion of a commercially available common-mode choke, with the cal-culation based on the results of Fig. 9 and the impedance of the common-mode choke. As is evident, the calculation agrees well with the measured values. On the other hand, a considerable discrepancy was confirmed for the other solu-tion. The noise source impedance found as explained above is accurate enough to predict the filtering effect.The noise source resistance in the common mode can be represented as in Fig. 12. Here Z 1 is the stray capacitance between the internal circuit and the case, and Z 2 is the stray capacitance between the case and the ground plate (or in the case of the ground wire, the impedance of the wire). The common-mode noise source impedance for a single-phase two-line EUT is primarily Z 2, becoming capacitive at low frequencies. Since the EUT is equipped with a filter, the influence of the primary rectifying diodes is not related to common-mode, and hence the data measured by the pro-posed method are very close to the static characteristics.However, this is not necessarily true in the case of a grounded line (Z 2 short-circuited) with no filter installed.In addition, here the full impedance as seen at the LISN is found; in practice, however, a filter or Z 1 is employed to suppress noise. Therefore, the impedance of the power cord is required as well as Z 1 and Z 2 in order to analyze the filtering effect. The impedance of the power cord or grounded wire can be easily determined by measurement or calculation. In our experiments without ground, the impedance is very close to Z 2; on the other hand, Z 1 might be measured by grounding the case and removing the filter (Fig. 12), and then used to analyze the filtering effect between the case and the lines. However, noise propagation in the inner circuit must be further investigated in order to estimate the noise-suppressing efficiency of Z 1.5. ConclusionsA new mode-separable LISN is proposed that sup-ports noise measurement without changing the impedance depending on the mode. The proposed LISN ensures accu-rate measurement for each mode, thus supporting imped-ance analysis.With the proposed LISN, an appropriate impedance is inserted at the EUT terminals, and the noise impedance can be found as a complex impedance, just as simply as with conventional measurement of the noise terminal voltage.The value of the inserted impedance must be chosen prop-erly in order to determine the phase accurately. The pro-posed method ensures sufficient accuracy not only to investigate noise propagation and design efficient counter-measures, but also to predict the filtering effect. The pro-posed technique can supply important data for future analysis of noise generation and propagation in switching power supplies.REFERENCES1.Matsuda H et al. Analysis of common-mode noise in switching power supplies. NEC Tech Rep 1998;51:60 65.2.Ogasawara S et al. Modeling and analysis of high-frequency leak currents generated by voltage-fed PWM inverter. Trans IEE Japan 1995;115-D:77 83.3.Iwasaki M, Ikeda T. Evaluation of noise filters for power supply. Tech Rep IEICE EMCJ 1999;90:1 6.4.Kamita M, Toyama K. A study on attenuation char-acteristics of power filters. Tech Rep IEICE EMCJ 1996;96:45 50.rmation technology equipment Radio distur-bance characteristics Limits and method of meas-urement. CISPR 22, 1997.Fig. 11. V ariation of noise level due to insertion ofanother impedance (measured and calculated data).Fig. 12. Equivalent circuit of common-mode noisesource impedance.6.K amita M, Oka N. Calculation of common-mode noise output impedance during operation. Tech Rep IEICE EMCJ 1998;98:59 65.7.Ran L, Clare C, Bradley K J, Chriistoopoulos C.Measurement of conducted electromagnetic emis-sions in PWM motor drive without the need for an LISN. IEEE Trans EMC 1999;41:50 55.8.Specification for radio disturbance and immunity measuring apparatus and method Part 1: Radio dis-turbance and immunity measuring apparatus. CISPR 16-1, 1993.AUTHORS (from left to right)Junichi Miyashita (member) graduated from Tohoku University in 1981 and joined the Precision Technology Research Institute of Nagano Prefecture. His research interests are EMC measurement and prevention. He is a member of IEICE.Masayuki Mitsuzawa (nonmember) graduated from Nagoya University in 1984 and joined the Precision Technology Research Institute of Nagano Prefecture. His research interests are EMC measurement and prevention. He is a member of JIEP .Toshiyuki Karube (nonmember) graduated from Waseda University in 1991 and joined the Precision Technology Research Institute of Nagano Prefecture. His research interests are EMC measurement and prevention. He is a member of IEICE and JIEP .Kiyohito Yamasawa (member) completed the M.E. program at Tohoku University in 1970. He has been a professor at Shinshu University since 1993. His research interests are magnetic device integration, microswitching power units, and microwave sensors. He holds a D.Eng. degree and is a member of IEICE, SICE, the Magnetics Society of Japan, the Japan AEM Society, and IEEE.Toshiro Sato (member) completed his doctorate at Chiba University in 1989 and joined Toshiba Research Institute. He has been an associate professor at Shinshu University since 1996. His research interests are magnetic thin-film devices. He received a 1994 IEE Japan Paper Award and a 1999 Japan Society of Applied Magnetism Paper Award. He holds a D.Sc. degree,and is a member of IEE Japan, IEICE, and the Magnetics Society of Japan.。

MicroPHYTM MII Evaluation Board DEMO BOARD MANUAL

78Q2123-DB78Q2133-DB78Q21x3-DB MicroPHY TMMII Evaluation BoardDEMO BOARD MANUALFebruary 2006DESCRIPTIONThe 78Q21x3-DB is a design example for a 10/100BASE-TX Mbit/second Fast Ethernet MII Interface adaptor. A 78Q2123 or 78Q2133 MicroPHY transceiver from Teridian provides the network physical interface and MII (Medium Independent Interface) interface.Teridian Semiconductor’s MicroPHY is an auto-sensing, auto-switching 10/100BASE-TX Fast Ethernet transceiver with full duplex operation capability. The device interfaces directly to the IEEE-802.3u MII port. Full-featured MII management functions are included along with an extended register set. The MicroPHY five bit PHY address is defaulted to 0x001. The MicroPHY interfaces to CAT5 UTP cable via a 1:1 transformer. The transceiver’s transmitter includes on-chip the pulse shaper and low power line driver. The receiver incorporates a sophisticated combination of real-time adaptive equalization, an adaptive DC offset adjustment circuit and baseline wander correction. Smart squelch circuitry further improves the receiver’s noise rejection. Full featured auto-negotiation or parallel detect modes are supported. The demo board requires operation with a +3.3V power supply.Design Kit contains:√ MicroPHY MII Demo Board √ Demo Board Parts List √ P.C.B. Gerber Files √ Demo Board schematic √ MicroPHY Data Sheet 10/100Base-TX InterfaceRJ45 Pin Assignment Pin Signal Pin Signal 1 TX+ 5 N/C 2 TX- 6 RX- 3 RX+ 7 N/C 4 N/C 8 N/CMII: Medium Independent InterfacePin Assignment: (40 Pin Male Subminiature D, 0.050) Pin Signal Pin Signal 1 +3.3V 21 +3.3V 2 MDIO 22 COMMON 3 MDC 23 COMMON 4 RXD3 24 COMMON 5 RXD2 25 COMMON 6 RXD1 26 COMMON 7 RXD0 27 COMMON 8 RXDV 28 COMMON 9 RXCLK 29 COMMON 10 RXER 30 COMMON 11 TXER 31 COMMON 12 TXCLK 32 COMMON 13 TXEN 33 COMMON 14 TXD0 34 COMMON 15 TXD1 35 COMMON 16 TXD2 36 COMMON 17 TXD3 37 COMMON 18 COL 38 COMMON 19 CRS 39 COMMON 20 +3.3V 40 +3.3VOrdering Number Description78Q21x3-DBMicroPHY MII Demo BoardMII ADAPTOR WITH MICROPHYUse With the Netcom Smart-BitsThe Netcom expects to be the master and defaults to 100BASE-TX Half-Duplex operation. Fast-Ether Windows may require the reconfiguration of the MicroPHY’s control register MR0 bits for similar operation. The MicroPHY defaults to auto-negotiate with full capabilities.After initialization the MicroPHY defaults to 100BASE-TX Full-Duplex operation. When connected to another fully capable transceiver the transceivers will be in full-duplex mode. The default configuration of the Netcom is 100BASE-TX Half-Duplex operation. If data transfers were to commence, the Netcom would display Collision errors (because it does not automatically read the transceivers and reconfigure).The default MII PHY address for the MicroPHY is 0x001. Additionally, the MicroPHY will respond to the broadcast address 0x000.If a transceiver is used which defaults to 100BASE-TX Half-Duplex operation, the MicroPHY will adjust itself for half-duplex operation (assuming the MicroPHY is setup for the proper technologies).To establish proper operation between the MicroPHY and the Netcom, click on the “Options” button followed by selecting “Full Duplex MII”. Repeat selecting “Full Duplex MII” twice to ensure that everything is configured identically.The MicroPHY can be configured for half-duplex operation to minimize incompatibilities with other transceivers and the Netcom.10/100Mbps Transformer SelectionThe line interface for the MicroPHY requires a pair of 1:1 isolation transformers. Integrated common-mode chokes are recommended for satisfying FCC radiated EMI requirements. Additional filtering is not required with the MicroPHY due to internal waveform shaping circuitry. The line transformer characteristics are outlined below:ConditionName ValueTurns Ratio 1 CT : 1 CT@ 10 mV, 10 kHzOpen-Circuit Inductance 350 µH (min)See Note 1.Leakage Inductance 0.40 µH (max) @ 1 MHz (min)Inter-Winding Capacitance 25 pF (max)D.C. Resistance 0.9 ohm (max)Insertion Loss 1.1 dB (typ) 0 - 100 MHzVrmsHIPOT 1500Note 1: The receive line transformer’s Open-Circuit Inductance can be as low as 100 µH for the MicroPHY. The MicroPHY incorporates baseline wander correction circuitry, which allows the receiver to track the incoming data signal when there is excessive transformer droop.For Commercial Temperature (0°C ~ 70°C)Teridian Semiconductor has performed line testing with the following transformers and found their performance acceptable with the MicroPHY:Manufacturer Part NumberTDKTLA-6T103Bel-Fuse S558-5999-46TG22-3506NDHaloPE-68515PulseST6118Valor20PMT04YCLThe following transformers are low profile packages (0.100 in/2.5 mm or less).TLA-6T118TDKTG110-S050HaloEPF8023GPCAThe following devices integrate the transformers with the RJ45 connector.TDKTLA-6T704RJS-1A08T089ADeltaThe following devices integrate the transformers, RJ45 connector, LEDs and termination resistors.J0011D21B/EPulseThe above evaluations were performed using Netcom’s Smart-Bits Fast Ethernet Analyzer. The Teridian Semiconductor MicroPHY MII Adapter and Lancast Fast Ethernet Adapter were attached to the Netcom’s Ports A & B respectively. Twisted pair Category 5 General Cable P/N 459360 was used to connect the two transceivers. 100 Mbps performance was measured using cable lengths of both 12 inches and 115 meters. 10 Mbps performance was evaluated using 100 meters of Category 3 cable.The Netcom was configured to use the Baseline Wander Packet file. Packet length was 1500 bytes.All transformers listed above met or exceeded IEEE’s 802.3 Bit Error Rate requirements of 10-8.For Industrial Temperature (-40°C ~ +85°C)Now most of the transformer vendors also offer industrial temp transformer, which will work with the 78Q2133. Here is the recommended industrial temp transformer list:Manufacturer Part NumberBelfuse S558-5999-U5HX1148PulseTG110-E050N5HaloPCB Layout ConsiderationsThe following recommendations enhance the MicroPHY’s performance while minimizing EMC emissions:1. The transformer to transceiver signal traces must be 100Ω differential transmission lines.2. Place the termination network components near the input data pins of the transceiver or transformer.3. Make all differential signal pairs short and of the same length.4. Decouple the transceiver thoroughly with 0.01µF and 0.1µF capacitors.5. Locate these decoupling capacitors as close as possible to the respective transceiver VCC and GNDpins.6. All decoupling capacitor and transceiver VCC and GND connections should tie immediately to a VCC orGND plane via with minimum trace inductance.7. Total decoupling capacitance should be greater than the load capacitance that the digital output driversmust drive.8. Use low inductance, ceramic surface mount decoupling capacitors.9. Use a multi-layer PCB with the inner layers dedicated to GND and VCC.10. A single VCC and GND plane is recommended for optimum performance. The lowest possible seriesimpedance is required between the analog and digital VCC and GND pins respectively of the transceiver.11. The outer layers of a 4 layer PCB are to be used for signal routing.12. Place the highest speed signals on the layer adjacent to the GND plane.13. Physically separate the analog signals from the digital signals by placing them on opposite layers orrouting them away from each other.14. Additional component and solder side ground layers may be added for maximum EMC containment.15. The GND plane should extend out to the transceiver side of the transformer. Remove the VCC and GNDplanes from the line side of the transformer to the RJ-45 connector.16. Do not allow the chassis ground plane to cross over the transceiver GND plane. Minimum separationmust accommodate over 1.5kV.17. Provide onboard termination of the unused signal pairs in the CAT-5 cable.18. Use a shielded RJ-45 connector with its case stakes soldered to the chassis ground.19. Locate the transformer adjacent to the RJ-45 to minimize the shunt capacitance to the line.20. Minimize RF current fringing by making the VCC plane 0.10 inch smaller than the GND plane. If multipletransceivers are used, provide partitions in the VCC and GND planes between the analog sections.Maintain the partition from the transformer up to the transceiver’s analog interface. Do not cross thesepartitions with signal traces, in particular any digital signals from adjacent transceivers.21. Add series resistors on all transceiver MII outputs to minimize digital output driver peak currents.22. Minimize the use of vias when routing the analog signal traces.23. Isolate the crystal and its capacitors from the analog signals with a guard ring.24. The crystal compensation capacitor value (C2 & C3) must be selected to trim the oscillator’s frequency to25.0000 MHz ±50ppm. The optimum value will be layout dependent. A mere ±4pF can shift the 25MHz±100Hz. The 25.0000 MHz ±50ppm is specified by the IEEE.Note: System vendors need to select the proper crystal according to their applications, such as operating environment, product lifetime, and etc since crystal aging, operating temperature, and other factors can affect the crystal frequency tolerance.MicroPHY MII Demo Board Parts ListQ T Y R EF ER E N C E N U M B E R D E S C R I P T I O N PA R T N U M B E R PA C KA G E MA N U FA C T U R E R1 U1 IC, 10/100Mbps LANTransceiverTSC 78Q2123 QFN32 TSC1 J2 RJ45, XFRM, LED,10BaseT/100BaseTX J0011D21Bwith LEDsPULSETLA-6T704without LEDsTDK1 Q1 CRYSTAL, 25.000MHZ ECCM1-25.000MHZ ECCM1 ECLIPTEK2 D1,D2 LED, Optional LU20125 R/A LUMEX7 R5,R6,R7,R8,R11,R12,R13,R14,R23,R25RES, 100 CC06032 R1,R2 RES, 680, Optional CC06033 R3,R4,R26 RES, 5.1K CC06031 R27 RES, 10K CC06034 R9,R10,R21,R22 RES, 49.9, 1% CC06034 C14,C15,C16,C17 CAP, CER, 10PF, Optional CC06032 C2,C3 CAP, CER, 27PF CC06033 C4,C12,C13 CAP, CER, 0.01UF CC060310 C6,C7,C8,C10,C11 CAP, CER, 0.1UF C1608Y51H104Z CC0603 TDK1 C9 CAP, CER, 10UF CC08051 P1 CONN, MALE, 40 PIN FCN-238P040-G/F FUJITSU1 P.C.B.Top SilkscreenTop LayerVCC LayerGround LayerBottom LayerNo responsibility is assumed by Teridian Semiconductor Corporation for use of this product or for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of Teridian Semiconductor Corporation, and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that the data sheet is current before placing orders.Teridian Semiconductor Corporation, 6440 Oak Canyon, Irvine, CA 92618-5201TEL: (714) 508-8800, FAX: (714) 508-887778Q2123-DB78Q2133-DB。

信号完整性和电源完整性分析

An Integrated Signal and Power Integrity Analysis for Signal Traces Through the Parallel Planes Using Hybrid Finite-Element andFinite-Difference Time-Domain TechniquesWei-Da Guo,Guang-Hwa Shiue,Chien-Min Lin,Member,IEEE,and Ruey-Beei Wu,Senior Member,IEEEAbstract—This paper presents a numerical approach that com-bines theﬁnite-element time-domain(FETD)method and theﬁ-nite-difference time-domain(FDTD)method to model and ana-lyze the two-dimensional electromagnetic problem concerned in the simultaneous switching noise(SSN)induced by adjacent signal traces through the coupled-via parallel-plate structures.Applying FETD for the region having the source excitation inside and FDTD for the remaining regions preserves the advantages of both FETD ﬂexibility and FDTD efﬁciency.By further including the transmis-sion-line simulation,the signal integrity and power integrity is-sues can be resolved at the same time.Furthermore,the numer-ical results demonstrate which kind of signal allocation between the planes can achieve the best noise cancellation.Finally,a com-parison with the measurement data validates the proposed hybrid techniques.Index Terms—Differential signaling,ﬁnite-element andﬁnite-difference time-domain(FETD/FDTD)methods,power integrity (PI),signal integrity(SI),simultaneous switching noise(SSN), transient analysis.I.I NTRODUCTIONI N RECENT years,considerable attention has been devotedto time-domain numerical techniques to analyze the tran-sient responses of electromagnetic problems.Theﬁnite-differ-ence time-domain(FDTD)method proposed by Yee in1966 [1]has become the most well-known technique because it pro-vides a lot of attractive advantages:direct and explicit time-marching scheme,high numerical accuracy with a second-order discretization error,stability condition,easy programming,and minimum computational complexity[2].However,it is often in-efﬁcient and/or inaccurate to use only the FDTD method to dealManuscript received March3,2006;revised November6,2006.This work was supported in part by the National Science Council,Republic of China,under Grant NSC91-2213-E-002-109,by the Ministry of Education under Grant93B-40053,and by Taiwan Semiconductor Manufacturing Company under Grant 93-FS-B072.W.-D.Guo,G.-H.Shiue,and R.-B.Wu are with the Department of Electrical Engineering and Graduate Institute of Communication Engi-neering,National Taiwan University,10617Taipei,Taiwan,R.O.C.(e-mail: f92942062@.tw;d9*******@.tw;rbwu@.tw).C.-M.Lin is with the Packaging Core Competence Department,Advanced Assembly Division,Taiwan Semiconductor Manufacturing Company,Ltd., 30077Taiwan,R.O.C.(e-mail:chienmin_lin@).Color versions of one or more of theﬁgures in this paper are available online at .Digital Object Identiﬁer10.1109/TADVP.2007.901595with some speciﬁc structures.Hybrid techniques,which com-bine the desirable features of the FDTD and other numerical schemes,are therefore being developed to improve the simula-tion capability in solving many realistic problems.First,the FDTD(2,4)method with a second-order accuracy in time and a fourth-order accuracy in space was incorporated to tackle the subgridding scheme[3]and a modiﬁed form was employed to characterize the electrically large structures with extremely low-phase error[4].Second,the integration with the time-domain method of moments was performed to analyze the complex geometries comprising the arbitrary thin-wire and inhomogeneous dielectric structures[5],[6].Third,theﬂexible ﬁnite-element time-domain(FETD)method was introduced locally for the simulation of structures with curved surfaces [6]–[8].With the advent of high-speed digital era,the simultaneous switching noise(SSN)on the dc power bus in the multilayer printed circuit boards(PCBs)causes paramount concern in the signal integrity and power integrity(SI/PI)along with the electromagnetic interference(EMI).One potential excitation mechanism of this high-frequency noise is from the signal traces which change layers through the via transition[9]–[11]. In the past,the transmission-line theory and the two-dimen-sional(2-D)FDTD method were combined successfully to deal with the parallel-plate structures having single-ended via transition[12],[13].Recently,the differential signaling has become a common wiring approach for high-speed digital system designs in beneﬁt of the higher noise immunity and EMI reduction.Nevertheless,for the real layout constraints,the common-mode currents may be generated from various imbal-ances in the circuits,such as the driver-phase skew,termination diversity,signal-path asymmetries,etc.Both the differential-and common-mode currents can inﬂuence the dc power bus, resulting in the SSN propagating within the planes.While applying the traditional method to manage this case,it will need a muchﬁner FDTD mesh to accurately distinguish the close signals transitioning through the planes.Such action not only causes the unnecessary waste of computer memory but also takes more simulation time.In order to improve the computa-tional efﬁciency,this paper incorporates the FETD method to the small region with two or more signal transitions inside,while the other regions still remain with the coarser FDTD grids.While the telegrapher’s equations of coupled transmission lines are further introduced to the hybrid FETD/FDTD techniques,the1521-3323/$25.00©2007IEEEFig.1.A typical four-layer differential-via structure.SI/PI co-analysis for differential traces through the planes can be accomplished as demonstrated in Section II and the numerical results are shown in Section III.For a group of signal vias,the proposed techniques can also tell which kind of signal alloca-tion to achieve the best performance as presented in Section III. Section IV thus correlates the measurement results and their comparisons,followed by brief conclusions in Section V.II.S IMULATION M ETHODOLOGYA typical differential-via structure in a four-layer board is il-lustrated in Fig.1.Along the signal-ﬂow path,the whole struc-ture is divided into three parts:the coupled traces,the cou-pled-via discontinuities,and the parallel plates.This section will present how the hybrid techniques integrate the three parts to proceed with the SI/PI co-simulation.At last,the stability consideration and computational complexity of the hybrid tech-niques are discussed as well.A.Circuit SolverWith reference to Fig.2,if the even/odd mode propagation coefﬁcients and characteristic impedances are given,it is recog-nized that the coupled traces can be modeled by theequivalentladder circuits,and the lossy effects can be well approxi-mated with the average values ofindividualand overthe frequency range of interest.The transient signal propagationis thus characterized by the telegrapher’s equations with the cen-tral-difference discretization both in time and space domains.The approach to predict the signal propagation through the cou-pled-via discontinuities is similar to that through the coupledtraces except for the difference of model-extracting method.To characterize the coupled-via discontinuities as depicted inFig.1,the structure can be separated into three segments:the viabetween the two solid planes,and the via above(and under)theupper(and lower)plane.Since the time delay of signals througheach segment is much less than the rising edge of signal,the cou-pled-via structure can be transformed into a SPICE passive net-work sketched in Fig.3by full-wave simulation[14],whererepresents the voltage of SSN induced by thecurrent on Ls2.By linking the extracted circuit models of coupled-via disconti-nuities,both the top-and bottom-layer traces together with suit-able driving sources and load terminations,the transient wave-forms throughout the interconnects are then characterized andcan be used for the SIanalyses.Fig.2.The k th element of equivalent circuit model of coupled transmissionlines.Fig.3.Equivalent circuit model of coupled-via structures.B.Plane SolverAs for the parallel-plate structure,because the separationbetween two solid planes is much smaller than the equiva-lent wavelength of signals,the electromagneticﬁeld inside issupposed to be uniform along the vertical direction.Thence,the2-D numerical technique can be applied to characterizethe SSN effects while the FETD method is set for the smallregion covering the signal transitions and the FDTD scheme isconstructed in the most regular regions.The FETD algorithm[15]starts from Maxwell’s two curl-equations and the vector equation is obtainedbyin(1)whereand denote the electricﬁeld and current density,re-spectively,in the losslessvolume.Applying the weak-formformulation or the Galerkin’s procedure to(1)gives(2)where is the weighting function that can be arbitrarily de-ﬁned.In use of theﬁnite-element method,the variational for-mula is thus discretized to implement the later numerical com-putation.In the present case,the linear basis function is chosento express theﬁelds inside each triangular element.After takingthe volume integration over each element and assembling theFig.4.FEM mesh in the source region and its interface with the FDTD grids. integrals from all the elements,(2)can be simpliﬁed into a ma-trix formof(3)whereand are the coefﬁcient vectors of electricﬁeld andcurrent density,respectively.In addition,the values of all matrixelements in(3)are formulatedasand(4)For the mesh proﬁle as illustrated in Fig.4,the FETD re-gion is chosen to be a block replacing the prime FDTD regioninto which the via transition penetrates.This is an initial valueproblem in time with thepreviousand being theinitial conditions as well as the boundary value problem in spacewith being Dirichlet boundary condition.To solve theinitial value problem in(3),the time derivative of electricﬁeldis approximated by the central difference,thatis(5)As for the electricﬁeld in the second term of(3),it can be for-mulated by the Newmark–Beta scheme[16]to be readas(6)Fig.5.Simulationﬂowchart of hybrid FETD and FDTD techniques to performthe SI/PI co-analysis for the coupled-via structure as illustrated in Fig.1.Moreover,in the triangular elements with the via transitioninside,the term in(3)as expressedbygridarea(7)is needed to serve as the excitation of the parallel-plate structurewith thecurrent shown in Fig.3through the via structurebetween Layers2and3.It is worth noting that the via transitionshould be placed on the bary-center of each triangular elementto achieve better accuracy.The hand-over scheme for theﬁeld in the overlapped region ofFDTD and FETD can be depicted in Fig.5.Given the boundaryﬁeld calculated by the FDTD algorithm at the timestep,all theﬁeld in the FETD region can be acquiredthrough the matrix solution of(3).The SSNvoltage in Fig.3is then determinedby(8)where is the averaging value of nodal electric-ﬁeldsenclosing the via transition,and is the separation between theplanes.Onceand at the FETD mesh nodes(node1,2,3,and4in Fig.4)become available,together with the ob-tained voltage/current values from the circuit solver and electric/magneticﬁelds of the FDTD region,the hybrid time-marchingscheme for the next time step can be implemented and so on.As a result of using the integrated schemes,thecurrent,arisen from the input signal through the via structure,can havethe ability to induce the voltage noise propagating within theFig.6.Physical dimensions of coupled traces and via pair.(a)Top view (Unit =mil ).(b)Side view.parallel plates.After a period of time,owing to the plane reso-nance and return path,the induced noise will cause the unwanted voltage ﬂuctuation on the coupled traces by the presence of the ﬁnite SSNvoltage .C.Stability Problem and Computational Complexity It is not dif ﬁcult to manifest that the FETD algorithm is un-conditionally stable.Substituting (5),(6),and (7)into (3)yields the following differenceequation:(9)where(10)the superscript “1”denotes the matrix inverse and thefactorgridareaWithout loss of generality,the time-stepping scheme in (9)is restatedas(11)Applyingthe -transform technique to (11)and solvingfor,de ﬁned asthe -transformof ,the resultreads(12)along with thedependent ,de ﬁned asthe -transformof in (11).Regardless of the timestep ,it can be easily de-duced that the poles of (12)is just on the unit circleof plane.This proves that the time marching by (9)is absolutely stable.The stability condition of these hybrid techniques is thus gov-erned by the transmission-line theory and the FDTD algorithm in the regular region,which are already known.Concerning the computational complexity,because of the consistence of simulation engines used for the circuitsolver,parison of differential-mode S -parameters from HFSS simulation and the equivalent circuit as depicted in Fig.3.the only work is to compare the ef ﬁciency of the hybrid FETD/FDTD technique with that of the traditional FDTD method.In use of only the FDTD scheme for cell discretization,the grid size should be chosen at most the spacing between the adjacent via transitions.However,as depicted in Fig.4,the hybrid techniques adopting the FEM mesh for the source region exhibit the great talent to segment the whole plane with the coarser FDTD grids.Owing to the sparsity of the FETD matrices in (4)and the much smaller number of unknowns,the computational time needed for each FETD operation can be negligible.The complexity of the hybrid techniques is therefore dominated by the FDTD divisions in the regular region.It is ev-ident that the total simulation time of the 2-D FDTD algorithmis,where denotes the number of the division in the whole space [7].The coarser the FDTD grids,the smaller the number of the grids and unknowns.Hence,the present hybrid techniques can preserve high accuracy without sacri ﬁcing the computational ef ﬁciency.III.N UMERICAL R ESULTSA.Coupled via TransitionConsider the geometry in Fig.1but with the coupled-via structure being 2cm away from the center of parallel plates,which is set as the origin ofthe–plane.The size of the plane is1010cm and the separation between the two metal planes is 20mils(0.05cm).The physical dimensions of the coupled traces and via pair are depicted in Fig.6.After extractingthe -parameters from the full-wave simulation,their equivalent circuit models of coupled-via structures as sketched in Fig.3can be thus constructed.In Fig.7,it is found that the differen-tial-mode -parameters of equivalent circuit models are in good agreement with those from the HFSS simulations [14]and the extracted parasitic values of inductive and capacitive lumped-el-ements are also listed in the attached table.The top-layer coupled traces are driven by differential Gaussian pulses with the rise time of 100ps and voltage ampli-tude of 2V while the traces are terminated with the matchedFig.8.Simulated TDR waveforms on the positive-signaling trace.(a)Late-time response for the signal skew of 10ps excluding the multire ﬂection phe-nomenon of common-mode signal.(b)Late-time response while no signal skew.TABLE IC OMPARISON OF C OMPUTATIONAL C OMPLEXITY B ETWEEN THE T WO M ETHODS(T IME D URATION =2:5ns)(CPU:Intel P43.0GHz,RAM:2GHz)loads at their ends.For simplicity,the transmission-line losses are not considered in the following analyses for the transient responses.By using the same mesh discretization as illustrated in Fig.4,the resultant segmentation for the plane con ﬁnes the ﬂexible FEM mesh in the vicinity of via transitions and the coarser FDTD division with the size of22mm elsewhere.Employing the perfect magnetic conductors for boundary conditions of the parallel-plate structure,the simulated TDR waveforms with and without the signal skew on the posi-tive-signaling trace are presented in Fig.8.In comparison of hybrid FETD/FDTD techniques and ﬁner FDTD method with center-to-center via spacing(0.66mm)as the grid size,the simulation results are in good agreement.Note that the voltage ﬂuctuation before 900ps is induced by the incident signal passing through the coupled-via structure while the occurrence of late-time response is accompanied by the parallel-plate resonances.As for the signal skew of 10ps,the voltage level of late-time response is found to be greater than that of no signal skew because of the existence of common-mode currents produced by the timing skew of differential signals.Moreover,the simulation time of both methods should be pro-portional to the number of grids multiplied by the total time steps.As the physical time duration is ﬁxed,the decrease of the FDTD division size would correspond to the increase of thetotalFig.9.Parallel plane with three current sources inside.(a)3-D view.(b)Zoom-in view of three sources on the plane in (a).(c).FETD/FDTD meshdiscretization.Fig.10.Simulated noise waveforms at the preallocated probe in reference to Fig.9(a).time steps.Consequently,as shown in Table I,it is demonstrated that the computational ef ﬁciency of the hybrid techniques is in-deed much better than that of the ﬁner FDTD method.B.Multiple Source TransitionIn addition to a pair of differential-via structure,there can be a group of signaling vias distributed in the various regions of planes.Considering the parallel-plate structure in Fig.9(a),three current sources are distributed around the center (0,0)and a probe is located at (1mm,9mm)to detect the voltage noise induced on the planes.The FEM meshes for the source region and the interface with the FDTD region are shown inFig.11.Parallel-plate structure with two differential pairs of current sources inside in reference to Fig.9(a).(a)Two differential pairs of sources on the plane in Fig.9(a).(b)FETD/FDTD meshdiscretization.parison of the simulated noise waveforms between three cases of differential-sources on the plane as in Fig.9(a).Fig.9(c).The current sources are Gaussian pulses with the rise time of 100ps and different current amplitudes of 0.5,0.25,and 0.3A.With the same settings of boundary conditions,the simulated voltage noise waveforms at the preallocated probe re-ferred to Fig.9(a)are presented in Fig.10.It is indicated that the hybrid FETD/FDTD techniques still reserves the great accuracy in predicting the traveling-wave behavior of plane noise.In the modern digital systems,many high-speed devices employ the multiple differential-traces for the purpose of data transmission.These traces are usually close to each other and may simultaneously penetrate the multilayered planes through via transitions.Hence,it is imperious for engineers to know how to realize the best power integrity by suitably arranging the positions of differential vias.Reconsidering the parallel plates in Fig.9(a),instead,two dif-ferential-current sources around the center and the probe is re-located at (25mm,25mm)as shown in Fig.11along with their corresponding mesh pro ﬁle.After serving for the same Gaussian pulses as input signals,the simulated waveformsatFig.13.At time of 400ps,the overall electric-ﬁeld patterns of three cases of differential-source settings in reference to Fig.12.(a)Case 1:one pair of dif-ferential sources.(b)Case 2:two pairs of differential sources with the same polarity.(c)Case 3:two anti-polarity pairs of differential sources.the probe are presented in Fig.12while three cases of source settings are pared with the noise waveform of one pair of differential sources,the signal allocations of mul-tiple differential-sources diversely in ﬂuence the induced voltage noise.For the more detailed understanding,Fig.13displays the overall electric-ﬁeld patterns at the time of 400ps for three casesFig.14.Speci ﬁcations and measurement settings of test board.(a)Top view.(b)Sideview.parisons between the simulated and measured waveforms at both the TDR end and the probe as in Fig.14.(a)The TDR waveforms.(b)The waveforms at the probe.of differential-source settings on the plane.Note that the out-ward-traveling electric ﬁeld of Case 3(the differential-sources with antipolarity)is the smallest ﬂuctuation since the appear-ance of two virtual grounds provided by the positive-and-nega-tive polarity alternates the signal allocation.IV .E XPERIMENTAL V ERIFICATIONIn order to verify the accuracy of hybrid techniques,a test board was fabricated and measured by TEK/CSA8000B time-domain re ﬂectometer.The designed test board comprises the single-ended and differential-via structures,connecting with the corresponding top-and bottom-layer traces.The design speci ﬁ-cations and measurement settings of test board are illustrated in Fig.14.To perform the time-domain simulation,the launching voltage sources are drawn out of re ﬂectometer.As thedrivingFig.16.Frequency-domain magnitude of the probing waveforms corre-sponding to Fig.15(b)and the plane resonances.signals pass through the differential vias,the parallel-plate structure is excited,incurring the SSN within the ter,the quiet trace will suffer form this voltage noise through the single-ended via transition.After extracting the equivalent circuit models of coupled-via structures and well dividing the parallel plates,the SI/PI co-analysis for test board can be achieved.Simulation results are compared with the measure-ment data as shown in Fig.15accordingly.As observed in Fig.15(a),the differential signals have the in-ternal skew of about 30ps and the bulgy noise arising at about 500ps is due to the series-wound connector used in the measure-ment.The capacitive effect of via discontinuities is occurred at about 900ps,while the deviations between the simulation and measurement are attributed to the excessive high-frequency loss of input signals.For the zoom-in view of probing waveforms as in Fig.15(b),it is displayed that the comparison is still in good agreement except for the lossy effect not included in the time-domain simulation.Applying the fast Fourier transform,the frequency-domain magnitude of probing waveforms is ob-tained in Fig.16.In addition to the similar trend of time-domain simulation and measurement results,the peak frequencies cor-respond to the parallel-plate resonances of test board exactly.Hence,the exactitude of the proposed hybrid techniques can be veri ﬁed.V .C ONCLUSIONA hybrid time-domain technique has been introduced and applied successfully to perform the SI/PI co-analysis for the differential-via transitions in the multilayer PCBs.The signalpropagation on the differential traces is characterized by the known telegrapher’s equations and the parallel-plate structure is discretized by the combined FETD/FDTD mesh schemes.The coarser FDTD segmentation for most of regular regions inter-faces with an unconditionally stable FETD mesh for the local region having the differential-via transitions inside.In use of hybrid techniques,the computational time and memory requirement are therefore far less than those of a traditional FDTD space with theﬁner mesh resolution but preserve the same degrees of numerical accuracy throughout the simulation.In face of the assemblages of multiple signal transitions in the speciﬁc areas,the hybrid techniques still can be adopted by slightly modifying the mesh proﬁles in the local FETD re-gions.Furthermore,the numerical results demonstrate that the best signal allocation for PI consideration is positive-and-nega-tive alternate.Once the boundary conditions between the FETD and FDTD regions are well deﬁned,it is expected that the hy-brid techniques have a great ability to deal with the more real-istic problems of high-speed interconnect designs concerned in the signal traces touted through the multilayer structures.R EFERENCES[1]K.S.Yee,“Numerical solution of initial boundary value problemsinvolving Maxwell’s equations in isotropic media,”IEEE Trans.Antennas Propag.,vol.AP-14,no.3,pp.302–307,May1966.[2]K.S.Kunz and R.J.Luebbers,The Finite Difference Time DomainMethod for Electromagnetics.Boca Raton,FL:CRC,1993,ch.2,3.[3]S.V.Georgakopoulos,R.A.Renaut,C.A.Balanis,and C.R.Birtcher,“A hybrid fourth-order FDTD utilizing a second-order FDTD subgrid,”IEEE Microw.Wireless Compon.Lett.,vol.11,no.11,pp.462–464,Nov.2001.[4]M.F.Hadi and M.Piket-May,“A modiﬁed FDTD(2,4)scheme formodeling electrically large structures with high-phase accuracy,”IEEETrans.Antennas Propag.,vol.45,no.2,pp.254–264,Feb.1997.[5]A.R.Bretones,R.Mittra,and R.G.Martin,“A hybrid technique com-bining the method of moments in the time domain and FDTD,”IEEEMicrow.Guided Wave Lett.,vol.8,no.8,pp.281–283,Aug.1998.[6]A.Monorchio,A.R.Bretones,R.Mittra,G.Manara,and R.G.Martin,“A hybrid time-domain technique that combines theﬁnite element,ﬁ-nite difference and method of moment techniques to solve complexelectromagnetic problems,”IEEE Trans.Antennas Propag.,vol.52,no.10,pp.2666–2674,Oct.2004.[7]R.-B.Wu and T.Itoh,“Hybridﬁnite-difference time-domain modelingof curved surfaces using tetrahedral edge elements,”IEEE Trans.An-tennas Propag.,vol.45,no.8,pp.1302–1309,Aug.1997.[8]D.Koh,H.-B.Lee,and T.Itoh,“A hybrid full-wave analysis of via-hole grounds usingﬁnite-difference andﬁnite-element time-domainmethods,”IEEE Trans.Microw.Theory Tech.,vol.45,no.12,pt.2,pp.2217–2223,Dec.1997.[9]S.Chun,J.Choi,S.Dalmia,W.Kim,and M.Swaminathan,“Capturingvia effects in simultaneous switching noise simulation,”in Proc.IEEEpat.,Aug.2001,vol.2,pp.1221–1226.[10]J.-N.Hwang and T.-L.Wu,“Coupling of the ground bounce noise tothe signal trace with via transition in partitioned power bus of PCB,”in Proc.IEEE pat.,Aug.2002,vol.2,pp.733–736.[11]J.Park,H.Kim,J.S.Pak,Y.Jeong,S.Baek,J.Kim,J.J.Lee,andJ.J.Lee,“Noise coupling to signal trace and via from power/groundsimultaneous switching noise in high speed double data rates memorymodule,”in Proc.IEEE pat.,Aug.2004,vol.2,pp.592–597.[12]S.-M.Lin and R.-B.Wu,“Composite effects of reﬂections and groundbounce for signal vias in multi-layer environment,”in Proc.IEEE Mi-crowave Conf.APMC,Dec.2001,vol.3,pp.1127–1130.[13]“Simulation Package for Electrical Evaluation and Design(SpeedXP)”Sigrity Inc.,Santa Clara,CA[Online].Available:[14]“High Frequency Structure Simulator”ver.9.1,Ansoft Co.,Pittsburgh,PA[Online].Available:[15]J.Jin,The Finite Element Method in Electromagnetics.New York:Wiley,1993,ch.12.[16]N.M.Newmark,“A method of computation for structural dynamics,”J.Eng.Mech.Div.,ASCE,vol.85,pp.67–94,Jul.1959.Wei-Da Guo was born in Taoyuan,Taiwan,R.O.C.,on September25,1981.He received the B.S.degreein communication engineering from Chiao-TungUniversity,Hsinchu,Taiwan,R.O.C.,in2003,andis currently working toward the Ph.D.degree incommunication engineering at National TaiwanUniversity,Taipei,Taiwan,R.O.C.His research topics include computational electro-magnetics,SI/PI issues in the design of high-speeddigitalsystems.Guang-Hwa Shiue was born in Tainan,Taiwan,R.O.C.,in1969.He received the B.S.and M.S.de-grees in electrical engineering from National TaiwanUniversity of Science and Technology,Taipei,Taiwan,R.O.C.,in1995and1997,respectively,and the Ph.D.degree in communication engineeringfrom National Taiwan University,Taipei,in2006.He is a Teacher in the Electronics Depart-ment of Jin-Wen Institute of Technology,Taipei,Taiwan.His areas of interest include numericaltechniques in electromagnetics,microwave planar circuits,signal/power integrity(SI/PI)and electromagnetic interference (EMI)for high-speed digital systems,and electrical characterization ofsystem-in-package.Chien-Min Lin(M’92)received the B.S.degreein physics from National Tsing Hua University,Hsinchu,Taiwan,R.O.C.,the M.S.degree in elec-trical engineering from National Taiwan University,Taipei,Taiwan,R.O.C.,and the Ph.D.degree inelectrical engineering from the University of Wash-ington,Seattle.He was with IBM,where he worked on the xSeriesserver development and Intel,where he worked onadvanced platform design.In January2004,he joinedTaiwan Semiconductor Manufacturing Company, Ltd.,Taiwan,as a Technical Manager in packaging design and assembly vali-dation.He has been working on computational electromagnetics for the designs of microwave device and rough surface scattering,signal integrity analysis for high-speed interconnect,and electrical characterization ofsystem-in-package.Ruey-Beei Wu(M’91–SM’97)received the B.S.E.E.and Ph.D.degrees from National Taiwan Univer-sity,Taipei,Taiwan,R.O.C.,in1979and1985,respectively.In1982,he joined the faculty of the Departmentof Electrical Engineering,National Taiwan Univer-sity,where he is currently a Professor and the De-partment Chair.He is also with the Graduate Instituteof Communications Engineering established in1997.From March1986to February1987,he was a Vis-iting Scholar at the IBM East Fishkill Facility,NY. From August1994to July1995,he was with the Electrical Engineering Depart-ment,University of California at Los Angeles.He was also appointed Director of the National Center for High-Performance Computing(1998–2000)and has served as Director of Planning and Evaluation Division since November2002, both under the National Science Council.His areas of interest include computa-tional electromagnetics,microwave and millimeter-wave planar circuits,trans-mission line and waveguide discontinuities,and interconnection modeling for computer packaging.。

格伦艾尔圆形连接器术语和定义说明书

Essential Connector Terms and Deﬁnitions for Speciﬁers of Interconnect Wiring SystemsBack-Mounted: A connector design used in panel or box applications in which the mounting ﬂange is located inside the equipment enclosure.Bayonet Coupling: A mating design utilizing pins on the receptacle and ramps on the plug for quick-connect and disconnect coupling. “Reverse” bayonet puts the pins on the plug and ramps on the receptacle.Circular Connector:Any of a thousand ﬂavors of mulitpin interconnects with cylindrical contact housings and circular contact interface geometries. Circular connectors are selected for ease of engagement and disengagement, their ability to conveniently house different types of contacts, their wide range of allowable contact voltages and currents, their ease of environmental sealing and their rugged mechanical performance. In military and other high-rel applications, the MIL-C-5015 and D38999 are the most commonly speciﬁed types.Note: A disadvantage of the circular design is loss of panel space when used in arrays.Closed Entry: A contact cavity design in which the entry diameter of the socket insulator is smaller than the O.D. of the socket contact. Closed entry limits the size or position of the mating contact to a maximum dimension.Connector Body:The metal or plastic shell of a connector. Its main purpose is to house the contacts, maintain their position and shield them from dust, dirt, moisture, and electrical interference. Coaxial Contacts (and Cable):A contact with inner and outer conductive elements separated by a center dielectric element. Coaxial contacts terminate coaxial cable, and are employed in high bandwidth, high-frequency applications such as video and audio. The cable offers a closed, controlled impedance medium for the transmission of RF energy. It also provides high frequency performance and RFI shielding.Contact:The conductive element in a connector. Contacts mate mechanically and electrically to transmit signals and/or power across a connector interface. Crimp style contacts are the most common type found in high-reliability cylindrical connectors. Male contacts are sometimes referred to as leads, posts or pins. Female contacts are universally known as sockets. Contact Arrangement or Pattern:The gauge, number, spacing and arrangement of contacts in a connector. Contact arrangement selections are based on the current and voltage requirements of the application, and the space available for the connector package.Contact Engaging and Separating Force:T ensile force required to engage or separate mating contacts. Measured in ounces, the force increases with the number of contacts and with contact size. Contact (or Circuit) Identiﬁer: Wiring schematics identify and label each and every circuit with numbers, letters or special codes. On the connector, this process is maintained by marking small numbers or letters next to each contact cavity on the connector.Contact Resistance:The measure of electrical resistance across a pair of fully mated contacts. Measured in ohms or millivolt drop at a speciﬁed current, contact resistance is affected by normal force (the static force on the contact interface), plating quality and the physical geometry of the contact.Contact Retainer:A locking clip or tang used to secure a crimp contact in place within the connector insert. Contact retention speciﬁcations deﬁne the force required to remove a properly seated contact for each class of connector.Contact Retention:The pressure a contact can withstand, in either direction, without being dislodged from the retaining clip which holds it within the connector.Contact Size:An assigned number denoting the outside diameter of the engaging end of the pin contact. The larger the number, the smaller the size. Contact Spacing:Also referred to as pitch, the distance, center-to-center, between adjacent contacts.Coupling Ring:An accessory feature of the connector plug which aids in mating and unmating plugs and receptacles and prevents decoupling of the connector. Self-locking coupling rings are used for high-vibration applications.Crimp: The physical compression (deformation) of a contact barrel around a conductor in order to make an electrical connection.Crimp Contact: A connector pin or socket, shipped loose with the connector body, and designed to be crimped onto the end of the wire conductor with a special tool. Often referred to as “crimp and poke” contacts, the terminated contact is poked into the connector body either by hand, or in the case of small gauge wires, with the aid of a hand-held tool. The ease of assembly and maintenance afforded by crimp contacts is preferred for aerospace and other high reliability applications not requiring a hermetic seal. Dielectric: A material having electrical insulating properties, such as the contact insulator in a connector or the jacketing on a wire.Electrical Connector: A separable device which provides mechanical and electrical contact between two elements of an electronic system without unacceptable signal distortion or power loss. Environmentally Sealed:Connectors and backshells designed to prevent ﬂuids, moisture, air or dust from degrading the performance of electrical contacts and conductors. “Environmental” components typically use gaskets, grommets, potting materials or interfacial and O-ring seals to prevent the penetration of foreign substances into the body of the part.Filter Contact or Filter Connector: Contact design which provides EMI suppression in addition to its normal function of transmitting electrical energy. Filtered connectors are typically speciﬁed for high-speed signal paths. Filtering is accomplished through the integration of capacitors into the contact to separate high-frequency noise from low-frequency signals. Firewall Connector: A class of high-reliability, feed-through connectors designed to prevent ﬁre or sparks from penetrating through a sealed bulkhead. Firewall connectors must continue to function for a speciﬁc period of time when exposed to ﬁre, and are typically speciﬁed in military applications such as ﬁghter jets and Navy ships.Flange:The integral mounting plate on some bulkhead and feed-through connectors used to attach the connector to the chassis or panel. The connector ﬂange is typically square, and is mounted to the panel with threaded screws.Front Mounted: A connector design used in panel or box applications in which the mounting ﬂange is located on the inside or outside of the equipment enclosure.Front Release: “Crimp and poke” style contacts may be removed from the connector for maintenance using a special hand-held tool. The proper insertion and removal tool must be used at all times. In front release designs, the tool is inserted into the mating face of the connector to disengage the contact from its retaining clip. The disengaged contact is then removed from the back (cable-side) of the connector by lightly pulling on the attached wire.Grommet:An elastomeric seal used on the back side of a connector to seal out ﬂuids, moisture, air and dust.Grounding (or EMI) Fingers: A set of spring ﬁngers in certain connectors, used to facilitate shell to shell grounding and enhance EMI performance. The grounding ﬁngers engage before contact mating and remain engaged until after contact separation. Guide Pins:Metal posts) with a rounded or pointed tip which projects beyond the contact interface, used to assist in the correct alignment and mating of connector shells and contacts. The post mates with a corresponding cavity on the mating connector before contacts are allowed to engage. Guide pins are typically used in rack and panel packaging and in other “blind-mate” applications. Guide pins can also be used to insure correct polarization.Hermetic Connector:A class of connectors equipped with a pressure seal for use in maintaining pressurized application environments. The hermetic element of the connector is typically fabricated from vitreous glass.Insert: A molded piece of dielectric material that ﬁts inside the connector shell and supports the connector contacts. Inserts are tooled for each shell size, and contact arrangement. Inserts made from resilient materials also contribute to environmental properties. Insulation Displacement:Forcing an insulated wire into a terminal slot smaller than the conductor diameter, displacing the insulation to make electrical contact.Interfacial Seal: An elastomeric seal providing overall sealing of the mated connectors and their individual contacts. “Cork & bottle” style seals feature a raised shoulder around each pin contact that compresses into a corresponding hole on the socket contact insulator. Key: A short pin (sometimes referred to as a “dog” by crusty old machinists) which slides into a corresponding slot or keyway to guide the plug and receptacle together during mating. The principal function of the key is to insure polarization of the mating contacts. Levels of Interconnection:A classiﬁcation system for connectors deﬁning connector types in terms of interconnect system function. The levels of most use include Level 4 (subassembly to subassembly), Level 5 (subassembly to I/O) and Level 6 (system to system). The lower levels (1, 2 and 3) all concern interconnection inside the microscopic world of printed circuit boards.Mating and Unmating Force: The force required to join and separate two halves of a connector. This is the sum of contact engaging forces plus any additional force necessary to overcome minor misalignment of connector halves and any dimensional variations in the connector shells.Normal Force:A measure of the spring pressure applied perpendicularly to contacts in mated connectors. The force of this spring pressure creates the gas-tight interface between contact surfaces which prevents corrosive contaminants from penetrating or forming between the contacts. High normal force reduces resistance across the contacts, but contributes to contact wear and may overstress the connector housing and even damage the spring properties of contact sockets. However, maintaining a constant normal force is an essential requirement for electrical integrity in the connector. Package Size: The length, width and height of the connector; or alternatively the dimensions of the entire interconnect system. Package size is an issue in many applications where system miniaturization, faster operating speeds, higher operating temperatures and other application requirements place new demands on the envelope of space the connector and its accessories may occupy.Plug: The half of a connector pair which is designed to attach to a wire or cable; as opposed to the receptacle half which is typically mounted to a bulkhead, panel or box. Even though we usually picture plugs as having male (pin) contacts, they can in fact house any type of contact—pins, sockets or even both. Thus it is the design and location of the connector which makes it a plug, not the gender of its contacts.Polarize:Design features on mating connectors—such as keyways or shell geometries—that insure connectors can be mated in only one possible orientation. The shape of a D-Sub connector shell, for example, assures that the two halves of the connector can be mated in only one way.Potting:The permanent sealing of the cable end of a connector with a compound or material to exclude moisture or to provide a strain relief. Glenair typically uses epoxy compounds for this purpose because of their dimensional stability and high-temperature resistance.Rear Release: “Crimp and poke” style contacts (see Crimp Contacts above) may be removed from the connector for maintenance using a special hand-held tool. The proper insertion and removal tool must be used to install and remove wires from such crimp and poke connectors. In rear release designs, the tool is inserted into the rear (cable side) of the connector to disengage the contact from its retaining clip. The disengaged contact is then removed from the connector by lightly pulling on the attached wire. Receptacle:The other half of the connector pair, designed to be mounted—with jam nut ﬁttings or other fastener hardware—to a bulkhead, panel or box. In-line receptacles are also available for cable-to-cable connections. As with the plug, it is the design and location of the receptacle in the system, not the gender of its contacts, which makes it a receptacle.Rectangular Connector:Any of the thousands of multipin interconnects with rectangular shell housings and rectangular insert interface geometries. Rectangular connectors are typically mounted in rack and panel conﬁgurations in which large arrays of ﬁxed receptacle connectors are mated with plugs attached to a movable rack for efﬁcient utilization of space. D-Subminiatures are the world’s most common rectangular connectors.Scoop-proof: Scoop-proof connectors feature a nice, long shell on the receptacle which prevents damage to the exposed contact pins during mating. No matter how hard that swabbie tries, it is impossible to cock the mating plug so as to damage the pins or electrically short the contacts.Service Rating:Also called Current Rating, the maximum voltage or current load a connector is designed to carry during continuous, long-term use. Good engineering practice usually entails preliminary testing of connectors which will be operated with most or all contacts at the maximum rated load. Designers will often maximize contact and wire size in such situations.Solder Cup: A connector design that typically uses potting material to permanently afﬁx the contacts inside the connector shell. Termination of contact to wire is then accomplished by soldering the wire into the cup-like barrel on the back of the contact. In the United Kingdom it is important to pronounce the “l” in solder. Brits also prefer to say “bucket” rather than “cup” when specifying solder contacts. Surface Mount: A termination method in which solder “tails” or leads on the connector are soldered directly to a printed circuit board. In high-reliability commercial and military applications, surface mount receptacle connectors are typically limited to rectangular designs such as D-Subminiatures and Micro-D’s. But some surface-mount applications do use a cylindrical connector mounted to the box with ribbon cable or ﬂying leads soldered directly to the PCB. The reason here is to provide a low-resistance pathway to ground of the shielded cable. In severe EMI applications, it is less satisfactory to bring the shielded cable directly to the printed circuit board because of the difﬁculty in shielding out interference conducted along the cable.Termination:Termination is the physical act of attaching a wire conductor to a contact. Effective termination contributes to electrical performance and to the durability and reliability of the interconnect system. Common termination methods include crimp, insulation displacement, surface mount, and soldering. Termination can also refer to the mechanical attachment of EMI shielding to the connector backshell.Threaded Coupling: An interconnect mating design which utilizes a threaded nut on the plug, and a corresponding set of threads on the receptacle, to mate the pair of components. The coupling nut is usually equipped with ﬂats or knurling for easy assembly. Different thread types, proﬁles and geometries provide different functionality. “Buttress” threads, for example, are often speciﬁed on plastic connectors due to their enhanced tensile strength. The MIL-C-38999 Series III connector incorporates a triple-start threaded coupling mechanism for greater vibration protection and faster mating and unmating.Wiping Effectiveness: Maintaining a clean, metallic path is essential if contacts are to perform with low and stable contact resistance. Surface ﬁlms and contaminants are removed from the surface of plated contacts each time mating occurs. This displacement of surface contaminants during mating is called contact wiping. Wiping effectiveness depends on the contact geometry, engagement length and normal force. Interestingly, oxide ﬁlm does not form on gold plated contacts, so wiping pressure can be lighter to displace only the occasional surface contaminant.Wire Pull-Out Force: This deﬁnes the force required to separate a wire from a contact. In properly terminated crimp contacts, the wire will generally break before it pulls away from the contact.。

multisim 共模扼流圈

multisim 共模扼流圈英文版Multisim Common-Mode ChokeIn the realm of electronics, Multisim stands as a powerful tool for simulating circuits and electronic systems. Among the various components that can be simulated in Multisim, the common-mode choke, or common-mode inductor, plays a crucial role in filtering and suppressing unwanted noise and interference.A common-mode choke is a type of inductor designed to block or reduce common-mode currents, which are currents that flow in the same direction in two conductors. These currents are often caused by electromagnetic interference (EMI) or electromagnetic compatibility (EMC) issues. By effectively blocking these currents, common-mode chokes improve the overall performance and reliability of electronic systems.In Multisim, simulating a common-mode choke allows engineers and hobbyists to analyze its impact on a circuit's behavior. By inserting a common-mode choke into a simulated circuit, it's possible to observe how it affects the flow of currents and how it mitigates EMI or EMC issues. This simulation capability is invaluable in the design and optimization of electronic systems.Moreover, Multisim's simulation of common-mode chokes enables users to experiment with different configurations and parameters, such as inductance values and circuit arrangements. This flexibility allows for a more comprehensive understanding of how common-mode chokes work and how they can be optimized for specific applications.In conclusion, Multisim's simulation of common-mode chokes is a powerful tool for electronic design and analysis. It enables users to gain valuable insights into the behavior of these components and how they can be effectively used to improve the performance and reliability of electronic systems.中文版Multisim共模扼流圈在电子领域，Multisim是一款强大的电路和电子系统仿真工具。

飞兆关于功率转换器的电磁兼容性设计指导

© 2004 Fairchild Semiconductor Corporation Fairchild Semiconductor Application NoteApril 2004Revised April 2004AN-4145 Electromagnetic Compatibility for Power ConvertersAN-4145Electromagnetic Compatibility for Power ConvertersElectromagnetic Compatibility (EMC) has become a household name of the past decade. In the mid 1990’s,Europe required a reduction on the level of radiated and conducted emission in products that were sold into the region. From that point on many products today have in their design cycle EMC testing.A common question asked is, what is EMC? EMC is the ability of a device, product, or system to operate properly in its intended electromagnetic environment (presence of EMI), without degradation and without being a source of interference. There are bodies that produce EMC stan-dards that must be followed such as IEC and CISPR.This application note speaks about EMC regulations deal-ing with both radiated and conducted emissions. Con-ducted emissions consist of both common mode and differential mode noise. In order to deal with common and differential mode noise, an AC power main filter is required and a description and example of one is provided. These noises can reside on the power lines entering the unit, but are also produced by internal switching devices.EMC RegulationsIn order to achieve a solid EMC design, one must under-stand the EMC requirements. The requirements that will follow do not deal with module power supplies; rather they deal with system level standards in both Europe and in North America.The International Electrotechnical Commission (IEC) is responsible for deriving the European requirements, in say-ing that, the Comite International Special des Perturbations Radioelectriques (CISPR) – International Special Commit-tee on Radio Interference is responsible for the EMC requirements with CISPR 22 defining the strictest limits on conducted emissions. These limits (conducted emissions)are described in the product standards EN 55022 (Figure 1) and EN 55011 (Figure 2). The class A and class B requirements on Figure 1 and Figure 2 refer to the indus-trial standard and the domestic standard respectively.Depending on the antenna used for detecting the noise,the European standards give two limits. The higher limit for a quasi-peak antenna and a lower limit for an average antenna, but both limits must be met for the equipment to pass the requirement. The FCC standards used in North America have similar specifications to the European EN requirements (see note below Figure 2). Two European standards that are used in testing power supplies are EN 55011 and EN 55022. Figure 3 and Figure 4 show the radiated levels of EN 55011 and the FCC part 15 subpart B (North America) respectively.In North America, radiated EMI is most often measured in the frequency range from 30 MHz to 10 GHz (according to the FCC), while conducted EMI is most often measured in the frequency range of several kHz to 30 MHz (according to the FCC).FIGURE 1. EN 55022 Conducted EmissionsFIGURE 2. EN55011/FCC Part 15 Subpart BConducted LevelsNote: After May 23, 2004 the FCC Part 15 Subpart B and the EN 55011 will have the same noise conduction level specification.FIGURE 3. EN 55011 Radiated Emissions at 3 meters 2A N -4145EMC Regulations (Continued)FIGURE 4. FCC Part 15 Subpart B Radiated Emissionsat 3 meters The goal here is to develop a system that can comply with some or all of the emissions presented above whether it is a stand alone device or incorporated into a larger system.Common Mode and Differential Mode NoiseThere are two major sources of noise, common mode and differential mode. Common mode noise (Figure 5) comes from common mode current. Common mode energy is common to both lines in a single phase system. This energy travels on all the lines, or wires, in the same direc-tion, and this energy is between all these wires and ground.Because the same level is on both wires at the same time,no attenuation is given by any device between the lines.FIGURE 5. Common Mode NoiseCommon mode noise from common mode current always exists on cables entering the device. One way to minimize these currents is to test the cables early on prototype mod-els (this gives the designer the ability to make any changes necessary before the design is finalized for production) and prior to performing EMC compliance testing. In a lot of cases if the device fails the common-mode current test, it will also fail the radiated emission test. The common mode current can be easily measured by using a high frequency clamp on current probe and a spectrum analyzer. A current probe with a response range of up to 250 MHz should be sufficient.Differential mode noise (Figure 6) is the opposite of com-mon mode noise. This noise is produced by current flowing along either the live or neutral conductor and returning by the other. This produces a noise voltage between the live and neutral conductors.FIGURE 6. Differential Mode NoiseAN-4145AC Power Line Main FilterFIGURE 7. Single Phase AC Line FilterAn example of a single phase AC line filter is shown in Fig-ure 7. Filters of this type are commonly used in reducing both differential and common mode noise from entering and leaving the power supply. The filter in Figure 7 has been broken up into different sections to help better describe its overall function.Note: Both Section A blocks and Section B blocks perform the same func-tion with the only difference being one is for noise entering the device where the other is used for noise exiting the device.BlocksSection AInductors L1/L2 and capacitor C1 represent a differential filter for any noise trying to enter the power supply. Differ-ential mode noise is produced by current flowing along either the line or neutral conductor and returning by the other. The combination of L1 and C1 or L2 and C1 repre-sent a voltage divider. Depending on the frequency of the noise, the capacitor C1 represents a smaller impedance (larger load) to the signal thereby reducing any noise on the line. As an example if the impedance of L1 is 10K and the impedance of C1 is 1K at a particular frequency, the noise passing through the filter would be a tenth of its origi-nal strength or a reduction of 20dB.Section BCapacitors C2 and C3 represent a common mode filter with a reference to ground. Common mode noise manifests itself as a current in phase with the live and neutral conduc-tors and returns via the safety earth. This produces a noise voltage between live/neutral and earth. With all C2, C3, C4,and C5 all being equal, any common mode noise on these lines will be shunted to ground.Note: Section B is not used in medical equipment due to leakage current.Section CSection C of Figure 7 represents the Zorro Inductor (com-mon mode choke) without a reference. The direction of each winding is chosen to give an opposing current flow so any noise present will be cancelled. Magnetic flux caused by common mode current is accumulated, producing impedance, thereby reducing any noise on the line. Since differential mode has currents running in different direc-tions, magnetic flux caused by differential mode current cancels each other, and impedance is not produced thereby having no effect.Note: Capacitors C1 and C6 are X Class capacitors, used to reduce differ-ential noise and are tested to withstand mains voltage. X Class capacitors usually run in the 0.01uF to 2uF range. Capacitors C2 through C5 are Y Class capacitors for common mode noise and are tested to ensure thatthey cannot fail to short circuit (more expensive than X Class). Y Class capacitors are smaller in value usually running between 0.002uF to 0.1uF.AC Power LineFilter Design Example(AD/DC Flyback Converter)Design Requirements:•Transformer turns ratio (a) = 10•Output Impedance (Zs) = 10Ω (load impedance, worst case for maximum output power)•Noise reduction required at 20 kHz = 35dB•Additional headroom for unknown frequency spike = 6dB •AC Line Frequency (Fl) = 60Hz•PWM Switching Frequency (Fs) = 100 kHzTo determine the values of the filter, the output load imped-ance must be recognized. In order to recognize this imped-ance the output load (worst case) must be reflected back to the primary across the transformer using equation 1.whereOn the input side, the filter will be designed for 10 times the line frequency (keeping the filter transparent to both the line and load), thereby resulting in a frequency of 600Hz. In saying this, the cutoff frequency (Fo) must not be below 600Hz. With a noise reduction of 41dB (35dB plus the 6dB of headroom) at 20 kHz, the designer divides 20 kHz by 2and subtracts 12dB from 41dB (see Table 1). Initially a sin-gle inductor will be used to see if this can be accomplished;if not a second series inductor will be needed. A single inductor will give a drop off of 12dB/octave or 40dB/decade. As shown in Table 1, a single inductor is sufficient for this design with the cutoff frequency (Fo) being 1.25kHz (above the minimum 600Hz limit).Zp =Primary Impedance Zs =Secondary Impedancea =Transformer Turns Ratio (Np/Ns) 4A N -4145AC Power Line Filter Design Example (AD/DC Flyback Converter)(Continued)TABLE 1. Input Inductor Determination Now that the cutoff frequency (Fo) is known, the value of the inductor can be created using equation 2.whereUsing Equation 3, one can determine the differential capacitance (Cd) required to complete the differential mode circuit (Section A).whereFor a balanced filter (an inductor on both the live and neu-tral lines), the value is divided by 2, giving 64mH. With the inductance being so large, two inductors will be used to reduce its size. Also an advantage to having more induc-tors is not only to reduce the inductance, but the Q of the filter decreases, thereby decreasing the risk of oscillations.Table 2 represents a second inductor added to the filter giv-ing a 24dB/octave reduction.TABLE 2. Addition of a Second Inductor Using Equation 4 and 5 the subsequent new inductor and capacitor values can be computed.whereAgain, for a balanced filter (an inductor on both the live and neutral lines), the result is divided by 2, giving 16mH.whereThe common mode Zorro inductor is the remaining device to be calculated. The Zorro inductor is calculated the same way in which inductor (L) was, but instead of starting off using the cutoff frequency (Fo), one uses the PWM switch-ing frequency (Fs) (see Table 3) and the same dB loss.Since two differential mode inductors are required, two Zorro inductors will be used to complete the filter.TABLE 3. Zorro Inductor Calculations Frequency (kHz)dB(Limit of Conducted Emissions)2041 (35dB plus 6 dB of headroom)10295172.551.25 (Fo)−7L =Differential InductorZp =Primary Impedance(reflected back from the secondary)Fo =Cutoff Frequency from Table 1L =Differential InductorZp =Primary Impedance(reflected back from the secondary)Frequency (kHz)dB(Limit of Conducted Emissions)2041 (35dB plus 6 dB of headroom)10175 (Fnew)−7Lnew =New Differential InductorZp =Primary Impedance(reflected back from the secondary)Fnew =Cutoff Frequency from Table 2Lnew =New Differential InductorZp =Primary Impedance(reflected back from the secondary)Frequency (kHz)dB(Limit of Conducted Emissions)10041 (35dB plus 6 dB of headroom)501725 (Foz)−7AN-4145AC Power Line Filter Design Example (AD/DC Flyback Converter)(Continued)Using Equations 6 and 7, the Zorro inductance (Lzorro)and Zorro capacitance (Czorro) can be found.wherewhereThe final design is shown in Figure 8.If there are problems at the high frequencies, ferrite beads can be added (ferrite beads act as resistors (50 to 200Ω) at low frequencies and inductors at high ones (30MHz)). If dif-ferential problems occur, increase the Lnew inductors some, or improve the quality of the Cdnew capacitance,they may have too much leakage at the frequency in ques-tion. Common mode problems can be combated by increasing Lzorro inductors.FIGURE 8. Final Filter DesignDesign Guide to Reduce Internal andExternal In Power ConvertersThere are three areas of noise generation in an AC to DC power supply:1.Any noise already present on the AC mains enteringthe power supply unit (common mode/differential mode)2.The switching frequency of the power supply (commonmode)3.The fast switching edges and ringing produced whenthe MOSFET is turned off (common mode)1) AC MainsWith noisy power main lines, an AC power line filter is used. When using an AC power line filter make sure that it is mounted as close as possible to where the AC power line enters the printed circuit board (PCB), see Figure 9.Also the ground connection to the filter should be as short as possible with many vias to the ground plane of the pri-mary side of the power supply.FIGURE 9. Grounding the Common Mode Capacitorsto the Ground Plane In order to reduce common mode and differential mode noise from leaving and entering the unit, an AC power line filter needs to be used. See section on AC Power Line Main Filter.Lzorro =Common Mode InductorZp =Primary Impedance(reflected back from the secondary)Foz =Cutoff Frequency from Table 3Lzorro =Common Mode InductorZp =Primary Impedance(reflected back from the secondary) 6A N -4145Design Guide to Reduce Internal and External In Power Converters(Contin-2) Switching Frequency of the Power SupplyJust like in a system that uses a system clock, many power supplies have a pulse width modulator (PWM) device that operates at a frequency that is used to control the output voltage. So where a system clock needs to be carefully laid out on a PCB, so does the PWM controller.In a flyback, forward or other topology design using a trans-former, it is important to make the trace from the primary winding to the drain of the switching MOSFET (either inter-nal or external) as wide and short as possible (see Figure 10). This reduces the inductance path thereby keeping the ringing to a minimum. A solid ground plane with a minimal number of holes is preferred to ground both the MOSFET and PWM controller too. There should always be a ground running parallel to the trace for current return (if stray capacitance is not a problem), if there still is a noise issue,one can minimize the drain trace capacitance to the trans-former by removing the ground plane from under the trace shown in Figure 10. There are already parasitic capacitors within the MOSFET switch structure that pump current to and from ground. If the ground plane is not removed below the “cross hatched ” trace, then additional current will be passed into the ground causing more common mode con-ducted noise.FIGURE 10. Reducing Drain Trace CapacitanceNote: Especially at higher frequencies, example 500kHzThe source of the MOSFET doing the switching must have a solid connection to the primary side ground plane. In order to accomplish this make a large landing pad for the ground terminal so that a proper number of vias (depend-ing on the sinking current) can be used to make a solid connection to the ground plane, see Figure 11.FIGURE 11. Connecting the Source of an Internal MOSFET to the Ground Planewith a Sufficient Number of Vias 3) PWM Switching Edges and Subsequent Ringing Figure 12 shows a Resistor Capacitor Diode (RCD) cir-cuitry (R1, C1, and D1) that serves two purposes; firstly C1shows down the collector voltage rise time (smoothening,reducing radiated EMI) when Q1 is turned off and secondly,it maintains the input voltage to 2V CC as not to exceed the breakdown voltage of the switching MOSFET. In making C1 large enough, the rising collector voltage and falling col-lector current intersect so low down that the transistor dissi-pation is decreased significantly.The ringing circuitry (Figure 12 (C2 and R2)) is also impor-tant and used to reduce the ringing of the primary side of the transformer caused when the MOSFET relaxes to the input voltage of the power supply, shown below in Figure 13 and Figure 14.FIGURE 12. RCD Snubber and RC Ringing CircuitryAN-4145Design Guide to Reduce Internal and External In Power Converters (Contin-FIGURE 13. Primary Voltage Waveform Without Ringing Circuitry (C2, R2)FIGURE 14. Primary Voltage Waveform with Ringing Circuitry (C2, R2)As a first pass, one method of determining the values for C2 and R2 is as follows:1.Determine the frequency of the ringing waveform andcalculate the period.2.Multiply the period, determined in Step 1, by 5.3.Assume a value for the resistor (usually less than100R).4.Calculate the size of the capacitor by dividing the num-ber obtained in Step 2 by the size of the resistor inStep 3.Note: The advantage of using the resistor R2 and the capacitor C2 network is that it reduces the ringing as shown in Figure 11, but the disadvantage is that the high frequency ripple passing through capacitor C2 gets dissipated as heat in resistor R2. If noise reduction is more important than efficiency then proceed, otherwise efficiency will drop off some.8A N -4145 E l e c t r o m a g n e t i c C o m p a t i b i l i t y f o r P o w e r C o n v e r t e r sPrinted Circuit Board Guidelines1.Take the time to place and orient the components prop-erly.2.If heat sinks are used, make sure they are grounded.3. A component shield maybe required.mon mode capacitors should have low ESR val-ues as well as maintain a short lead length to the ground place.5.If a snubber circuit is being used across the trans-former to slow down the rise time of the MOSFET switch turning off, make sure that the trace lengths from the drain and two primary transformer pins are short. If possible place the snubber circuitry between the two primary pins.6.avoid slots in the ground and power (if used) planes7.Under 50 MHz (don ’t forget to consider the harmonicsof the PWM controller) traditional decoupling methods are effective. Use one or two decoupling capacitors (often 0.1 or 0.01 uF) placed close to the IC power and ground pins. Consider the loop area formed between the decoupling capacitor and the IC, and place the capacitor for minimum loop area.8.Keep ground runs as short as possible and as thickand large as possible.9.Avoid sharp corners on traces.10.Try to group all noisy component in the same area justin case shielding is e multi-layer printed circuit board if possible.Safety Dealing with Medical EquipmentCommon mode noise is a problem for sensitive equipment such as those in the medical field. If a device touches a patient, the total system leakage is limited to 100uA. This means that most power supply designers want to restrict this leakage current 20 to 40uA. In order to meet this strin-gent requirement, common mode filters with capacitors to ground are not used. Using common mode chokes, feed through capacitors (high frequency noise is shunted to the chassis ground instead of signal ground) to ground and adding a transformer or isolating the power supply lines into the power supply reduces these common mode con-ducted emission pulses. Safety standard: IEC950/UL1950class II is used in medical equipment.ConclusionEMC is an important stage of system design today and will become more stringent as time moves on. One must keep in mind that when switching occurs, so does noise whether it be conducted or radiated noise. This application note spoke about board level techniques to reduce noise, if more noise reduction is required, especially on the radia-tion side, conductive enclosures are an option. There is additional cost with all that is added so as a design engi-neer, standard compliance, safety compliance, and cost all play an important role in the final product.References:EMI Filter Design (1996)Richard Lee OzenbaughFairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.。

台达--开关电源基本原理与设计介绍

開關電源基本原理与設計介紹Summary基本原理介紹開關電源中的相關設計基本原理介紹¾DC-DC變換器主要架构及其拓補¾EMI 部分¾PFC 部分¾同步整流部分¾均流技術¾保護与控制線路SPS基本原理框圖基本原理簡介一般由三部分組成:一是輸入回路.二是輸出回路.三是控制回路.輸入回路由EMI濾波電路.高壓整流濾波.隔離變壓器初級和高壓方波切割元件所組成，其與電網直接連接高電壓.輸出回路由隔離變壓器次級.低壓整流濾波電路所組成，其與控制回路都由低壓電子元器件組成.輸入回路與輸出回路兩者間採用隔離變壓器進行隔離確保人身與低壓電子器件之安全，這樣不僅達到高低電壓隔離,還做到高低電壓的轉換功能.工作原理交流輸入電壓(AC)經EMI濾波電路濾波一些電網來的干擾與雜訊後, 直接予以整流與濾波得到高壓直流(DC).再將直流高壓進入方波切割器件(MOSFET)中,切割成20~200KHZ的高頻電壓方波信號.該方波信號進入隔離變壓器初級,而由次級所感應出的低壓交流電勢經整流濾波後,得到低壓穩定直流輸出,供給負載.不管輸入電壓有無變化或輸出負載是否變動,都要保持輸出直流電壓的穩定.因此,經直流輸出監控電路對輸出電壓加以監控,並把信號回饋給PWM邏輯控制電路調整占空比.從而調整輸出電壓達到穩定效果.當負載發生故障(如:短路,過載等)時可通過保護電路把信號迅速回饋給PWM邏輯控制電路使方波切換元件停止工作,達到保護的功能.Boost DC-DC 變換器主要架构peak drain current.peak drain voltage2. Boost (step up)Ideal transfer functionDiode voltages(vrmAverage diode currentsBoost變換器工作狀態Boost DC-DC變換器主要架构DPS-350MB ABOOST CIRCUITBuck DC-DC 變換器主要架构1.Buck (step down)peak drain currentIdeal transfer functionpeak drain voltageAverage diode currentsDiode voltages (vrm)Buck變換器工作狀態Buck變換器工作原理當S關閉時,電流就會順向地流經電感器L,此時在負載上就會有帶極性的輸出電壓產生,如上面圖2所示,當開關打開時,電感器L會改變磁場,二級体D則為順向偏壓狀態,因此在電容器C 中就會有電流流過,因此在負載RL上輸出電壓的極性仍是相同的,一般我們稱此二級体D為飛輪二級体.由于此種轉換動作,使得輸出電源是一种連續而非脈動電流形式,相對的由于開關S在ON/OFF之間改變,所以輸入電流則為不連續形式,也就是所謂的脈動電流形式.Buck DC-DC變換器主要架构實際舉例DPS-350MB A BUCK CIRCUITBuck&Boost DC-DC變換器主要架构Voltage and current waveformsBuck BoostBUCK-BUST(FLYBACK)變換器原理圖BUCK-BUST(FLYBACK)變換器工作狀態BUCK-BUST(FLYBACK)變換器工作原理當電路中的開關S關閉時,電流就會流經電感L,並將能量儲存于其中,由于電壓極性的關系,二級体D是在逆向偏壓狀態,此時負載電阻RL上就沒有電壓輸出.當開關S打開時,由于磁場的消失,電感L呈逆向極性,二級体D 為順向偏壓,環路中則有Ic感應電流產生,因此負載RL上的輸出電壓极性正好和輸入電壓极性相反,由于開關ON/OFF的作用,使得電感器的電流交替地在輸入与輸出間,連續不斷的改變其方向,不過這二者電流都是屬于脈動電流形式.所以該變換器電路中,當開關是在導通周期時,能量是儲存在電感器裏,反之,當開關是在打開周期時能量會轉移至負載上.Isolated Forward DC-DC變換器拓補3. Isolated Forward Ideal transfer functionPeak drain currentPeak drain voltageAverage diode currents Diode voltages(vrm)Isolated Forward工作原理由于該轉換器中使用的隔离元件是一個真正的變壓器,因此為了獲得正确有效的能量轉移,必須在輸出端有電感器,作為次級感應的能量儲存元件.而變壓器的初級繞組和次級繞組有相同的極性.當電晶體Q1在ON時,初級繞組漸漸會有電流流過,并將能量轉移至輸出,且同時經由順向偏壓二級体D2,儲存与電感器L中,此時的二級体D3為逆向偏壓狀態.當Q1換成OFF狀態時,變壓器的繞組電壓會反向,D2二級体此時就處于逆向偏壓的狀況,此時与飛輪二級体D3則為順向偏壓,在輸出回路上有導通電流流過,並經由電感器L,將能量傳導至負載上.變壓器上的第三個繞組与D1互相串聯在一起,可達到變壓器消磁的作用,如此可避免Q1在OFF時,變壓器的磁能會轉回至輸入直流匯流排上.Forward實際舉例300LB A FORWARD CIRCUITIsolated Flyback DC-DC變換器拓補4. Isolated Flyback Ideal transfer functionPeak drain currentPeak drain voltageDiode voltages(vrm)Average diode currentsIsolated Flyback工作原理當電晶體Q1導通時,變壓器的初級繞組漸漸會有初級電流流過,並將能量儲存与其中,由于變壓器扼流圈的輸入与輸出繞組,其極性是相反的,因此二級体被逆向偏壓,此時沒有能量轉移至負載,當電晶體不導通時,由于磁場的消失導致繞組的極性反向,此時二級体D會被導通,輸出電容器C會被充電,負載RL上有IL的電流流過.由于此種隔离元件的動作就象是變壓器与扼流圈,因此在反擊式轉換器輸出部分,就不需要額外的電感器了,但是在實際應用中,為了抑制高頻的轉換電訊波尖,還是會在整流器与輸出電容之間加裝小型電感器.Flyback實際舉例DPS-200PB-135 B FLYBACK CIRCUITVoltage and current waveformsForward FlybackForward&Flyback DC-DC 變換器拓補TWO-SWITCH FORWARDIdeal transfer functionPeak drain currentPeak drain voltageAverage diode currentsAverage diode currents Tow Switch Forward DC-DC 變換器拓補DC-DC變換器拓補Voltage and current waveforms 實際舉例DC-DC變換器拓補HALF BRIDGE Ideal transfer functionPeak drain currentPeak drain voltage Average diode currentsDiode voltages(vrm)DC-DC變換器拓補FULL BRIDGE Ideal transfer functionPeak drain currentPeak drain voltageAverage diode currentsDiode voltages(vrm)DC-DC變換器拓補Voltage and current waveformsHALF BRIDGE FULL BRIDGEFULL BRIDGE circuitDPS-1001AB C FULLBRIDGE CIRCUIT零電流開關變換器軟開關ZCS變換器在大功率的開關電源中,為了降低電路的開關損耗及提高開關器件的電壓應力和電流應力,軟開關技術也就得到了研究並得到了迅速發展.所謂軟開關通常指的是零電壓開關ZVS和零電流開關ZCS.軟開關的實現主要是借助于附加的電感L和電容C的諧振,使開關器件中電流(或電壓)按正弦規律來變化,當電流過零時,使器件關斷,當電壓下降到零時,使器件導通.此次討論零電流開關變換器---ZCS-PWM.ZCS-PWM變換器是ZCS-QRC和PWM開關變換器的綜合,同時兼有二者的特點.在一個周期內,電路有時以ZCS準諧振方式運行,有時又以PWM方式運行.以Buck ZCS-PWM為例,對此電路的工作過程進行討論和分析.基本電路BUCK變換器基本電路在此電路中將開關S用零電流諧振開關代替后,就构成了下圖的零電流開關諧振Buck變換電路.基本變換電路BUCK ZCS-QRS變換電路在Buck ZCS-QRS變換電路的基礎上增加一個功率開關管Q2以及與其反并聯的二極體D2就构成了Buck ZCS-PWM變換電路.基本變換電路Buck ZCS-PWM變換器基本變換電路Buck ZCS-PWM變換器工作原理Lri設初始時刻主開關管Q1和輔助開關管Q2均處于關斷狀態,輸出負載電流Io從續流二极管D上流過,電容Cr兩端的電壓為零.一個開關從主開關管Q1的導通開始.當Q1在Snubber電感Lr作用下零電流導通後,電感電流將在電源電壓作用下線性上升,當上升倒等於IO時,續流二極體D關斷.之後,D2導通,LR 與CR諧振.經過半個諧振週期, 以諧振方式再次達到IO, 以諧振方式上升到,此時由於輔助開關管Q2處於關斷狀態,故與將保持在該值上,無法繼續諧振.這個狀態的持續時間由電路輸出的PWM控制要求確定.如果這一段時間等於零,則ZCS-PWM電路就完全等同於ZCS-QRC電路了.當電路的輸出PWM控制要求關斷主開關管Q1時,首先應導通開關管Q2(在SNUBBER電感LR 的作用下零電流導通),之後與再次諧振.當電感電流諧振到零時,二極體D1導通,之後, 繼續向反方向諧振並再次諧振到零.在電感電流反方向運行期間,主開關管Q1可在零電流零電壓下完成關斷過程.在此之後,電容電壓將在輸出電流的作用下線性衰減到零,使續流二極體D自然導通,直到下一個開關週期到來..輔助開關管Q2可以在D到同之後及下一個開關週期到來之前的任何inVLriLri crvinV2LricrvrLrCLricrV以下分析都是在下列條件成立時進行的:a.所有元器件都是理想的,即開通時管壓降為零,關斷時漏電流為零,開通與關斷瞬間完成.b.濾波電感足夠大,故濾波器及負載在一個開關週期中,可用其值等於該週期輸出電流Io的恆流源代替.Buck ZCS-PWM 變換電路的開關周期可分為六個時間段來描述,對應于六種基本的電路拓扑模式,如下圖所示.設電路初始狀態為主電路開關Q1關斷,輔助開關Q2關斷,續流二极管D導通,輸出電流全部通過D續流,電感電流=0,電容電壓=0.工作過程分析.f L f f C L −L R Lr i cr v 時刻,以零電壓零電流方式完成關斷過程.從上述工作原理可看出,在ZCS-PWM 電路中,所有開關管及二極體都是在零電壓或零電流下完成通斷的.同時,電路可以以恆定頻率通過調節輸出脈寬占空比來調節輸出電壓.各時間段的電路拓補圖主要電量波形半橋式轉換器介紹雙輸入電壓半橋式轉換器二个主要优點,第一点就是它能在數放交流电压115V或230Vac的工作情况下,不需使用到高压晶体管.第二点就是我们只需使用到簡單的方法就能来平衡每一轉換晶体管的伏特-秒(volt-senconds)区间,而功率變压器不需有間隙且不需使用到价格高的对称修正電路,雙輸入電壓半橋式轉換器在半橋式轉換器結構中,功率變壓器有一端點連接到由串聯電容器C1與C2所産生的浮點電壓值端點,其浮點電壓值爲Vin/2,所以在標準的輸入電壓下,其值爲160Vdc.變壓器的另一端點則經由串聯電容器C3連接到Q1的射極與Q2的集極接頭處,當Q1電晶體ON時,此處變壓器端點會産生正的160V電壓脈波,當Q1電晶體OFF,Q2電晶體ON時,變壓器的初級圈會極性反轉,因此,會産生負的160V電壓脈波,在這Q1與Q2電晶體ON-OFF動作中,其産生的峰對方波電壓值爲320V,經由變器轉換降低爲次級電壓,再經過整流,濾波而得到直流輸出電壓.RCC(Ringing choke converter)電路RCC電路的工作原理以DPS-180KB-1 D 的STANDBY電路為例如圖所示,Q902的控制极(G极)由R914A~R914C得到啟動電壓后,Q902開始導通,電流經過T901的8,10腳,Q902的漏源极和R906到地,同時T901開始儲能,R906的電壓也同時升高,當R906的電壓達到一定值的時候,Q901導通,使得Q902的G极電壓拉低,Q902截止.在Q902截止的期間內,由開關變壓器T901向負載提供能量,在T901次級繞組的電流經過LC濾波后得到直流輸出.當Q901由導通變為截止時,Q902再次導通,如此反复的循環,形成自激振蕩.RCC電路舉例Input EMI SectionEMI的定義EMI 的產生和傳播及處理方式在SPS中的架構模型EMI的處理及量測裝置LISN的原理與使用開關電源的雜訊分析EMI濾波器的組成元件EMI的定義•EMI:Electromagnetic interference 電磁干扰•EMI包括傳導(conduction)和輻射(radiation)兩個部分.•傳導EMI是待測物經由導線(電源線)所傳遞出來的雜訊.•輻射EMI是直接由開放空間傳遞的.Input EMI Section 架构EMI的產生傳播及處理方式噪聲傳遞的主要方式為﹕（1）傳導耦合﹒2）公共阻抗耦合﹒（3）輻射耦合﹒根据電磁干扰的傳播途徑﹐開關電源中的電磁干扰可以分為輻射干扰和傳導干扰﹐兩种干扰可以相互轉換﹒傳導干扰可以分為共模（Common Mode－CM）干扰和差模（Differential Mode－DM）干扰﹒由于寄生參數的存在以及開關電源中開關器件的高頻開通和關斷﹐使得開關電源在其輸入端（即交流電网側）產生較大的共模干扰和差模干扰﹒傳導EMI經由介質進行傳導﹒因此﹐在電路上經常是加濾波器的方式抑制雜訊﹒但是輻射EMI不經由介質﹐雜訊可以bypass EMI而影響其他系統﹒因此其處理方式多為屏蔽（shielding）接地（grounding）濾波等﹒開關電源的雜訊分析•由LISN所取得的雜訊中,都包含有CM雜訊(common-mode noise)及DM雜訊(differential-mode noise)兩個分量•CM雜訊由CM雜訊電流產生,DM雜訊有DM雜訊電流產生.其中CM雜訊電流ICM是L,N相對于接地線共同的雜訊,而DM雜訊電流IDM是直接經L,N而不經過接地線的雜訊分量.此兩分量用數學表示如下:DMCMtotalIIIrrr+=totalIr為總雜訊電流,它是流經LISN的50ohm阻抗所產生的雜訊電壓50*totaltotalIVrr=開關電源的雜訊分析CM雜訊電流與DM雜訊電流由什么造成的?根据前人的實驗結果,發現CM雜訊主要是由Power MOSFET及變壓器上的寄生電容及雜散電容造成的.而DM雜訊電流則由電源電路初級端的非連續電流機輸入端濾波大電容(bulk capacitor)上的寄生電感所造成的.EMI濾波器的組成元件常見的EMI濾波元件共有四種:CM電感DM電感X電容Y電容1. CM電感CM電感是將兩組線圈繞在一個鐵芯上製成的.且其繞線的方嚮能使得其DM電流所產生的磁場H相互抵消, 而對CM電流而言,DM由于其是對地而言的,因此兩組線圈可看成是L,N對地獨立電感,其所產生的磁場H是相同方嚮的.CM同時由于DM的磁場相互抵消的關系,CM電感比較不易飽和,因此一選用u值較高的ferrite core作為鐵芯.2. DM電感DM電感的濾波原理和電源供應器輸出端的濾波電感並無不同,由于需要流經大電流,因此材質多用u值較低的powder core以避免飽和.EMI濾波器的組成元件3.X電容X電容是跨接于電源的L,N兩端.一般為金屬皮鏌(metal film)為材質,其容值規格為0.015uF0.1uF 0.22uF 0.33uF 0.47uF 0.68uF 最大為1uF.4.Y電容Y電容扮演的是CM電容的角色.其最大的特點是以兩個為一組而存在.一般Y電容均為高壓陶瓷電容,其電容容值較小,從470pF1000pF 2200pF 3300pF到最大為4700pF.。

Infineon 2EDF7275F驱动器解决方案

Infineon 2EDF7275F双路隔离MOSFET栅极驱动器解决方案infineon公司的EiceDRIVER™2EDF7275F是双路隔离MOSFET栅极驱动器集成电路系列,通过无芯变压器(CT)技术,提供功能(2EDFx)或加强(2EDSx)输入/输出隔离性能.由于高驱动电流,极好的共模抑制和快速信号传输,2EDi系列特别适合于开速开关电源系统中驱动中/高压MOSFET器件(CoolMOS™, OptiMOS™, CoolSIC™).2EDSx, 2EDFx双路加强(安全)和功能隔离产品有不同的驱动强度:4A/8A低欧姆功率MOSFET,1A/2A高Ron MOSFET或更低开关瞬态(EMI).器件提供4A/8A或1A/2A源/沉输出电流,高达10MHz PWM开关频率,PWM信号传输时延0.37ns:通路不匹配3ns和+7/-6 ns传播延迟方差.输出电源电压从4.5V到20V,工作温度TJ = -40℃到+150℃.主要用在服务器,通信和工业开关电源(SMPS),同步整流,砖型转换器,UPS和电池存储,EV充电工业自动化,马达驱动和电动工具.为您整理如下详细资料，本文介绍了2EDF7275F主要特性,2EDi系列框图,以及评估板EVAL_3K3W_TP_PFC_SIC主要特性,指标.The EiceDRIVER™ 2EDi is a family of fast dual-channel isolated MOSFET gate-driver ICs providing functional(2EDFx) or reinforced (2EDSx) input-to-output isolation by means of coreless transformer (CT) technology. Dueto high driving current, excellent common-mode rejection and fast signal propagation,2EDi is particularly wellsuited for driving medium- to high-voltage MOSFETs (CoolMOS™, OptiMOS™, CoolSIC™) in fast-switching power systems.The gate drivers of the EiceDRIVER™ 2EDi product family are designed for fast-switching, medium to high powersystems with MOSFET switches. They are optimized for high timing accuracy over temperature and productionspread. The reliable accurate timing simp lifi es system design and provides better power conversion efficiency.The 2EDSx, 2EDFx dual-channel reinforced (safe) and functional isolated product variants are available withdifferent drive strengths: 4 A/8 A for low-ohmic power MOSFETs, 1 A/2 A for higher Ron MOSFETs or slowerswitching transients (EMI). The 1 A/2 A reinforced isolation driver can also be used as a PWM Data Coupler incombination with a non-isolated boost gate driver such as 1EDNx 4 A/8 A placed in closest proximity to theSuperjunction power switches.Two independent and galvanically isolated gate driver channels ensure that all 2EDi versions can be used in anypossible configuration of low- and high-side switches.Improved system robustness is supported by min. 150 V/ns Common Mode Transient Immunity (CMTI), PWMinputs with 18 ns noise filter, UVLO on output side including a safety self-lock-down of driver outputs in case ofinput UVLO (VDDI < 3 V), PWM outputs with up to 5 A peak reverse current capability and an intrinsically robustgate driver design.The 2EDi product table is provided as a first quick device selection guide; more detailed specifications areprovided in the product features, package dimension and testing chapters of this datasheet.2EDF7275F主要特性:• 4 A/8 A or 1 A/2 A source/sink output current• Up to 10 MHz PWM switching frequency• PWM signal propagation delay typ. 37 ns with– 3 ns channel-to-channel mismatch– +7/-6 ns propagation delay variance• Resistor-programmable Dead Time Control (DTC) ranging from 15 ns to 250 ns• Common Mode Transient Immunity CMTI >150 V/ns• Fast safety turn-off in case of input side Undervoltage Lockout (UVLO)• Output supply voltage from 4.5 V to 20 V with 4 V or 8 V UVLO threshold• Wide temperature operating range TJ = -40°C to +150°C• RoHS compliant wide /narrow-body (WB/NB) DSO16 and 5mm x 5mm LGA packages• Fully qualified according to JEDEC for Industrial ApplicationsIsolation and safety certificates• 2EDSx with reinforced isolation:– DIN V VDE V 0884-10 (2006-12) compliant with VIOTM = 8 kVpk and VIOSM = 6.25 kVpk (tested at 10kVpk)– certified according to UL1577 (Ed. 5) opto-coupler component isolation standard with VISO = 5700 VRMS– certified according to DIN EN 62368-1 and DIN EN 60950-1 and corresponding CQC certificates– certified according to EN 61010-1 (reinforced isolation, 300 Vrms mains voltage, overvoltage category III)• 2EDFx with functional isolation: Production test with 1.5 kVDC for 10 ms2EDF7275F潜在应用:• Server, telecom and industrial SMPS• Synchronous r ectification, brick converters, UPS and battery storage• EV charging industry automation, motor drives and power tools图1.EiceDRIVER™ 2EDi系列框图图2.EiceDRIVER™ 2EDi系列和5V控制器和高边VDD自举的应用电路评估板EVAL_3K3W_TP_PFC_SICThe EVAL_3K3W_TP_PFC_SIC board is a system solution enabled by Infineon Technologiespower semicon ductors as well as drivers and microcontroller. The evaluation board consists of a bridgeless totem-pole topology and it is intended for high-end applications in which the highest efficiency is required. Furthermore, the totem-pole topology is simple and offers a reduced part count and full utilization of the PFC inductor and switches [1]. For these reasons, totem-pole PFC enables high power density at a limited system cost for high-performance systems. In addition, theEVAL_3K3W_TP_PFC_SIC board provides reverse power flow (inverter operation for grid-connected applications) due to the inherent bi-directional power flow capability of the totem-pole topology.The totem-pole topology in PFC applications with CCM operation is feasible by using wide band-gap semiconductors [1]. In this case, the Infineon CoolSiC™ MOSFET in TO-247 four-pin package is used to push the efficiency to 99 percent at half-load (Figure 2). The converter operates exclusively at high-line (176 Vrms minimum, 230 Vrms nominal) in CCM with 65 kHz switching frequency.The PFC function to achieve bulk voltage regulation while demanding high-quality current from the grid is implemented with an Infineon XMC1404 microcontroller [2]. Further detail on PFC control implementation in the XMC™ 1000 family can be found in the application notes of other Infineon PSU and PFC evaluation boards with classic boost or dual boost topologies [3][4][5].The 3300 W bridgeless bi-directional (PFC/AC-DC and inverter/AC-DC) totem-pole presented in thisapplication note is a system solution developed with Infineon power semiconductors as well as Infineon drivers and controllers. The Infineon devices used in the implementation of theEVAL_3K3W_TP_PFC_SIC board are listed below.64 mΩ 650 V CoolSiC™ (IMZA65R048M1) in TO-247 four-pin package, as totem-pole PFChigh-frequency switches17 mΩ 600 V CoolMOS™ C7 (IPW60R017C7) in TO-247 package, for the totem-pole PFC return path (low-frequency bridge)2EDF7275F isolated gate drivers (EiceDRIVER™)ICE5QSAG QR Flyback controller and 950 V CoolMOS™ P7 (IPU95R3K7P7) for the bias auxil iar y supplyXMC1404 microcontroller for PFC control implementationA simplified block diagram of the bridgeless topology with the mentioned devices from the Infineon portfolio is shown in Figure 3. The diode bridge in front of the totem-pole PFC converter is meant to be a current path for start-up or surge conditions and it is not part of the current path during the steady-state converter operation. The power flow direction, which will select the converter operation – forward power flow or PFC operation versus reverse power flow or inverter operation – can be selected by a switch connected to the XMC™ microcontroller as a digital input pin.This document presents a system solution based on Infineon superjunction (SJ) (CoolMOS™) and wide band-gap (CoolSiC™) power semiconductors, drivers and microcontroller for a bridgeless totem-pole Power Factor Corrector (PFC) with bi-directional capability. The EVAL_3K3W_TP_PFC_SIC board is intended for those applications which require the highest efficiency (99 percent) and high power density (73 W/in3), such as high-end servers and telecoms. In addition, the bi-directional power flow capability would allow this design to be used in battery chargers or battery formation applications. The totem pole implemented in the EVAL_3K3W_TP_PFC_SIC board operates in Continuous Conduction Mode (CCM) in both rectifier (PFC) and inverter mode, with full digital control implementation on the Infineon XMC™ 1000 series microcontroller.The Infineon components used in the 3300 W bridgeless bi-directional totem-pole board are as follows:600 V CoolMOS™ C7 SJ MOSFET and 650 V CoolSiC™ silicon carbide MOSFET2EDF7275F isolated gate drivers (EiceDRIVER™)XMC1404 microcontrollerICE5QSAG CoolSET™ QR Flyback controller950 V CoolMOS™ P7 SJ MOSFET图3.3300W无桥图腾柱PFC和CoolSiC™, CoolMOS™ and XMC™控制板评估板EVAL_3K3W_TP_PFC_SIC主要特性:High efficiency bridgeless totem-pole PFCHigh power densityEnabled by CoolSiC™ MOSFET 650VDigitally controlled with XMC1404Bidirectional capability (DC-AC operation)BenefitsEfficiency close to 99%Compact form factor (72W/in3)Low component countBidirectional operation (digital control)图4.3300W无桥图腾柱PFC板(EVAL_3K3W_TP_PFC_SIC)简化框图图5.3300W无桥图腾柱PFC板和650V CoolSiC和600V C7 C OS MOSFET和XMC控制位置图。

电机驱动系统平衡结构共模电压消除策略

电机驱动系统平衡结构共模电压消除策略姚月琴;王秀琳【摘要】为了优化电机驱动系统电磁兼容性能,提出了一种电机驱动系统平衡结构共模电压消除策略,以减少或消除接地漏电流、轴承电流和共模电磁干扰.所提出的平衡结构拓扑将每相桥臂开关一分为二,可产生2个互补的平衡三相输出电压,进而消除系统中的共模电压.新方案的优势在于无需额外的滤波器组件、修改调制策略或增加设备额定容量.最后,基于电机驱动平台开展了相关试验,试验结果验证了新型策略能有效抑制共模电压.【期刊名称】《电气传动》【年(卷),期】2019(049)004【总页数】5页(P23-27)【关键词】电机驱动;共模电压;电磁干扰;三相逆变器【作者】姚月琴;王秀琳【作者单位】盐城工业职业技术学院机电工程学院,江苏盐城 224005;盐城工学院电气工程学院,江苏盐城 224001【正文语种】中文【中图分类】TM921电机驱动系统中逆变器的脉宽调制（pulse width modulated，PWM）策略具有高效率和易于控制的优点，得到了广泛应用［1-2］。

传统两电平PWM逆变器将产生高频的共模电压（common mode voltage，CMV）［3-4］，CMV 会引起诸如接地漏电流、轴承电流、传导和辐射电磁干扰（electromagnetic interference，EMI）等问题［5-6］。

同时，随着功率半导体技术的不断发展，开关频率的不断增加，进一步加剧了CMV的相关问题。

对于电机驱动系统中PWM逆变器的CMV问题，通常使用的解决方案是一些工程措施，例如，接地漏电流通常被共模扼流圈抑制［7］；轴承电流通常使用接地电刷或绝缘轴承来降低［8］；而电磁干扰则可以通过安装EMI滤波器或屏蔽电缆处理［9-10］。

虽然这些解决方案工程效果明显，但这些措施施加后通常只能解决1个特定问题，因为它们都不涉及CMV的源头抑制。

最近，有源滤波器被提出用于抑制系统CMV ［11-12］，但有源滤波器需要高带宽放大器和外部电压源，因此实现困难、代价昂贵。

贝尔登无铠装变频驱动 (VFD) 电缆端接指南说明书

Unarmored Variable Frequency Drive (VFD) Cable Termination GuideA Step-by-Step Look atthe Connection/Terminationof Unarmored VFD CablesT erminating Unarmored Variable Frequency Drive (VFD) Cables Foil-Braid or Copper-Tape Shield ConstructionsThis Belden VFD Cable Termination Guide takes a step-by-step approach to the connection/termination of unarmored VFD cables with either foil-braid or copper-tape shield constructions. The instructions cover the termination of the cables in external and self-contained enclosures, at the motor junction box or using an alternative method. VFD Cable Installation Location ConsiderationsIt is advisable to maintain as much separation as possible between noise-susceptible cables and VFD cables – a minimum of one foot for shielded instrumentation cables and three feet for unshielded instrumentation cables. If the two types of cable must lie close to each other, it is best to minimize the amount of parallel runs between them, limiting these stretches to 10 feet or less to reduce the likelihood of radiated noise pickup. Also, if the two types of cables must cross, it is preferable to cross them perpendicularly at a single point.As you use this step-by-step VFD CableTermination Guide, please note the references to the drive or motor manufacturer’srecommendations. You should be familiar with the manufacturer’s termination guidelines as well. If you have specific questions on the instructions given within this guide, please contact Belden Technical Support at 1.800.BELDEN.1 (1.800.235.3361).Belden VFD Cables are designed for quick and easy termination.One 16 AWG Shielded Signal Pair for Brake with Drain WireOverall Duofoil Shield + 85% TC Braid plus full size TC Drain WireOriginal DesignOriginal Design with Signal PairOriginal Symmetrical DesignOne Full-sized Insulated Ground (same AWG as Circuit Conductors)Three StrandedTC Circuit Conductors with XLPE InsulationBelden’s Variable Frequency Drive (VFD) Cable Offering See VFD Cable Matrix (page 3) for additional information.2Belden VFD Cable Matrix34STEP 1STEP 4STEP 5STEP 6STEP 2STEP 3General T ermination InstructionsTo properly and effectively terminate a VFD cable system, first ensure the following: • Ideally, the shield and jacket should beintact all the way back to the drive so they do not introduce any jumping off points for the common mode currents carried on the common mode current containment system. In this case, no special tools, materials or termination kits are required.• Shield grounding cable glands should beavoided at the enclosure ingress as they may introduce jumping off points for the common mode currents into the metal work — in addition to undesirable and uncontrolled electrical noise.• Intermediate termination of the cable ele-ments on terminal blocks should be avoided as the terminations may significantly reduce the ability of the shielding system to conduct and contain harmful high frequency currents.• The cable’s outer jacket system serves animportant role in isolating the common mode current containment system. The outer jacket should not be removed before the cable enters the drive proper as this introduces the potential for uncontrolled ground currents. Care should be taken to minimize contact between exposed cable shield, and any enclosure metal, especially in the close vicinity of sensitive equipment that is likely present near the drive.VFD Cable T ermination Instructions — Foil-Braid Constructions External and Self-Contained Drive EnclosuresA. Ingress the enclosure using an isolating cablegland with a suitable protection rating for the enclosure and the environment. Allow a sufficient length of cable to easily reach the drive without unnecessary cable strain. Do not remove the outer cable jacket.B. Secure the cable with suitable cable ties,or through cable duct as appropriate. C. If the drive is open style, route the jacketedcable assembly back to the drive vicinity.A. If the drive is in an internal enclosure, ingressthe drive through a suitable insulating cablegland. Measure and mark the cable to determine the jacket strip location and cutoff length. B. If possible, remove the measured cable andplace the end for preparation on a suitable work surface.A. Remove the exposed shield andcable fillers where exposed. A. Push the remaining braid forward,and use a tool to open the braid.A. Neatly remove the outer cable jacket,exposing sufficient conductor to reach the drive terminals, while still leaving some excess conductor length for trimming (after neatly routing to the drive terminals). B. It is desirable to combine the shielding drainsand braid for termination intact at the ground terminal of the drive.A. Push the exposed braid backover the cable jacket.5STEP 13STEP 10STEP 11STEP 12STEP 7STEP 8STEP 9A. Push the primary conductors and groundthrough an opening in the braid, separating the intact braid system from the conductors.A. T erminate the ground and drain permanufacturer’s recommendations.A. Leave the drain wire inside the braid system. A. Apply heat shrink tubing to the drain and braid.A. Apply 3-5 inches of heat shrink tubing over theentire cable assembly, centered at the jacket strip point. Shrink this piece completely.B. Secure the cable jacket to the drive (orenclosure) if it is not secured by a cable gland.A. Route and trim the conductors to the powerterminals, leaving sufficient material for phase reversal, if necessary.A. T erminate the motor leads per the drivemanufacturer’s recommendations.B. Trim the ground wire to sufficient length toreach the drive ground terminal.6A. Route and trim the conductors to the motorterminals, leaving sufficient material for phase reversal, if necessary. Use the termination system recommended by the motor manufacturer.B. T erminate the motor leads per the motormanufacturer’s recommendations, or trained practices of a qualified electrician.C. Trim the ground wire to sufficient length toreach the motor ground terminal.D. Heat shrink the drain wire covering and trim tolength for connection to the drive ground terminal. Strip to expose conductor as necessary.E. T erminate the ground and drain usinga standard lug, or on the provided connection point.VFD Cable T ermination Instructions — Foil-Braid Constructions Motor Junction BoxA. Ingress the motor junction box through anisolating cable gland with a suitable protection rating for the enclosure. Do not remove theouter cable jacket. Measure and mark the cable for length. When possible, it is desirable to remove the cable from the motor junction box for ease of preparation.B. Neatly remove the outer cable jacket, exposingsufficient conductor to reach the motor leads and ground lug, while still leaving some excess conductor length for trimming (after neatly routing to the motor terminals). C. Follow the cable preparation instruction aboveas specified for the drive end connection.D. Secure the cable jacket to the motor bytightening the isolating cable gland.7STEP 1STEP 4STEP 2STEP 5STEP 3STEP 6VFD Cable T ermination Instructions — Foil-Braid Constructions Alternate Method: Conductive Cable GlandA. Ingress the motor junction conduit box throughthe conductive cable gland. A. Prepare the cable per the glandmanufacturer’s recommendations. A. Trim the foil at least back to the prepared edgeof the braid.B. Secure the cable to the gland per glandmanufacturer’s recommendations, and pass the cable into the motor junction box.A. T erminate the ground and drain usinga standard lug, or on the provided connection point. A. T erminate the motor leads per the motormanufacturers recommendations, or trained practices of a qualified electrician.A. Secure the cable jacket to the motor bytightening the cable gland lock nut.B. Route and trim the conductors to the motorterminals, leaving sufficient material for phase reversal if necessary. Use the connection system as recommended by the motor manufacturer.C. Trim the ground wire to sufficient length toreach the motor ground terminal.D. Heat shrink the drain wire(s) covering and trimto length for connection to the drive ground terminal. Strip to expose conductor as necessary.How to Terminate in a Conductive Cable GlandNote: It may be more desirable to terminate the braid in a conductive cable gland at the motor connection. If so, suitable conductive cable glands are available through your Belden Distributor. It should be noted, however, that this will be no more effective for common mode current containment than terminating the braid intact, and will involve a more expensive connector. This connection may provideadditional mechanical security, depending onthe connector selection, and could reduce EMI in very close proximity to the motor junction box.8A. If the drive is in an internal enclosure,ingress the drive through a suitable insulating cable gland.B.Neatly remove the outer cable jacket,exposing sufficient conductor to reach thedrive terminals, while still leaving some excess conductor length for trimming (after neatly routing to the drive terminals).A. Remove the exposed copper tape shield.B.De-cable the exposed conductors and grounds.VFD Cable T ermination Instructions — Copper T ape Shield Constructions External and Self-Contained Drive EnclosuresA.Ingress the enclosure with an isolating cablegland with a suitable protection rating for the enclosure and the environment. Allow a sufficient length of cable to easily reach the drive without unnecessary cable strain. Do not remove the outer cable jacket.B. Secure the cable with suitable cable ties,or through cable duct as appropriate.C. If the drive is open style, route the jacketedcable assembly back to the drive vicinity.A. Combine the exposed ground wires by twistingthem together.A. Apply heat shrink tubing to the grounds.A. Apply 3-6 inches of heat shrink tubing over theentire cable assembly, centered at the jacket strip point. Shrink this piece completely.B. Secure the cable jacket to the drive (or enclosure)if it is not secured by a cable gland.9A. Trim back the copper tape shield, and any fillersin the cable.B. De-cable the exposed conductors and grounds.A. Combine the ground wires by twisting themtogether. Apply heat shrink tubing to the combined grounds. B. Secure the cable jacket to the motor bytightening the isolating cable gland.C. Route and trim the conductors to the motorterminals, leaving sufficient material for phase reversal, if necessary. Use the connection system as recommended by the motor manufacturer.D. T erminate the motor leads per the motormanufacturer’s recommendations, or trained practices of a qualified electrician.E.Trim the ground wire to sufficient length toreach the motor ground terminal. F . T erminate the ground using a standardlug, or on the provided connection point.A. Ingress the motor junction box through anisolating cable gland with a suitable protection rating for the enclosure. Do not remove the outer cable jacket.B. Measure and mark the cable for jacket removalinside the motor junction box.C. Neatly remove the outer cable jacket, exposingsufficient conductor to reach the motor leads and ground lug, while still leaving some excess conductor length for trimming after neatly routing to the motor terminals.How to Terminate at the Motor Junction BoxA. Trim the ground wire(s) to sufficient length toreach the drive ground terminal.B. T erminate the ground per the drivemanufacturer’s recommendations. Note that there is no shield termination for copper tape shielded constructions.A. Route and trim the conductors to the powerterminals, leaving sufficient material for phase reversal, if necessary.B. T erminate the motor leads per the drivemanufacturer’s recommendations. Use lugs and ferrules as appropriate. No special pieces are required.VFD Cable T ermination Instructions — Copper T ape Shield Constructions Motor Junction BoxMore Questions? Contact Belden T echnical Support at 1.800.BELDEN.1 (1.800.235.3361).conductors from the terminal block to the drive can create significant electrical noise, which may affect other sensitive components, or networks within the enclosure. Connections on terminal blocks can also reduce the effectiveness of the shielding and should be avoided when possible.11Additional InformationIf you need information on the type of VFD cable that is appropriate for your specific installation, or if you have questions related to the instructions given within this guide, please contact Belden Technical Support at with a bending radius of not more than 10 times the cable diameter.VFD Cables overcome the challenges found in the toughest of environments.UNITED STATESDivision Headquarters – Americas2200 U.S. Highway 27 South Richmond, IN 47374 Phone: 765-983-5200 Inside Sales: 800-235-3361 Fax: 765-983-5294 ***************web: Contact for Belden Brand2200 U.S. Highway 27 South Richmond, IN 47374 Inside Sales: 1-800-BELDEN-1 (1-800-235-3361)Phone: 765-983-5200 Fax: 765-983-5294 ***************web: Contact for Hirschmann and Lumberg Automation Brands1540 Orchard DriveChambersburg, PA 17201 Phone: 717-217-2200 Fax: 717-217-2279CANADANational Business Center2280 Alfred-Nobel Suite 200Saint-Laurent, QC Canada H4S 2A4 Phone: 514-822-2345Fax: 514-822-7979LATIN AMERICA and the CARIBBEAN ISLANDSRegional Office6100 Hollywood Boulevard Suite 110Hollywood, Florida 33024 Phone: 954-987-5044 Fax: 954-987-8022 ******************For worldwide Industrial Sales and Technical Support, visit: /industrial©Copyright 2011, Belden Inc. Printed in U. S. A.VFDCDG 2011GLOBAL LOCATIONS。

RD2资料

Load Regulation (10%-100%)
10 W ± 0.7% ± 5%
Efficiency (115 V input, 8 W out)
75%
Output Ripple Voltage
± 50 mV MAX
Safety
IEC 950 / UL1950
EMI
VDE B (VFG243 B)
CISPR22
Figure 2. Table of Key Electrical Parameters.
May 1996
元器件交易网 RD2
C6 47nF 250VAC
X2
1
BR1 + DF06M
RA 470 KΩ JP1* JUMPER
+ C1 10 µF
200 V
VR1 BZY97-C200
Custom
SU9V-02080
Tokin
KMG200VB10RM10X16 United Chemicon
LXF16VB331M8X15
United Chemicon
LXF16VB121M6.3X11.5 United Chemicon
KME10VB47RM5X12.5 United Chemicon
Fully Protected by TOPSwitch • Primary safety current limit • Output short circuit protection • Thermal shutdown protects entire power supply
Designed for World Wide Operation • Designed for IEC/UL safety requirements • Meets VDE Class B EMI specifications

开关电源外文翻译()

开关电源外文翻译()————————————————————————————————作者：————————————————————————————————日期：Modeling, Simulation, and Reduction of Conducted Electromagnetic Interference Due to a PWM Buck Type Switching Power Supply IA. FarhadiAbstract:Undesired generation of radiated or conducted energy in electrical systems is called Electromagnetic Interference (EMI). High speed switching frequency in power electronics converters especially in switching power supplies improves efficiency but leads to EMI. Different kind of conducted interference, EMI regulations and conducted EMI measurement are introduced in this paper. Compliancy with national or international regulation is called Electromagnetic Compatibility (EMC). Power electronic systems producers must regard EMC. Modeling and simulation is the first step of EMC evaluation. EMI simulation results due to a PWM Buck type switching power supply are presented in this paper. To improve EMC, some techniques are introduced and their effectiveness proved by simulation.Index Terms:Conducted, EMC, EMI, LISN, Switching SupplyI. INTRODUCTIONFAST semiconductors make it possible to have high speed and high frequency switching in power electronics []1. High speed switching causes weight and volume reduction of equipment, but some unwanted effects such as radio frequency interference appeared []2. Compliance with electromagnetic compatibility (EMC) regulations is necessary for producers to present their products to the markets. It is important to take EMC aspects already in design phase []3. Modeling and simulation is the most effective tool to analyze EMC consideration before developing the products. A lot of the previous studies concerned the low frequency analysis of power electronics components []4[]5. Different types of power electronics converters are capable to be considered as source of EMI. They could propagate the EMI in both radiated and conducted forms. Line Impedance Stabilization Network (LISN) is required for measurement and calculation of conducted interference level []6. Interference spectrum at the output of LISN is introduced as the EMC evaluation criterion []7[]8. National or international regulations are the references for the evaluation of equipment in point of view of EMC []7[]8.II. SOURCE, PATH AND VICTIM OF EMIUndesired voltage or current is called interference and their cause is called interferencesource. In this paper a high-speed switching power supply is the source of interference.Interference propagated by radiation in area around of an interference source or by conduction through common cabling or wiring connections. In this study conducted emission is considered only. Equipment such as computers, receivers, amplifiers, industrial controllers, etc that are exposed to interference corruption are called victims. The common connections of elements, source lines and cabling provide paths for conducted noise or interference. Electromagnetic conducted interference has two components as differential mode and common mode []9.A. Differential mode conducted interferenceThis mode is related to the noise that is imposed between different lines of a test circuit by a noise source. Related current path is shown in Fig. 1 []9. The interference source, path impedances, differential mode current and load impedance are also shown in Fig. 1.B. Common mode conducted interferenceCommon mode noise or interference could appear and impose between the lines, cables or connections and common ground. Any leakage current between load and common ground could be modeled by interference voltage source.and Fig. 2 demonstrates the common mode interference source, common mode currents Icm1 and the related current paths[]9.The power electronics converters perform as noise source Icm2between lines of the supply network. In this study differential mode of conducted interference is particularly important and discussion will be continued considering this mode only.III. ELECTROMAGNETIC COMPATIBILITY REGULATIONS Application of electrical equipment especially static power electronic converters in different equipment is increasing more and more. As mentioned before, power electronics converters are considered as an important source of electromagnetic interference and have corrupting effects on the electric networks []2. High level of pollution resulting from various disturbances reduces the quality of power in electric networks. On the other side some residential, commercial and especially medical consumers are so sensitive to power system disturbances including voltage and frequency variations. The best solution to reduce corruption and improve power quality is complying national or international EMC regulations. CISPR, IEC, FCC and VDE are among the most famous organizations from Europe, USA and Germany who are responsible for determining and publishing the most important EMC regulations. IEC and VDE requirement and limitations on conducted emission are shown in Fig. 3 and Fig. 4 []7[]9.For different groups of consumers different classes of regulations could be complied. Class A for common consumers and class B with more hard limitations for special consumers are separated in Fig. 3 and Fig. 4. Frequency range of limitation is different for IEC and VDE that are 150 kHz up to 30 MHz and 10 kHz up to 30 MHz respectively. Compliance of regulations isevaluated by comparison of measured or calculated conducted interference level in the mentioned frequency range with the stated requirements in regulations. In united European community compliance of regulation is mandatory and products must have certified label to show covering of requirements []8.IV. ELECTROMAGNETIC CONDUCTED INTERFERENCE MEASUREMENTA. Line Impedance Stabilization Network (LISN)1-Providing a low impedance path to transfer power from source to power electronics converter and load.2-Providing a low impedance path from interference source, here power electronics converter, to measurement port.Variation of LISN impedance versus frequency with the mentioned topology is presented inFig. 7. LISN has stabilized impedance in the range of conducted EMI measurement []7.Variation of level of signal at the output of LISN versus frequency is the spectrum of interference. The electromagnetic compatibility of a system can be evaluated by comparison of its interference spectrum with the standard limitations. The level of signal at the output of LISN in frequency range 10 kHz up to 30 MHz or 150 kHz up to 30 MHz is criterion of compatibility and should be under the standard limitations. In practical situations, the LISN output is connected to a spectrum analyzer and interference measurement is carried out. But for modeling and simulation purposes, the LISN output spectrum is calculated using appropriate software.For a simple fixed frequency PWM controller that is applied to a Buck DC/DC converter, it is) changes slow with respect to the switching frequency, the possible to assume the error voltage (vepulse width and hence the duty cycle can be approximated by (1). Vp is the saw tooth waveform amplitude.A. PWM waveform spectral analysisThe normalized pulse train m (t) of Fig. 8 represents PWM switch current waveform. The nth pulse of PWM waveform consists of a fixed component D/fs , in which D is the steady state duty cycle, and a variable component dn/f sthat represents the variation of duty cycle due to variation of source, reference and load.As the PWM switch current waveform contains information concerning EMI due to powersupply, it is required to do the spectrum analysis of this waveform in the frequency range of EMI studies. It is assumed that error voltage varies around V e with amplitude of V e1 as is shown in (2).fm represents the frequency of error voltage variation due to the variations of source, reference and load. The interception of the error voltage variation curve and the saw tooth waveform with switching frequency, leads to (3) for the computation of duty cycle coefficients []10.Maximum variation of pulse width around its steady state value of D is limited to D1. In each period of Tm=1/fm , there will be r=fs/fm pulses with duty cycles of dn. Equation (4) presents the Fourier series coefficients Cn of the PWM waveform m (t). Which have the frequency spectrum of Fig.9.B-Equivalent noise circuit and EMI spectral analysisTo attain the equivalent circuit of Fig.6 the voltage source Vs is replaced by short circuit and) as it has shown in Fig. 10. converter is replaced by PWM waveform switch current (IexThe transfer function is defined as the ratio of the LISN output voltage to the EMI current source as in (5).The coefficients di, ni (i = 1, 2, … , 4) correspond to the parameters of the equivalent circuit. Rc and Lc are respectively the effective series resistance (ESR) and inductance (ESL) of the filter capacitor Cf that model the non-ideality of this element. The LISN and filter parameters are as follows: CN = 100 nF, r = 5 Ω, l = 50 uH, RN =50 Ω, LN=250 uH, Lf = 0, Cf =0, Rc= 0, Lc= 0, fs =25 kHzThe EMI spectrum is derived by multiplication of the transfer function and the source noise spectrum. Simulation results are shown in Fig. 11.VI. PARAMETERS AFFECTION ON EMIA. Duty CycleThe pulse width in PWM waveform varies around a steady state D=0.5. The output noise spectrum was simulated with values of D=0.25 and 0.75 that are shown in Fig. 12 and Fig. 13. Even harmonics are increased and odd ones are decreased that is desired in point of view of EMC.On the other hand the noise energy is distributed over a wider range of frequency and the level of EMI decreased []11.B. Amplitude of duty cycle variationThe maximum pulse width variation is determined by D1. The EMI spectrum was simulatedwith D1=0.05. Simulations are repeated with D1=0.01 and 0.25 and the results are shown in Fig.14and Fig.15.Increasing of D1 leads to frequency modulation of the EMI signal and reduction in level of conducted EMI. Zooming of Fig. 15 around 7th component of switching frequency in Fig. 16 shows the frequency modulation clearly.C. Error voltage frequencyThe main factor in the variation of duty cycle is the variation of source voltage. The fm=100 Hz ripple in source voltage is the inevitable consequence of the usage of rectifiers. The simulation is repeated in the frequency of fm=5000 Hz. It is shown in Fig. 17 that at a higher frequency for fm the noise spectrum expands in frequency domain and causes smaller level of conducted EMI. On the other hand it is desired to inject a high frequency signal to the reference voltage intentionally.D. Simultaneous effect of parametersSimulation results of simultaneous application of D=0.75, D1=0.25 and fm=5000 Hz that leadto expansion of EMI spectrum over a wider frequencies and considerable reduction in EMI level is shown in Fig. 18.VII. CONCLUSIONAppearance of Electromagnetic Interference due to the fast switching semiconductor devices performance in power electronics converters is introduced in this paper. Radiated and conducted interference are two types of Electromagnetic Interference where conducted type is studied in this paper. Compatibility regulations and conducted interference measurement were explained. LISN as an important part of measuring process besides its topology, parameters and impedance were described. EMI spectrum due to a PWM Buck type DC/DC converter was considered and simulated. It is necessary to present mechanisms to reduce the level of Electromagnetic interference. It shown that EMI due to a PWM Buck type switching power supply could be reduced by controlling parameters such as duty cycle, duty cycle variation and reference voltage frequency.VIII. REFRENCES[1] Mohan, Undeland, and Robbins, “Power Electronics Converters, Applications and Design” 3rdedition, John Wiley & Sons, 2003.[2] P. Moy, “EMC Related Issues for Power Electronics”, IEEE, Automotive Pow er Electronics, 1989, 28-29 Aug. 1989 pp. 46 – 53.[3] M. J. Nave, “Prediction of Conducted Interference in Switched Mode Power Supplies”, Session 3B, IEEE International Symp. on EMC, 1986.[4] Henderson, R. D. and Rose, P. J., “Harmonics and their Effec ts on Power Quality and Transformers”, IEEE Trans. On Ind. App., 1994, pp. 528-532.[5] I. Kasikci, “A New Method for Power Factor Correction and Harmonic Elimination in Power System”, Proceedings of IEEE Ninth International Conference on Harmonics and Q uality of Power, Volume 3, pp. 810 – 815, Oct. 2000.[6] M. J. Nave, “Line Impedance Stabilization Networks: Theory and Applications”, RFI/EMI Corner, April 1985, pp. 54-56.[7] T. Williams, “EMC for Product Designers” 3rd edition 2001 Newnes.[8] B. Ke isier, “Principles of Electromagnetic Compatibility”, 3rd edition ARTECH HOUSE 1987.[9] J. C. Fluke, “Controlling Conducted Emission by Design”, Vanhostrand Reinhold 1991.[10] M. Daniel,”DC/DC Switching Regulator Analysis”, McGrawhill 1988[11] M. J. Nave,” The Effect of Duty Cycle on SMPS Common Mode Emission: theory and experiment”, IEEE National Symposium on Electromagnetic Compatibility, Page(s): 211-216, 23-25 May 1989.作者：A. Farhadi国籍：伊朗出处：基于压降型PWM开关电源的建模、仿真和减少传导性电磁干扰IIA. Farhadi作者：A. Farhadi国籍：伊朗出处：摘要：电子设备之中杂乱的辐射或者能量叫做电磁干扰(EMI)。

有刷电机换向尖峰电路

有刷电机换向尖峰电路Brushed motors are a common type of electric motor that relies on the physical contact between brushes and a commutator to change the direction of current flow and generate rotational motion. However, this process is not without its challenges, particularly in terms of the peak current that occurs during the commutation process. This peak current can lead to various issues, includingexcessive wear and tear on the brushes and commutator, as well as increased electromagnetic interference. As a result, the design of a peak current circuit, also known as a snubber circuit, becomes crucial in order to mitigate these problems and ensure the smooth operation of the brushed motor.One of the main purposes of a snubber circuit in a brushed motor is to suppress the peak current that occurs during the commutation process. This is achieved byproviding a low impedance path for the current to flow,thus preventing it from flowing through the brushes andcommutator. By diverting the current away from these components, the snubber circuit helps to reduce the wear and tear on them, resulting in increased longevity and reliability of the motor.Another important aspect of a snubber circuit is its ability to minimize electromagnetic interference (EMI). When the brushes make contact with the commutator, arcing occurs due to the high voltage difference between them. This arcing not only generates noise but also produces electromagnetic waves that can interfere with other electronic devices in the vicinity. The snubber circuit helps to suppress this arcing and reduce the EMI, ensuring that the motor operates smoothly without causing any disturbances to other sensitive equipment.Furthermore, the snubber circuit also plays a role in improving the overall efficiency of the brushed motor. By diverting the peak current away from the brushes and commutator, the circuit helps to minimize power losses that would otherwise occur due to excessive heating. This leads to a more efficient motor, as less energy is wasted in theform of heat, resulting in improved performance and reduced operating costs.In terms of the design of a snubber circuit, there are several factors that need to be considered. The most important one is the selection of suitable components that can handle the high peak currents and voltages involved. Capacitors and resistors are commonly used in snubber circuits to provide the necessary impedance and energy dissipation capabilities. The values of these components need to be carefully chosen to ensure optimal performance and protection for the motor.Additionally, the physical layout of the snubbercircuit is also crucial. It should be placed as close to the brushes and commutator as possible to minimize the length of the current path and reduce the effects of stray inductance. Proper grounding and shielding techniques should also be employed to further mitigate EMI issues.In conclusion, the design and implementation of a snubber circuit in a brushed motor are essential foraddressing the challenges associated with peak currents during commutation. By suppressing these currents, the snubber circuit helps to protect the brushes and commutator, reduce electromagnetic interference, and improve theoverall efficiency of the motor. Careful consideration of component selection, circuit layout, and grounding techniques is necessary to ensure optimal performance and reliability.。

dcdc电路中隔离变压器的作用

dcdc电路中隔离变压器的作用英文回答：Isolation Transformer in DC-DC Circuit.An isolation transformer in a DC-DC circuit plays a crucial role in providing galvanic isolation between the input and output sides. Galvanic isolation refers to the physical separation of electrical circuits, preventing current flow between them. This isolation is achieved by using a transformer with a non-conductive barrier between the primary and secondary windings.The need for galvanic isolation arises in various applications. Here are some key reasons why an isolation transformer is employed in a DC-DC circuit:1. Safety: Isolation transformers protect users from electric shock by blocking the flow of current between the high-voltage input side and the low-voltage output side. Incase of insulation breakdown within the transformer, the galvanic isolation prevents hazardous voltages from reaching the output circuit, ensuring user safety.2. Noise Reduction: Isolation transformers help suppress electromagnetic interference (EMI) and common-mode noise between the input and output sides. By creating an electrical barrier, the transformer prevents conducted and radiated noise from propagating through the circuit, improving overall system performance and signal integrity.3. Ground Loop Elimination: Ground loops occur when multiple electrical devices are connected to different ground points, creating a closed loop for current to flow. Isolation transformers break this loop by providing a separate ground reference for the output circuit, eliminating ground loop currents and reducing potential interference.4. Voltage Conversion: In addition to providing isolation, transformers can also serve as voltage converters. They allow for step-up or step-down voltageconversion between the input and output sides. This feature enables the use of different voltage levels in different parts of the circuit, matching the requirements of specific components or subsystems.The selection of an isolation transformer for a DC-DC circuit involves considering various factors such asvoltage rating, current capacity, isolation voltage, frequency range, and size constraints. Proper selection ensures optimal performance, safety, and reliability of the circuit.中文回答：DC-DC电路中的隔离变压器。

CLC型PWM逆变器端无源滤波器的设计

第19卷第3期电源学报Vol. 19 No. 3 2021 年5 月Journal of Power Supply May 2021D O I：10.13234/j.issn.2095-2805.2021.3.33 中图分类号：TM464 文献标志码：ACLC型PWM逆变器端无源滤波器的设计杨玉岗，孙鹤鸣(辽宁工程技术大学电气与控制工程学院，葫芦岛125105)摘要：由于PWM逆变器输出电压中含有较多的高频分量，所以逆变器输出端必须加入低通滤波器来减小谐波含量。

借鉴在PWM逆变器与电机之间插入共模变压器来消除逆变器输出端共模电压的方法，通过分析共模变压器带有漏感时的等效电路，提出了一种新型的CLC型逆变器端无源滤波器。

利用共模变压器产生的漏感代替差模电感来抑制差模电压dv/dt，同时该滤波器对共模电压也有着很好的抑制作用。

与传统滤波器相比，该滤波器可通过1个共模变压器同时对共模及差模电压dv/dt起到抑制作用，减少了滤波器的体积规模。

最后，仿真和实验结果验证了该滤波器的有效性。

关键词：共模电压；差模电压；PWM逆变器；共模变压器Design of CLC-type PWM Inverter Passive FilterYANG Yugang，SUN Heming(Faculty of Electrical and Control Engineering, Liaoning Technical University，Huludao 125105，China)Abstract ：Since the output voltage of a PWM inverter contains more high-frequency components，a low-pass filter must be added to its output terminal to reduce the harmonic content. By referring to the method in which a common-mode (CM) transformer is inserted between the PWM inverter and a motor to eliminate the CM voltage output from the inverter，the equivalent circuit of the CM transformer with leakage inductance is analyzed, and a novel CLC-type inverter passive filter is put forward. The differential-mode voltage (dv/dt) is suppressed by the leakage inductance generated by the CM transformer instead of the differential-mode inductor. Meanwhile, this filter also has a satisfying inhibitory effect on the CM voltage. Compared with the traditional filter, it can suppress both the CM and differential-mode voltage (dv/dt) through one CM transformer, thereby reducing its size. Simulation and experimental results verified the effectiveness of the proposed filter.Keywords： common-mode (CM) voltage; differential-mode voltage; PWM inverter, common-mode (CM) transformer现代工业中，PWM功率变换器已经成为必不可少的器件，但随着电力电子器件开关频率和输出功率的不断提高，逆变器输出电压中含有的大量高频谐波成分所带来的电磁干扰等负面效应也曰趋严重，这不但缩短了仪器的使用寿命，而且严重威胁了周边其他电气设备的安全稳定运行。

工厂常见英语单词

组装、冲压、喷漆等专业词汇Assembly line组装线Layout布置图Conveyer流水线物料板Rivet table拉钉机Rivet gun拉钉枪Screw driver起子Electric screw driver电动起子Pneumatic screw driver气动起子worktable 工作桌OOBA开箱检查fit together组装在一起fasten锁紧(螺丝)fixture 夹具(治具)pallet栈板barcode条码barcode scanner条码扫描器fuse together熔合fuse machine热熔机repair修理operator作业员QC品管supervisor 课长ME制造工程师MT制造生技cosmetic inspect外观检查inner parts inspect内部检查thumb screw大头螺丝lbs. inch镑、英寸EMI gasket导电条front plate前板rear plate后板chassis基座bezel panel面板power button电源按键reset button重置键Hi-pot test of SPS高源高压测试V oltage switch of SPS电源电压接拉键sheet metal parts 冲件plastic parts塑胶件SOP制造作业程序material check list物料检查表work cell工作间trolley台车carton纸箱sub-line支线left fork叉车personnel resource department人力资源部production department生产部门planning department企划部QC Section品管科stamping factory冲压厂painting factory烤漆厂molding factory成型厂common equipment常用设备uncoiler and straightener整平机punching machine 冲床robot机械手hydraulic machine油压机lathe车床planer |'plein|刨床miller铣床grinder磨床driller??床linear cutting线切割electrical sparkle电火花welder电焊机staker=reviting machine铆合机position职务president董事长general manager总经理special assistant manager特助factory director厂长department director部长deputy manager | =vice manager副理section supervisor课长deputy section supervisor =vice sectionsuperisor副课长group leader/supervisor组长line supervisor线长assistant manager助理to move, to carry, to handle搬运be put in storage入库pack packing包装to apply oil擦油to file burr 锉毛刺final inspection终检to connect material接料to reverse material 翻料wet station沾湿台Tiana天那水cleaning cloth抹布to load material上料to unload material卸料to return material/stock to退料scraped |'skræpid|报废scrape ..v.刮;削deficient purchase来料不良manufacture procedure制程deficient manufacturing procedure制程不良oxidation |' ksi'dein|氧化scratch刮伤dents压痕defective upsiding down抽芽不良defective to staking铆合不良embedded lump镶块feeding is not in place送料不到位stamping-missing漏冲production capacity生产力education and training教育与训练proposal improvement提案改善spare parts=buffer备件forklift叉车trailer=long vehicle拖板车compound die合模die locker锁模器pressure plate=plate pinch压板bolt螺栓name of a department部门名称administration/general affairs dept总务部automatic screwdriver电动启子thickness gauge厚薄规gauge(or jig)治具power wire电源线buzzle蜂鸣器defective product label不良标签identifying sheet list标示单screwdriver holder起子插座pedal踩踏板stopper阻挡器flow board流水板hydraulic handjack油压板车forklift叉车pallet栈板glove(s)手套glove(s) with exposed fingers割手套thumb大拇指forefinger食指midfinger中指ring finger无名指little finger小指band-aid创可贴iudustrial alcohol工业酒精alcohol container沾湿台head of screwdriver起子头sweeper扫把mop拖把vaccum cleaner吸尘器rag 抹布garbage container灰箕garbage can垃圾箱garbage bag垃圾袋chain链条jack升降机production line流水线chain链条槽magnetizer加磁器lamp holder灯架to mop the floor拖地to clean the floor扫地to clean a table擦桌子air pipe 气管packaging tool打包机packaging打包missing part漏件wrong part错件excessive defects过多的缺陷critical defect极严重缺陷major defect主要缺陷minor defect次要缺陷not up to standard不合规格dimension/size is a little bigger尺寸偏大(小)cosmetic defect外观不良slipped screwhead/slippery screw head螺丝滑头slipped screwhead/shippery screwthread滑手speckle斑点mildewed=moldy=mouldy发霉rust生锈deformation变形burr(金属)flash(塑件)毛边poor staking铆合不良excesssive gap间隙过大grease/oil stains油污inclusion杂质painting peel off脏污shrinking/shrinkage缩水mixed color杂色scratch划伤poor processing 制程不良poor incoming part事件不良fold of pakaging belt打包带折皱painting make-up补漆discoloration羿色water spots水渍polishing/surface processing表面处理exposed metal/bare metal金属裸露lack of painting烤漆不到位safety安全quality品质delivery deadline交货期cost成本engineering工程die repair模修enterprise plan = enterprise expansionprojects企划QC品管die worker模工production, to produce生产equipment设备to start a press开机stop/switch off a press关机classification整理regulation整顿cleanness清扫conservation清洁culture教养qualified products, up-to-gradeproducts良品defective products, not up-to-gradeproducts不良品waste废料board看板feeder送料机sliding rack滑料架defective product box不良品箱die change 换模to fix a die装模to take apart a die拆模to repair a die修模packing material包材basket蝴蝶竺plastic basket胶筐isolating plate baffle plate; barricade隔板carton box纸箱to pull and stretch拉深to put material in place, to cut material, to input落料to impose lines压线to compress, compressing压缩character die字模to feed, feeding送料transportation运输(be)qualfied, up to grade合格not up to grade, not qualified不合格material change, stock change材料变更feature change 特性变更evaluation评估prepare for, make preparations for 准备parameters参数rotating speed, revolution转速manufacture management制造管理abnormal handling异常处理production unit生产单位lots of production生产批量steel plate钢板roll material卷料manufacture procedure制程operation procedure作业流程to revise, modify修订to switch over to, switch---tothrow--over switching over切换engineering, project difficulty工程瓶颈stage die工程模automation自动化to stake, staking, reviting铆合add lubricating oil加润滑油shut die架模shut height of a die架模高度analog-mode device类模器die lifter举模器argon welding氩焊vocabulary for stamping冲压常词汇stamping, press冲压punch press, dieing out press冲床uncoiler & strainghtener整平机feeder送料机rack, shelf, stack料架cylinder油缸robot机械手taker取料机conveyer belt输送带transmission rack输送架top stop上死点bottom stop下死点one stroke一行程inch寸动to continue, cont.连动to grip(material)吸料location lump, locating piece, blockstop 定位块reset复位smoothly顺利dent压痕scratch刮伤deformation变形filings铁削to draw holes抽孔inquiry, search for查寻to stock, storage, in stock库存receive领取approval examine and verify审核processing, to process加工delivery, to deliver 交货to return delivenry to.to send delinery backto retrn of goods退货registration登记registration card登记卡to control管制to put forward and hand in提报safe stock安全库存acceptance = receive验收to notice通知application form for purchase请购单consume, consumption消耗to fill in填写abrasion磨损reverse angle = chamfer倒角character die字模to collect, to gather收集failure, trouble故障statistics统计demand and supply需求career card履历卡to take apart a die卸下模具to load a die装上模具to tight a bolt拧紧螺栓to looser a bolt拧松螺栓to move away a die plate移走模板easily damaged parts易损件standard parts标准件breaking.(be)broken,(be)cracked 断裂to lubricate润滑common vocabulary for dieengineering模具工程常用词汇die 模具figure file, chart file图档cutting die, blanking die冲裁模progressive die, follow (-on)die连续模compound die复合模punched hole冲孔panel board镶块to cutedges=side cut=side scrap切边to bending折弯to pull, to stretch拉伸Line streching, line pulling线拉伸engraving, to engrave刻印upsiding down edges翻边to stake铆合designing, to design设计design modification设计变化die block模块folded block折弯块sliding block滑块location pin定位销lifting pin顶料销die plate, front board模板padding block垫块stepping bar垫条upper die base上模座lower die base下模座upper supporting blank上承板upper padding plate blank上垫板spare dies模具备品spring 弹簧bolt螺栓document folder文件夹file folder资料夹to put file in order整理资料spare tools location手工备品仓first count初盘人first check初盘复棹人second count 复盘人second check复盘复核人equipment设备waste materials废料work in progress product在制品casing = containerazation装箱quantity of physical invetory secondcount 复盘点数量quantity of customs count会计师盘,点数量the first page第一联filed by accounting department forreference会计部存查end-user/using unit(department)使用单位summary of year-end physicalinventory bills年终盘点截止单据汇总表bill name单据名称This sheet and physical inventory listwill be sent to accountingdepartment together (Those of NHKwill be sent to financialdepartment)本表请与盘点清册一起送会计部－(NHK厂区送财会部)Application status records of year-endphysical inventory List andphysical inventory card 年终盘点卡与清册使用－状况明细表blank and waste sheet NO.空白与作废单号plate电镀mold成型material for engineering mold testing工程试模材料not included in physical inventory不列入盘点sample样品incoming material to be inspected进货待验description品名steel/rolled steel钢材material statistics sheet物料统计明细表meeting minutes会议记录meeting type 会别distribution department分发单位location地点chairman主席present members出席人员subject主题conclusion结论decision items决议事项responsible department负责单位pre-fixed finishing date预定完成日approved by / checked by / prepared by核准/审核/承办PCE assembly production schedulesheetPCE组装厂生产排配表model机锺work order工令revision版次remark备注production control confirmation生产确认checked by初审approved by核准department部门stock age analysis sheet库存货龄分析表on-hand inventory现有库存available material良品可使用obsolete material良品已呆滞to be inspected or reworked待验或重工total合计cause description原因说明part number/ P/N 料号type形态item/group/class类别quality品质prepared by制表notes说明year-end physical inventory difference analysis sheet年终盘点差异分析表physical inventory盘点数量physical count quantity帐面数量difference quantity差异量cause analysis原因分析raw materials原料materials物料finished product成品semi-finished product半成品packing materials包材good product/accepted goods/ accepted parts/good parts良品defective product/non-good parts不良品disposed goods处理品warehouse/hub仓库on way location在途仓oversea location海外仓spare parts physical inventory list备品盘点清单spare molds location模具备品仓skid/pallet栈板tox machine自铆机wire EDM线割EDM放电机coil stock卷料sheet stock片料tolerance工差score=groove压线cam block滑块pilot导正筒trim剪外边pierce剪内边drag form压锻差pocket for the punch head挂钩槽slug hole废料孔feature die公母模expansion dwg展开图radius半径shim(wedge)楔子torch-flame cut火焰切割set screw止付螺丝form block折刀stop pin定位销round pierce punch=die button圆冲子shape punch=die insert异形子stock locater block定位块under cut=scrap chopper清角active plate活动板baffle plate挡块cover plate盖板male die公模female die母模groove punch压线冲子air-cushion eject-rod气垫顶杆spring-box eject-plate弹簧箱顶板bushing block衬套insert 入块club car高尔夫球车capability能力parameter参数factor系数phosphate皮膜化成viscosity涂料粘度alkalidipping脱脂main manifold主集流脉bezel斜视规blanking穿落模dejecting顶固模demagnetization去磁;消磁high-speed transmission高速传递heat dissipation热传rack上料degrease脱脂rinse水洗alkaline etch龄咬desmut剥黑膜D.I. rinse纯水次Chromate铬酸处理Anodize阳性处理seal封孔revision版次part number/P/N料号good products良品scraped products报放心品defective products不良品finished products成品disposed products处理品barcode条码flow chart流程表单assembly组装stamping冲压molding成型spare parts=buffer备品coordinate座标dismantle the die折模auxiliary fuction辅助功能poly-line多义线heater band 加热片thermocouple热电偶sand blasting喷沙grit 砂砾derusting machine除锈机degate打浇口dryer烘干机induction感应induction light感应光response=reaction=interaction感应ram连杆edge finder巡边器concave凸convex凹short射料不足nick缺口speck瑕疵shine亮班splay 银纹gas mark焦痕delamination起鳞cold slug冷块blush 导色gouge沟槽;凿槽satin texture段面咬花witness line证示线patent专利grit沙砾granule=peuet=grain细粒grit maker抽粒机cushion缓冲magnalium镁铝合金magnesium镁金metal plate钣金lathe车mill锉plane刨grind磨drill铝boring镗blinster气泡fillet镶;嵌边through-hole form通孔形式voller pin formality滚针形式cam driver铡楔shank摸柄crank shaft曲柄轴augular offset角度偏差velocity速度production tempo生产进度现状torque扭矩spline=the multiple keys花键quenching淬火tempering回火annealing退火carbonization碳化alloy合金tungsten high speed steel钨高速的moly high speed steel钼高速的organic solvent有机溶剂bracket小磁导liaison联络单volatile挥发性resistance电阻ion离子titrator滴定仪beacon警示灯coolant冷却液crusher破碎机模具工程类plain die简易模pierce die冲孔模forming die成型模progressive die连续模gang dies复合模shearing die剪边模riveting die铆合模pierce冲孔forming成型(抽凸,冲凸)draw hole抽孔bending折弯trim切边emboss凸点dome凸圆semi-shearing半剪stamp mark冲记号deburr or coin压毛边punch riveting冲压铆合side stretch侧冲压平reel stretch卷圆压平groove压线blanking下料stamp letter冲字(料号)shearing剪断tick-mark nearside正面压印tick-mark farside反面压印冲压名称类extension dwg展开图procedure dwg工程图die structure dwg模具结构图material材质material thickness料片厚度factor系数upward向上downward向下press specification冲床规格die height range适用模高die height闭模高度burr毛边gap间隙weight重量total wt.总重量punch wt.上模重量五金零件类inner guiding post内导柱inner hexagon screw内六角螺钉dowel pin固定销coil spring弹簧lifter pin顶料销eq-height sleeves=spool等高套筒pin销lifter guide pin浮升导料销guide pin导正销wire spring圆线弹簧outer guiding post外导柱stop screw止付螺丝located pin定位销outer bush外导套模板类top plate上托板（顶板）top block上垫脚punch set上模座punch pad上垫板punch holder上夹板stripper pad脱料背板up stripper上脱料板male die公模(凸模)feature die公母模female die母模(凹模)upper plate上模板lower plate下模板die pad下垫板die holder下夹板die set下模座bottom block下垫脚bottom plate下托板(底板) stripping plate内外打(脱料板) outer stripper外脱料板inner stripper内脱料板lower stripper下脱料板零件类punch冲头insert入块(嵌入件)deburring punch压毛边冲子groove punch压线冲子stamped punch字模冲子round punch圆冲子special shape punch异形冲子bending block折刀roller滚轴baffle plate挡块located block定位块supporting block for location定位支承块air cushion plate气垫板air-cushion eject-rod气垫顶杆trimming punch切边冲子stiffening rib punch = stinger 加强筋冲子ribbon punch压筋冲子reel-stretch punch卷圆压平冲子guide plate定位板sliding block滑块sliding dowel block滑块固定块active plate活动板lower sliding plate下滑块板upper holder block上压块upper mid plate上中间板spring box弹簧箱spring-box eject-rod弹簧箱顶杆spring-box eject-plate弹簧箱顶板bushing bolck衬套cover plate盖板guide pad导料块塑件&模具相关英文compre sion molding压缩成型flash mold溢流式模具plsitive mold挤压式模具split mold分割式模具cavity型控母模core模心公模taper锥拔leather cloak仿皮革shiver饰纹flow mark流痕welding mark溶合痕post screw insert螺纹套筒埋值self tapping screw自攻螺丝striper plate脱料板piston活塞cylinder汽缸套chip细碎物handle mold手持式模具移转成型用模具encapsulation molding低压封装成型射出成型用模具two plate两极式（模具）well type蓄料井insulated runner绝缘浇道方式hot runner热浇道runner plat浇道模块valve gate阀门浇口band heater环带状的电热器spindle阀针spear head刨尖头slag well冷料井cold slag冷料渣air vent排气道h=0.02~0.05mmw=3.2mmL=3~5mmwelding line熔合痕eject pin顶出针knock pin顶出销return pin回位销反顶针sleave套筒stripper plate脱料板insert core放置入子runner stripper plate浇道脱料板guide pin导销eject rod (bar)（成型机）顶业捧subzero深冷处理three plate三极式模具runner system浇道系统stress crack应力电裂orientation定向sprue gate射料浇口，直浇口nozzle射嘴sprue lock pin料头钩销(拉料杆) slag well冷料井side gate侧浇口edge gate侧缘浇口tab gate搭接浇口film gate薄膜浇口flash gate闸门浇口slit gate缝隙浇口fan gate扇形浇口dish gate因盘形浇口H=F=1/2t~1/5tT=2.5~3.5mmdiaphragm gate隔膜浇口ring gate环形浇口subarine gate潜入式浇口tunnel gate隧道式浇口pin gate针点浇口Φ0.8~1.0mmRunner less无浇道(sprue less)无射料管方式long nozzle延长喷嘴方式sprue浇口;溶渣品质人员名称类QC quality control 品质管理人员FQC final quality control 终点品质管制人员IPQC in process quality control制程中的品质管制人员OQC output quality control 最终出货品质管制人员IQC incoming quality control 进料品质管制人员TQC total quality control 全面质量管理POC passage quality control 段检人员QA quality assurance 质量保证人员OQA output quality assurance 出货质量保证人员QE quality engineering 品质工程人员品质保证类FAI first article inspection 新品首件检查FAA first article assurance 首件确认TVR tool verification report 模具确认报告3B 3B 模具正式投产前确认CP capability index 能力指数CPK capability index of process 模具制程能力参数SSQA standardized supplier quality合格供应商品质评估OOBA out of box audit 开箱检查QFD quality function deployment品质机能展开FMEA failure model effectivenessanalysis 失效模式分析8 disciplines 8项回复内容FA final audit 最後一次稽核CAR corrective action request 改正行动要求corrective action report 改正行动报告FQC运作类AQL Acceptable Quality Level 运作类允收品质水准S/S Sample size 抽样检验样本大小ACC Accept 允收REE Reject 拒收CR Critical 极严重的MAJ Major 主要的MIN Minor 轻微的AOQ Average Output Quality 平均出厂品质AOQL Average Output QualityLevel 平均出厂品质Q/R/S Quality/Reliability/Service品质/可靠度服务MIL-STD Military-Standard 军用标准S I-S IV Special I-Special IV 特殊抽样水准等级P/N Part Number 料号L/N Lot Number 特采AOD Accept On Deviation 特采UAI Use As It 首件检查报告FPIR First Piece Inspection Report百万分之一PPM Percent Per Million 批号制程统计品管专类SPC Statistical Process Control 统计制程管制SQC Statistical Quality Control 统计品质管制R Range 全距AR Averary Range 全距平均值UCL Upper Central Limit 管制上限LCL Lower Central Limit 管制下限MAX Maximum 最大值MIN Minimum 最小值GRR GaugeReproducibility&Repeatability 量具之再制性及重测性判断量可靠与否DIM Dimension 尺寸DIA Diameter 直径FREQ Frequency 频率N Number 样品数其它品质术语类QCC Quality Control Circle 品质圈QIT Quality Improvement Team 品质改善小组PDCA Plan Do Check Action 计划执行检查总结ZD Zero Defect 零缺点QI Quality Improvement 品质改善QP Quality Policy 目标方针TQM Total Quality Management 全面品质管理MRB Material Reject Bill 退货单LQL Limiting Quality Level 最低品质水准RMA Return Material Audit 退料认可QAN Quality Amelionrate Notice 品质改善活动ADM Absolute Dimension Measuremat 全尺寸测量QT Quality Target 品质目标7QCTools 7 Quality Controll Tools品管七大手法通用之件类ECN Engineering Change Notes 工程变更通知(供应商)ECO Engineering Change Order 工程改动要求(客户)PCN Process Change Notice 工序改动通知PMP Product Management Plan 生产管制计划SIP Specification In Process 制程检验规格SOP Standard Operation Procedure制造作业规范IS Inspection Specification 成品检验规范BOM Bill Of Material 物料清单PS Package Specification 包装规范SPEC Specification 规格DWG Drawing 图面系统文件类QS Quality System 品质系统ES Engineering Standarization 工程标准CGOO China General PCE龙华厂文件H Huston (美国)休斯敦C Compaq (美国)康伯公司C China 中国大陆A Assembly 组装(厂)S Stamping 冲压(厂)P Painting 烤漆(厂)I Intel 英特尔公司T TAIWAN 台湾IWS International WorkmanStandard 工艺标准ISO International StandardOrganization 国际标准化组织GS General Specification 一般规格CMCS C-China M-ManufactC-Compaq S-Stamping Compaq产品在龙华冲压厂制造作业规范CQCA Q-Quality A-AssemblyCompaq产品在龙华组装厂品管作业规范CQCP P-Painting Compaq产品在龙华烤漆厂品管作业规范部类PMC Production & MaterialControl 生产和物料控制PPC Production Plan Control 生产计划控制MC Material Control 物料控制ME Manafacture Engineering 制造工程部PE Project Engineering 产品工程部A/C Accountant Dept 会计部P/A Personal & Administration 人事行政部DC Document Center 资料中心QE Quality Engineering 品质工程(部)QA Quality Assurance 品质保证(处)QC Quality Control 品质管制(课)PD Product Department 生产部LAB Labratry 实验室IE Industrial Engineering 工业工程R&D Research & Design 设计开发部P Painting 烤漆(厂)A Asssembly 组装(厂)S Stamping 冲压(厂)生产类PCS Pieces 个(根,块等)PRS Pairs 双(对等)CTN Carton 卡通箱PAL Pallet/skid 栈板PO Purchasing Order 采购订单MO Manufacture Order 生产单D/C Date Code 生产日期码ID/C Identification Code (供应商)识别码SWR Special Work Request 特殊工作需求L/N Lot Number 批号P/N Part Number 料号其它OEM Original Equipment Manufacture 原设备制造PCE Personal Computer Enclosure 个人电脑外设PC Personal Computer 个人电脑CPU Central Processing Unit 中央处理器SECC SECC` 电解片SGCC SGCC 热浸镀锌材料NHK North of Hongkong 中国大陆PRC People's Republic of China 中国大陆U.S.A the United States of America 美国A.S.A.P As Soon As Possible 尽可能快的E-MAIL Electrical-Mail 电子邮件N/A Not Applicable 不适用QTY Quantity 数量VS 以及REV Revision 版本JIT Just In Time 零库存I/O Input/Output 输入/输出OK Ok 好NG Not Good 不行,不合格C=0 Critical=0 极严重不允许ESD Electry-static Discharge 静电排放5S 希腊语整理,整顿,清扫,清洁,教养ATIN Attention 知会CC Carbon Copy 副本复印相关人员APP Approve 核准,认可,承认CHK Check 确认AM Ante Meridian 上午PM Post Meridian 下午CD Compact Disk 光碟CD-ROM Compact Disk Read-OnlyMemory 只读光碟FDD Floppy Disk Drive 软碟机HDD Hard Disk Drive 碟碟机REF Reference 仅供参考CONN Connector 连接器CA V Cavity 模穴CAD Computer Aid Design 计算机辅助设计ASS'Y Assembly 装配,组装MAT'S Material 材料IC Integrated Circuit 集成电路T/P True Position 真位度TYP Type 类型WDR Weekly Delivery Requitement周出货需求C?T Cycle Time 制程周期L/T Lead Time 前置时间(生产前准备时间)S/T Standard Time 标准时间P/M Product Market 产品市场3CComputer,Commumcation,Consumerelectronic's 消费性电子5WIHWhen,Where,Who,What,Why,How to5MMan,Machine,Material,Method,Measurement4MIHMan,Materia,Money,Method,Time人力,物力,财务,技术,时间(资源)SQA Strategy Quality Assurance策略品质保证DQA Desigh Quality Assurance 设计品质保证MQA Manufacture QualityAssurance 制造品质保证SSQA Sales and service QualityAssurance 销售及服务品质保证LRR Lot Rejeet Rate 批退率BS Brain storming 脑力激荡EMI Electronic Magnetion Inspect高磁测试FMI Frequency Modulatim Inspect高频测试B/M Boar/Molding(flat cable)C/P Connector of PCA/P AssemblySPS Switching power supply 电源箱DT Desk Top 卧式(机箱)MT Mini-Tower 立式(机箱)DVD Digital Vedio DiskVCD Vdeio Compact DiskLCD Liquid Crystal DisplayCAD Computer AID DesignCAM Computer AID ManufacturingCAE Computer AID EngineeringABIOS Achanced Basic input/output system 先进的基本输入/输出系统CMOS Complemeruary MetollOxide Semiconductor 互补金属氧化物半导体PDA Personal Digital Assistant 个人数字助理IC Integrated Circuit 集成电路ISA Industry Standard Architecture 工业标准体制结构MCA Micro Channel Architecture 微通道结构EISA Extended Industry Standard Architecture 扩充的工业标准结构SIMM Single in-line memory module 单项导通汇流组件DIMM Dual in-line Memory Module 双项导通汇流组件LED Light-Emitting Diode 发光二级管FMEA Failure Mode Effectivenes 失效模式分析W/H Wire Harness 金属线绪束集组件F/C Flat Calle 排线PCB Printed Circuit Board 印刷电路板CAR Correction Action Report 改善报告NG Not Good 不良WPR Weekly Delivery Requirement 周出货要求PPM Parts Per Million 百万分之一TPM Total Production Maintenance 全面生产保养MRP Material Requiremcnt Planning 物料需计划OC Operation System 作业系统TBA To Be Design 待定,定缺D/C Drawing ChangeP/P Plans & ProceduneEMI Electrical-Music Industry 电子音乐工业RFI Read Frequency Input 读频输入MMC Maximum Material ConditionMMS Maximum Material SizeLMC Least Material ConditionLMS Least Material Size模具技术用语各种模具常用成形方式accurate die casting 精密压铸powder forming 粉末成形calendaring molding 压延成形powder metal forging 粉末锻造cold chamber die casting 冷式压铸precision forging 精密锻造cold forging 冷锻press forging 冲锻compacting molding 粉末压出成形rocking die forging 摇动锻造compound molding 复合成形rotaryforging 回转锻造compression molding 压缩成形rotational molding 离心成形dip mold 浸渍成形rubber molding橡胶成形encapsulation molding 注入成形sand mold casting 砂模铸造extrusion molding 挤出成形shellcasting 壳模铸造foam forming ?泡成形sinter forging烧结锻造forging roll 轧锻six sides forging 六面锻造gravity casting 重力铸造slushmolding 凝塑成形hollow(blow) molding 中空(吹出)成形squeeze casting 高压铸造hot chamber die casting 热室压铸swaging 挤锻hot forging 热锻transfer molding 转送成形injection molding 射出成形warmforging 温锻investment casting 精密铸造matched die method 对模成形法laminating method 被覆淋膜成形low pressure casting 低压铸造lost wax casting 脱蜡铸造matchedmould thermal forming 对模热成形模各式模具分类用语bismuth mold 铋铸模landed plungermold 有肩柱塞式模具burnishing die 挤光模landed positivemold 有肩全压式模具button die 镶入式圆形凹模loadingshoe mold 料套式模具center-gated mold 中心浇口式模具loose detail mold 活零件模具chill mold 冷硬用铸模loose mold活动式模具clod hobbing 冷挤压制模louveringdie 百叶窗冲切模composite dies 复合模具manifolddie 分歧管模具counter punch 反凸模modular mold组合式模具double stack mold 双层模具multi-cavity mold 多模穴模具electroformed mold 电铸成形模multi-gate mold 复式浇口模具expander die 扩径模offswt bendingdie 双折冷弯模具extrusion die 挤出模palletizing die叠层模family mold 反套制品模具plastermold 石膏模blank through dies 漏件式落料模porous mold 通气性模具duplicated cavity plate 复板模positive mold 全压式模具fantail die 扇尾形模具pressure die 压紧模fishtail die 鱼尾形模具profile die 轮廓模flash mold 溢料式模具progressive die 顺序模gypsum mold 石膏铸模protable mold 手提式模具hot-runner mold 热流道模具prototype mold 雏形试验模具ingot mold 钢锭模punching die 落料模lancing die 切口模raising(embossing) 压花起伏成形re-entrant mold 倒角式模具sectional die 拼合模runless injection mold 无流道冷料模具sectional die 对合模具segment mold 组合模semi-positive mold 半全压式模具shaper 定型模套single cavity mold 单腔模具solid forging die 整体锻模split forging die 拼合锻模split mold 双并式模具sprueless mold 无注道残料模具squeezing die 挤压模stretch form die拉伸成形模sweeping mold 平刮铸模swing die振动模具three plates mold 三片式模具trimming die 切边模unit mold 单元式模具universal mold通用模具unscrewing mold 退扣式模具yoketype die 轭型模模具厂常用之标准零配件air vent vale 通气阀anchor pin 锚梢angular pin 角梢baffle 调节阻板angular pin 倾斜梢baffle plate 折流档板ball button 球塞套ball plunger 定位球塞ball slider 球塞滑块binder plate 压板blank holder 防皱压板blanking die落料冲头bolster 上下模板bottom board 浇注底板bolster 垫板bottom plate 下固定板bracket 托架bumper block 缓冲块buster 堵口casting ladle 浇注包casting lug 铸耳cavity 模穴(模仁)cavity retainer plate 模穴托板centerpin 中心梢clamping block 锁定块coil spring螺旋弹簧cold punched nut 冷冲螺母coolingspiral 螺旋冷却栓core 心型core pin 心型梢cotter 开口梢cross 十字接头cushion pin 缓冲梢diaphragm gate盘形浇口die approach 模头料道die bed 型底die block 块形模体die body 铸模座die bush 合模衬套die button 冲模母模die clamper 夹模器die fastener 模具固定用零件die holder 母模固定板die lip 模唇die plate 冲模板die set 冲压模座direct gate 直接浇口dog chuck 爪牙夹头dowel 定位梢dowel hole 导套孔dowel pin 合模梢dozzle 辅助浇口dowel pin 定位梢draft 拔模锥度draw bead 张力调整杆drive bearing传动轴承ejection pad 顶出衬垫ejector 脱模器ejector guide pin 顶出导梢ejectorleader busher 顶出导梢衬套ejector pad 顶出垫ejector pin 顶出梢ejector plate 顶出板ejector rod 顶出杆ejector sleeve 顶出衬套ejector valve顶出阀eye bolt 环首螺栓filling core 椿入蕊film gate 薄膜形浇口finger pin 指形梢finish machined plate 角形模板finish machined round plate 圆形模板fixed bolster plate 固定侧模板flanged pin 带凸缘?flash gate 毛边形浇口flask 上箱floating punch 浮动冲头gate 浇口gate land 浇口面gib 凹形拉紧?goose neck 鹅颈管guide bushing 引导衬套guide pin 导梢guide post 引导柱guide plate 导板guide rail 导轨head punch 顶?冲头headless punch直柄冲头heavily tapered solid 整体模蕊盒hose nippler 管接头impact damper 缓冲器injection ram压射柱塞inlay busher 嵌入衬套inner plunger内柱塞。

4EE-14资料

1• 15W Isolated Output • Remote ON/OFF Control • 4:1 Input Range • Efficiency to 82% • Six-Sided Shield • 200KHz Switching FrequencyNOTE: 1.Nominal Input Voltage 24 or 48 VDCMODEL INPUT OUTPUT OUTPUT INPUT CURRENT % EFF.CASENUMBER VOLTAGE VOLTAGE CURRENT NO LOAD FULL LOAD 4EE-014EE-024EE-034EE-044EE-054EE-064EE-074EE-084EE-114EE-124EE-134EE-144EE-154EE-164EE-174EE-189-36 VDC18-72 VDC5 VDC 12 VDC 15 VDC±12 VDC ±15 VDC 5/±12 VDC 5/±15 VDC +5/+12/-5 VDC5 VDC 12 VDC 15 VDC±12 VDC ±15 VDC 5/±12 VDC 5/±15 VDC +5/+12/-5 VDC3000 mA 1250 mA 1000 mA ±625 mA ±500 mA 1500/±310 mA 1500/±250 mA 1500/310/500 mA3000 mA 1250 mA 1000 mA ±625 mA ±500 mA 1500/±310 mA 1500/±250 mA 1500/310/500 mA15 mA 15 mA 15 mA 20 mA 20 mA 20 mA 20 mA 20 mA 10 mA 10 mA 10 mA 15 mA 15 mA 15 mA 15 mA 15 mA810 mA 780 mA 780 mA 780 mA 780 mA 780 mA 780 mA 715 mA 410 mA 390 mA 390 mA 380 mA 380 mA 380 mA 380 mA 350 mA77808080808080807780808282828282EEBEHLMAN2Specifications4E EAll Specifications Typical At Nominal Line,Full Load and 25˚C Unless Otherwise Noted.INPUT SPECIFICATIONS:Input Voltage Range.........................................................................................................................................................24V ....................................................9-36V48V ...................................................18-72VInput Filter....................................................................................................................................................................................................................................Pi TypeOUTPUT SPECIFICATIONS:Voltage AccuracySingle Output........................................................................................................................................................................................................................±1.0% max.Dual +Output........................................................................................................................................................................................................................±1.0% max.-Output........................................................................................................................................................................................................................±3.0% max.Triple,5V .................................................................................................................................................................................................................................±2.0% max.12V/15V .......................................................................................................................................................................................................................±3.0% max.Voltage Balance (Dual).......................................................................................................................................................................................................±1.0% max.Transient Response:Single,25% Step Load Change...........................................................................................................................................................................................<500µsec.Dual,FL-1/2L±1% Error Band.................................................................................................................................................................................................<500µsec.External Trim Adj.Range...............................................................................................................................................................................................................±10%.Ripple & Noise,20MHz BW.........................................................................................................................................................................................10mV RMS,max.75mV p-p max.Temperature Coefficient.....................................................................................................................................................................................................±0.02%/°C Short Circuit Protection......................................................................................................................................................................................................Continuous Line Regulation 1,Single/Dual.............................................................................................................................................................................................±0.2% max.Triple...................................................................................................................................................................................................±1.0% max.Load Regulation 2,Single/Dual...........................................................................................................................................................................................±1.0% max.Triple..................................................................................................................................................................................................±5.0% max.GENERAL SPECIFICATIONS:Efficiency .........................................................................................See Table Isolation Voltage.......................................................................500 VDC min Isolation Resistance.........................................................................109ohms Switching Frequency ..................................................................200KHz,min Operating Temperature Range.........................................-25°C to + 71°C Case Temperature.....................................................................100˚C max.Cooling..........................................................................Free-Air Convection Storage Temperature Range...........................................-55°C to + 105°C EMI/RFI..............................................................Six-Sided Continuous Shield Dimensions...............................................................2.56 x 3.0 x 0.83 inches(65 x 76.2 x 21.1 mm)Case Material................................................Black Coated Copper withNon-Conductive BaseCASE EAll Dimensions In Inches(mm)NOTE:1.Measured From High Line to Low Line2.Measured From Full Load to 1/4 LoadRemote On/Off ControlLogic Compatibility EC-On EC-OffShutdown Idle Current Input Resistance Control Common CMOS or Open Collector TTL >+5.5VDC or Open Circuit<1.8 VDC 10 mA100K ohms (Ein 0 VDC to 9 VDC)Referenced to Input MinusExternal Output TrimmingOutput may optionally be externally trimmed (±10%) with a fixed resistor or an external trimpot as shown.PIN 4PIN 6RT 1OR RT 210K ohms TRIMPOTTRIM DOWNPIN 7PIN 4TRIM UPPIN 6PIN 7PIN 4PIN CONNECTIONPin Single Output Daul Output Triple Output 1.2.3.4.5.6.7.8.+Input-InputNo PinOutput TrimNo Pin+Output-Output+Input -Input +Output Common -Output No Pin No Pin +Input -Input +Output Common -Output +5V Output No PinRemote On/Off ControlTRIPLE OUTPUT LOADING TABLE (1)AmperesMin.(2) Nom.Output Voltage( Pin No.)63 & 53 & 53 & 5+5+12 or -12+15 or -15+12 & -50.250.100.100.10/0.101.50.310.250.31/0.50NOTE:1.Maximum total power from all outputs is limited to 15 watts but no output should be allowed to exceed its maximum current.2.Minimum current on each output is required to maintain specified regulation.BEHLMAN4532 Telephone Road Suite 103 Ventura, CA 93003 80 Cabot Court Hauppauge, NY 11788(805 ) 642-0660 (800)456-2006 Fax (805) 642-0790 e-mail: sales@ (631)435-0410 (800)874-6727 Fax(631)951-4341Web-site: 。

MX5000 APC Matrix-UPS 5kVA 208V 240V 商品说明书

MX5000APC Matrix-UPS 5kVA 208V/240V In 120/208/240V OutStandard Lead Time : Usually Ships within 2 WeeksAPC Matrix-UPS, 3750 Watts / 5000VA,Input 208V / Output 120V, 208V, Interface Port DB-9 RS-232, SmartSlot, Extended runtime modelIncludes : CD with software, Smart UPS signalling RS-232 cable, User ManualMatrix-UPS Features & BenefitsAvailabilityAutomatic internal bypassSupplies utility power to the connected loads in the event of a UPS overload condition or fault.Intelligent Battery Management Maximizes battery performance, life, and reliability through intelligent, precision charging.Hot-swappable batteriesEnsures clean, uninterrupted power to protected equipment while batteries are being replacedHot-swappable modulesEnsures clean, uninterrupted power to protected equipment during Power Module replacement.Scalable runtime Allows additional run time to be quickly added as needed.Automatic self-testPeriodic battery self-test ensures early detection of a battery that needs to be replaced.Manageable external batteries Reduces preventative maintenance service needs by monitoring the health and status of the external batteries and their expected runtime. Battery modules connected in parallelDelivers higher availability through redundant batteries. Automatic restart of loads after UPS shutdownAutomatically starts up the connected equipment upon the return of utility power. Modular design Provides fast serviceability and reduced maintenance requirements via self-diagnosing, field-replaceable modules.AdaptabilityAdjustable voltage-transfer points Maximizes useful battery life by widening the input voltage window or tightening the output voltage regulation.Plug-and-Play external batteries Ensures clean, uninterrupted power to the loads when adding extra runtime to the UPS. Field-replaceable power distribution panelEnsures compatibility with equipment that has different plug types. ManageabilitySmartSlot Customize UPS capabilities with management cards.LCD displayAlpha-Numeric Display which displays system parameters and alarms. Serial Connectivity Provides management of the UPS via a serial port.InfraStruXureManager CompatibleEnables centralized management via the APC InfraStruXure® Manager.ServiceabilityUser-replaceable batteriesIncreases availability by allowing a trained user to perform upgrades and replacements of the batteries reducing Mean Time to Repair (MTTR) Predictive failure notificationProvides early-warning fault analysis ensuring proactive component replacement.User-replaceable batteriesIncreases availability by allowing a trained user to perform upgrades and replacements of the batteries reducing Mean Time to Repair (MTTR) User-replaceable power modules Enables simple upgrades and replacements of the Power Modules.Audible AlarmsActively let you know if the unit is on battery, if the battery is low or if there is an overload condition.ProtectionOutputOutput Power Capacity 3750 Watts / 5000 VAMax Configurable Power 3750 Watts / 5000 VANominal Output Voltage 120V,208VEfficiency at Full Load 93%Output Voltage Distortion Less than 5% at full loadOutput Frequency (sync to mains) 57 - 63 Hz for 60 Hz nominalCrest Factor up to 5 : 1Waveform Type Sine waveOutput Connections(6) NEMA 5-15R(1) NEMA L14-30R(2) NEMA L6-30RBypass Internal Bypass (Automatic and Manual)InputNominal Input Voltage 208VInput Frequency 60 Hz +/- 5 HzInput ConnectionsNEMA L6-30PCord Length 1.83 metersInput voltage range for main156 - 252 (208) / 176 - 282 ( 240V)VoperationsOther Input Voltages 240Batteries & RuntimeBattery Type Maintenance-free sealed Lead-Acid battery with suspended electrolyte : leakproof Typical recharge time 3.30 hour(s)RBC™ Quantity 2Replacement battery cartridge note The MX5000 ships with 2-SmartCell's. There is no RBC available for a standardSmartCell. If a SmartCell-XR is being used,then an RBC14 may be purchased. Typical Backup Time27.8 minutes (1875 Watts)at Half LoadTypical Backup Time 10.2 minutes (3750 Watts)at Full LoadRuntime Chart Matrix-UPSExtended Run Options APC Matrix-UPS 5kVA 208V/240V In 120/208/240V OutCommunications & ManagementInterface Port(s) DB-9 RS-232,SmartSlot1Available SmartSlot™ InterfaceQuantityControl panel Multi-function LCD status and control consoleAudible Alarm Alarm when on battery : distinctive low battery alarm : configurable delays Emergency Power Off (EPO) YesPhysicalMaximum Height 683.00 mmMaximum Width 351.00 mmMaximum Depth 452.00 mmNet Weight 137.73 KGShipping Weight 155.91 KGColor BeigeUnits per Pallet 1.00EnvironmentalOperating Environment 0 - 40 °COperating Relative Humidity 0%Operating Elevation 0-3000 metersStorage Temperature -15 - 45 °CStorage Relative Humidity 0%Storage Elevation 0-15000 meters60.00 dBAAudible noise at 1 meter fromsurface of unitOnline Thermal Dissipation 900.00 BTU/hrConformanceRegulatory Approvals CE,CSA,FCC Part 15 Class A,UL 1778Standard Warranty 2 years repair or replace,optional on-site warranties available,optional extended**The time to recharge to 90% of full battery capacity following a discharge to shutdown using a load rated for 1/2 the full load rating of the UPS.8.0 Storing the UPS8.1 Storage ConditionsThe UPS should be covered and stored in a cool dry location. The UPS should be stored with the Battery Packs in a fully charged state. That is, the reported battery capacity should be at 100% before the UPS is switched off for storage. Disconnect the Battery Packs from the UPS and from each other (where applicable). Store the Battery Packs in an upright position.8.2 Extended StorageTo achieve expected run time following extended storage, the UPS should be allowed to refresh the Battery Packs every 6 months in environments where the ambient temperature is -15°C to +30°C (5°F to 86°F). For extended storage in environments where the ambient temperature is +30°C to +45°C (86°F to 113°F), the UPS should be allowed to refresh the Battery Packs every 3 months.9.0 SpecificationsNote: Where specification ratings differ, values for the UPS configured for 240 Vac operation are given in brackets [ ].9.1 InputNominal input voltage:single phase 208 Vac [240 Vac].Nominal input frequency: 60 Hz.On-line efficiency @ full load: > 92%, > 93% with fully charged batteries for the 3000VA and 5000VA models, respectively.Input circuit breaker: 20 Amp, 30 Amp; for the 3000VA and 5000VA models, respectively.Input connector: NEMA L6-30P (250V/30A).9.2 Transfer CharacteristicsFrequency limits for on-line operation: 60 Hz, ±5%.Input voltage limits for on-line operation: -25% to +15% of the nominal input voltage.Transfer to/from on-battery: 0 ms typical with computer loads, 1.5 ms maximum. Transfer occurs synchronous with the utility voltage phase.Transfer to/from bypass: Transfers to and from bypass occur synchronously with the utility voltage phase. Transfers both to and from bypass mode occur in 0 mS typically.9.3 Output CharacteristicsMaximum load:*****************************;**************************** [5000VA,*********************]forthe3000VAand5000VAmodels,respectively.Nominal output voltages: 208 Vac / 120 Vac [240 Vac / 120 Vac].On-line voltage regulation: ±5%. When "Auto" or "Low" utility failure sensitivity is selected by the user, the output voltage regulation may become relaxed to +5%, -12%.On-line frequency regulation: 60 Hz, ±5% (synchronized to the utility).On-battery output voltage regulation: ±5%.On-battery output frequency regulation: 60 Hz, ±0.1 Hz unless synchronized to utility frequency during utility brownout.On-battery output voltage total harmonic distortion: < 5%.Protection: overcurrent and short circuit protected, latching shutdown upon overload.Output connections:(6) NEMA 5-15R receptacles, (1) NEMA L14-30R receptacle, and (2) NEMA L6-30R receptacles.9.4 Noise and Surge IsolationIsolation: galvanic isolation, output neutral bonded to ground.Normal mode EMI/RFI noise attenuation: 40 to 60 dB over 100 kHz to 30 MHz range. Common mode EMI/RFI noise attenuation: 40 to 60 dB over 100 kHz to 30 MHz range.Normal mode let-through:< 1% of applied ANSI C62.41 Category A or B ±6 kV test.Common mode let-through:< 2% of applied ANSI C62.41 Category A or B ±6 kV test.9.5 Battery PackBattery type: spill proof, maintenance free sealed lead-acid.Nominal battery pack voltage: 48 Vdc.Typical battery life: 3 to 6 years (depends upon number of discharge cycles and normal ambient temperature).Recharge time: see table in section 9.9.Maximum number of Battery Packs: limited only by desired recharge time.9.6 EnvironmentOperating temperature: 0°C to 40°C (32°F to 104°F).Storage temperature: -15°C to 45°C (5°F to 113°F).Operating and storage relative humidity: 0 to 95%, non-condensing.Operating elevation: 0 to 3,000 m (10,000 ft).Storage elevation: 0 to 15,000 m (50,000 ft).Electromagnetic immunity: IEC 801-2, 801-3, 801-4, 801-5; severity level III or IV.Audible noise: < 55 dBA at 1 m (3 ft).9.7 PhysicalUPS dimensions (EU and IU mated): 17.8" H x 13.8" W x 17.8" D (45.2 x 35.1 x 45.2 cm). Battery pack dimensions: 9.1" H x 6.9" W x 17.8" D (23.1 x 17.5 x 45.2 cm).UPS weight (EU and IU mated): 145 lb (65.8 kg), 176 lb (79.8 kg) for the 3000VA and 5000VA models, respectively.Electronics Unit (EU) weight: 40 lb (18.1 kg), 45 lb (20.4 kg) for the 3000VA and 5000VA models, respectively. Add 8 lbs (3.6 kg) for shipping independent of IU.Battery pack weight: 64 lbs (29.0 kg). Add 5 lbs (2.3 kg) for shipping independent of UPS.Total shipping weight - 3000VA model: 244 lb (110.7 kg). Includes weight of packaging, mated EU and IU, and one (1) Battery Pack.Total shipping weight - 5000VA model: 344 lb (156.0 kg). Includes weight of packaging, mated EU and IU, and two (2) Battery Packs.Color: beige.9.8 ApprovalsSafety approvals: UL per 1778, CSA per C22.2.EMC verification: FCC, CDC Class A verified.9.9 Typical On-Battery Run TimesTypical On-Battery Run Time Versus Load, 3000 VA Matrix-UPS with SmartCells, in HoursNumber of SmartCellsComputer Load12345678 (VA)250 3.077.2011.5615.9320.2924.6529.0233.38500 1.46 3.52 5.808.2410.6913.1315.5718.0110000.57 1.46 2.46 3.52 4.58 5.807.028.2415000.330.83 1.46 2.11 2.81 3.52 4.23 4.9920000.220.570.99 1.46 1.93 2.46 2.99 3.5225000.170.460.78 1.18 1.59 1.99 2.45 2.9030000.130.360.620.92 1.25 1.59 1.92 2.30Recharge Time, in Hours1.22.8 2.73.84.9678.1Calculations based on loads with a .75 power factor. Lower power factor loads will yield higher run times.Run times are typical at 25° C (77° F).Recharge times to 90% of rated capacity after discharge into 50% of rated load.Typical On-Battery Run Time Versus Load, 3000 VA Matrix-UPS with SmartCell XR Battery Packs, in HoursNumber of SmartCell XR Battery PacksComputer Load12345678 (VA)10003 6.7510.7514.7518.7522.7526.7530.751500 1.8 4.3 6.99.512.114.717.319.92000 1.2357911131525000.9 2.44 5.67.28.810.41230000.75 1.8 3.25 4.7 6.157.69.0510.5Recharge Time, in Hours3.88.112.516.921.325.730.134.5Calculations based on loads with a .75 power factor. Lower power factor loads will yield higher run times.Run times are typical at 25° C (77° F).Recharge times to 90% of rated capacity after discharge into 50% of rated load.Typical On-Battery Run Time Versus Load, 5000 VA Matrix-UPS with SmartCells, in HoursNumber of SmartCellsComputer Load2345678 (VA)500 3.07 5.027.209.3811.5613.7515.931000 1.46 2.46 3.52 4.58 5.807.028.2415000.83 1.46 2.11 2.81 3.52 4.23 4.9920000.570.99 1.46 1.93 2.46 2.99 3.5225000.460.78 1.18 1.59 1.99 2.45 2.9030000.360.620.92 1.25 1.59 1.92 2.3040000.240.420.620.83 1.08 1.33 1.5950000.170.310.460.620.780.98 1.18Recharge Time, in Hours2.8 2.73.84.9678.1The case of one SmartCell does not apply to 5000 VA Matrix-UPS.Calculations based on loads with a .75 power factor. Lower power factor loads will yield higher run times.Run times are typical at 25° C (77° F).Recharge times to 90% of rated capacity after discharge into 50% of rated load.Typical On-Battery Run Time Versus Load, 5000 VA Matrix-UPS with SmartCell XR Battery Packs, in HoursNumber of SmartCell XR Battery PacksComputer Load12345678 (VA)10003 6.7510.7514.7518.7522.7526.7530.75 1500 1.8 4.3 6.99.512.114.717.319.9 2000 1.23579111315 25000.9 2.44 5.67.28.810.412 30000.75 1.8 3.25 4.7 6.157.69.0510.5 40000.53 1.25 2.25 3.25 4.25 5.25 6.257.25 50000.370.9 1.6 2.4 3.24 4.8 5.6Recharge Time, in Hours3.88.112.516.921.325.730.134.5 Calculations based on loads with a .75 power factor. Lower power factor loads will yield higher run times.Run times are typical at 25° C (77° F).Recharge times to 90% of rated capacity after discharge into 50% of rated load.MX5000。