MC74LCX16373

DT SUFFIX PLASTIC TSSOP PACKAGE CASE 12s OEn LEn D0–D15 O0–O15 Function Output Enable Inputs Latch Enable Inputs Inputs Outputs
Near Zero Static Supply Current in All Three Logic States (20µA) Substantially Reduces System Power Requirements • Latchup Performance Exceeds 500mA
MC74LCX16373
LOW–VOLTAGE CMOS 16–BIT TRANSPARENT LATCH
• • • • • • • • •
Designed for 2.7 to 3.6V VCC Operation 5.4ns Maximum tpd 5V Tolerant — Interface Capability With 5V TTL Logic Supports Live Insertion and Withdrawal IOFF Specification Guarantees High Impedance When VCC = 0V LVTTL Compatible LVCMOS Compatible 24mA Balanced Output Sink and Source Capability
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low-Voltage CMOS 16-Bit Transparent Latch
With 5V-Tolerant Inputs and Outputs (3-State, Non-Inverting)
The MC74LCX16373 is a high performance, non–inverting 16–bit transparent latch operating from a 2.7 to 3.6V supply. The device is byte controlled. Each byte has separate Output Enable and Latch Enable inputs. These control pins can be tied together for full 16–bit operation. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A VI specification of 5.5V allows MC74LCX16373 inputs to be safely driven from 5V devices. The MC74LCX16373 contains 16 D–type latches with 3–state 5V–tolerant outputs. When the Latch Enable (LEn) inputs are HIGH, data on the Dn inputs enters the latches. In this condition, the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH–to–LOW transition of LE. The 3–state outputs are controlled by the Output Enable (OEn) inputs. When OE is LOW, the outputs are enabled. When OE is HIGH, the standard outputs are in the high impedance state, but this does not interfere with new data entering into the latches.
• ESD Performance: Human Body Model >2000V; Machine Model >200V
11/96
© Motorola, Inc. 1996
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REV 1
MC74LCX16373
LOGIC DIAGRAM
1 OE1 1 O0 2 O1 3 GND 4 O2 5 O3 6 VCC 7 O4 8 O5 9 GND 10 O6 11 O7 12 O8 13 O9 14 GND 15 O10 16 O11 17 VCC 18 O12 19 O13 20 GND 21 O14 22 O15 23 OE2 24 48 LE1 47 D0 46 D1 45 GND 44 D2 43 D3 42 VCC 41 D4 40 D5 39 GND 38 D6 37 D7 36 D8 35 D9 34 GND 33 D10 32 D11 31 VCC 30 D12 29 D13 28 GND 27 D14 26 D15 25 LE2 37 D7 nLE Q D 12 O7 D15 26 nLE Q D 23 O15 38 D6 D 40 D5 nLE Q D nLE Q 11 O6 D14 27 D D4 nLE 41 D 9 O5 D13 29 Q 8 O4 D12 30 D 20 Q D nLE Q 22 O14 O13 nLE Q 19 O12 D3 43 nLE Q D 6 O3 D11 32 nLE Q D 17 O11 D2 44 nLE Q D 5 O2 D10 33 nLE Q D 16 O10 D1 nLE 46 D Q 3 O1 D9 35 D nLE Q 14 O9 47 D0 D OE1 48 LE1 nLE Q 2 O0 D8 36 D LE2 nLE Q 13 O8 OE2 25 24