C9950中文资料

3.3V, 180-MHz, Multi-Output Clock DriverC9950Product Features•180-MHz Clock Support•Supports PowerPC™, Intel ®, and RISC Processors •9 Clock Outputs: Frequency Configurable •Oscillator or Crystal Reference Input •Output Disable Control•Spread Spectrum Compatible •Pin Compatible with MPC950•Industrial Temp. Range: –40°C to +85°C •32-Pin TQFP PackageNote:1.x = is the reference input frequencyTable 1.Frequency Table [1]SEL (A:D)FB_SEL = 1FB_SEL = 1QA QB QC (0,1)QD (0:4)QA QB QC (0,1)QD (0:4)00004x 2x 2x 2x 8x 4x 4x 4x 00014x 2x 2x x 8x 4x 4x 2x 00104x 2x x 2x 8x 4x 2x 4x 00114x 2x x x 8x 4x 2x 2x 01004x x 2x 2x 8x 2x 4x 4x 01014x x 2x x 8x 2x 4x 2x 01104x x x 2x 8x 2x 2x 4x 01114x x x x 8x 2x 2x 2x 10002x 2x 2x 2x 4x 4x 4x 4x 10012x 2x 2x x 4x 4x 4x 2x 10102x 2x x 2x 4x 4x 2x 4x 10112x 2x x x 4x 4x 2x 2x 11002x x 2x 2x 4x 2x 4x 4x 11012x x 2x x 4x 2x 4x 2x 11102x x x 2x 4x 2x 2x 4x 11112xxxx4x2x2x2xNote:2.PD = Internal Pull-Down, PU = Internal Pull-Up.Pin Description [2]Pin Name PWRI/O TypeDescription8XIN I Oscillator Input. Connect to a crystal.9XOUT 0Oscillator Output. Connect to a crystal.30TCLK I External Test Clock Input.28QA VDDC O Clock Output. See Frequency Table. 26QB VDDC O Clock Output. See Frequency Table.22, 24QC(1,0)VDDC O Clock Outputs. See Frequency Table.12, 14, 16, 18, 20QD(4:0)VDDC O Clock Outputs. See Frequency Table.2FB_SELIPD Feedback Select Input.If FB_SEL = 1, then the (÷8) counter is selected in the PLL feed-back loop.If FB_SEL = 0, then the (÷16) counter is selected in the PLL feedback loop.10MR/OE#IMaster Reset/Output Enable Input. When asserted HIGH, resets all of the internal flip-flops and also disables all of the outputs. When pulled LOW, releases the internal flip-flops from reset and enables all of the outputs.31PLL_EN I PLL Enable Input. When asserted HIGH, PLL is enabled. And when set LOW, PLL is bypassed.32REF_SEL I Reference Select Input. When HIGH, TCLK is the reference clock and when LOW, the crystal oscillator is selected.3, 4, 5, 6SEL(A:D)IFrequency Select Inputs. See Frequency Table.If SEL_ = 1, then QA divider = ÷4, QB:D divider = ÷8If SEL_ = 0, then QA divider = ÷2, QB:D divider = ÷411, 15, 19, 23, 27VDDC 3.3V Power Supply for Output Clock Buffers.1VDD 3.3V Power Supply for PLL 7, 13, 17, 21, 25,29VSSCommon GroundDescriptionThe C9950 has an integrated PLL that provides low skew and low jitter clock outputs for high-performance microprocessors.The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz and 480 MHz. This allows a wide range of output frequencies from 25 MHz to 180 MHz.The internal VCO frequency is divided by 8 or 16 and com-pared to the input reference clock. These selectable dividers allow for input reference clock flexibility. The internal VCO isthe outputs Q(B:D) depending on the configuration (see Table 2). The use of even dividers ensures that the output duty cycle remains at 50%.Output FrequencyThe C9950 generates outputs with programmable frequency relationships. As a result, the input reference frequency is a function of the desired output frequency (Table 1). The follow-ing block diagram illustrates the corresponding parameters that are needed to calculate the output frequency.Fref = FVCO/m, FVCO = FQn x N Fref = (FQn x N) / mWhere m = 8 (FB_SEL = 1) or m = 16 (FB_SEL = 0), and N = 2, 4, or 8 depending on SEL_ as shown in Table 1.Table 2.INPUTSOUTPUTSSELA SELB SELC SELD QA QBQC QD 0000VCO/2VCO/4VCO/4VCO/40001VCO/2VCO/4VCO/4VCO/80010VCO/2VCO/4VCO/8VCO/40011VCO/2VCO/4VCO/8VCO/80100VCO/2VCO/8VCO/4VCO/40101VCO/2VCO/8VCO/4VCO/80110VCO/2VCO/8VCO/8VCO/40111VCO/2VCO/8VCO/8VCO/81000VCO/4VCO/4VCO/4VCO/41001VCO/4VCO/4VCO/4VCO/81010VCO/4VCO/4VCO/8VCO/41011VCO/4VCO/4VCO/8VCO/81100VCO/4VCO/8VCO/4VCO/41101VCO/4VCO/8VCO/4VCO/81110VCO/4VCO/8VCO/8VCO/41111VCO/4VCO/8VCO/8VCO/8Notes:3.For best performance and accurate frequencies from this device, It is recommended but not mandatory that the chosen crystal meets or exceeds thesespecificationsrger values may cause this device to exhibit oscillator startup problemsTable 3.Suggested Oscillator Crystal Parameters Parameter Description ConditionsMin.Typ.Max.Unit T C Frequency ToleranceNote 1--±100PPM T S Frequency T emperature Stability (T A –10 to +60°C)[3]--±100PPM T A Aging(first 3 years @ 25°C)[3]--5PPM/Yr C L Load Capacitance The crystal ’s rated load [3]-20-pF R ESREffective Series Resistance (ESR)Note 4-4080OhmsMaximum Ratings [5]Maximum Input Voltage Relative to V SS :............ V SS – 0.3V Maximum Input Voltage Relative to V DD :.............V DD + 0.3V Storage Temperature:................................–65°C to + 150°C Operating Temperature:................................–40°C to +85°C Maximum ESD protection..............................................2 KV Maximum Power Supply:................................................5.5V Maximum Input Current:..................................................±20 mAThis device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however,precautions should be taken to avoid application of any volt-age higher than the maximum rated voltages to this circuit. For proper operation, V in and V out should be constrained to the range:V SS < (V in or V out ) < V DDUnused inputs must always be tied to an appropriate logic volt-age level (either V SS or V DD ).Notes:5.The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.6.Inputs have internal pull-up/pull-down resistors that affect input current .7.Driving series or parallel terminated 50Ω (or 50Ω to V DD /2) transmission. Output buffers are dual staged to control drive strength in order to reduce over / undershoot.8.Parameters are guaranteed by design and characterization. Not 100% tested in production.9.Maximum and minimum input reference is limited by the VCO lock range.10.Outputs loaded with 30 pF each.DC Parameters: V DD = V DDC = 3.3V ±5%, T A = –40°C to +85°CParameter DescriptionConditionsMin.Typ.Max.Unit V IL Input Low Voltage 0.8V V IH Input High Voltage2.0V I IL Input Low Current (@V IL = V SS )Note 6–120µA I IH Input High Current (@V IL =V DD )Note 6120µA V OL Output Low Voltage I OL = 40 mA, Note 70.5V V OH Output High Voltage I OH = –40 mA, Note 7 2.4V I DDC Quiescent Supply Current All V DDC and V DD 1520mA I DD PLL Supply Current V DD only1520mA C inInput Capacitance4pFAC Parameters [8]: V DD = V DDC = 3.3V ±5%, T A = –40°C to +85°CParameter DescriptionConditionsMin.Typ.Max.Unit Tr/Tf TCLK Input Rise/Fall 3.0ns Fref Reference Input Frequency Note 9Note 2MHz Fxtal Crystal Oscillator Frequency See Table 3 for details1025MHz FrefDC Reference Input Duty Cycle 2575%Fvco PLL VCO Lock Range 200480MHz Tlock Maximum PLL lock Time 10ms Tr/Tf Output Clocks Rise/Fall Time [10]0.8V to 2.0V 0.101.0ns FoutMaximum Output FrequencyQA = (÷2)180MHzQA/QB = (÷4)120QB = (÷8)60FoutDC Output Duty CycleTCYCLE/2 – 1TCYCLE/2 + 1ns tpZL, tpZH Output enable time (all outputs)6ns tpLZ, tpHZ Output disable time (all outputs)7ns TCCJ Cycle to Cycle Jitter (peak to peak)[10]±100ps TSKEW0Any Output to Any Output Skew [10]200350psPackage Drawing and DimensionsNote:11.The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below.32-Pin TQFP Outline DimensionsOrdering InformationPart Number [11]Package Type Production FlowC9950AA32-Pin TQFPIndustrial, –40°C to +85°CDocument Title: C9950 3.3V, 180-MHz, Multi-Output Clock Driver Document Number: 38-07072REV.ECN NO.IssueDateOrig. ofChange Description of Change**10710806/11/01IKA Convert from IMI to Cypress*A10812507/03/01NDP Delete Pull Down in Pin 10, 30, & 32 and Pull Up in Pin 3, 4, 4, 5, 6, & 31(Seepage 2)*B10980202/08/02DSG Convert from Word to Frame*C12275712/22/02RBI Add power up requirements to maximum ratings information。