A416316AV-40L中文资料
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Symbol VCC VSS VIH VIL Input Voltage Description Supply Voltage
(Ta = 0°C to +70°C) Min. 4.5 0.0 2.4 -1.0 Typ. 5.0 0.0 Max. 5.5 0.0 VCC + 1 0.8 Unit V V V V
A0 – A7 I/O0 - I/O15
RAS
PRELIMINARY
A416316AS
(October, 1999, Version 0.1)
A416316AV
UCAS
LCAS
WE OE
VCC VSS NC
1
AMIC Technology, Inc.
元器件交易网
A416316A Series
Selection Guide
Symbol tRAC tAA tCAC tOEA tRC tPC ICC1 ICC6 Description Maximum RAS Access Time Maximum Column Address Access Time Maximum CAS Access Time Maximum Output Enable ( OE ) Access Time Minimum Read or Write Cycle Time Minimum Fast Page Mode Cycle Time Maximum Operating Current Maximum CMOS Standby Current -30 30 16 10 10 65 19 95 2 -35 35 18 11 11 70 21 85 2 -40 40 20 12 12 75 23 75 2 Unit ns ns ns ns ns ns mA mA
X0 - X7
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
LCAS
LCAS CLOCK GENERATOR
WE
WE CLOCK GENERATOR
OE
OE CLOCK GENERATOR SUBSTRATE BIAS GENERATOR
Recommended Operating Conditions
RAS
UCAS
H L H
LCAS
H L L
WE
OE
Address L Row/Col. Row/Col.
I/Os L Data Out I/O0-7 = Data Out I/O8-15 = High-Z I/O0-7 = High-Z I/O8-15 = Data Out Data In I/O0-7 = Data In I/O8-15 = X I/O0-7 = X I/O8-15 = Data In Data Out → Data In Data Out Data Out Data In Data In Data In Data In Data Out Data In → High-Z High-Z X L
PRELIMINARY
(October, 1999, Version 0.1)
2
AMIC Technology, Inc.
元器件交易网
A416316A Series
Block Diagram
I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8
Preliminary
Features
n Organization: 65,536 words X 16 bits n Part Identification: - A416316A - A416316A-L (with self-refresh mode) n High speed - 30/35/40 ns RAS access time - 16/18/20 ns column address access time - 10/11/12 ns CAS access time n Low power consumption - Operating: 75mA (-30 max) - Standby: 3 mA (TTL) Separate CAS ( UCAS , LCAS ) for byte selection Self refresh mode 256 refresh cycles, 4 ms refresh interval Read-modify-write, RAS -only, CAS -before- RAS , Hidden refresh capability n TTL-compatible, three-state I/O n JEDEC standard packages - 400mil, 40-pin SOJ - 400mil, 40/44 TSOP type II package n Single 5V power supply/built-in VBB generator n n n n
VCC VSS
REFRESH CONTROLLER
Y0 - Y7 COLUMN DECODER SENSE AMP
UPPER BYTE DATA I/O BUFFER
256 X 16 LOWER BYTE DATA I/O BUFFER
பைடு நூலகம்
A0 RAS RAS CLOCK GENERATOR A1 A2 A3 A4 A5 UCAS UCAS CLOCK GENERATOR A6 A7 ADDRESS BUFFERS ROW DECODER 256 256 X 256 X 16 ARRAY
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Pin Configuration n SOJ n TSOP
Pin Descriptions
Symbol
VCC I/O0 I/O 1 I/O 2 I/O 3 VCC I/O 4 I/O 5 I/O 6 I/O 7 NC NC WE RAS NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS I/O 15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE NC A7 A6 A5 A4 VSS VCC I/O0 I/O 1 I/O 2 I/O 3 VCC I/O 4 I/O5 I/O 6 I/O 7 NC NC WE RAS NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 25 24 23 VSS I/O 15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE NC A7 A6 A5 A4 VSS
Functional Description
The A416316A is a high performance CMOS Dynamic Random Access Memory organized as 65,536 words X 16 bits. The A416316A is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The A416316A features a high speed page mode operation in which high speed read, write and read-write are performed on any of the bits defined by the column address. The asynchronous column address uses an extremely short row address capture time to ease the system level timing constraints associated with multiplexed addressing. Output is tri-stated by a column address strobe ( UCAS and LCAS ) which acts as an output enable independent of RAS . Very fast UCAS and LCAS to output access time eases system design. All inputs are TTL compatible. Fast Page Mode operation allows random access up to 256 X 16 bits within a page, with cycle time as short as 19/21/23 ns. The A416316A is best suited for graphics, digital signal processing and high performance peripherals. The A416316A is available in JEDEC standard 40-pin plastic SOJ package and 40/44 TSOP type II package.
元器件交易网
A416316A Series
Preliminary
Document Title 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE Revision History
Rev. No.
0.0 0.1
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Description Address Inputs Data Input/Output Row Address Strobe Column Address Strobe/Upper Byte Control Column Address Strobe/Lower Byte Control Write Enable Output Enable +5V Power Supply Ground No Connection
PRELIMINARY
(October, 1999, Version 0.1)
3
AMIC Technology, Inc.
元器件交易网
A416316A Series
Truth Table
Function Standby Read: Word Read: Lower Byte
History
Initial issue Change ICC7 test condition from “all other input high levels are VCC-0.2V or input low levels are VSS+0.2V” to “all other input low levels are VSS+0.2V”
Issue Date
September 7, 1999 October 26, 1999
Remark
Preliminary
PRELIMINARY
(October, 1999, Version 0.1)
AMIC Technology, Inc.
元器件交易网
A416316A Series
(Ta = 0°C to +70°C) Min. 4.5 0.0 2.4 -1.0 Typ. 5.0 0.0 Max. 5.5 0.0 VCC + 1 0.8 Unit V V V V
A0 – A7 I/O0 - I/O15
RAS
PRELIMINARY
A416316AS
(October, 1999, Version 0.1)
A416316AV
UCAS
LCAS
WE OE
VCC VSS NC
1
AMIC Technology, Inc.
元器件交易网
A416316A Series
Selection Guide
Symbol tRAC tAA tCAC tOEA tRC tPC ICC1 ICC6 Description Maximum RAS Access Time Maximum Column Address Access Time Maximum CAS Access Time Maximum Output Enable ( OE ) Access Time Minimum Read or Write Cycle Time Minimum Fast Page Mode Cycle Time Maximum Operating Current Maximum CMOS Standby Current -30 30 16 10 10 65 19 95 2 -35 35 18 11 11 70 21 85 2 -40 40 20 12 12 75 23 75 2 Unit ns ns ns ns ns ns mA mA
X0 - X7
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
LCAS
LCAS CLOCK GENERATOR
WE
WE CLOCK GENERATOR
OE
OE CLOCK GENERATOR SUBSTRATE BIAS GENERATOR
Recommended Operating Conditions
RAS
UCAS
H L H
LCAS
H L L
WE
OE
Address L Row/Col. Row/Col.
I/Os L Data Out I/O0-7 = Data Out I/O8-15 = High-Z I/O0-7 = High-Z I/O8-15 = Data Out Data In I/O0-7 = Data In I/O8-15 = X I/O0-7 = X I/O8-15 = Data In Data Out → Data In Data Out Data Out Data In Data In Data In Data In Data Out Data In → High-Z High-Z X L
PRELIMINARY
(October, 1999, Version 0.1)
2
AMIC Technology, Inc.
元器件交易网
A416316A Series
Block Diagram
I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8
Preliminary
Features
n Organization: 65,536 words X 16 bits n Part Identification: - A416316A - A416316A-L (with self-refresh mode) n High speed - 30/35/40 ns RAS access time - 16/18/20 ns column address access time - 10/11/12 ns CAS access time n Low power consumption - Operating: 75mA (-30 max) - Standby: 3 mA (TTL) Separate CAS ( UCAS , LCAS ) for byte selection Self refresh mode 256 refresh cycles, 4 ms refresh interval Read-modify-write, RAS -only, CAS -before- RAS , Hidden refresh capability n TTL-compatible, three-state I/O n JEDEC standard packages - 400mil, 40-pin SOJ - 400mil, 40/44 TSOP type II package n Single 5V power supply/built-in VBB generator n n n n
VCC VSS
REFRESH CONTROLLER
Y0 - Y7 COLUMN DECODER SENSE AMP
UPPER BYTE DATA I/O BUFFER
256 X 16 LOWER BYTE DATA I/O BUFFER
பைடு நூலகம்
A0 RAS RAS CLOCK GENERATOR A1 A2 A3 A4 A5 UCAS UCAS CLOCK GENERATOR A6 A7 ADDRESS BUFFERS ROW DECODER 256 256 X 256 X 16 ARRAY
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Pin Configuration n SOJ n TSOP
Pin Descriptions
Symbol
VCC I/O0 I/O 1 I/O 2 I/O 3 VCC I/O 4 I/O 5 I/O 6 I/O 7 NC NC WE RAS NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS I/O 15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE NC A7 A6 A5 A4 VSS VCC I/O0 I/O 1 I/O 2 I/O 3 VCC I/O 4 I/O5 I/O 6 I/O 7 NC NC WE RAS NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 25 24 23 VSS I/O 15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE NC A7 A6 A5 A4 VSS
Functional Description
The A416316A is a high performance CMOS Dynamic Random Access Memory organized as 65,536 words X 16 bits. The A416316A is fabricated with advanced CMOS technology and designed with innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The A416316A features a high speed page mode operation in which high speed read, write and read-write are performed on any of the bits defined by the column address. The asynchronous column address uses an extremely short row address capture time to ease the system level timing constraints associated with multiplexed addressing. Output is tri-stated by a column address strobe ( UCAS and LCAS ) which acts as an output enable independent of RAS . Very fast UCAS and LCAS to output access time eases system design. All inputs are TTL compatible. Fast Page Mode operation allows random access up to 256 X 16 bits within a page, with cycle time as short as 19/21/23 ns. The A416316A is best suited for graphics, digital signal processing and high performance peripherals. The A416316A is available in JEDEC standard 40-pin plastic SOJ package and 40/44 TSOP type II package.
元器件交易网
A416316A Series
Preliminary
Document Title 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE Revision History
Rev. No.
0.0 0.1
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Description Address Inputs Data Input/Output Row Address Strobe Column Address Strobe/Upper Byte Control Column Address Strobe/Lower Byte Control Write Enable Output Enable +5V Power Supply Ground No Connection
PRELIMINARY
(October, 1999, Version 0.1)
3
AMIC Technology, Inc.
元器件交易网
A416316A Series
Truth Table
Function Standby Read: Word Read: Lower Byte
History
Initial issue Change ICC7 test condition from “all other input high levels are VCC-0.2V or input low levels are VSS+0.2V” to “all other input low levels are VSS+0.2V”
Issue Date
September 7, 1999 October 26, 1999
Remark
Preliminary
PRELIMINARY
(October, 1999, Version 0.1)
AMIC Technology, Inc.
元器件交易网
A416316A Series