MCP4011-4012-4013-4014_cn
40系列 数字集成电路 功能型号表
40系列数字集成电路功能型号表_为明天奋斗百度空间 | 百度首页 | 登录为明天奋斗学习交流与人生启迪主页博客相册|个人档案 |好友查看文章40系列数字集成电路功能型号表2007-12-26 10:504000系列4000 双3输入或非门加1输入反相器4001 四2输入或非门4002 双4输入或非门4006 18位串入串出静态移位寄存器4007 双互补对加反相器4008 4位二进制超前进位全加器4009 六缓冲器/电平变换器（反相）4010 六缓冲器/电平变换器（同相）4011 四2输入与非门4012 双4输入与非门4013 双D型触发器（带预置和清除端）4014 8位串入/并入串出移位寄存器4015 双4位串入并出移位寄存器4016 四双向模拟开关4017 十进制计数/分配器4018 可预置1/N计数器4019 四2选1数据选择器4020 14位二进制串行计数器4021 8位静态移位寄存器4022 八进制计数/分配器4023 三3输入与非门4024 7位二进制串行计数器/分频器4025 三3输入或非门4026 十进制计数/七段译码器4027 双J—K主从触发器4028 BCD十进制译码器4029 4位可预置/可逆计数器4030 四异或门4031 64位静态移位寄存器4032 三串行加法器（同相）4033 十进制计数/七段译码器4034 8位通用总线寄存器4035 4位并入/并出移位寄存器4038 三串行加法器（反相）4040 12位二进制计数器4041 四同相/反相缓冲器4042 四D型锁存器4043 四或非R—S锁存器（三态）4044 四与非R—S锁存器（三态）4045 21位计数器4046 锁相环4047 无稳态/单稳态多谐振荡器4048 8输入多功能门（三态可扩展） 4049 六缓冲器/电平变换器（反相） 4050 六缓冲器/电平变换器（同相） 4051 单8通道模拟开关4052 双4通道模拟开关4053 三2通道模拟开关4054 四段液晶显示驱动4055 BCD—7段液晶显示译码/驱动器 4056 BCD—7段液晶显示译码/驱动器 4058 双4位锁存器4059 1/N计数器4060 14位二进制串行计数器/分频器 4063 4位数值比较器4066 四双向模拟开关4067 单16通道模拟开关4068 8输入与非/与门4069 六反相器4070 四异或门4071 四2输入或门4072 双4输入或门4073 三3输入与门4075 三3输入或门4076 四D型寄存器（三态）4077 四异或非门4078 8输入或非/或门4081 四2输入与门4082 双4输入与门4085 双2路2输入与或非门4086 四2输入与或非门4089 二进制系数乘法器4093 四2输入与非施密特触发器4094 8位移位存贮总线寄存器4095 3输入J—K触发器4096 3输入J—K触发器4097 双8通道模拟开关4098 双可再触发单稳态触发器4099 8位可寻址锁存器4500系列4501 双4输入端与非门4502 六反相器/缓冲器4503 六缓冲器（三态）4504 六电平变换器4505 64位静态随机存贮器4506 双2输入可扩展或非门4507 四异或门4508 双4位D锁存器4510 可预置BCD可逆计数器4511 BCD-七段译码器 /驱动器4512 8选1数据选择器4513 BCD-七段译码器 /驱动器4514 4-16线译码器4515 4-16线译码器4516 可预置二进制可逆计数器4517 双64位静态移位寄存器4518 双BCD同步加计数器4519 4位与或选择器4520 双4位二进制同步加计数器 4521 24组分频器4522 可预置BCD 同步1/N计数器 4526 可预置4位二进制1/N计数器 4527 BCD系数乘法器4528 双可重触发单稳态触发器4529 双四通道模拟开关4530 双5输入过半数逻辑门4531 12位奇偶校验器4532 8位优先编码器4534 实时五、十进制计数器4536 可编程定时器4538 双精密可重触发单稳态触发器 4539 双4通道数选择器4541 可编程定时器4543 BCD-七段译码器 /驱动器4544 BCD-七段译码器 /驱动器4547 BCD-译码/大流动驱动器4549 近似函数寄存器4551 四2通道模拟开关4553 三数字BCD计数器4555 双4选1译码器4556 双4选1译码器4557 1－64位可变长度移位寄存器 4558 BCD-七段译码器4559 近似函数寄存器4560 “N”BCD加法器4561 “9”求补器4562 128位静态移位寄存器4566 工业定时基准发生器4568 相位比较器和可编程计数器4569 双可预置BCD/二进计数器4572 四反相器输入或/与非门4574 四可编程电压比较器4582 超前进位电路4583 双施密特触发器4584 六施密特触发器4585 4位数值比较器4590 单4位锁存器4597 8位总线兼容锁存器（三态）4599 8位可寻址锁存器40000系列40100 32级静态左/右移位寄存器40101 9位奇偶发生器/校验器40102 可预置2位十进制减法计数器40103 可预置8位二进制减法计数器40104 4通用双向移位寄存器40105 16×4先入先出寄存器（三态）40106 六施密特触发器（反相）40107 双3输入与非缓冲器/驱动器40108 4×4多路寄存器（三态）40109 四电平变换器40110 十进制计数/锁存/译码/驱动40147 10～4线BCD优先编码器40160 可预置十进制计数器40161 可预置二进制计数器40162 可预置十进制计数器40163 可预置4位二进制计数器40174 六D型触发器40175 四D触发器40181 4位算术逻辑单元40182 超前进位发生器40192 可预置十进制可逆计数器40193 可预置二进制可逆计数器40194 4位双向通用移位寄存器40195 4位双向通用移位寄存器类别：电子 | 添加到搜藏 | 浏览(210) | 评论 (0) 上一篇：常用数字集成电路集锦下一篇：74系列数字集成电路型号功能表相关文章：•数字集成电路分析与设计(第三版)... •74系列数字集成电路型号功能表•【集成电路常用4000系列标准数字... •数字集成电路:电路系统与设计(第...•数字集成电路功能测试仪存在的严... •数字集成电路使用注意事项•数字集成电路的分类•数字集成电路的分类与命名1•数字集成电路测试设备(ATE)量值... •数字集成电路讲座(10)最近读者：登录后，您就出现在这里。
CD4011UBMT,CD4011UBMT,CD4011UBMT,CD4011UBM,CD4011UBMT,CD4011UBMT,CD4011UBMT, 规格书,Datasheet 资料
Data sheet acquired from Harris SemiconductorSCHS022D – Revised September 2003The CD4011UB types are supplied in 14-leadhermetic dual-in-line ceramic packages(F3A suffix), 14-lead dual-in-line plasticpackages (E suffix), 14-lead small-outlinepackages (M, MT, M96, and NSR suffixes),and 14-lead thin shrink small-outlinepackages (PW and PWR suffixes).Copyright © 2003, Texas Instruments IncorporatedPACKAGING INFORMATIONOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)CD4011UBE ACTIVE PDIP N1425Pb-Free(RoHS)CU NIPDAU N/A for Pkg TypeCD4011UBEE4ACTIVE PDIP N1425Pb-Free(RoHS)CU NIPDAU N/A for Pkg Type CD4011UBF ACTIVE CDIP J141TBD A42N/A for Pkg Type CD4011UBM ACTIVE SOIC D1450Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4011UBM96ACTIVE SOIC D142500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4011UBM96E4ACTIVE SOIC D142500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4011UBM96G4ACTIVE SOIC D142500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4011UBME4ACTIVE SOIC D1450Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4011UBMG4ACTIVE SOIC D1450Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4011UBMT ACTIVE SOIC D14250Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4011UBMTE4ACTIVE SOIC D14250Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4011UBMTG4ACTIVE SOIC D14250Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4011UBNSR ACTIVE SO NS142000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4011UBNSRE4ACTIVE SO NS142000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4011UBNSRG4ACTIVE SO NS142000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4011UBPWR ACTIVE TSSOP PW142000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4011UBPWRE4ACTIVE TSSOP PW142000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD4011UBPWRG4ACTIVE TSSOP PW142000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan-The planned eco-friendly classification:Pb-Free(RoHS),Pb-Free(RoHS Exempt),or Green(RoHS&no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free(RoHS Exempt):This component has a RoHS exemption for either1)lead-based flip-chip solder bumps used between the die and package,or2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free(RoHScompatible)as defined above.Green(RoHS&no Sb/Br):TI defines"Green"to mean Pb-Free(RoHS compatible),and free of Bromine(Br)and Antimony(Sb)based flame retardants(Br or Sb do not exceed0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.TAPE AND REEL INFORMATION*All dimensions are nominalDevicePackage Type Package Drawing Pins SPQReel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant CD4011UBM96SOIC D 142500330.016.4 6.59.0 2.18.016.0Q1CD4011UBMT SOIC D 14250330.016.4 6.59.0 2.18.016.0Q1CD4011UBNSR SO NS 142000330.016.48.210.5 2.512.016.0Q1CD4011UBPWRTSSOPPW142000330.012.46.95.61.68.012.0Q1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) CD4011UBM96SOIC D142500367.0367.038.0 CD4011UBMT SOIC D1*******.0367.038.0 CD4011UBNSR SO NS142000367.0367.038.0CD4011UBPWR TSSOP PW142000367.0367.035.0IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,enhancements,improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B.Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All semiconductor products(also referred to herein as“components”)are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its components to the specifications applicable at the time of sale,in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products.Testing and other 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TI is not responsible or liable for any such statements.Buyer acknowledges and agrees that it is solely responsible for compliance with all legal,regulatory and safety-related requirements concerning its products,and any use of TI components in its applications,notwithstanding any applications-related information or support that may be provided by TI.Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures,monitor failures and their consequences,lessen the likelihood of failures that might cause harm and take appropriate remedial actions.Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications.In some cases,TI components may be promoted specifically to facilitate safety-related applications.With such components,TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements.Nonetheless,such components are subject to these terms.No TI components are authorized for use in FDA Class III(or similar life-critical medical equipment)unless authorized officers of the parties have executed a special agreement specifically governing such use.Only those TI components which TI has specifically designated as military grade or“enhanced plastic”are designed and intended for use in military/aerospace applications or environments.Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk,and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use.TI has specifically designated certain components which meet ISO/TS16949requirements,mainly for automotive ponents which have not been so designated are neither designed nor intended for automotive use;and TI will not be responsible for any failure of such components to meet such requirements.Products ApplicationsAudio /audio Automotive and Transportation /automotiveAmplifiers Communications and Telecom /communicationsData Converters Computers and Peripherals /computersDLP®Products Consumer Electronics /consumer-appsDSP Energy and Lighting /energyClocks and Timers /clocks Industrial /industrialInterface Medical /medicalLogic Security /securityPower Mgmt Space,Avionics and Defense /space-avionics-defense Microcontrollers Video and Imaging /videoRFID OMAP Mobile Processors /omap TI E2E Community Wireless Connectivity /wirelessconnectivityMailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2012,Texas Instruments Incorporated。
无源停电报警器
无源停电报警器摘要这里介绍的停电报警器不需要备用电池，当220V交流电网停电时，它就会发出长约5min急促的“嘟-嘟-”报警声。
它是根据光电耦合器4N25的性能，来改变具有振荡器功能与非门CD4011的工作状态,当起振时陶瓷片B就会发出报警声音。
它可用于装有自动打铃装置学校的传达室中，知道停电后，可采用人工打铃保证学校作息时间不受影响。
关键字：关键字：无源报警器、光电耦合器4N25、CD4011目录第一章前言 (1)第二章电路原理及主要功能模块 (2)2.1电路原理图及其工作原理分析 (2)2.2振荡电路模块 (3)2.3整流电路模块 (5)2.3光电耦合电路模块 (7)第三章电路集成块和集成芯片基本功能介绍 (9)3.1二输入端四与非门CD4011集成电路 (9)3.2光电耦合器4N25 (11)第四章元器件选择及其分析介绍 (14)4.1电容 (14)4.2电阻 (15)4.3二极管 (16)4.4压电陶瓷片 (18)第五章电路装置、调试及其故障分析 (19)5.1 元器件检测 (19)5.2 面包板调试其电路功能 (19)5.3 印刷电路板的规划及其元器件的安装 (19)5.4 手工焊接 (20)5.5电路的调试、故障分析及其结果 (21)第六章结束语 (22)6.1论文总结 (22)6.2工作展望 (22)参考文献、资料索引 (23)致谢 (24)第一章前言在电子科学技术高速发展的今天，电子产品越来越多的应用在我们的日常生活中，像日常我们工作所用的电脑、手机等等，这些高科技产品给我们带来了极大的方便，这要归功于科学技术的高度发达。
如今，日常生活也越来越走向电子化。
无源停电报警器是我们所要做的毕业设计课题。
它的电路主要包括振荡电路、整流电路和光电耦合电路三大部分。
无源停电报警器涉及到《模拟电子技术》、《数字电子技术》中的相关知识。
特别是对一些电路的分析都涉及到《模拟电子技术》中所讲到的知识以及面对电路时的分析方法、思路。
集成电路命名规则汇总
C1470 电机稳速 1992-99
C1490HA 红外接收 1991-110
C1676 超高频放大 1995s-199
C1891A 环绕声处理器 1992-24
C7642 单片收音机 1991-95
CA3069 运放 1994x-184
BA3822LS 5段均衡 1994-180
BA508 遥控电路 1995s-171
BA5102 音频前置 1993x-108
BA5102 遥控电风扇编码 1995s-119
BA5104 电风扇遥控 1995s-183
BA527 音频功放 1991-168
BA5302 红外接收头 1995s-183
集成电路应用索引
741 运算放大器
2063A JRC杜比降噪
20730 双功放
24C01AIPB21 存储器
27256 256K-EPROM
27512 512K-EPROM
2SK212 显示屏照明
3132V 32V三端稳压
3415D 双运放
AN7812 三端稳压器 1994s-299
AN78N05 三端稳压器 1994s-298
AP500/A DC功放驱动 1995s-60
AP500/A 双声道DC功放驱动 1995s-156
AT24C01 存储器 1994x-46
ATC105 充电控制 1993x-191
AX5212D 微机鼠标编码 1994s-183
AN51354 中放/音频/视频解调 1994s-255
AN5138K 图象通道 1994-308
AN5265 音频功放 1994s-298
CD4013双D触发器制作的红外线四路遥控开关
CD4013双D触发器制作的红外线四路遥控开关红外遥控是目前家用电器中用得较多的遥控方式，它具有稳定、可靠、成功率高、不干扰其它电器设备等优点。
我们知道，人的眼睛看到的可见光按波长从长到短排列，依次为红、橙、黄、绿、青、蓝、紫。
其中红外的波长范围是0.62——0.76微米，比红光波长还长的光叫红外线。
红外线遥控就是和用波长为0.76——1.5微米之间的红外线来传送控制信号的。
为青少年及无线电爱好者了解红外线的特性，建立编解码的基本概念，掌握双稳态电路的一般性能，红外线四路遥控开关的实验器材，同时是全国少年电子技师等级认定活动的指定器材，具有电路结构清晰、制作成功率高、使用性能好、工作稳定可靠等优点。
广泛实用于家庭、工厂、学校、医院、娱乐场所等。
本遥控开关由发射系统和接收系统两部分组成。
接收系统具有手动功能，既可以实现红外遥控接收又可以手控。
一、电路工作原理1、发射电路发射部分的主要元件为红外发光二极管，它实际上是一只特殊的发光二极管，由于其内部材料不同于普通发光二极管，因而其两端施加一定电压时，它便发出的是红外线而不是可见光。
其外与普通5发光二极管相同，红外线发光二极管一般有黑色、深蓝、透明三种颜色。
发射器由SM5021A编码集成块、驱动放大电路和红外线发射管组成。
SM5021A有8个数据输入脚，对应接收解码集成块SM5032B的2个锁存和6个非锁存输出端，在此采用了4个非锁存输出，即SM502 1A的3、4、5、6脚，当按键K1、K2、K3、K4任一键按下时，脚12、13对应的内部电路与455KHZ的陶瓷滤波器及电容C2、C3组成的振荡器产生振荡，经IC1内部整形、分频后作为编码集成块内部时钟和38KHZ载频。
SM5021A的1、2脚为用户码输入脚，便于与使用同类遥控器时进行码区分。
本遥控器中该两脚全接地，也就是说用户码是“0 0”，当按键按下时，将对应串行码信号调制的38KHZ载频由15脚输出，再经三极管VT1、VT2放大后驱动红外线发射管工作，这样控制信号以红外线的形式发送出去。
cd4011工作原理
cd4011工作原理
CD4011是一种集成电路，属于四个二输入NAND门的直流型CMOS(IN74HC00)芯片。
它的工作原理如下：
1. N通道MOS管：在输入端为低电平时导通，高电平时截断。
2. P通道MOS管：在输入端为高电平时导通，低电平时截断。
3. CD4011具有四个相同的二输入NAND门，每个门都有两个输入端和一个输出端。
4. 如果任一输入端为高电平（逻辑1），输出端将会为低电平（逻辑0）；如果两个输入端都为低电平（逻辑0），输出端
将会为高电平（逻辑1）。
5. 对于每个二输入NAND门，如果两个输入端都为高电平
（逻辑1），那么两个P通道MOS管将导通，而两个N通道MOS管将截断，从而输出端为低电平（逻辑0）。
6. 如果任一输入端为低电平（逻辑0），那么至少有一个P通
道MOS管将截断，导致输出端为高电平（逻辑1）。
7. CD4011的输出端也可以作为其他门电路的输入端，以进一
步组合形成更复杂的逻辑功能。
这就是CD4011的简单工作原理。
通过合理组合和连接多个
CD4011芯片，可以实现各种逻辑功能和电路设计。
MICROCHIP MCP4021 2 3 4 数据手册
参数
符号 最小值 典型值 最大值
单位
条件
电阻端接输入电压范围 （A、 B 和 W 端） 流经 A、 W 或 B 端的最大电流 注入 A、 W 或 B 端的泄漏电流
电容 （PA） 电容 （Pw） 电容 （PB） 带宽 -3 dB 数字输入 / 输出 （CS， U/D） 输入高电平 输入低电平 高电平输入下限 高电平输入上限 CS 上拉 / 下拉电阻 CS 弱上拉 / 下拉电流 输入泄漏电流 CS 和 U/D 引脚电容 RAM （电刷）值 值域 EEPROM 耐久性 EEPROM 范围 初始出厂设置 电源要求 输入电源敏感度 （仅 MCP4021 和 MCP4023）
应用
• 电源的调整和校准 • 可在新设计中取代传统机械电位计 • 仪表、偏置和增益调节
说明
MCP4021/2/3/4 系列器件是 6 位分辨率的非易失性数字 电位计，它既可以配置成电位计，也可以配置成变阻 器。通过简单的 Up/Down （U/D）串行接口对电刷设置 进行控制。
该系列器件采用了 Microchip 的 WiperLock 技术，它允 许在 EEPROM 中保存应用特定的校准设置，而不需要 使用额外的写保护引脚。
2006 Microchip Technology Inc.
DS21945C_CN 第 3 页
MCP4021/2/3/4
AC/DC 特性 （续）
电气规范：除非另有说明，否则所有参数适用于规定的工作范围。 TA = -40°C 至 +125°C， 2.1kΩ， 5 kΩ， 10kΩ 和 50 kΩ 器件。典型值参数条件是在 VDD = 5.5V， VSS = 0V， TA = +25°C。
更多相关信息。 8： 外部连接 MCP4021，以符合 MCP4022 和 MCP4024 的配置，然后进行测试。
摩萨 EDS-4012 系列 8+4G 端口（带 8 802.3bt PoE 端口选项）管理网关交换
EDS-4012Series8+4G-port (with 8802.3bt PoE port option)managed Ethernet switchesFeatures and Benefits•Developed according to the IEC 62443-4-1and compliant with the IEC62443-4-2industrial cybersecurity standards•Support for IEEE 802.3bt PoE for up to 90W output per port•Turbo Ring and Turbo Chain (recovery time <20ms @250switches)1,andRSTP/STP for network redundancy•Wide range of power input options for flexible deployment •Compact and flexible housing design to fit into confined spaces •Supports MXstudio for easy,visualized industrial network managementCertificationsIntroductionThe EDS-4012Series is a range of 12-port managed Fast Ethernet switches with the option for four 1Gbps fiber-optic uplink ports.This Series also offers models with four 10/100BaseT(X)802.3af (PoE),802.3at (PoE+),and 802.3bt-compliant Ethernet PoE port options to connect high-bandwidth PoE devices.Redundant Ethernet technologies such as Turbo Ring,Turbo Chain,and RSTP/STP increase the reliability of your system and improve the availability of your network backbone.The EDS-4012Series is designed specifically for demanding applications such as video and process monitoring,ITS,and DCS systems,all of which can benefit from a scalable backbone.The EDS-4012Series is compliant with the IEC 62443-4-2and IEC 62443-4-1Industrial Cybersecurity certifications,which cover both product security and secure development life-cycle requirements,helping our customers meet the compliance requirements of secure industrial network design.SpecificationsEthernet Interface10/100BaseT(X)Ports (RJ45connector)EDS-4012-4GS-LV/-HV/-T models:8EDS-4012-4GC-LV/-HV/-T models:8Auto negotiation speed Full/Half duplex modeAuto MDI/MDI-X connectionPoE Ports (10/100BaseT(X),RJ45connector)EDS-4012-8P-4GS-LVA/-LVB/-T models:8100/1000BaseSFP PortsEDS-4012-4GS-LV/-HV/-T models:4EDS-4012-8P-4GS-LVA/-VB/-T models:41.If the port link speed is 1Gigabit or higher,the recovery time is <50ms.Combo Ports(10/100/1000BaseT(X)or100/EDS-4012-4GC-LV/-HV/-T models:41000BaseSFP)Standards IEEE802.3for10BaseTIEEE802.3u for100BaseT(X)and100BaseFXIEEE802.3ab for1000BaseT(X)IEEE802.3z for1000BaseXIEEE802.3x for flow controlIEEE802.3ad for Port Trunk with LACPIEEE802.1Q for VLAN TaggingIEEE802.1D-2004for Spanning Tree ProtocolIEEE802.1w for Rapid Spanning Tree ProtocolIEEE802.1p for Class of ServiceIEEE802.1X for authenticationEthernet Software FeaturesFilter GMRP,GVRP,GARP,802.1Q VLAN,IGMP Snooping v1/v2/v3,IGMP QuerierManagement IPv4/IPv6,Flow control,Back Pressure Flow Control,DHCP Server/Client,ARP,RARP,LLDP,Port Mirror,Linkup Delay,SMTP,SNMP Trap,SNMP Inform,SNMPv1/v2c/v3,RMON,TFTP,SFTP,HTTP,HTTPS,Telnet,Syslog,Private MIBMIB P-BRIDGE MIB,Q-BRIDGE MIB,IEEE8021-SPANNING-TREE-MIB,IEEE8021-PAE-MIB,IEEE8023-LAG-MIB,LLDP-EXT-DOT1-MIB,LLDP-EXT-DOT3-MIB,SNMPv2-MIB,RMON MIB Groups1,2,3,9Redundancy Protocols STP,RSTP,Turbo Ring v2,Turbo Chain,Ring Coupling,Dual-Homing,Link AggregationSecurity Broadcast storm protection,Rate Limit,Trust access control,Static Port Lock,MACSticky,HTTPS/SSL,SSH,RADIUS,TACACS+,Login and Password PolicyTime Management SNTP,NTP Server/Client,NTP AuthenticationProtocols IPv4/IPv6,TCP/IP,UDP,ICMP,ARP,RARP,TFTP,DNS,NTP Client,DHCP Server,DHCP Client,802.1X,QoS,HTTPS,HTTP,Telnet,SMTP,SNMPv1/v2c/v3,RMON,SyslogSwitch PropertiesMAC Table Size16KJumbo Frame Size9.216KBMax.No.of VLANs256VLAN ID Range VID1to4094IGMP Groups512Priority Queues4Packet Buffer Size1MBLED InterfaceLED Indicators PWR1,PWR2,STATE,FAULT,MSTR/HEAD,CPLR/TAIL,SYNCSerial InterfaceConsole Port RS-232(TxD,RxD,GND),8-pin RJ45(115200,n,8,1)USB InterfaceUSB Connector USB Type A(Reserved)Input/Output InterfaceAlarm Contact Channels1,Relay output with current carrying capacity of1A@24VDCDigital Input Channels1Digital Inputs+13to+30V for state1-30to+3V for state0Max.input current:8mAButtons Reset buttonDIP Switch ConfigurationDIP Switches Turbo Ring,Master,Coupler,ReservePower ParametersConnection2removable4-contact terminal block(s)Pre-installed Power Module-LV/-LV-T models:PWR-100–LV-HV/-HV-T models:PWR-105-HV-I-LVA/-LVA-T models:PWR-101-LV-BP-I-LVB/-LVB-T models:PWR-103-LV-VB-INote The EDS-4012Series supports modular power supplies.The model names and powerparameters are determined by the installed power module.For example:EDS-4012-4GS-T+PWR-100–LV=EDS-4012-4GS-LV-TEDS-4012-4GS-T+PWR-105-HV-I=EDS-4012-4GS-HV-TIf you install a different power module,refer to the specifications of the correspondingmodel.For example,if you replace the power module of the EDS-4012-4GS–LV-Twith the PWR-105–HV-I,refer to the specifications of the EDS-4012–4GS-HV-T.Input Voltage-LV/-LV-T models:12/24/48VDC,Redundant dual inputs-HV/-HV-T models:110/220VDC/VAC,Single input-LVA/-LVA-T models:48VDC,Redundant dual inputs-LVB/-LVB-T models:12/24/48VDC,Redundant dual inputsOperating Voltage-LV/-LV-T models:9.6to60VDC-HV/-HV-T models:88to300VDC,85to264VAC-LVA/-LVA-T models:44to57VDC(>52VDC for PoE+output recommended)-LVB/-LVB-T models:12to57VDC(>52VDC for PoE+output recommended)Input Current-LV/-LV-T models:12-48VDC,1.50-0.40A or24VDC,0.70A-HV/-HV-T models:110-220VAC,50-60Hz,0.30-0.20A or110-220VDC,0.30-0.20A-LVA/-LVA-T models:48VDC,5.42A-LVB/-LVB-T models:12/48VDC,7.46/4.27A or24VDC,7.26APower Consumption(Max.)EDS-4012-4GS-LV/-T models:10.52WEDS-4012-4GS-HV-/T models:12.22WEDS-4012-4GC-LV/-T models:10.7WEDS-4012-4GC-HV/-T models:13.35WEDS-4012-8P-4GS-LVA/-T models:Without PoE:13.34WWith PoE:Max.240W for total PD power consumption@48VDC inputEDS-4012-8P-4GS-LVB/-T models:Without PoE:15.32WWith PoE:Max.180W for total PD power consumption@48VDC inputMax.150W for total PD power consumption@24VDC input(Max.120W for-T model)Max.62W for total PD consumption@12VDC inputMax.PoE Power Output per Port90WOverload Current Protection SupportedReverse Polarity Protection SupportedPhysical CharacteristicsIP Rating IP40Dimensions55x140x120mm(2.17x5.51x4.72in)Weight827g(1.82lb)Installation DIN-rail mounting,Wall mounting(with optional kit) Housing MetalEnvironmental LimitsOperating Temperature Standard Models:-10to60°C(14to140°F)Wide Temp.Models:-40to75°C(-40to167°F) Storage Temperature(package included)-40to85°C(-40to185°F)Ambient Relative Humidity5to95%(non-condensing)Standards and CertificationsIndustrial Cybersecurity IEC62443-4-1IEC62443-4-2Safety UL61010-2-201,EN62368-1(LVD)EMC EN55032/35,EN61000-6-2/-6-4EMI CISPR32,FCC Part15B Class AEMS IEC61000-4-2ESD:Contact:8kV;Air:15kVIEC61000-4-3RS:80MHz to1GHz:20V/mIEC61000-4-4EFT:Power:4kV;Signal:4kVIEC61000-4-5Surge:Power:4kV;Signal:4kVIEC61000-4-6CS:10VIEC61000-4-8PFMFMaritime-LV/-LV-T,PoE/PoE-T models:DNV,ABS,NK,LR Vibration IEC60068-2-6Shock IEC60068-2-27Freefall IEC60068-2-32Railway EN50121-4Traffic Control NEMA TS2Power Substation IEC61850-3,IEEE1613Class1MTBFTime EDS-4012-4GC-LV/-T models:1,036,336hrsEDS-4012-4GC-HV/-T models:497,392hrsEDS-4012-4GS-LV/-T models:874,838hrsEDS-4012-4GS-HV/-T models:456,870hrsEDS-4012-8P-4GS-LVA/-T models:799,780hrsEDS-4012-8P-4GS-LVB/-T models:759,924hrs Standards Telcordia SR332WarrantyWarranty Period5yearsDetails See /warrantyPackage ContentsDevice1x EDS-4012Series switchDocumentation1x quick installation guide1x product notice,Simplified Chinese1x product certificates of quality inspection,Simplified Chinese1x warranty cardDimensionsOrdering InformationModel Name 10/100BaseT(X)Ports(RJ45Connector)PoE10/100BaseT(X)Ports(RJ45Connector)100/1000BaseSFPSlotsCombo Ports(10/100/1000BaseT(X)or100/1000BaseSFP)OperatingVoltagePre-installedPower ModuleOperatingTemp.EDS-4012-4GS-LV8–4–9.6to60VDC PWR-100-LV-10to60°C EDS-4012-4GS-LV-T8–4–9.6to60VDC PWR-100-LV-40to75°CEDS-4012-4GS-HV8–4–88to300VDC,85to264VACPWR-105-HV-I-10to60°CEDS-4012-4GS-HV-T8–4–88to300VDC,85to264VACPWR-105-HV-I-40to75°CEDS-4012-4GC-LV8––49.6to60VDC PWR-100-LV-10to60°C EDS-4012-4GC-LV-T8––49.6to60VDC PWR-100-LV-40to75°CEDS-4012-4GC-HV8––488to300VDC,85to264VACPWR-105-HV-I-10to60°CEDS-4012-4GC-HV-T8––488to300VDC,85to264VACPWR-105-HV-I-40to75°CEDS-4012-8P-4GS-LVA–84–44to57VDC(>52VDC for PoE+outputrecommended)PWR-101-LV-BP-I-10to60°CEDS-4012-8P-4GS-LVA-T –84–44to57VDC(>52VDC for PoE+outputrecommended)PWR-101-LV-BP-I-40to75°CEDS-4012-8P-4GS-LVB–84–12to57VDC(>52VDC for PoE+outputrecommended)PWR-103-LV-VB-I-10to60°CEDS-4012-8P-4GS-LVB-T –84–12to57VDC(>52VDC for PoE+outputrecommended)PWR-103-LV-VB-I-40to75°CAccessories(sold separately)SFP ModulesSFP-1GEZXLC SFP module with11000BaseEZX port with LC connector for110km transmission,0to60°C operatingtemperatureSFP-1GEZXLC-120SFP module with11000BaseEZX port with LC connector for120km transmission,0to60°C operatingtemperatureSFP-1GLHLC SFP module with11000BaseLH port with LC connector for30km transmission,0to60°C operatingtemperatureSFP-1GLHXLC SFP module with11000BaseLHX port with LC connector for40km transmission,0to60°C operatingtemperatureSFP-1GLSXLC SFP module with11000BaseLSX port with LC connector for1km/2km transmission,0to60°Coperating temperatureSFP-1GLXLC SFP module with11000BaseLX port with LC connector for10km transmission,0to60°C operatingtemperatureSFP-1GSXLC SFP module with11000BaseSX port with LC connector for300m/550m transmission,0to60°Coperating temperatureSFP-1GZXLC SFP module with11000BaseZX port with LC connector for80km transmission,0to60°C operatingtemperatureSFP-1GLHLC-T SFP module with11000BaseLH port with LC connector for30km transmission,-40to85°C operatingtemperatureSFP-1GLHXLC-T SFP module with11000BaseLHX port with LC connector for40km transmission,-40to85°Coperating temperatureSFP-1GLSXLC-T SFP module with11000BaseLSX port with LC connector for1km/2km transmission,-40to85°Coperating temperatureSFP-1GLXLC-T SFP module with11000BaseLX port with LC connector for10km transmission,-40to85°C operatingtemperatureSFP-1GSXLC-T SFP module with11000BaseSX port with LC connector for300m/550m transmission,-40to85°Coperating temperatureSFP-1GZXLC-T SFP module with11000BaseZX port with LC connector for80km transmission,-40to85°C operatingtemperatureSFP-1G10ALC WDM-type(BiDi)SFP module with11000BaseSFP port with LC connector for10km transmission;TX1310nm,RX1550nm,0to60°C operating temperatureSFP-1G10BLC WDM-type(BiDi)SFP module with11000BaseSFP port with LC connector for10km transmission;TX1550nm,RX1310nm,0to60°C operating temperatureSFP-1G20ALC WDM-type(BiDi)SFP module with11000BaseSFP port with LC connector for20km transmission;TX1310nm,RX1550nm,0to60°C operating temperatureSFP-1G20BLC WDM-type(BiDi)SFP module with11000BaseSFP port with LC connector for20km transmission;TX1550nm,RX1310nm,0to60°C operating temperatureSFP-1G40ALC WDM-type(BiDi)SFP module with11000BaseSFP port with LC connector for40km transmission;TX1310nm,RX1550nm,0to60°C operating temperatureSFP-1G40BLC WDM-type(BiDi)SFP module with11000BaseSFP port with LC connector for40km transmission;TX1550nm,RX1310nm,0to60°C operating temperatureSFP-1G10ALC-T WDM-type(BiDi)SFP module with11000BaseSFP port with LC connector for10km transmission;TX1310nm,RX1550nm,-40to85°C operating temperatureSFP-1G10BLC-T WDM-type(BiDi)SFP module with11000BaseSFP port with LC connector for10km transmission;TX1550nm,RX1310nm,-40to85°C operating temperatureSFP-1G20ALC-T WDM-type(BiDi)SFP module with11000BaseSFP port with LC connector for20km transmission;TX1310nm,RX1550nm,-40to85°C operating temperatureSFP-1G20BLC-T WDM-type(BiDi)SFP module with11000BaseSFP port with LC connector for20km transmission;TX1550nm,RX1310nm,-40to85°C operating temperatureSFP-1G40ALC-T WDM-type(BiDi)SFP module with11000BaseSFP port with LC connector for40km transmission;TX1310nm,RX1550nm,-40to85°C operating temperatureSFP-1G40BLC-T WDM-type(BiDi)SFP module with11000BaseSFP port with LC connector for40km transmission;TX1550nm,RX1310nm,-40to85°C operating temperatureSFP-1FELLC-T SFP module with1100Base single-mode with LC connector for80km transmission,-40to85°Coperating temperatureSFP-1FEMLC-T SFP module with1100Base multi-mode,LC connector for2/4km transmission,-40to85°C operatingtemperatureSFP-1FESLC-T SFP module with1100Base single-mode with LC connector for40km transmission,-40to85°Coperating temperaturePower SuppliesHDR-60-2460W/2.5A DIN-rail24VDC power supply,universal85to264VAC or120to370VDC input voltage,-30to70°C operating temperatureNDR-120-24120W/5.0A DIN-rail24VDC power supply,universal90to264VAC or127to370VDC input voltage,-20to70°C operating temperatureNDR-120-48120W/2.5A DIN-rail48VDC power supply,universal90to264VAC or127to370VDC input voltage,-20to70°C operating temperatureNDR-240-48240W/5.0A DIN-rail48VDC power supply,universal90to264VAC or127to370VDC input voltage,-20to70°C operating temperatureMDR-40-24DIN-rail24VDC power supply with40W/1.7A,85to264VAC,or120to370VDC input,-20to70°Coperating temperatureMDR-60-24DIN-rail24VDC power supply with60W/2.5A,85to264VAC,or120to370VDC input,-20to70°Coperating temperature©Moxa Inc.All rights reserved.Updated Jun17,2022.This document and any portion thereof may not be reproduced or used in any manner whatsoever without the express written permission of Moxa Inc.Product specifications subject to change without notice.Visit our website for the most up-to-date product information.。
微芯,DSPIC30F系列,规格书,Datasheet 资料
© 2010 Microchip Technology Inc.DS70102K-page1dsPIC30F1.0OVERVIEW AND SCOPEThis document defines the programming specification for the dsPIC30F family of Digital Signal Controllers (DSCs). The programming specification is required only for the developers of third-party tools that are used to program dsPIC30F devices. Customers using dsPIC30F devices should use development tools that already provide support for device programming.This document includes programming specifications for the following devices:•dsPIC30F2010/2011/2012•dsPIC30F3010/3011/3012/3013/ 3014•dsPIC30F4011/4012/4013•dsPIC30F5011/5013/5015/5016•dsPIC30F6010/6011/6012/6013/6014/6015•dsPIC30F6010A/6011A/6012A/6013A/6014A2.0PROGRAMMING OVERVIEW OF THE dsPIC30FThe dsPIC30F family of DSCs contains a region of on-chip memory used to simplify device programming. This region of memory can store a programming executive, which allows the dsPIC30F to be programmed faster than the traditional means. Once the programming executive is stored to memory by an external programmer (such as Microchip’s MPLAB ®ICD 2, MPLAB PM3, PRO MATE ® II, or MPLAB REAL ICE™), it can then interact with the external programmer to efficiently program devices.The programmer and programming executive have a master-slave relationship, where the programmer is the master programming device and the programming executive is the slave, as illustrated in Figure 2-1.FIGURE 2-1:OVERVIEW OF dsPIC30F PROGRAMMINGTwo different methods are used to program the chip in the user’s system. One method uses the Enhanced In-Circuit Serial Programming™ (Enhanced ICSP™) protocol and works with the programming executive. The other method uses In-Circuit Serial Programming (ICSP) protocol and does not use the programming executive.The Enhanced ICSP protocol uses the faster, high-voltage method that takes advantage of the programming executive. The programming executive provides all the necessary functionality to erase, program and verify the chip through a small command set. The command set allows the programmer to program the dsPIC30F without having to deal with the low-level programming protocols of the chip.The ICSP programming method does not use the programming executive. It provides native, low-level programming capability to erase, program and verify the chip. This method is significantly slower because it uses control codes to serially execute instructions on the dsPIC30F device.This specification describes the ICSP and Enhanced ICSP programming methods. Section 3.0 “Programming Executive Application” describes the programming executive application and Section 5.0 “Device Programming” describes its application programmer’s interface for the hostprogrammer.Section 11.0 “ICSP™ Mode”describes the ICSP programming method.2.1 Hardware RequirementsIn ICSP or Enhanced ICSP mode, the dsPIC30F requires two programmable power supplies: one for V DD and one for MCLR. For Bulk Erase programming, which is required for erasing code protection bits, V DD must be greater than 4.5 volts. Refer to Section 13.0 “AC/DC Characteristics and Timing Requirements”for additional hardware parameters.Programmer dsPIC30F DeviceProgramming Executive On-chip Memory 2dsPIC30F Flash Programming SpecificationdsPIC30F Flash Programming SpecificationDS70102K-page 2© 2010 Microchip Technology Inc.2.2Pins Used During ProgrammingThe pins identified in Table 2-1 are used for device programming. Refer to the appropriate device data sheet for complete pin descriptions.TABLE 2-1:dsPIC30F PIN DESCRIPTIONS DURING PROGRAMMINGPin Name Pin TypePin Description MCLR/V PP P Programming Enable V DD P Power Supply V SS P Ground PGC I Serial Clock PGDI/OSerial Data2.3Program Memory MapThe program memory space extends from 0x0 to 0xFFFFFE. Code storage is located at the base of the memory map and supports up to 144 Kbytes (48K instruction words). Code is stored in three, 48 Kbyte memory panels that reside on-chip. Table 2-2 shows the location and program memory size of each device.Locations 0x800000 through 0x8005BE are reserved for executive code memory. This region stores either the programming executive or debugging executive. The programming executive is used for device programming, while the debug executive is used for in-circuit debugging. This region of memory cannot be used to store user code.Locations 0xF80000 through 0xF8000E are reserved for the Configuration registers. The bits in these registers may be set to select various device options, and are described in Section 5.7 “Configuration Bits Programming”.Locations 0xFF0000 and 0xFF0002 are reserved for the Device ID registers. These bits can be used by the programmer to identify what device type is being programmed and are described in Section 10.0 “Device ID”. The device ID reads out normally, even after code protection is applied.Figure 2-2 illustrates the memory map for the dsPIC30F devices.2.4Data EEPROM MemoryThe Data EEPROM array supports up to 4 Kbytes of data and is located in one memory panel. It is mapped in program memory space, residing at the end of User Memory Space (see Figure 2-2). Table 2-2 shows the location and size of data EEPROM in each device.TABLE 2-2:CODE MEMORY AND DATA EEPROM MAP AND SIZE DeviceCode Memory map (Size in Instruction Words)Data EEPROM Memory Map(Size in Bytes)dsPIC30F20100x000000-0x001FFE (4K)0x7FFC00-0x7FFFFE (1K)dsPIC30F20110x000000-0x001FFE (4K)None (0K)dsPIC30F20120x000000-0x001FFE (4K)None (0K)dsPIC30F30100x000000-0x003FFE (8K)0x7FFC00-0x7FFFFE (1K)dsPIC30F30110x000000-0x003FFE (8K)0x7FFC00-0x7FFFFE (1K)dsPIC30F30120x000000-0x003FFE (8K)0x7FFC00-0x7FFFFE (1K)dsPIC30F30130x000000-0x003FFE (8K)0x7FFC00-0x7FFFFE (1K)dsPIC30F30140x000000-0x003FFE (8K)0x7FFC00-0x7FFFFE (1K)dsPIC30F40110x000000-0x007FFE (16K)0x7FFC00-0x7FFFFE (1K)dsPIC30F40120x000000-0x007FFE (16K)0x7FFC00-0x7FFFFE (1K)dsPIC30F40130x000000-0x007FFE (16K)0x7FFC00-0x7FFFFE (1K)dsPIC30F50110x000000-0x00AFFE (22K)0x7FFC00-0x7FFFFE (1K)dsPIC30F50130x000000-0x00AFFE (22K)0x7FFC00-0x7FFFFE (1K)dsPIC30F50150x000000-0x00AFFE (22K)0x7FFC00-0x7FFFFE (1K)dsPIC30F50160x000000-0x00AFFE (22K)0x7FFC00-0x7FFFFE (1K)dsPIC30F60100x000000-0x017FFE (48K)0x7FF000-0x7FFFFE (4K)dsPIC30F6010A 0x000000-0x017FFE (48K)0x7FF000-0x7FFFFF (4K)dsPIC30F60110x000000-0x015FFE (44K)0x7FF800-0x7FFFFE (2K)dsPIC30F6011A 0x000000-0x015FFE (44K)0x7FF800-0x7FFFFE (2K)dsPIC30F60120x000000-0x017FFE (48K)0x7FF000-0x7FFFFE (4K)dsPIC30F6012A 0x000000-0x017FFE (48K)0x7FF000-0x7FFFFE (4K)dsPIC30F60130x000000-0x015FFE (44K)0x7FF800-0x7FFFFE (2K)dsPIC30F6013A 0x000000-0x015FFE (44K)0x7FF800-0x7FFFFE (2K)dsPIC30F60140x000000-0x017FFE (48K)0x7FF000-0x7FFFFE (4K)dsPIC30F6014A 0x000000-0x017FFE (48K)0x7FF000-0x7FFFFE (4K)dsPIC30F60150x000000-0x017FFE (48K)0x7FF000-0x7FFFFE (4K)Legend:I = Input, O = Output, P = Power© 2010 Microchip Technology Inc.DS70102K-page 3dsPIC30F Flash Programming SpecificationFIGURE 2-2:PROGRAM MEMORY MAPU s e r M e m o r y S p a c e000000Configuration RegistersUser Flash Code Memory 018000017FFE C o n f i g u r a t i o n M e m o r y S p a c eData EEPROM (48K x 24-bit)(2K x 16-bit)800000F80000(8 x 16-bit)F8000E F80010Device ID FEFFFE FF0000FFFFFEReservedF7FFFE Reserved7FF0007FEFFE 8005BE 8005C0Executive Code Memory7FFFFE ReservedFF0002FF0004Reserved(2 x 16-bit)(Reserved)Note:The address boundaries for user Flash code memory and data EEPROM are device-dependent.Unit ID (32 x 24-bit)8005FE 800600dsPIC30F Flash Programming SpecificationDS70102K-page 4© 2010 Microchip Technology Inc.3.0PROGRAMMING EXECUTIVE APPLICATION3.1Programming Executive OverviewThe programming executive resides in executive memory and is executed when Enhanced ICSP Programming mode is entered. The programming exec-utive provides the mechanism for the programmer (host device) to program and verify the dsPIC30F, using a simple command set and communication protocol.The following capabilities are provided by the programming executive:•Read memory-Code memory and data EEPROM -Configuration registers -Device ID •Erase memory-Bulk Erase by segment -Code memory (by row)-Data EEPROM (by row)•Program memory -Code memory-Data EEPROM-Configuration registers •Query-Blank Device-Programming executive software versionThe programming executive performs the low-level tasks required for erasing and programming. This allows the programmer to program the device by issuing the appropriate commands and data.The programming procedure is outlined in Section 5.0 “Device Programming”.3.2Programming Executive Code MemoryThe programming executive is stored in executive code memory and executes from this reserved region of memory. It requires no resources from user code memory or data EEPROM.3.3Programming Executive Data RAMThe programming executive uses the device’s data RAM for variable storage and program execution. Once the programming executive has run, no assumptions should be made about the contents of data RAM.4.0CONFIRMING THE CONTENTS OF EXECUTIVE MEMORYBefore programming can begin, the programmer must confirm that the programming executive is stored in exec-utive memory. The procedure for this task is illustrated in Figure 4-1.First, ICSP mode is entered. The unique application ID word stored in executive memory is then read. If the programming executive is resident, the application ID word is 0xBB, which means programming can resume as normal. However, if the application ID word is not 0xBB, the programming executive must be programmed to Executive Code memory using the method described in Section 12.0 “Programming the Programming Executive to Memory”.Section 11.0 “ICSP™ Mode” describes the process for the ICSP programming method. Section 11.13 “Reading the Application ID Word” describes the procedure for reading the application ID word in ICSP mode.FIGURE 4-1:CONFIRMING PRESENCE OF THE PROGRAMMING EXECUTIVEIsStartEnter ICSP™ ModeApplication ID0xBB?Resident in MemoryYesNoProg. Executive is Application ID Read the be ProgrammedProg. Executive must from Address 0x8005BEFinishdsPIC30F Flash Programming Specification5.0DEVICE PROGRAMMING5.1Overview of the ProgrammingProcessOnce the programming executive has been verified in memory (or loaded if not present), the dsPIC30F can be programmed using the command set shown in Table 5-1. A detailed description for each command is provided in Section 8.0 “Programming Executive Commands”.TABLE 5-1:COMMAND SET SUMMARY Command DescriptionSCHECK Sanity checkREADD Read data EEPROM, Configurationregisters and device IDREADP Read code memoryPROGD Program one row of data EEPROMand verifyPROGP Program one row of code memory andverifyPROGC Program Configuration bits and verify ERASEB Bulk Erase, or erase by segment ERASED Erase data EEPROMERASEP Erase code memoryQBLANK Query if the code memory and dataEEPROM are blankQVER Query the software versionA high-level overview of the programming process is illustrated in Figure 5-1. The process begins by enter-ing Enhanced ICSP mode. The chip is then bulk erased, which clears all memory to ‘1’ and allows the device to be programmed. The Chip Erase is verified before programming begins. Next, the code memory, data Flash and Configuration bits are programmed. As these memories are programmed, they are each verified to ensure that programming was successful. If no errors are detected, the programming is complete and Enhanced ICSP mode is exited. If any of the verifications fail, the procedure should be repeated, starting from the Chip Erase.If Advanced Security features are enabled, then individual Segment Erase operations need to be performed, based on user selections (i.e., based on the specific needs of the user application). The specific operations that are used typically depend on the order in which various segments need to be programmed for a given application or system.Section 5.2 “Entering Enhanced ICSP Mode”through Section 5.8 “Exiting Enhanced ICSP Mode”describe the programming process in detail.FIGURE 5-1:PROGRAMMING FLOWStartProgram andProgram andProgram and verifyConfiguration bitsFinishverify codeverify dataEnter EnhancedExit Enhanced ICSPModePerform ChipEraseProgramConfigurationregisters toICSP™ modedefault value© 2010 Microchip Technology Inc.DS70102K-page 5dsPIC30F Flash Programming SpecificationDS70102K-page 6© 2010 Microchip Technology Inc.5.2Entering Enhanced ICSP ModeThe Enhanced ICSP mode is entered by holding PGC and PGD high, and then raising MCLR/V PP to V IHH (high voltage), as illustrated in Figure 5-2. In this mode, the code memory, data EEPROM and Configuration bits can be efficiently programmed using the program-ming executive commands that are serially transferred using PGC and PGD.FIGURE 5-2:ENTERING ENHANCED5.3Chip EraseBefore a chip can be programmed, it must be erased. The Bulk Erase command (ERASEB ) is used to perform this task. Executing this command with the MS command field set to 0x3 erases all code memory, data EEPROM and code-protect Configuration bits. The Chip Erase process sets all bits in these three memory regions to ‘1’.Since non-code-protect Configuration bits cannot be erased, they must be manually set to ‘1’ using multiple PROGC commands. One PROGC command must be sent for each Configuration register (see Section 5.7 “Configuration Bits Programming”).If Advanced Security features are enabled, then indi-vidual Segment Erase operations would need to be performed, depending on which segment needs to be programmed at a given stage of system programming. The user should have the flexibility to select specific segments for programming.Note:The Device ID registers cannot be erased. These registers remain intact after a Chip Erase is performed.5.4Blank CheckThe term “Blank Check” means to verify that the device has been successfully erased and has no programmed memory cells. A blank or erased memory cell reads as ‘1’. The following memories must be blank checked: •All implemented code memory •All implemented data EEPROM•All Configuration bits (for their default value)The Device ID registers (0xFF0000:0xFF0002) can be ignored by the Blank Check since this region stores device information that cannot be erased. Additionally, all unimplemented memory space should be ignored from the Blank Check.The QBLANK command is used for the Blank Check. It determines if the code memory and data EEPROM are erased by testing these memory regions. A ‘BLANK’ or ‘NOT BLANK’ response is returned. The READD command is used to read the Configuration registers. If it is determined that the device is not blank, it must be erased (see Section 5.3 “Chip Erase”) before attempting to program the chip.Note 1:The sequence that places the device intoEnhanced ICSP mode places all unused I/Os in the high-impedance state.2:Before entering Enhanced ICSP mode,clock switching must be disabled using ICSP , by programming the FCKSM<1:0> bits in the FOSC Configuration register to ‘11’ or ‘10’.3:When in Enhanced ICSP mode, the SPIoutput pin (SDO1) will toggle while the device is being programmed.dsPIC30F Flash Programming Specification5.5Code Memory Programming5.5.1OVERVIEWThe Flash code memory array consists of 512 rows ofthirty-two, 24-bit instructions. Each panel stores 16Kinstruction words, and each dsPIC30F device haseither 1, 2 or 3 memory panels (see Table 5-2).TABLE 5-2:DEVICE CODE MEMORY SIZEDevice Code Size(24-bitWords)NumberofRowsNumberofPanelsdsPIC30F20104K1281 dsPIC30F20114K1281 dsPIC30F20124K1281 dsPIC30F30108K2561 dsPIC30F30118K2561 dsPIC30F30128K2561 dsPIC30F30138K2561 dsPIC30F30148K2561 dsPIC30F401116K5121 dsPIC30F401216K5121 dsPIC30F401316K5121 dsPIC30F501122K7042 dsPIC30F501322K7042 dsPIC30F501522K7042 dsPIC30F501622K7042 dsPIC30F601048K15363 dsPIC30F6010A48K15363 dsPIC30F601144K14083 dsPIC30F6011A44K14083 dsPIC30F601248K15363 dsPIC30F6012A48K15363 dsPIC30F601344K14083 dsPIC30F6013A44K14083 dsPIC30F601448K15363 dsPIC30F6014A48K15363 dsPIC30F601548K153635.5.2PROGRAMMING METHODOLOGY Code memory is programmed with the PROGP command. PROGP programs one row of code memory to the memory address specified in the command. The number of PROGP commands required to program a device depends on the number of rows that must be programmed in the device.A flowchart for programming of code memory is illus-trated in Figure 5-3. In this example, all 48K instruction words of a dsPIC30F6014A device are programmed. First, the number of commands to send (called ‘RemainingCmds’ in the flowchart) is set to 1536 and the destination address (called ‘BaseAddress’) is set to ‘0’. Next, one row in the device is programmed with a PROGP command. Each PROGP command contains data for one row of code memory of the dsPIC30F6014A. After the first command is processed successfully, ‘RemainingCmds’ is decremented by 1 and compared to 0. Since there are more PROGP commands to send, ‘BaseAddress’ is incremented by 0x40 to point to the next row of memory.On the second PROGP command, the second row of each memory panel is programmed. This process is repeated until the entire device is programmed. No special handling must be performed when a panel boundary is crossed.FIGURE 5-3:FLOWCHART FORPROGRAMMINGdsPIC30F6014A CODEMEMORYIsPROGP responsePASS?IsRemainingCmds0?BaseAddress = 0x0RemainingCmds = 1536RemainingCmds =RemainingCmds – 1FinishBaseAddress =BaseAddressNoNoYesYes+ 0x40StartFailureReport ErrorSend PROGPCommand to ProgramBaseAddress© 2010 Microchip Technology Inc.DS70102K-page 7dsPIC30F Flash Programming SpecificationDS70102K-page 8© 2010 Microchip Technology Inc.5.5.3PROGRAMMING VERIFICATIONOnce code memory is programmed, the contents of memory can be verified to ensure that programming was successful. Verification requires code memory to be read back and compared against the copy held in the programmer’s buffer.The READP command can be used to read back all the programmed code memory.Alternatively, you can have the programmer perform the verification once the entire device is programmed using a checksum computation, as described in Section 6.8 “Checksum Computation”.5.6Data EEPROM Programming5.6.1OVERVIEWThe panel architecture for the data EEPROM memory array consists of 128 rows of sixteen 16-bit data words. Each panel stores 2K words. All devices have either one or no memory panels. Devices with data EEPROM provide either 512 words, 1024 words or 2048 words of memory on the one panel (see Table 5-3).TABLE 5-3:DATA EEPROM SIZEDevice Data EEPROM Size (Words)Number of RowsdsPIC30F201051232dsPIC30F201100dsPIC30F201200dsPIC30F301051232dsPIC30F301151232dsPIC30F301251232dsPIC30F301351232dsPIC30F301451232dsPIC30F401151232dsPIC30F401251232dsPIC30F401351232dsPIC30F501151232dsPIC30F501351232dsPIC30F501551232dsPIC30F501651232dsPIC30F60102048128dsPIC30F6010A 2048128dsPIC30F6011102464dsPIC30F6011A 102464dsPIC30F60122048128dsPIC30F6012A 2048128dsPIC30F6013102464dsPIC30F6013A 102464dsPIC30F60142048128dsPIC30F6014A 2048128dsPIC30F601520481285.6.2PROGRAMMING METHODOLOGYThe programming executive uses the PROGD command to program the data EEPROM. Figure 5-4 illustrates the flowchart of the process. Firstly, the number of rows to program (RemainingRows) is based on the device size, and the destination address (DestAddress) is set to ‘0’. In this example, 128 rows (2048 words) of data EEPROM will be programmed.The first PROGD command programs the first row of data EEPROM. Once the command completes successfully, ‘RemainingRows’ is decremented by 1 and compared with 0. Since there are 127 more rows to program, ‘BaseAddress’ is incremented by 0x20 to point to the next row of data EEPROM. This process is then repeated until all 128 rows of data EEPROM are programmed.FIGURE 5-4:FLOWCHART FOR PROGRAMMINGdsPIC30F6014A DATA EEPROMIsPROGD responsePASS?IsRemainingRows0?Remaining Rows = 128BaseAddress = 0RemainingRows =RemainingRows – 1FinishBaseAddress =BaseAddress NoNoYes Yes+ 0x20StartSend PROGD Command with BaseAddressFailure Report ErrordsPIC30F Flash Programming Specification5.6.3PROGRAMMING VERIFICATIONOnce the data EEPROM is programmed, the contents of memory can be verified to ensure that the programming was successful. Verification requires the data EEPROM to be read back and compared against the copy held in the programmer’s buffer. The READD command reads back the programmed data EEPROM. Alternatively, the programmer can perform the verification once the entire device is programmed using a checksum computation, as described in Section 6.8 “Checksum Computation”.Note:TBLRDL instructions executed within a REPEAT loop must not be used to readfrom Data EEPROM. Instead, it isrecommended to use PSV access.5.7Configuration Bits Programming5.7.1OVERVIEWThe dsPIC30F has Configuration bits stored in seven 16-bit registers. These bits can be set or cleared to select various device configurations. There are two types of Configuration bits: system-operation bits and code-protect bits. The system-operation bits determine the power-on settings for system-level components such as the oscillator and Watchdog Timer. The code- protect bits prevent program memory from being read and written. The FOSC Configuration register has three different register descriptions, based on the device. The FOSC Configuration register description for the dsPIC30F2010 and dsPIC30F6010/6011/6012/6013/ 6014 devices are shown in Table 5-4.Note:If user software performs an erase opera-tion on the configuration fuse, it must befollowed by a write operation to this fusewith the desired value, even if the desiredvalue is the same as the state of theerased fuse.The FOSC Configuration register description for the dsPIC30F4011/4012 and dsPIC30F5011/5013 devicesis shown in Table 5-5.The FOSC Configuration register description forall remaining devices (dsPIC30F2011/2012, dsPIC30F3010/3011/3012/3013, dsPIC30F3014/ 4013, dsPIC30F5015 and dsPIC30F6011A/6012A/ 6013A/ 6014A) is shown in Table 5-6. Always use the correct register descriptions for your target processor.The FWDT, FBORPOR, FBS, FSS, FGS and FICD Configuration registers are not device-dependent. The register descriptions for these Configuration registersare shown in Table 5-7.The Device Configuration register maps are shown in Table 5-8 through Table 5-11.TABLE 5-4:FOSC CONFIGURATION BITS DESCRIPTION FOR dsPIC30F2010 ANDdsPIC30F6010/6011/6012/6013/6014Bit Field Register DescriptionFCKSM<1:0>FOSC Clock Switching Mode1x =Clock switching is disabled, Fail-Safe Clock Monitor is disabled01 =Clock switching is enabled, Fail-Safe Clock Monitor is disabled00 =Clock switching is enabled, Fail-Safe Clock Monitor is enabledFOS<1:0>FOSC Oscillator Source Selection on POR11 =Primary Oscillator10 =Internal Low-Power RC Oscillator01 =Internal Fast RC Oscillator00 =Low-Power 32 kHz Oscillator (Timer1 Oscillator)FPR<3:0>FOSC Primary Oscillator Mode1111 = ECIO w/PLL 16X – External Clock mode with 16X PLL. OSC2 pin is I/O1110 = ECIO w/PLL 8X – External Clock mode with 8X PLL. OSC2 pin is I/O1101 = ECIO w/PLL 4X – External Clock mode with 4X PLL. OSC2 pin is I/O1100 = ECIO – External Clock mode. OSC2 pin is I/O1011 = EC – External Clock mode. OSC2 pin is system clock output (F OSC/4)1010 = Reserved (do not use)1001 = ERC – External RC Oscillator mode. OSC2 pin is system clock output(F OSC/4)1000 = ERCIO – External RC Oscillator mode. OSC2 pin is I/O0111 = XT w/PLL 16X – XT Crystal Oscillator mode with 16X PLL0110 = XT w/PLL 8X – XT Crystal Oscillator mode with 8X PLL0101 = XT w/PLL 4X – XT Crystal Oscillator mode with 4X PLL0100 = XT – XT Crystal Oscillator mode (4 MHz-10 MHz crystal)001x = HS – HS Crystal Oscillator mode (10 MHz-25 MHz crystal)000x = XTL – XTL Crystal Oscillator mode (200 kHz-4 MHz crystal)© 2010 Microchip Technology Inc.DS70102K-page 9dsPIC30F Flash Programming SpecificationTABLE 5-5:FOSC CONFIGURATION BITS DESCRIPTION FOR dsPIC30F4011/4012 AND dsPIC30F5011/5013Bit Field Register DescriptionFCKSM<1:0>FOSC Clock Switching Mode1x =Clock switching is disabled, Fail-Safe Clock Monitor is disabled01 =Clock switching is enabled, Fail-Safe Clock Monitor is disabled00 =Clock switching is enabled, Fail-Safe Clock Monitor is enabledFOS<1:0>FOSC Oscillator Source Selection on POR11 =Primary Oscillator10 =Internal Low-Power RC Oscillator01 =Internal Fast RC Oscillator00 =Low-Power 32 kHz Oscillator (Timer1 Oscillator)FPR<3:0>FOSC Primary Oscillator Mode1111 =ECIO w/PLL 16X – External Clock mode with 16X PLL. OSC2 pin is I/O1110 =ECIO w/PLL 8X – External Clock mode with 8X PLL. OSC2 pin is I/O1101 =ECIO w/PLL 4X – External Clock mode with 4X PLL. OSC2 pin is I/O1100 =ECIO – External Clock mode. OSC2 pin is I/O1011 =EC – External Clock mode. OSC2 pin is system clock output (F OSC/4)1010 =FRC w/PLL 8x – Internal fast RC oscillator with 8x PLL. OSC2 pin is I/O1001 =ERC – External RC Oscillator mode. OSC2 pin is system clock output(F OSC/4)1000 =ERCIO – External RC Oscillator mode. OSC2 pin is I/O0111 =XT w/PLL 16X – XT Crystal Oscillator mode with 16X PLL0110 =XT w/PLL 8X – XT Crystal Oscillator mode with 8X PLL0101 =XT w/PLL 4X – XT Crystal Oscillator mode with 4X PLL0100=XT – XT Crystal Oscillator mode (4 MHz-10 MHz crystal)0011 =FRC w/PLL 16x – Internal fast RC oscillator with 16x PLL. OSC2 pin is I/O0010=HS – HS Crystal Oscillator mode (10 MHz-25 MHz crystal)0001 =FRC w/PLL 4x – Internal fast RC oscillator with 4x PLL. OSC2 pin is I/O0000=XTL – XTL Crystal Oscillator mode (200 kHz-4 MHz crystal)DS70102K-page 10© 2010 Microchip Technology Inc.dsPIC30F Flash Programming Specification TABLE 5-6:FOSC CONFIGURATION BITS DESCRIPTION FOR dsPIC30F2011/2012,dsPIC30F3010/3011/3012/3013/3014, dsPIC30F4013, dsPIC30F5015/5016,dsPIC30F6010A/6011A/6012A/6013A/6014A AND dsPIC30F6015 Bit Field Register DescriptionFCKSM<1:0>FOSC Clock Switching Mode1x =Clock switching is disabled, Fail-Safe Clock Monitor is disabled01 =Clock switching is enabled, Fail-Safe Clock Monitor is disabled00 =Clock switching is enabled, Fail-Safe Clock Monitor is enabledFOS<2:0>FOSC Oscillator Source Selection on POR111 = Primary Oscillator110 = Reserved101 = Reserved100 = Reserved011 = Reserved010 = Internal Low-Power RC Oscillator001 = Internal Fast RC Oscillator (no PLL)000 = Low-Power 32 kHz Oscillator (Timer1 Oscillator)FPR<4:0>FOSC Primary Oscillator Mode (when FOS<2:0> = 111b)11xxx = Reserved (do not use)10111 = HS/3 w/PLL 16X – HS/3 crystal oscillator with 16X PLL(10 MHz-25 MHz crystal)10110 = HS/3 w/PLL 8X – HS/3 crystal oscillator with 8X PLL(10 MHz-25 MHz crystal)10101 = HS/3 w/PLL 4X – HS/3 crystal oscillator with 4X PLL(10 MHz-25 MHz crystal)10100 = Reserved (do not use)10011 = HS/2 w/PLL 16X – HS/2 crystal oscillator with 16X PLL(10 MHz-25 MHz crystal)10010 = HS/2 w/PLL 8X – HS/2 crystal oscillator with 8X PLL(10 MHz-25 MHz crystal10001 = HS/2 w/PLL 4X – HS/2 crystal oscillator with 4X PLL(10 MHz-25 MHz crystal)10000 = Reserved (do not use)01111 = ECIO w/PLL 16x – External clock with 16x PLL. OSC2 pin is I/O01110 = ECIO w/PLL 8x – External clock with 8x PLL. OSC2 pin is I/O01101 = ECIO w/PLL 4x – External clock with 4x PLL. OSC2 pin is I/O01100 = Reserved (do not use)01011 = Reserved (do not use)01010 = FRC w/PLL 8x – Internal fast RC oscillator with 8x PLL. OSC2 pin is I/O01001 = Reserved (do not use)01000 = Reserved (do not use)00111 = XT w/PLL 16X – XT crystal oscillator with 16X PLL00110 = XT w/PLL 8X – XT crystal oscillator with 8X PLL00101 = XT w/PLL 4X – XT crystal oscillator with 4X PLL00100 = Reserved (do not use)00011 = FRC w/PLL 16x – Internal fast RC oscillator with 8x PLL. OSC2 pin is I/O00010 = Reserved (do not use)00001 = FRC w/PLL 4x – Internal fast RC oscillator with 4x PLL. OSC2 pin is I/O00000 = Reserved (do not use)© 2010 Microchip Technology Inc.DS70102K-page 11。
CD4011集成电路课件—第四周全
AB
Y
00
1
01
1
10
1
11
0
CD4011交替 闪烁信号灯
上电后，假设3 脚输出为0, 4脚 输出为1， LED1点亮， LED2熄灭，通 过R4对C2充电， 对C1反向充电 （放电）。
§1-2 面包板
面包板是由于板子上有很多小插孔， 专为电子电路的无焊接实验设计制
§1-2 面包板
板底有金属条，在板上对应位置打 孔使得原件插入孔中时能够与金属 条接触，从而达到导电目的。一般 将每5个孔板用一条金属条连接。
板子中央一般有一条凹槽，这是 针对需要集成电路、芯片试验而 设计的。板子两侧有两排竖着的 插孔，也是5个一组。这两组插孔 是用于给板子上的元件提供电源。
Байду номын сангаас §1-2 面包板
造的。
由于各种电子元器件可根据需要 随意插入或拔出，免去了焊接， 节省了电路的组装时间，而且元 件可以重复使用，所以非常适合 电子电路的组装、调试和训练。
§1-2 面包板
面包板是由于板子上有很多小插孔， 专为电子电路的无焊接实验设计制
造的。
由于各种电子元器件可根据需要 随意插入或拔出，免去了焊接， 节省了电路的组装时间，而且元 件可以重复使用，所以非常适合 电子电路的组装、调试和训练。
§1-2 面包板
cd4012
CC4012------双4输入与非门简要说明CC4011为4输入正向逻辑与非门。
CC4011与非门为系统设计者提供了直接的与非功能，补充了已有COS/MOS 门系列，所有输入和输出经过缓冲，改善了输入/输出传输特性，使得由于负载容量的增加而引起的传输时间的变化维持到最小。
CC4011提供了14引线多层陶瓷双列直插（D）、熔封陶瓷双列直插（J）、塑料双列直插（P）和陶瓷片状载体（C）4种封装形式。
引出端符号1A－2A，1B－2B，1C－2C，1D－2D输入端1Y－2Y 输出端V DD正电源Vss 地推荐工作条件电源电压范围…………3V～15V输入电压范围…………0V～V DD工作温度范围M类…………－55℃～125℃E类………….－40℃～85℃极限值电源电压…...－0.5V～18V输入电压……－0.5V~V DD+0.5V输入电流…………….±10mA储存稳定…………－65℃～150℃逻辑符号引出端排列（俯视）逻辑图（1/2）逻辑表达式静态特性：测试条件规范值参数V O （V）V I（V）V DD（V）-55℃-40℃ 25℃ 85℃ 125℃单位V OL输出低电平电压（最大）- 5/010/015/05.010.015.00.05 VV OH输出高电平电压（最小）- 5/010/015/05.010.015.04.959.9514.95VV IL输入低电平电压（最大）4.59.013.5- 5.010.015.01.53.04.0VV IH输入高电平电压（最小）4.5/0.59.0/1.013.5/1.5- 5.010.015.03.57.011.0VI OH输出高电平电流（最小）2.54.69.513.55/05/010/015/05.05.010.015.0-2.0-0.64-1.6-4.2-1.8-0.61-1.5-4.0-1.6-0.51-1.3-3.4-1.3-0.42-1.1-2.8-1.15-0.36- 0.9-2.4mAI OL输出低电平电流（最小）0.40.51.55/010/015/05.010.015.00.641.64.20.611.54.00.511.33.40.421.12.80.360.92.4mAI I输入电流- 15/015.0±0.1 ±1.0 µAI DD电源电流（最大）- 5/010/015/05.010.015.00.250.51.00.250.51.07.515.030.0µA动态特性（TA＝25℃）：规范值参数测试条件V DD（V）最小最大单位t PLH输出由低电平到高电平传输延迟时间5.010.015.0- 25012090nst PHL输出由高电平到低电平传输延迟时间5.010.015.0- 25012090nst TLH输出由低电平到高电平转换时间5.010.015.0- 20010080nst THL输出由高电平到低电平转换时间5.010.015.0- 20010080nsC I输入电容（任一输入端）C L＝50pFR L＝200kt r＝20nst f＝20ns- - 7.5 pF。
MCP41010中文 数字电位器
0
LSB 编码 FFh， VDD = 3V，请参见图 2-25
+2
LSB 编码 00h， VDD = 5V，请参见图 2-25
+2
LSB 编码 00h， VDD = 3V，请参见图 2-25
电压范围
VA,B,W
0
电容 （CA 或 CB） 电容
－
CW
－
动态特性 （测试所有动态特性时 VDD = 5V）
带宽 -3dB
BW
－
稳定时间
tS
－
－
VDD
注4
15
－
pF f = 1 MHz，编码 80h，请参见图 2-30
5.6
－
pF f = 1 MHz，编码 80h，请参见图 2-30
1
－
MHz VB = 0V，在编码为 80h，输出负载 = 30 PF 时测得
2
－
µS VA = VDD， VB = 0V，误差范围为 ±1%，编码从 00h 过
施密特触发器高电平输入电压
VIH
0.7VDD
－
－
V
施密特触发器低电平输入电压
VIL
－
－
.3VDD
V
施密特触发器输入迟滞
VHYS
－
.05VDD
－
低输出电压
VOL
－
－
高输出电压
VOH
VDD - 0.5
－
输入泄漏电流
ILI
-1
－
引脚电容 （所有输入 / 输出）
CCIONU和T
－
10
电源要求
0.40 － +1 －
封装类型
PDIP/SOIC
计通电量仪MCP400说明书
注意：VOLTS MODE=3 WIRE WYE 只能在电压平衡的情况下提供精确的测量。如果 B 相电压不等 于 A 相和 C 相电压，则功率读数将达不到仪表的精度。
注意： 1、VOLT MODE = 3 WIRE WYE 2、注意每个 PT 和 CT 的极性。
2.5 三相星型（Y）系统连接
4 线和 3 线 Y 型系统接线图。MCP400 检测各相线对地的电压，如果监测是 100V-347V 系统，输 入可以直接连接。
MCP400 仪表上的 VOLTS MODE 应设置为：4 WIRE WYE。
注意： 1、VOLT MODE =4 WIRE WYE。 2、注意每个 CT 的极性。
如果系统电压超过 347/600V，必须采用 PT，PT 初级和次级必须接成星型（Y），超过 25W 则次级必须用保险丝。
VOLT MODE 应设置为：4 WIRE WYE
注意： 1、VOLT MODE = 4 WIRE WYE。 2、 注意每个 PT 和 CT 的极性。
2.6 三相△形（DELTA）系统的连接
当设置为不接地（浮地）△形接线，则需要 PT 及检测各相的线间（L-L）电压，电压模式应 设为 3 线△形：VOLTS MODE=3 WIRE DELTA
在开放式的△形方式中，MCP400 可以两种方式连接：使用 2 个或 3 个 CT。
注意： 1、VOLT MODE = 3 WIRE DETA 2、 注意每个 PT 和 CT 的极性
MCP400 标准电力监测仪 使用说明书
Installation & Operation Manual Version 2.0
CD4011组成的触摸延时开关电路图
CD4011组成的触摸延时开关电路图图中为触摸延时开关实验电路。
它由整流二极管VD1～VD4组成全波桥式整流电路，作为集成电路工作电源，四2输入端与非门4011、单向晶闸管VS1等组成触摸开关电路。
全波桥式整流电路输出高达200V脉动直流电，经过电阻器R1、R2分压，并通过电容器C1滤波，输出约13V的直流电，作为IC工作电源。
在照明灯EL亮时，4011(点击查看:CD4011中文资料(功能,真值表,引脚图及电气参数))稳态工作总电流不到20μA，灯熄灭时401l电流(用50μA量程)几乎无法测出，足见CMOS集成电路的低功耗.此外，在照明灯EL点亮时，R2分压降至2V，4011仍能工作，这就是选用CMOS数字集成电路的原因。
图触摸延时开关电路当用手触摸金属片A端时，通过降压电阻器R3、R4将感应交流电信号加在IC—1输入端，在交流电正半周时，IC-1的L、2脚为高电平，其输出端下跌为低电平，与之相连IC-2输出端4脚上升为高电平，通过开关二极管VD5向定时电容器C2充电，使得IC-3输入端上升到高电平，其输出端10脚为低电平，IC-4输出端11脚为高电平，通过电阻器R7加在单向晶闸管控制电极G上，触发VS1导通，负载照明灯EL点亮。
当C2充电电荷通过定时电阻器R6逐渐放电，使电压下降到低于CMOS 门开启电压时，IC-3输出端上升为高电平，IC-4输出端为低电平，单向晶闸管阻断，EL熄灭。
当R6为1MΩ、C2为10μF时，触摸开关控制延时约17s，C2换成22μF 时，延时增加一倍，C2为47μF延时已绰绰有余。
在触摸开关电路中，R5为下拉电阻器，尽管其电阻值为1MΩ，但与非门IC-1输入端为低电平，说明CMOS数字集成电路输入阻抗非常高。
四2输入端与非门4011剩余的输入端不能悬空，采用并接方式，当作非门使用。
IC也可选用四2输入端或非门4001(点击查看:CD4001中文资料(功能,引脚图,电气参数))。
数字电位器MCP41010在止鼾器中的应用
数字电位器MCP41010在止鼾器中的应用作者：金贵马显光邓玲来源：《现代电子技术》2010年第04期摘要:在设计的止鼾器恒流源电路中采用MCP41010数字电位器来改变恒流源对人体的刺激电流,从而可以根据人体对止鼾器刺激电流的适应程度适时改变电流的大小。
在此介绍Microchip公司生产的MCP41010数字电位器的工作原理和主要特点,描述MCP41010的指令字格式。
采用MCP41010作为恒流源电路的射极电阻,AVR单片机AT90S8535的I/O口与MCP41010相连接,单片机程序模拟MCP41010的SPI总线时序,从而达到改变阻值的目的。
实验结果表明,使用MCP41010达到了很好的效果。
关键词:数字电位器;MCP41010;止鼾器;SPI总线;AT90S8535中图分类号:TP274文献标识码:B文章编号:1004-373X(2010)04-187-03Application of Digital Potentiometer MCP41010 in Snore-ceasing EquipmentsJIN Gui,MA Xianguang,DENG Ling(College of Biomedical Engineering & Medical Imaging,Third Military MedicalUniversity,Chongqing,400030,China)Abstract:Applying MCP41010 digital potentiometer of designed snore-ceasing eq uipments′shuman body,so as to change the current according to adaptation of stimulate current.The principle and features of MCP41010 digital potentiometers produced by Microchip Company,and the instruction format are also introduced.Connecting MCP41010 with I/O interface of AT90S8535 and simulating SPI of MCP4010 to change the resistance.Results prove that it gains good effects.Keywords:digital potentiometer;MCP41010;snore-ceasing equipment;SPI bus;AT90S85350 引言MCP41010是Microchip公司生产的一种集成数字电位器。
mcp4017控制代码
mcp4017控制代码题目：MCP4017控制代码解读与应用摘要：本文将详细解读MCP4017数字电位计芯片的控制代码，并结合实际应用场景，逐步分析该芯片的工作原理、编程方法以及使用技巧，并阐述其在电子设备调节和自动化控制系统中的重要作用。
引言：MCP4017是一款高精度数字电位计芯片，具有广泛的应用领域，如电子设备调节、功率控制和自动化控制系统等。
该芯片通过I2C接口进行通信，并利用控制代码实现电阻值的精确调节。
本文将围绕MCP4017的控制代码展开讨论，帮助读者理解该芯片的工作原理和使用方法。
一、MCP4017芯片的特点与工作原理MCP4017是一款具备8位非易失性电阻存储器的数字电位计芯片。
它具有低温漂移特性和高精度的电阻调节范围，能够满足各种精确调节要求。
芯片内部由电阻栅极和开关转换电路组成，通过控制代码的调节，实现电子设备的精细控制。
二、MCP4017控制代码的编程方法1. 引入I2C库函数：在控制代码开头，需要引入相应的I2C库函数，以便使用I2C接口与芯片进行通信。
2. 初始化MCP4017：调用初始化函数，设置MCP4017芯片的工作参数，如I2C通信速率、增益设置和阻尼系数等。
3. 清零和校准：在开始工作前，需要对MCP4017进行清零和校准操作，以确保输出数据的准确性。
4. 数据读取和写入：通过I2C通信接口，读取和写入MCP4017内部的数据寄存器，实现对电阻值的调节。
5. 保存和读取配置：可以使用EEPROM等非易失性存储器保存MCP4017的配置参数，以便下次使用时读取。
三、MCP4017控制代码的使用技巧1. 了解芯片的工作范围：在编写控制代码前，需了解MCP4017的电阻调节范围以及调节精度，以确保代码的正确性。
2. 寻找最佳调节步长：根据具体应用场景，选择合适的调节步长，避免过大或过小的调节幅度影响系统性能。
3. 添加错误处理机制：在实际应用中，可能会遇到通信错误或其他异常情况。
MCP3901_CN
ppm/°C -40°C 至 +125°C
—
dB
1： 此参数规范意味着 ADC 输出在整个差分范围内有效，并在整个输入范围内没有失真或不稳定。动态性能规 范适用于低于最大信号范围 -0.5 dB， VIN = -0.5 dBFS @ 50/60 Hz = 353 mVRMS， VREF = 2.4V。 2： 参考术语部分的定义。 3： 特性参数，未经 100% 测试。 4： 对于这些工作电流，把下列位设置成：SHUTDOWN<1:0>=00， RESET<1:0>=00， VREFEXT=0， CLKEXT=0。 5： 对于这些工作电流，把下列配置位设置成：SHUTDOWN<1:0>=11， VREFEXT=1， CLKEXT=1。 6： 适用于所有增益。失调误差取决于 PGA 增益设置，关于典型值，请参见图 2-19。 7： 超出此范围，未对 ADC 的精度进行规范。 ±6V 的扩展输入电压范围的信号可连续施加到器件而不会导致 器件损坏。 8： 为保证正常工作以保持 ADC 精度，在 BOOST 位关断时， AMCLK 应保持在 1 MHz 至 5 MHz 范围内；在 BOOST 位开启时， AMCLK 应保持在 1 MHz 至 8.192 MHz 范围内。 AMCLK = MCLK/PRESCALE。如果使用晶体振荡器，那么 CLKEXT 位应设置为 0。
电气特性
电气规范：除非另外说明，否则 AVDD = 4.5 至 5.5V， DVDD = 2.7 至 5.5V ； -40°C<TA<+85°C， MCLK = 4 MHz ； PRESCALE = 1 ； OSR = 64 ； GAIN = 1 ；关闭抖动处理； VIN = -0.5 dBFS = 353 mVRMS （50/60 Hz 时） 。 参数 内部参考电压 内部参考电压容差 温度系数 输出阻抗 参考电压输入 输入电容 差分输入电压范围 （VREF+ - VREF-） REFIN+ 引脚上的绝对电压 REFIN- 引脚上的绝对电压 ADC 性能 分辨率 （无丢失码） 采样频率 注 fS 24 — 请参见表 4-2 — bits kHz OSR = 256 （见表 5-3） fS = DMCLK = MCLK / (4 x PRESCALE) VREF VREF+ VREF— 2.2 1.9 -0.3 — — — — 10 2.6 2.9 0.3 pF V V V VREF = (VREF+ - VREF-)， VREFEXT = 1 VREFEXT = 1 VREF TCREF ZOUTREF -2% — 2.37 12 7 +2% — — V kΩ VREFEXT = 0 AVDD=5V， VREFEXT = 0 ppm/°C VREFEXT = 0 符号 最小值 典型值 最大值 单位 条件
LED背光控制集成块MP4012工作特点与检修
LED 背光控制集成块MP4012 工作特点与检修MP4012 是一块高精度电流控制型LED 驱动控制IC，能为高亮度LED 发光二极管提供8V-55V 直流供电，广泛用在LED 液晶显示器的背光驱动电路中。
用此IC 设计的驱动电路架构有多种，如同步激励拓扑驱动型（SEPIC ）、自举升压型（BOOST ）、降压型（BUCK ）以及升压降压型（BUCK-BOOST ）。
这些电路工作模式可设计成对外挂的MOSFET 管驱动采取恒定工作频率方式，也可设计成恒定的关时间工作模式。
长虹HSU25D -1M6 375 、HSU25D -1M6 300 、HSS35D-1MF 260 、HSS35D-1MF 241 、HSS35D-1MC220 、HSS35D-I MG 240 、HSS30D-1MB 190 、HSM45D-1MJ 260 、HSM45D-6M4 240 等二合一电源板中的背光驱动电路，均采用MP4012 作为LED 背光驱动控制IC 、其实测电压见表1。
下面对该IC 的各引脚功能进行具体介绍。
1. MP4012引脚功能①脚（VIN ）为供电脚，供电范围在8V-55V之间。
① 脚内接线性调整电路，形成②脚的VDD电压。
该IC在长虹HSM45D -6M4 240 二合一电源板上的供电电路如图1 所示。
二次开机时，主板送来高电平的电源开机信号PS-ON 使Q403 截止。
与此同时，开关电源送来12.3V 电压接入Q411 的e 极。
另外，控制系统送出高电平的BL-ON 背光开启信号，Q408饱和导通，Q411随之饱和导通，12.3V通过Q411 的c、e 极及D403降压后得到约11.6V 电压，为IC 的①脚供电。
②脚（VDD ）,为内部线性电源调整块输出滤波端，外接滤波电容，为IC 内所有的电路包括给外部MOSFET 栅极提供驱动供电。
在长虹电源中，此脚外接电容C126 。
②脚电压在7.25V〜8.15V之间。
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MCP4014 SOT-23-5 变阻器
W B A 5 W
4 CS
框图
A VDD 上电和 欠压 控制
应用
• 电源调整和校准 • 在新设计中用以替换机械式电位器 • 仪表中的失调和增益调整
VSS 滑动端寄存器 （寄存器阵列）
CS U/D
说明
MCP4011/2/3/4 器件是一款易失性 6 位数字电位器，可 以被配置为电位器或变阻器。通过一个简单的递增 / 递 减 （U/D）串行接口控制滑动端的设置。
双线 接口 和 控制 逻辑
W
B
器件特性
存储器 类型 POR 时的 滑动端设置 可选的阻值 （kΩ） 中央刻度 中央刻度 中央刻度 中央刻度 2.1, 5.0, 10.0, 50.0 2.1, 5.0, 10.0, 50.0 2.1, 5.0, 10.0, 50.0 2.1, 5.0, 10.0, 50.0 抽头 数量 VDD 工作电压 范围 (2) 控制接口 电阻 （典型值） 器件 滑动端配置 滑动 电阻 （Ω） 75 75 75 75 WiperLock™ 技术 无 无 无 无
交流 / 直流特性
电气规范： 除非另外指明，否则所有参数均适用于指定的工作范围。 TA = -40°C 至 +125°C （2.1 kΩ、 5 kΩ、 10 kΩ 和 50 kΩ 器件） 。 典型规范值表示 VDD = 2.7V 至 5.5V、 VSS = 0V 且 TA = +25°C 条件下 的值。 参数 工作电压范围 符号 VDD VDD 最小值 2.7 — 典型值 — 1.8 最大值 5.5 — 单位 V V VDD = 1.8V， CS：VIHH = 8.5V、 VIH = 1.8V 且 VIL = 0V， U/D：VIH = 1.8V 且 VIL = 0V CS 引脚将位于以下三种输入电平 之一 （VIL、 VIH 或 VIHH） 。 （注 6） 5.5V、 CS = VSS 且 fU/D = 1 MHz 2.7V、 CS = VSS 且 fU/D = 1 MHz 串行接口无效 （CS = VIH 且 U/D = VIH） -202 器件 （注 1） -502 器件 （注 1） -103 器件 （注 1） -503 器件 （注 1） 条件
5： 电阻的 A 端、 W 端或 B 端相对于其他两者的极性不作限制。 6： 此规范仅供设计参考。 7： 滑动电阻 （RW）会影响输出阻值的非线性度，阻值随电压和温度的变化非常显著。更多信息请参见第 6.0 节 “电 阻” 。 8： 对于电压低于 2.7V 的情况，请参见第 2.0 节 “典型性能曲线” 。 9： 对 MCP4011 进行了外部连接的与 MCP4012 和 MCP4014 的配置匹配后，才进行测试。
MCP4011/2/3/4
低成本 64 级易失性数字电位器
特性
• 易失性数字电位器，具有 SOT-23、 SOIC、 MSOP 和 DFN 封装形式 • 64 个抽头 ： 在 A 端和 B 端之间连有 63 个电阻， 并 且电阻之间具有抽头 • 简单递增 / 递减 （U/D）协议 • 上电时恢复默认的抽头设置 - 可以自定义上电复位时的抽头设置 （联系厂商） • 电阻值：2.1 kΩ、 5 kΩ、 10 kΩ 或 50 kΩ • 低温度系数： - 绝对 （变阻器） ：50 ppm （0°C 至 70°C 时的典型 值） - 相对 （电位器） ：10 ppm （典型值） • 低滑动电阻：75Ω （典型值） • 数字输入可承受较高的电压：最高可达 12.5V • 低功耗运行：最大静态电流为 1 礎 • 宽工作电压范围： - 1.8V 至 5.5V ——正常的器件工作 - 2.7V 至 5.5V ——指定电阻特性 • 扩展的温度范围： -40 鸆至 +125 鸆
MCP4011 MCP4012 MCP4013 MCP4014 注
.
电位器 (1) 变阻器 电位器 变阻器
RAM RAM RAM RAM
64 64 64 64
1.8V 至 5.5V U/D 1.8V 至 5.5V U/D 1.8V 至 5.5V U/D 1.8V 至 5.5V U/D
1： 将 A 端或 B 端中的一端悬空即可使器件用于变阻器模式。 2： 模拟特性 （阻值）是在 2.7V 至 5.5V 工作电压条件下测得的。
DS21978A_CN 第 2 页
2006 Microchip Technology Inc.源自MCP4011/2/3/4
交流 / 直流特性 （续）
电气规范： 除非另外指明，否则所有参数均适用于指定的工作范围。 TA = -40°C 至 +125°C （2.1 kΩ、 5 kΩ、 10 kΩ 和 50 kΩ 器件） 。 典型规范值表示 VDD = 2.7V 至 5.5V、 VSS = 0V 且 TA = +25°C 条件下 的值。 参数 分辨率 步进电阻值 滑动端的阻值 （注 3 和注 4） 标称电阻温度系数 符号 N RS RW ∆R/∆T — — — — — — 电位器温度系数 满量程误差 （仅 MCP4011/13） 零刻度误差 （仅 MCP4011/13） 注 1： 2： 3： 4： ∆VWA/∆T VWFSE VWZSE — -0.5 -0.5 最小值 典型值 64 RAB/63 70 70 50 100 150 10 -0.1 +0.1 — 125 325 — — — — +0.5 +0.5 最大值 单位 抽头数 Ω Ω Ω ppm/°C ppm/°C ppm/°C ppm/°C LSb LSb 注6 5.5V 2.7V TA = -20°C 至 +70°C TA = -40°C 至 +85°C TA = -40°C 至 +125°C 仅适用于 MCP4011 和 MCP4013，代码 = 1Fh 代码为 3Fh， 2.7V ≤ VDD ≤ 5.5V 代码为 00h， 2.7V ≤ VDD ≤ 5.5V 条件 不丢失任何代码
此处的阻值指的是电位器 A 端和 B 端之间的阻值。 INL 和 DNL 是 VA = VDD 且 VB = VSS 时在 VW 测得的。 （-202 器件的 VA = 4V） 。 仅适用于 MCP4011/13，测试条件为：IW = 1.9 mA 且代码 = 00h。 仅适用于 MCP4012/14，测试条件如下： 器件 阻值 2.1 kΩ 5 kΩ 10 kΩ 50 kΩ 不同电压下的电流 5.5V 2.25 mA 1.4 mA 450 µA 90 µA 2.7V 1.1 mA 450 µA 210 µA 40 µA 备注 MCP4012 包含 VWZSE MCP4014 包含 VWFSE
5： 电阻的 A 端、 W 端或 B 端相对于其他两者的极性不作限制。 6： 此规范仅供设计参考。 7： 滑动电阻 （RW）会影响输出阻值的非线性度，阻值随电压和温度的变化非常显著。更多信息请参见第 6.0 节 “电 阻” 。 8： 对于电压低于 2.7V 的情况，请参见第 2.0 节 “典型性能曲线” 。 9： 对 MCP4011 进行了外部连接的与 MCP4012 和 MCP4014 的配置匹配后，才进行测试。
封装类型
MCP4011 SOIC、 MSOP 和 DFN 电位器
VDD 1 VSS 2 A 3 W 4 A W B 8 U/D 7 NC 6 B 5 CS VDD 1 VSS 2 U/D 3 B
MCP4012 SOT-23-6 变阻器
A W 6 A 5 W 4 CS
MCP4013 SOT-23-6 电位器
CS 输入电压
VCS
VSS
—
12.5
V
供电电流
IDD
— — —
45 15 0.3 2.1 5 10 50
— — 1 2.52 6.0 12.0 60.0
µA µA µA kΩ kΩ kΩ kΩ
阻值 （±20%）
RAB
1.68 4.0 8.0 40.0
注
1： 2： 3： 4：
此处的阻值指的是电位器 A 端和 B 端之间的阻值。 INL 和 DNL 是 VA = VDD 且 VB = VSS 时在 VW 测得的。 （-202 器件的 VA = 4V） 。 仅适用于 MCP4011/13，测试条件为：IW = 1.9 mA 且代码 = 00h。 仅适用于 MCP4012/14，测试条件如下： 器件 阻值 2.1 kΩ 5 kΩ 10 kΩ 50 kΩ 不同电压下的电流 5.5V 2.25 mA 1.4 mA 450 µA 90 µA 2.7V 1.1 mA 450 µA 210 µA 40 µA 备注 MCP4012 包含 VWZSE MCP4014 包含 VWFSE
2006 Microchip Technology Inc.
DS21978A_CN 第 3 页
MCP4011/2/3/4
交流 / 直流特性 （续）
电气规范： 除非另外指明，否则所有参数均适用于指定的工作范围。 TA = -40°C 至 +125°C （2.1 kΩ、 5 kΩ、 10 kΩ 和 50 kΩ 器件） 。 典型规范值表示 VDD = 2.7V 至 5.5V、 VSS = 0V 且 TA = +25°C 条件下 的值。 参数 电位器的积分非线性误差 电位器的微分非线性误差 变阻器的积分非线性误差 MCP4011 （注 4 和注 9） MCP4012 和 MCP4014 （注 4） 符号 INL DNL R-INL 最小值 -0.5 -0.5 -0.5 -8.5 -0.5 -5.5 -0.5 -3 -0.5 -1 变阻器的微分非线性误差 MCP4011 （注 4 和注 9） MCP4012 和 MCP4014 （注 4） R-DNL -0.5 -1 -0.5 -1 -0.5 -0.5 -0.5 -0.5 注 1： 2： 3： 4： 典型值 ±0.25 ±0.25 ±0.25 +4.5 见第 2.0 节 ±0.25 +2.5 见第 2.0 节 ±0.25 +1 见第 2.0 节 ±0.25 +0.25 见第 2.0 节 ±0.25 +0.5 见第 2.0 节 ±0.25 +0.25 见第 2.0 节 ±0.25 0 见第 2.0 节 ±0.25 0 见第 2.0 节 最大值 +0.5 +0.5 +0.5 +8.5 +0.5 +5.5 +0.5 +3 +0.5 +1 +0.5 +2 +0.5 +1.25 +0.5 +0.5 +0.5 +0.5 单位 LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb 50 kΩ 10 kΩ 5 kΩ 2.1 kΩ 50 kΩ 10 kΩ 5 kΩ 条件 仅 MCP4011/13 （注 2） 仅 MCP4011/13 （注 2） 2.1 kΩ 5.5V 2.7V （注 7） 1.8V （注 7 和注 8） 5.5V 2.7V （注 7） 1.8V （注 7 和注 8） 5.5V 2.7V （注 7） 1.8V （注 7 和注 8） 5.5V 2.7V （注 7） 1.8V （注 7 和注 8） 5.5V 2.7V （注 7） 1.8V （注 7 和注 8） 5.5V 2.7V （注 7） 1.8V （注 7 和注 8） 5.5V 2.7V （注 7） 1.8V （注 7 和注 8） 5.5V 2.7V （注 7） 1.8V （注 7 和注 8）