8125L-AB3-D-B中文资料
8125规格书 V1.0
产品规格书
一、概述
LG11EA机芯由机芯板﹑按键板﹑遥控接收板和遥控器组成，由于按键板和遥控接收板的规格因机壳不同而不同，在后面的机芯说明中不再进行详细的说明。
该产品采用GenesisFLI8125芯片方案，伴音处理采用AN5832A或者TDA9874A ，音频功率放大器采用TDA1517。
适用于配接26英寸以下TTL电平和LVDS接口的液晶屏，包括AU、SAMUSUNG、HANSTAR、SHARP、BOE、LG、CMO等。
本机芯适应于中东、亚洲及澳洲等地区。
二、主要特性
2.其他功能
●童锁
●时钟
附表2：本机按键功能表（视机壳的不同，按键与对应的电压值可相互交换）
附表3： PC 支持模式表
三、主板外观图 1. 单TV 模块
四、接口定义及电参数
六、结构尺寸
1.PCB厚度+最高零件的高度=20 mm 2．螺丝孔规格: 直径3.3 mm螺丝孔
3. 如结构尺寸和实物有偏差请以实物为准。
GM8125数据手册
4.2 多通道工作模式
当模式控制引脚 MS = 0 时，芯片工作在多通道工作模式下，多通道模式允许 5 个子串口同
时全双工地工作。在该工作模式下，芯片的地址线 STADD2~0 是输入口，由 MCU 控制选择希
表 5 命令字寄存器的默认状态
参数名
默认状态
BR2~0
000（1200bps）
FL
1（11bit 一帧）
注：该芯片不具备上电复位功能，用户在使用前必须通过复位引脚对芯片进行复位。
4.4 芯片的工作方式设置
芯片的工作方式设置包括串口帧格式设置和通讯波特率设置。芯片进行工作方式设置时， MS 为‘0’、STADD2~0 为‘000’时写命令字，MS 为‘1’、STADD2~0 全为 0 时读命令字。 此时芯片的帧格式和母串口工作波特率与上一次进行数据通讯时一致，比如上一次通讯采用
地址线可以不相同，则连接到母串口上的 RXD 和 TXD 可以属于不同的子串口。
注意：通讯时不能将 STADD 置为‘000’。
单通道工作模式各地址线定义如表 2：
表 2 单通道工作模式下地址线定义
STADD2 STADD1 STADD0 SRADD2 SRADD1 SRADD0
定义
001～101
0
旧版 文档页数
当前版本 文档页数
主题（和旧版本相比的主要变化）
１１
１４
增加封装机械尺寸、取消 ＤＩＰ 封装
１４
１４
修改读命令字操作的工作方式
１４
１４
修改输入高电平 ＶＩＨ 的最小值
１４
5B-3B(V8.3) 说明书X
5B-3B 型（V8.3 版）多参数水质分析仪
第4页
共 45 页
连华科技
LIANHUA TECHNOLOGY
因为专一 所以专业
Therefore,because the single-minded professional
第一节
引
言
尊敬的用户：您好！ 感谢您选用我公司研制生产的碧月牌 5B-3B 型（ V8.3 版）多参数水质分析仪。为确保正确使用仪器， 请在使用前仔细阅读本手册。 化学需氧量（ Chemical Oxygen Demand ）简称 COD 。是在一定的条件下，采用一定的强氧化剂处 理水样时，所消耗的 氧化剂量。它是表示水中还原性物质多少的一个指标。水中的还原性物质有各种有 机物、亚硝酸盐、硫化物、亚铁盐等，但主要的是有机物。因此，化学需氧量（ COD ）又往往作为衡量 水中有机物质含量多少的指标。化学需氧量越大，说明水体受有机物的污染越严重。 本仪器采用一种特制试剂，它含有一种复合催化剂，既加速反应，又对氯离子具有抗干扰作用。水样与特制 试剂在消解器中进行快速氧化还原反应，反应后产生三价铬离子，通过分光光度法测定其浓度，从而得出相应 COD 值。 我公司在二十世纪八十年代初，就发明了快速测定污水中化学需氧量 （COD）的方法---催化快速法。并在 国内首家研制出第一代实验室用 COD 速测仪，用以替代长期以来国内外普遍使用的“两小时回流消解、滴定求 值”的测定方法。使其具备快速、低耗、简便、准确、可靠等特点，将测定 COD 需用三到四个小时的传统方法 变成历史。 我们本着：在严格遵循传统法科学性的基础上，对烦琐的实验步骤进行了合理的优化。通过我公司的多年努 力，目前我公司的测定仪系列产品检测数据，不但与传统法可比，而且大大简化了实验过程和时间。 5B-3B 型（V8.3 版）多参数水质分析仪是我公司的第八代产品，完全依据国家新法规《快速消解分光光度 法(HJ/T 399-2007)》设计制造，适用于国内外众多检测标准。专门根据我国水质情况及国家法规要求而开发的一 款能同时测量 COD、氨氮、总磷、浊度等多种参数的高档测定仪，此仪器性能稳定、准确度高、测量范围宽、 显示清晰、测量迅速、使用简单方便，其配套的高档智能消解器使测试过程更加安全可靠。 5B-3B 型（ V8.3 版）多参数水质分析仪为实验室智能型测定仪，精度高，寿命长，更稳定。在测 COD 之 外，还具有测定氨氮、总磷的功能，并可扩展测定水中大多数污染物，同时支持比色皿(池)和比色管两种比色方 式；兼具智能数据分析功能，图表、列表显示数据，分析一目了然；高清晰度彩色液晶显示屏，中文显示界面， 全中文键盘，人性化操作提示，使用更简单。能够广泛的应用于各种行业（工业废水、城市污水、生活污水及江 湖流域地表水）废水的检测。可适合不同用户的多种需求，可在化工、石油、焦化、造纸、冶金、酿造、医药等 工业废水及各种生活污水监测应用。 连华人将在以后的成长中，凭借雄厚的技术力量和优秀的工作团体，回报广大用户的支持。我们本着以卓越 的科技立足行业、以优质的服务赢得客户、以共同的追求汇聚英才、以完善的管理求得飞跃的宗旨，为创造一个 节能减排的和谐社会贡献自己的力量。
三极管标识
1EN 2SC4084 Roh N - npn 20V 2.0GHz TV tuners
1Ep BC847A Phi N SOT23 BC547A
1Fs BC847BT Sie N SC75 BC547B
1Fs BC847BW Sie N SOT323 BC547B
1Ft BC847B Phi N SOT23 BC547B
1Ft BC847BW Phi N SOT323 BC547B
1F- BC847BW Phi N SOT323 BC547B
1Fp BC847B Phi N SOT23 BC547B
1FR BC847BR Phi R SOT23R BC547B
1Fs BC847B Sie N SOT23 BC547B
1Js BC848AW Sie N SOT323 BC548A
1Js BCV61A Sie VQ SOT143 npn current mirror hFe 180
1JZ BC848A Zet N SOT23 BC548A
1Jp BCV61A Phi VQ SOT143 npn current mirror hFe 180
1JR BC848AR Phi R SOT23R BC548A
1Js BC848A Sie N SOT23 BC548A
1LR BC848CR Phi R SOT23R BC548C
1Ls BC848C Sie N SOT23 BC548C
1Ls BC848CW Sie N SOT323 BC548C
1M MMBTA13 Mot N SOT23 MPSA13 darlington
TPS8125 6中文资料
TPS8125 6 SLVSAZ93-W，高效率的升压转换器中MicroSiP™包装检查样品：TPS81256特点∙在4MHz运行效率91％∙宽V∙我≥ 550毫安在V OUT = 5.0V，V IN ≥ 3.3V∙±2％总直流电压精度∙43μA电源电流∙最好的一流的电压和负载瞬态∙V IN ≥至五输出操作∙低纹波轻载PFM模式∙真正的负载断开在关机期间∙热关断及过载保护∙分1毫米简介解决方案∙整体解决方案尺寸<9毫米2∙9针MicroSiP 商标包装应用∙手机，智能手机，平板电脑∙单声道和立体声演艺学院应用∙U SB-OTG功能，HDMI应用∙U SB充电接口（5V）图1。
效率与负载电流描述TPS8125x器件是的完整MicroSiP™的DC / DC升压用于电池供电的便携式应用的电源解决方案。
包中包含的开关稳压器，电感器和输入/输出电容器。
只有一个很小的额外的输出电容要求完成设计。
TPS8125x是基于高频率同步升压型DC / DC转换为电池供电的便携式应用而优化。
该DC / DC转换器工作在规定的4 MHz的开关频率，并进入省电模式在轻负载电流在整个负载电流范围内保持高效率的运作。
PFM模式扩展电池寿命，电源电流降低至43 μ A（典型值）在轻负荷运行。
TPS8125x支持低功耗应用的目的，一个完整的锂离子电池电压范围超过3W的输出功率。
在关机模式下的输入电流小于1μA（典型值），从而最大限度地延长电池寿命。
TPS8125x提供的比9毫米非常小解决方案尺寸，由于外部元件的最低金额。
在紧凑低调（2.6毫米x2.9毫米）（1.0MM）BGA封装标准的表面贴装设备的自动化装配合适的解决方案打包。
图2。
最小解决方案尺寸的应用请注意，一个重要的通知有关可用性，标准保修，并使用在关键应用德州仪器公司的半导体产品和免责条款及其出现在此数据表的结束。
MicroSiP是德州仪器的商标。
除非另有说明，本文件包含版权所有©2012年，德州仪器生产数据信息为出版日期。
螺纹底径
6.561 5.566 11.445 14.950 18.631 20.587 24.117 27.877 30.291 34.939 38.952 44.845 50.788 56.656
10.3 10.42 10.25
12.5 12.73 12.43
12.5 12.62 12.37
12.5 12.52 12.31
14.5 14.83 14.49
14.5 14.62 14.37
16.5 16.83 16.49
16.5 16.62 16.37
19.0 19.04 18.58
18.5 18.62 18.37
2級?紋內徑m305m407m508m61m8125m1015m10125m101m12175m1215m12125v142m1415m162m1615m1825m1815m2025m20153142526384105104103125125125145145165165190185210205管用?紋pf稱呼標准徑d1上限d1下限ab級?紋內徑稱呼鑽頭徑d1上限d1下限m8m8m10m10m10m12m12m12m12m14m14m14m16m16m16m18m18m20m201251151251175151251215121511511517447559329449551121113211441155131013321355151015321555173217551932195511301140115011601320134013601520154015601740176019401960山?節距換算表山?每254mm1008807726460節距mmno080unfno172unfno267unfno356unfno448unfno544unfno640unfno836unfno1032unfno1228unf1428unf51624unf3824unf71620unf1220unf91618unf5818unf3416unf7814unf112unf11812unf11412unf13812unf11212unf125155185210240270290350410460550690850990115012901451752052322652953283600254003175035180396904233管用?紋psab級?紋內徑稱呼鑽頭徑d1上限663286371154915054187732425930471391324502556836d1下限649084951134114846184892397530111387724466556476pf11628pf1828pf1419pf3819pf1214pf5814pf3414pf7814pf111pf11811pf11411pf11211pf13411pf211670870117015219021024528230535239245051057068438848189015395191722112824658284183093135579395924
浙江渤海电器有限公司 A200358 产品说明书
Installation InstructionsNOTE: Read the entire instruction manual before starting the installation.A200358SAFETY CONSIDERATIONSImproper installation, adjustment, alteration, service, maintenance, or use can cause explosion, fire, electrical shock, or other conditions which may cause death, personal injury or property damage. Consult a qualified installer, service agency, or your distributor or branch for information or assistance. The qualified installer or agency must use factory-authorized kits or accessories when modifying this product.Refer to the individual instructions packaged with kits or accessories when installing.Follow all safety codes. Wear safety glasses, protective clothing and work gloves. Have a fire extinguisher available. Read these instructions thoroughly and follow all warnings or cautions included in literature and attached to the unit. Consult local building codes and the current editions of the National Electrical Code (NEC) NFPA 70.In Canada, refer to the current editions of the Canadian Electrical Code CSA C22.1.Recognize safety information. This is the safety-alert symbol . When you see this symbol on the unit and in instruction manuals, be alert to the potential for personal injury.Understand the signal words DANGER, WARNING, and CAUTION.These words are used with the safety-alert symbol. DANGER identifies the most serious hazards which will result in severe personal injury or death. WARNING signifies hazards which could result in personal injury or death. CAUTION is used to identify unsafe practices which may result in minor personal injury or product and property damage.NOTE is used to highlight suggestions which will result in enhanced installation, reliability, or operation.IntroductionThe purpose of this kit is to add a directional-flow air diffuser to the exhaust opening of the OptiClean™ Air Scrubber.Description and UsageThe Accessory Air Diffuser consists of:•pre-assembled diffuser with internal 1ʺ foil-faced insulation •hardware bag with self-tapping screws and instructions.Installation1.Turn off all electrical supply to the unit.2.Remove the assembled diffuser and hardware bag from the carton.3.If the factory supplied duct transition has been installed on the unit’s exhaust opening, remove and store or discard. Only a duct transition or a diffuser should be installed.4.Position the diffuser over the unit's exhaust opening flanges.5.Attach the diffuser to the flanges with the provided hardware.6.Restore power to the unit.KFADG0101SML / KFADG0101LRGAccessory Air Diffuserfor use with OptiClean™ Air Scrubber Model FN1AAFPart Number Use With Scrubber Model Carton Dimensions – in.KFADG0101SML FN1AAF005FN1AAF00617.875 x 11.625 x 20.25KFADG0101LRGFN1AAF01526 x 21 x 13WARNING!ELECTRICAL OPERATION HAZARDFailure to follow this warning result in personal injury or death.Before installing or servicing unit, always turn off all power to unit.There may be more than 1 disconnect switch.WARNING!MOVING PARTS & SHARP EDGES HAZARDFailure to follow this warning could result in personal injury.Wear gloves when handling.Keep hands and face away.Do not place objects on top of the discharge plenum.Avoid rotating blower wheel, which can cause serious injury.Do not allow unsupervised children to play near the unit.CAUTION!CUT HAZARDFailure to follow this caution may result in personal injury.Sheet metal parts may have sharp edges or burrs. Use care and wear appropriate protective clothing, safety glasses and gloves when handling parts.© 2020 Carrier. All rights reserved.A Carrier CompanyEdition Date: 08/20Catalog No: IIK-KFADG-01Replaces: NewKFADG0101SML / KFADG0101LRG: Installation InstructionsManufacturer reserves the right to change, at any time, specifications and designs without notice and without obligations.2A200349Fig. 1 – Dimensions (KFADG0101LRG shown)Table 1 – Dimensions — in. (mm)Model A B C D E Outlet Grille Size KFADG0101SML 16.04 (407)17.44 (443) 3.50 (89)11.21 (285) 3.28 (83)12 x 8 (305 x 203)KFADG0101LRG19.56 (497)22.32 (567)4.50 (114)11.25 (286)1.06 (27)16 x 16 (406 x 406)E。
MX25L512中文资料
MX25L512512K-BIT [x 1] CMOS SERIAL FLASH FEATURESGENERAL• Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3• 524,288 x 1 bit structure• 16 Equal Sectors with 4K byte each- Any Sector can be erased individually• S ingle Power Supply Operation- 2.7 to 3.6 volt for read, erase, and program operations• L atch-up protected to 100mA from -1V to Vcc +1VPERFORMANCE• H igh Performance- Fast access time: 85MHz serial clock (15pF + 1TTL Load) and 66MHz serial clock (30pF + 1TTL Load)- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)- Fast erase time: 60ms(typ.) and 120ms(max.)/sector (4K-byte per sector) ; 1s(typ.) and 2s(max.)/chip(512Kb)• L ow Power Consumption- Low active read current: 12mA(max.) at 85MHz, 8mA(max.) at 66MHz and 4mA(max.) at 33MHz- Low active programming current: 15mA (max.)- Low active erase current: 15mA (max.)- Low standby current: 10uA (max.)- Deep power-down mode 1uA (typical)• M inimum 100,000 erase/program cyclesSOFTWARE FEATURES• Input Data Format- 1-byte Command code• Block Lock protection- The BP0~BP1 status bit defines the size of the area to be software protected against Program and Erase in-structions.• Auto Erase and Auto Program Algorithm- Automatically erases and verifies data at selected sector- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first)• Status Register Feature• Electronic Identification- JEDEC 2-byte Device ID- RES command, 1-byte Device IDHARDWARE FEATURES• SCLK Input- Serial clock input• SI Input- Serial Data Input• SO Output- Serial Data Output• WP# pin- Hardware write protection• HOLD# pin- pause the chip without diselecting the chip• PACKAGE- 8-pin SOP (150mil)- 8-USON (2x3mm)- All Pb-free devices are RoHS CompliantGENERAL DESCRIPTIONMX25L512 is a CMOS 524,288 bit serial Flash memory, which is configured as 65,536 x 8 internally. MX25L512 features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the device is enabled by CS# input.MX25L512 provide sequential read operation on whole chip.After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the spec-ified page or sector/block locations will be executed. Program command is executed on page (256 bytes) basis, and erase command is executes on chip or sector (4K-bytes).To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit.When the device is not in operation and CS# is high, it is put in standby mode and draws less than 10uA DC cur-rent.The MX25L512 utilize MXIC's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles.PIN CONFIGURATIONSSYMBOL DESCRIPTION CS#Chip SelectSI Serial Data Input SO Serial Data Output SCLK Clock InputHOLD#Hold, to pause the device without deselecting the device WP#Write ProtectionVCC + 3.3V Power Supply GNDGroundPIN DESCRIPTION8-PIN SOP (150mil)CS#SO WP#GND VCC HOLD#SCLK SI8-LAND USON (2x3mm)CS#SO WP#GND VCC HOLD#SCLK SIBLOCK DIAGRAMDATA PROTECTIONMX25L512 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state ma-chine in the standby mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.• Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary.• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation:- Power-up- Write Disable (WRDI) command completion- Write Status Register (WRSR) command completion- Page Program (PP) command completion- Sector Erase (SE) command completion- Block Erase (BE) command completion- Chip Erase (CE) command completion• Software Protection Mode (SPM): by using BP0-BP1 bits to set the part of Flash protected from data change.• Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP1 bits and SRWD bit from data change.• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from writing all commands except Release from deep power down mode command (RDP) and Read Electronic Sig-nature command (RES).Table 1. Protected Area SizesStatus bitProtect level 512b BP1 BP00 0 0 (none) None 0 1 1 (All)All 1 0 2 (All)All 113 (All)AllHOLD FEATUREHOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress.The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Se-rial Clock(SCLK) signal is being low( if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low), see Figure 1.The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low.Figure 1. Hold Condition OperationTable 2. COMMAND DEFINITION(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.(2) BE command may erase whole 512Kb chip.(3) It is not recommended to adopt any other code which is not in the above command definition table.COMMAND (byte)WREN (write enable)WRDI (write disable)RDID (readidentification)RDSR (read status register)WRSR (write status register)READ(read data)Fast Read(fast readdata)1st 06 (hex)04 (hex)9F (hex)05 (hex)01 (hex)03 (hex)0B (hex)2nd AD1AD13rd AD2AD24th AD3AD35th xActionsets the (WEL) write enable latch bit resets the (WEL) write enable latchbit outputs manufacturer ID and 2-byte device IDto read out the status register to write new values to the status register n bytes read out until CS# goes highCOMMAND (byte)SE(Sector Erase)BE (2)(Block Erase)CE (Chip Erase)PP(Page Program)DP(Deep Power Down) RDP(Release from Deep Power-down) RES (ReadElectronicID)REMS (ReadElectronicManufacturer& Device ID)1st 20 (hex)52 or D8 (hex)60 or C7 (hex)02 (hex) B9 (hex)AB (hex)AB (hex)90 (hex)2nd AD1AD1AD1x x 3rd AD2AD2AD2x x 4th AD3AD3AD3xADD(1)5th ActionOutput the manufacturer ID and deviceIDDEVICE OPERATION1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-eration.2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby modeuntil next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS# rising edge.4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The difference of SPI mode 0 and mode 3 is shown as Figure 2.Figure 2. SPI Modes SupportedSCLKMSBCPHA shift inshift outSI 01CPOL(Serial mode 0)(Serial mode 3)1SO SCLKMSB5. For the following instructions: RDID, RDSR, READ, FAST_READ, RES and REMS the shifted-in instruction se-quence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP , RDP and DP the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglect-ed and not affect the current operation of Write Status Register, Program, Erase. Table 3. Memory OrganizationNote:CPOL indicates clock polarity of SPI master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which SPI mode is supported.Sector Address Range1500F000h 00FFFFh:::3003000h 003FFFh 2002000h 002FFFh 1001000h 001FFFh 0000000h 000FFFhCOMMAND DESCRIPTION(1) Write Enable (WREN)The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE, BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN in-struction setting the WEL bit.The sequence of issuing WREN instruction is: CS# goes low-> sending WREN instruction code-> CS# goes high. (see Figure 11)(2) Write Disable (WRDI)The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.The sequence of issuing WRDI instruction is: CS# goes low-> sending WRDI instruction code-> CS# goes high. (see Figure 12)The WEL bit is reset by following situations:- Power-up- Write Disable (WRDI) instruction completion- Write Status Register (WRSR) instruction completion- Page Program (PP) instruction completion- Sector Erase (SE) instruction completion- Block Erase (BE) instruction completion- Chip Erase (CE) instruction completion(3) Read Identification (RDID)RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC Manu-facturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID of second-byte ID is as followings: 10(hex) for MX25L512.The sequence of issuing RDID instruction is: CS# goes low→sending RDID instruction code→24-bits ID data out on SO→to end RDID operation can use CS# to high at any time during data out. (see Figure. 13)While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cy-cle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.(4) Read Status Register (RDSR)The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program, erase, or write status register operation is in progress. The sequence of issuing RDSR instruction is: CS# goes low→sending RDSR instruction code→Status Register data out on SO (see Figure. 14)The definition of the status register bits is as below:WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle.WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the de-vice will not accept program/erase/write status register instruction.BP1, BP0 bits. The Block Protect (BP1, BP0) bits, non-volatile bits, indicate the protected area(as defined in table 1) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed)SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protec-tion (WP#) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP# pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP1, BP0) are read only.Note: 1. See the table "Protected Area Sizes".2. The endurance cycles of protect bits are 100,000 cycles; however, the tW time out spec of protect bits isrelaxed as tW = N x 15ms (N is a multiple of 10,000 cycles, ex. N = 2 for 20,000 cycles) after 10,000 cycles on those bits.bit7bit6bit5bit4bit3bit2bit1bit0SRWD (status register write protect)0BP1 (level of protected block)BP0 (level of protected block)WEL (write enable latch)WIP (write inprogress bit)1=status register write disable(note 1)(note 1)1=write enable 0=not write enable 1=write operation 0=not in write operation(5) Write Status Register (WRSR)The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ad-vance. The WRSR instruction can change the value of Block Protect (BP1, BP0) bits to define the protected area of memory (as shown in table 1). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered.The sequence of issuing WRSR instruction is: CS# goes low-> sending WRSR instruction code-> Status Register data on SI-> CS# goes high. (see Figure 15)The WRSR instruction has no effect on b6, b5, b4, b1, b0 of the status register.The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.Table 4. Protection ModesNote:1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 1.As the table above showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM). Software Protected Mode (SPM):- When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can changethe values of SRWD, BP1, BP0. The protected area, which is defined by BP1, BP0, is at software protected mode (SPM).- When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values ofSRWD, BP1, BP0. The protected area, which is defined by BP1, BP0, is at software protected mode (SPM)ModeStatus register condition WP# and SRWD bit status Memory Software protectionmode (SPM)Status register can be written in (WEL bit is set to "1") andthe SRWD, BP0-BP1bits can be changed WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1The protected areacannotbe program or erase.Hardware protectionmode (HPM)The SRWD, BP0-BP1 of status register bits cannot bechangedWP#=0, SRWD bit=1The protected areacannotbe program or erase.Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed.Hardware Protected Mode (HPM):- When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP1, BP0 and hard-ware protected mode by the WP# to against data modification.Note: to exit the hardware protected mode requires WP# driving high once the hardware protected mode is entered. If the WP# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP1, BP0.(6) Read Data Bytes (READ)The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached.The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→ 3-byte address on SI→ data out on SO→ to end READ operation can use CS# to high at any time during data out. (see Figure. 16) (7) Read Data Bytes at Higher Speed (FAST_READ)The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached.The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→ 3-byte address on SI→ 1-dummy byte address on SI→data out on SO→ to end FAST_READ operation can use CS# to high at any time during data out. (see Figure. 17)While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im-pact on the Program/Erase/Write Status Register current cycle.(8) Sector Erase (SE)The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". A Write Enable (WREN) in-struction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see table 3) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.Address bits [Am-A12] (Am is the most significant address) select the sector address.The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI → CS# goes high. (see Figure 19)The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.(9) Block Erase (BE)The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". A Write Enable (WREN) in-struction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (see table 3) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.The sequence of issuing BE instruction is: CS# goes low → sending BE instruction code→ 3-byte address on SI → CS# goes high. (see Figure 20)The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page.(10) Chip Erase (CE)The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc-tion must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the sector (see table 3) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not ex-ecuted.The sequence of issuing CE instruction is: CS# goes low→ sending CE instruction code→ CS# goes high. (see Figure 20)The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is protected by BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP1, BP0 all set to "0".(11) Page Program (PP)The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). If the eight least sig-nificant address bits (A7-A0) are not all 0, all transmitted data which goes beyond the end of the current page are programmed from the start address if the same page (from the address whose 8 least significant address bits (A7-A0) are all 0). The CS# must keep during the whole Page Program cycle. The CS# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the request address of the page without effect on other address of the same page.The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→at least 1-byte on data on SI→ CS# goes high. (see Figure 18)The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by BP1, BP0 bits, the Page Program (PP) instruction will not be executed.(12) Deep Power-down (DP)The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to enter-ing the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not ac-tive and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep power-down mode. It's different from Standby mode.The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high. (see Fig-ure 22)Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic Signature (RES) instruction. (RES instruction to allow the ID been read out). When Power-down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES)The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max), as specified in Table 6. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new deisng, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/ write cycle in progress.The sequence is shown as Figure 23,24.The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeat-edly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction.The RDP instruction is for releasing from Deep Power Down Mode.(14) Read Electronic Manufacturer ID & Device ID (REMS)The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID.The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initi-ated by driving the CS# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for MXIC (C2h) and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in figure 25. The Device ID values are listed in Table of ID Definitions on page 16. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving CS# high.Table of ID Definitions:RDID Command manufacturer ID memory type memory density C22010RES Command electronic ID05REMS Command manufacturer ID device ID C205。
ABB i-bus DALI Gateways DG S 产品介绍说明书
15 16
DALI Gateway DG/S 1.16.1 Basic Characteristics
Map 16 DALI-Groups with 64 DALI-Devices on KNX
Thereby lighting groups with a great number of DALI Devices can be controlled simultaneous
each of the 64 DALI devices Over separate objects the hole quantity of DALI failures and the group or device
number of the faulty DALI device is send via KNX The failure telegrams can be blocked via 1 Bit Communication Object.
Additional Functions
+
Scene, Dynamic, Burn-In, Slave
Programming
++
Per characteristic up to 8 parameters must change
Commissioning
++
No addressing is necessary
0
Addressing of 64 devices and assigned them in 16 light groups
ห้องสมุดไป่ตู้
© ABB Group June 30, 2009 | Slide 3
MRF7S18125BHR3;MRF7S18125BHR5;MRF7S18125BHSR3;MRF7S18125BHSR5;中文规格书,Datasheet资料
RF Power Field Effect TransistorsN-Channel Enhancement-Mode Lateral MOSFETsDesigned for GSM and GSM EDGE base station applications with frequencies from 1800 to 2000 MHz. Can be used in Class AB and Class C for all typical cellular base station modulations.GSM Application•Typical GSM Performance: V DD = 28 Volts, I DQ = 1100 mA, P out =125Watts CW, f = 1930 MHz.Power Gain — 16.5 dB Drain Efficiency — 55%GSM EDGE Application•Typical GSM EDGE Performance: V DD = 28 Volts, I DQ = 1100 mA,P out = 57 Watts Avg., Full Frequency Band (1930-1990 MHz).Power Gain — 17 dB Drain Efficiency — 39%Spectral Regrowth @ 400 kHz Offset = -60 dBc Spectral Regrowth @ 600 kHz Offset = -74 dBc EVM — 2.6% rms•Capable of Handling 5:1 VSWR, @ 28 Vdc, 1960 MHz, 125 Watts CW Output Power•Typical P out @ 1 dB Compression Point ] 140 Watts CW Features•Characterized with Series Equivalent Large-Signal Impedance Parameters •Internally Matched for Ease of Use •Integrated ESD Protection •RoHS Compliant•In Tape and Reel. R3 Suffix = 250 Units per 56 mm, 13 inch Reel .Table 1. Maximum RatingsRatingSymbol Value Unit Drain-Source Voltage V DSS -0.5, +65Vdc Gate-Source Voltage V GS -6.0, +10Vdc Operating VoltageV DD 32, +0Vdc Storage Temperature Range T stg -65 to +150°C Case Operating Temperature T C 150°C Operating Junction Temperature (1,2)T J225°CTable 2. Thermal CharacteristicsCharacteristicSymbol Value (2,3)Unit Thermal Resistance, Junction to Case Case Temperature 81°C, 125 W CW Case Temperature 81°C, 71 W CWR θJC0.310.35°C/W1.Continuous use at maximum temperature will affect MTTF.2.MTTF calculator available at /rf. Select Software & Tools/Development Tools/Calculators to access MTTF calculators by product.3.Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to /rf. Select Documentation/Application Notes - AN1955.Document Number: MRF7S18125BHRev. 0, 11/2008Freescale Semiconductor Technical DataMRF7S18125BHR3 MRF7S18125BHSR3Table 3. ESD Protection CharacteristicsTest MethodologyClass Human Body Model (per JESD22-A114)1B (Minimum)Machine Model (per EIA/JESD22-A115) A (Minimum)Charge Device Model (per JESD22-C101)IV (Minimum)Table 4. Electrical Characteristics (T C = 25°C unless otherwise noted)CharacteristicSymbolMinTypMaxUnitOff CharacteristicsZero Gate Voltage Drain Leakage Current (V DS = 65 Vdc, V GS = 0 Vdc)I DSS ——10μAdc Zero Gate Voltage Drain Leakage Current (V DS = 28 Vdc, V GS = 0 Vdc)I DSS ——1μAdc Gate-Source Leakage Current (V GS = 5 Vdc, V DS = 0 Vdc)I GSS——1μAdcOn CharacteristicsGate Threshold Voltage(V DS = 10 Vdc, I D = 316 μAdc)V GS(th) 1.2 1.9 2.7Vdc Gate Quiescent Voltage(V DS = 28 Vdc, I D = 1100 mAdc)V GS(Q)— 2.7—Vdc Fixture Gate Quiescent Voltage (1)(V DD = 28 Vdc, I D = 1100 mAdc, Measured in Functional Test)V GG(Q)4 5.37Vdc Drain-Source On-Voltage(V GS = 10 Vdc, I D = 3.16 Adc)V DS(on)0.10.20.3VdcDynamic Characteristics (1)Reverse Transfer Capacitance(V DS = 28 Vdc ± 30 mV(rms)ac @ 1 MHz, V GS = 0 Vdc)C rss — 1.15—pF Output Capacitance(V DS = 28 Vdc ± 30 mV(rms)ac @ 1 MHz, V GS = 0 Vdc)C oss —673—pF Input Capacitance(V DS = 28 Vdc, V GS = 0 Vdc ± 30 mV(rms)ac @ 1 MHz)C iss—309—pFFunctional Tests (In Freescale Test Fixture, 50 ohm system) V DD = 28 Vdc, I DQ = 1100 mA, P out = 125 W CW, f = 1930 MHzPower Gain G ps 1516.518dB Drain Efficiency ηD 5155—%Input Return LossIRL—-12-7dB1.V GG = 2 x V GS(Q). Parameter measured on Freescale Test Fixture, due to resistive divider network on the board. Refer to Test Circuit schematic.2.Part internally matched both on input and output.(continued)MRF7S18125BHR3 MRF7S18125BHSR3Table 4. Electrical Characteristics (T C = 25°C unless otherwise noted) (continued)CharacteristicSymbol Min Typ Max Unit Typical Performances (In Freescale Test Fixture, 50 ohm system) V DD = 28 Vdc, I DQ = 1100 mA, 1930-1990 MHz BandwidthP out @ 1 dB Compression PointP1dB —140—W IMD Symmetry @ 125 W PEP , P out where IMD Third Order Intermodulation ` 30 dBc(Delta IMD Third Order Intermodulation between Upper and Lower Sidebands > 2 dB)IMD sym—10—MHzVBW Resonance Point(IMD Third Order Intermodulation Inflection Point)VBW res —35—MHz Gain Flatness in 60 MHz Bandwidth @ P out = 125 W CW G F — 1.02—dB Average Deviation from Linear Phase in 60 MHz Bandwidth @ P out = 125 W CWΦ— 3.3—°Average Group Delay @ P out = 125 W CW, f = 1960 MHz Delay — 2.49—ns Part-to-Part Insertion Phase Variation @ P out = 125 W CW, f = 1960 MHz, Six Sigma Window ΔΦ— 6.7—°Gain Variation over Temperature (-30°C to +85°C)ΔG —0.016—dB/°C Output Power Variation over Temperature (-30°C to +85°C)ΔP1dB—0.01—dBm/°CTypical GSM EDGE Performances (In Freescale GSM EDGE Test Fixture, 50 ohm system) V DD = 28 Vdc, I DQ = 1100 mA, P out = 57 W Avg., 1930-1990 MHz EDGE Modulation Power Gain G ps —17—dB Drain Efficiency ηD —39—%Error Vector MagnitudeEVM — 2.6—% rms Spectral Regrowth at 400 kHz Offset SR1—-60—dBc Spectral Regrowth at 600 kHz OffsetSR2—-74—dBcMRF7S18125BHR3 MRF7S18125BHSR3Figure 1. MRF7S18125BHR3(HSR3) Test Circuit SchematicZ80.200″ x 0.083″ Microstrip Z9 1.045″ x 0.083″ Microstrip Z100.071″ x 0.083″ Microstrip Z110.227″ x 0.083″ Microstrip Z121.280″ x 0.080″ Microstrip Z13, Z140.760″ x 0.080″ MicrostripPCBTaconic TLX-8 RF35, 0.031″, εr = 2.55Z10.227″ x 0.083″ Microstrip Z20.697″ x 0.083″ Microstrip Z30.618″ x 0.083″ Microstrip Z40.568″ x 1.000″ Microstrip Z50.092″ x 1.000″ Microstrip Z60.095″ x 1.000″ Microstrip Z70.565″ x 1.000″ MicrostripTable 5. MRF7S18125BHR3(HSR3) Test Circuit Component Designations and ValuesPartDescriptionPart NumberManufacturer C11 μF, 50 V Chip Capacitor 12065G105AT2A AVX C2, C3, C4, C5 4.7 μF, 50 V Chip CapacitorsGRM55ER71H475KA01L Murata C6220 μF, 63 V Electrolytic Chip Capacitor 2222 136 68221Vishay C7, C8, C9, C10, C11 6.8 pF Chip Capacitors ATC100B6R8BT500XT ATC C12, C131 pF Chip Capacitors ATC100B1R0BT500XT ATC C14, C15, C16, C17, C180.2 pF Chip Capacitors ATC100B0R2BT500XT ATC R1, R210 k Ω, 1/4 W Chip Resistors CRCW12061001FKEA Vishay R310 Ω, 1/4 W Chip ResistorCRCW120610R1FKEAVishayFigure 2. MRF7S18125BHR3(HSR3) Test Circuit Component LayoutMRF7S18125BHR3 MRF7S18125BHSR3MRF7S18125BHR3 MRF7S18125BHSR3TYPICAL CHARACTERISTICSP out , OUTPUT POWER (WATTS) CW100131817151410300Figure 5. Power Gain versus Output PowerG p s , P O W E R G A I N (d B )161000.110TWO−TONE SPACING (MHz)Figure 6. Intermodulation Distortion Productsversus Two-Tone Spacing1MRF7S18125BHR3 MRF7S18125BHSR3TYPICAL CHARACTERISTICS60P in , INPUT POWER (dBm)53515034373552363839Figure 7. Pulsed CW Output Power versusInput PowerP o u t , O U T P U T P O W E R (d B c )54555657404142433001815103020P out , OUTPUT POWER (WATTS) CWFigure 8. Power Gain and Drain Efficiencyversus Output PowerG p s , P O W E R G A I N (d B )17.51710040585916.51615.51514.51413.51325354550556065E V M , E R R O R V E C T O R M A G N I T U D E (% r m s )063142)P out , OUTPUT POWER (WATTS)20Figure 11. Spectral Regrowth at 400 kHzversus Output Power S P E C T R A L R E G R O W T H @ 400 k H z (d B c )4020060801001201401601803350P out , OUTPUT POWER (WATTS)20Figure 12. Spectral Regrowth at 600 kHzversus Output Power402006080100120140160180ηD , D R A I N E F F I C I E N C Y (%)MRF7S18125BHR3 MRF7S18125BHSR3TYPICAL CHARACTERISTICSP out , OUTPUT POWER (WATTS) AVG.500122420160101820604030010Figure 13. EVM and Drain Efficiency versusOutput PowerE V M , E R R O R V E C T O R M A G N I T U D E (% r m s )141918171615f, FREQUENCY (MHz)Figure 14. Power Gain versus FrequencyG p s , P O W E R G A I N (d B )41005025010990T J , JUNCTION TEMPERATURE (°C)Figure 15. MTTF versus Junction TemperatureThis above graph displays calculated MTTF in hours when the device is operated at V DD = 28 Vdc, P out = 125 W CW, and ηD = 55%.MTTF calculator available at /rf. Select Software & Tools/Development Tools/Calculators to access MTTF calculators by product.107106105110130150170190M T T F (H O U R S )2102301081930194019501960197019801990ηD , D R A I N E F F I C I E N C Y (%)MRF7S18125BHR3 MRF7S18125BHSR3GSM TEST SIGNALFigure 16. EDGE Spectrum−10−20−30−40−50−60−70−80−90−100200 kHzSpan 2 MHzCenter 1.96 GHz−110(d B )MRF7S18125BHR3 MRF7S18125BHSR3Z o = 5ΩZ loadZ sourcef = 2040MHzf = 1880MHzf = 1880MHzf = 2040MHzV DD = 28 Vdc, I DQ = 1100 mA, P out = 125 W CWfMHzZ sourceWZ loadW1880 1.31 - j3.61 1.32 - j3.061900 1.25 - j3.061.30 - j2.921920 1.21 - j3.30 1.28 - j2.791940 1.17 - j3.17 1.26 - j2.671960 1.13 - j3.06 1.23 - j2.551980 1.10 - j2.92 1.20 - j2.422000 1.06 - j2.83 1.18 - j2.3020200.99 - j2.75 1.16 - j2.1820400.91 - j2.66 1.12 - j2.07Z source=Test circuit impedance as measured fromgate to ground.Z load=Test circuit impedance as measuredfrom drain to ground.Figure 17. Series Equivalent Source and Load ImpedanceZ source Z loadOutputMatchingNetwork分销商库存信息:FREESCALEMRF7S18125BHR3MRF7S18125BHR5MRF7S18125BHSR3 MRF7S18125BHSR5。
红宝石捉宠金手指
红宝石捉宠金手指001 - Bulbasaur--203妙蛙种子:C3CA837757EA5B41 002 - Ivysaur--204 妙蛙草:1AD3998C333FE45D003 - Venusaur--205妙蛙花:1CCD362C7037B890004 - Charmander--206小火龙:71B047AD7F5EF2F8005 - Charmeleon--207火恐龙:F5DE3E4BDF75AEDA006 - Charizard--208喷火龙:87BB1EEC2F496722007 - Squirtle--209杰尼龟:2CACE52C773FD195008 - Wartortle--210卡咪龟:7A60E261FDA36FBD009 - Blastoise--211水箭龟:9743CF688B567664010 - Caterpie--212绿毛虫:CAC699B9D739BA8F011 - Metapod--213铁甲蛹:C39155A904B27966012 - Butterfree--214巴大蝴:775C1CFCED08BA4A013 - Weedle--215独角虫:90ED4341A4DF0EAE014 - Kakuna--216铁壳昆:9AA76ECF95DF88A9015 - Beedrill--217大针蜂D5EC7D4701E6759 016 - Pidgey--218波波:E6135AACF54D8E99017 - Pidgeotto--219比比鸟:A09E9C6CEC6D33C6 018 - Pidgeot--220比雕:217061C45C2F3D0F019 - Rattata--221小拉达:9A1BF0B7BAB4C487 020 - Raticate--222拉达:5D34335503990EBF021 - Spearow--223烈雀:64F8DDB30537A93E022 - Fearow--224大嘴雀:16BAF1CB402DE332 023 - Ekans--225阿柏蛇:2396E3E4F60524FF 024 - Arbok--226阿柏怪45867836173FA78025 - Pikachu--156皮卡丘25512DB2DF919F1 026 - Raichu--157雷丘:B4BBE2B9A4B9D629027 - Sandshrew--112穿山鼠:3BC81FC2638534B3 028 - Sandslash--113穿山王C23DD11843B4A94 029 - Nidoran Female--227尼多兰(女):30DACAA731988574 030 - Nidorina--228尼多力娜:6030FEB9291DB8BD031 - Nidoqueen--229尼多后:E2DAC8AA1EFED05D032 - Nidoran Male--230尼多兰(男):4C12CE821B96C94A033 - Nidorino--231尼多力诺:3B02F908C4512241034 - Nidoking--232尼多王:7FC2C78DDF50E92F035 - Clefairy--233皮皮:91A609283E6148F8036 - Clefable--234皮可西:2695BE012917841C037 - Vulpix--153六尾:066B8CEF1ADB049B038 - Ninetales--154九尾:72FD1EBD2EC1374E039 - Jigglypuff--138胖丁C495B8B8E825FFB040 - Wigglytuff--139胖可丁:BA6F11C900A6A38C041 - Zubat--063超音蝠:B7BDA0370B8AAC4B042 - Golbat--064大嘴蝠:62A79FA7AB79A9D4043 - Oddish--088走路草:6971CE5B60066E61044 - Gloom--089臭臭花:0E489DB0E657E5A3 045 - Vileplume--090 霸王花:8329A70015ACEE77046 - Paras--235派拉斯:6FC1C4CAB9780A22 047 - Parasect--236派拉斯特:EC937EEF0EBD00B4 048 - Venonat--237毛球336F131E36EB634049 - Venomoth--238末入蛾:8570B5D8DE5F5D88 050 - Diglett--239地鼠:A3806D0122529670 051 - Dugtrio--240三地鼠:3692F35B25A30744 052 - Meowth--241喵喵:8B9D990AE785886D 053 - Persian--242猫老大:AF810D0DAB29A73B 054 - Psyduck--158可达鸭:32BD5ECAD11A6C61 055 - Golduck--159哥达鸭:895F497F4C4E899A 056 - Mankey--243猴怪:B302E801BD75B191 057 - Primeape--244火爆猴:01B318BC36B50D34 058 - Growlithe--245凯蒂狗:165DC3624BA993C6 059 - Arcanine--246风速狗:44750FD1EC36C18D 060 - Poliwag--247蚁香蝌蚪:B38A0B471E3745D1061 - Poliwhirl--248蚁香蛙:93028AC58EF1C9AB 062 - Poliwrath--249快泳蛙:6008CD4745E22D89 063 - Abra--039凯西:8143FDB909A334DF 064 - Kadabra--040勇吉拉:4338BF488DC21DD2 065 - Alakazam--041胡地:6DC3D475172E97A3 066 - Machop--073腕力:FF5D0B15DA6B543D 067 - Machoke--074豪力:1332F1E49F347CE2 068 - Machamp--075怪力:9F96F565E1069F7A 069 - Bellsprout--250喇叭芽:E134AB209D482E14 070 - Weepinbell--251口呆花:42F2672FDE673719 071 - Victreebel--252大食花:153BA656B6C3B2C0 072 - Tentacool--066玛瑙水母:ED74544F99CE7A29 073 - Tentacruel--067毒刺水母:8773652C98449515 074 - Geodude--057小拳石:258EF243BE3E7576 075 - Graveler--058隆隆石:AE99BC9795FB0533076 - Golem--059隆隆岩:964018D1FE7D20E9 077 - Ponyta--253小火马1E9044C912375F2078 - Rapidash--254烈焰马:6DB99ABBECB98E70 079 - Slowpoke--255呆呆兽:BA8AE09722FA6BD0 080 - Slowbro--256呆河马:80FAD58D162BA0F5 081 - Magnemite--082小磁怪:114042DBD805F707 082 - Magneton--083三合一磁怪:B1A86FCD813FDE3E 083 - Farfetch'd--257大葱鸭:FD0D99244ECD7670 084 - Doduo--092嘟嘟:5FEE770DB2E4994C085 - Dodrio--093嘟嘟利:37D6379360D8A71A 086 - Seel--258小海狮:C8D45BFB8A876B90 087 - Dewgong--259白海狮A224FD2CA6FC5B9 088 - Grimer--106臭泥:7ECE775EE657569A089 - Muk--107臭臭泥:8AE2B4F80CD73F2C 090 - Shellder--260大舌贝:CCFAFA1977934FA3091 - Cloyster--261铁甲贝:6C3F5881A796509F 092 - Gastly--262鬼斯:AE4E8C90407CC4A6 093 - Haunter--263鬼斯通:AA5B46B5C44EF1F4 094 - Gengar--264耿鬼:F3CBD8CD84F03D13 095 - Onix--265大岩蛇64E181BAEE4A515 096 - Drowzee--266素利普:7407842FFCCE8901 097 - Hypno--267素利柏:FEAE217EACEAEE13 098 - Krabby--268大钳蟹:F0D5CE20468BD5B3 099 - Kingler--269巨钳蟹:AACE1E9B851738C0 100 - V oltorb--084雷电球:78A98FB639D77DE5 101 - Electrode--085顽皮蛋:1D82764B9E90C7F0 102 - Exeggcute--270蛋蛋:38F03E93B39AED23 103 - Exeggutor--271椰蛋树:034C1E6A92391C0A 104 - Cubone--272可拉可拉:5BAB5D71637CC8F8 105 - Marowak--273嘎拉嘎拉:5CF2F0AEB6D3484F106 - Hitmonlee--274沙瓦郎:A3C6B8F3A4B30F31 107 - Hitmonchan--275艾比郎:3D764F7D1369AEB8 108 - Lickitung--276大舌头:CF9A481E37F97AF5 109 - Koffing--108瓦斯弹:FA13F6041D3642D8 110 - Weezing--109双弹瓦斯:37D4652CEC9B26E0 111 - Rhyhorn--169铁甲犀牛:64B3C7665B990DF0 112 - Rhydon--170铁甲暴龙:2E7A385089A0A7A7 113 - Chansey--277吉利蛋:0E7B81253D1476B2 114 - Tangela--278蔓藤怪:7C471E9A6BF476F1 115 - Kangaskhan--279袋龙:923114C06B382FB5 116 - Horsea--184墨海马:F5A48F4A29490E1B 117 - Seadra--185海刺龙:841558E5DA96307C 118 - Goldeen--050角金鱼:E5EA742ABADB8A81 119 - Seaking--051金鱼王:7072B52AA44A0248 120 - Staryu--143海星星:A240049426CB6D37121 - Starmie--144宝石海星:46E294E3581DEE84122 - Mr.Mime--280吸盘魔偶:26D87E389ECFD129123 - Scyther--281飞天螳螂:4E4BD8E8552A5EE7124 - Jynx--282迷唇姐:58420B0C7E01C023125 - Electabuzz--283电击兽:27D750234C2E3E13126 - Magmar--284鸭嘴火龙:8DA07E1AACAA301C127 - Pinsir--167大甲:B5ADE00E46D994DF128 - Tauros--285肯泰罗:33E6FD7D92B41D6F129 - Magikarp--052鲤鱼王:62BDC317B4F50AEF130 - Gyarados--053暴鲤龙:CFA44518C0BF3ECE131 - Lapras--286乘龙:CEDA6217079F786B132 - Ditto--287百变怪:E720C4D16151A36F 133 - Eevee--288 伊布:3797DB7217DDE415134 - Vaporeon--289水精灵:7D06135F4C69D9C2135 - Jolteon--290雷精灵:98D4B756F907B5A9136 - Flareon--291火精灵:07FF6A8E554AB313 137 - Porygon--2923D龙:AC701F2E7168ADD1 138 - Omanyte--293菊石兽:754CFF13B81E24A8 139 - Omastar--294多刺菊石兽:40461E6C8A7EF2B1 140 - Kabuto--295化石盔:9133792D35EBA0C6 141 - Kabutops--296镰刀盔:015EC9F17A084033 142 - Aerodactyl--297化石翼龙:3EB3920638FFBC0B 143 - Snorlax--298卡比兽:BD858C60BFAFF914 144 - Articuno--299急冻鸟:12E86945D70E3363 145 - Zapdos--300闪电鸟:8549B0C940EC97DC 146 - Moltres--301火焰鸟:F6FB968EE75A8455 147 - Dratini--302迷你龙:ACC9F13AFE3BA813 148 - Dragonair--303哈克龙:B7E1B04A4920F88D 149 - Dragonite--304快龙:2ED04229D88ED840150 - Mewtwo--305超梦3C45A21B0BA8A60151 - Mew--306梦幻:828A2C1A8905A8EF152 - Chikorita--30773E52E8FA1C46499153 - Bayleef--308EDF2D5E5B76DA1D7154 - Meganium--30910D938FC0B2F8D8C155 - Cyndaquil--3102ED4EA73AA649062156 - Quilava--3114B0EBF88B6B76AA2157 - Typhlosion--312A1B00540E906922E158 - Totodile--31394AD9E921C6E1F44159 - Croconaw--3144CAA0EB77509AFB0160 - Feraligatr--3150C986569021B50C8161 - Sentret--31698A32E64DFB69694162 - Furret--3179E5C11A9740CCD09163 - Hoothoot--318A0DEE79564F06453164 - Noctowl--3195A1BFDE82A258BC6165 - Ledyba--320FB3B87E502108A12166 - Ledian--321 457968195085941C167 - Spinarak--322 BE79DF4A2783C091 168 - Ariados--323D0441CF94AA02CAF169 - Crobat--065F5C20C6F77A97B4D170 - Chinchou--181 63D9716B97D57559 171 - Lanturn--182DB215D2E6DED406A172 - Pichu--1556EC81AEC83CB7326173 - Cleffa--324A16456D4AC3C6CF2174 - Igglybuff--137A7DF693E20F30F2C175 - Togepi--325B4A9C52CB83CA9FC176 - Togetic--326FC423FF6E401C204 177 - Natu--16241DB1EECC5EACADF178 - Xatu--1633E29AE7217AA3A9D179 - Mareep--327AA94F996A4792DB6180 - Flaaffy--328D8F0E3CD39598C90181 - Ampharos--329 94457814358BE661 182 - Bellossom--0910DC6061BF234315D183 - Marill--055E7CA144476E402CF184 - Azumarill--056 51888D9ECC903039 185 - Sudowoodo--330 C35C81FED930850E 186 - Politoed--33150F446D178E9EFF0187 - Hoppip--332479DB63414054037188 - Skiploom--33396BDB240AE6E1B77189 - Jumpluff--3345B3740306117B1B1190 - Aipom--33539FBA7686ACC4BE6191 - Sunkern--336104AE92FB2E6AB0C192 - Sunflora--337 DA91935C6BE9936D 193 - Yanma--3387F8F6F38EC73AE87194 - Wooper--339 7646251E5C90346E 195 - Quagsire--340 174C6CDA3D16CEC8 196 - Espeon--3418DCC886174EC14DB197 - Umbreon--3421B6FEA1D0131DA22198 - Murkrow--343 432152446DF6167C 199 - Slowking--344 AC1ED799DF038302 200 - Misdreavus--345 E6A02BA8D8FC396F 201 - Unown--3465D419EAA8B77A1A0202 - Wobbuffet--161 DDFD15679FA4D945 203 - Girafarig--164 7674A7133C5C399E204 - Pineco--3476FC56532DDB546CB205 - Foretress--348 342443A99344D1DF 206 - Dunsparce--349 F4FE26141D5EA0CA 207 - Gligar--350BF1FAD36FA987A92208 - Steelix--3512FBBF2D4C2064262209 - Snubbull--352 9893420778E664F2 210 - Granbull--353 25DC599A5C9E73DC 211 - Qwilfish--3549BF018C0B783949B212 - Scizor--355655C476D0B65AF82213 - Shuckle--3561EFB49C64345EFD6214 - Heracross--168 0796EFF37D78514A 215 - Sneasel--3578D258FCC8BDE140D216 - Teddiursa--358 71605510BEE90A56 217 - Ursaring--359 33F21A1CF9C2ECAB 218 - Slugma--10398C53A6E963B37FB219 - Magcargo--104 592C085E061B0DFF 220 - Swinub--360 444FF32DA2E13172 221 - Piloswine--361E96D3A5784DFA29E222 - Corsola--180 BAA1EF14741F03FF 223 - Remoraid--362 EA828AD97C7C35A8 224 - Octillery--36320EBDE3B2A18279B225 - Delibird--3649B9AF9EE3C13086D226 - Mantine--365C3CBE2DF8DACCC87227 - Skarmory--115 FA5C1D22ED450587 228 - Houndour--366 40E2F486B31FC4B2 229 - Houndoom--367 C6BA4E54F5249AD4 230 - Kingdra--18646F10C11E8369C21231 - Phanpy--1653A52CE7B44ED6E93232 - Donphan--16630BD8A44E4C9FD44233 - Porygon2--3686D7844A1ED1E9291234 - Stantler--369B559C94172BBABF8235 - Smeargle--370A3158BFCFE05F0F1236 - Tyrogue--37153014C51B3C02C55237 - Hitmontop--3727E17EF9478F8B4F7238 - Smoochum--373谜唇妹:4547BC2AB09A2DC9239 - Elekid--374电力小子7123038EE09CCCD240 - Magby--375小火鸭:C31B4C3BC63F4042241 - Miltank--376巨奶牛:9673E17023F03D3B 242 - Blissey--377吉利蛋：27AABB8166FD35E2 243 - Raikou--378雷皇:A491EA9EB14255F1 244 - Entei--379炎帝:347CF0C18404DBBB 245 - Suicune--380水君:2A517D12459538E4 246 - Larvitar--381幼甲兽:7D99A1A4C5520E2E 247 - Pupitar--382小甲兽:FC526DBE375ABF97 248 - Tyranitar--383巨大甲兽:657E1C139590464C 249 - Lugia--384洛奇亚:48983DA47B562EA1 250 - Ho-oh--385凤王:7B268F6D20DB6AA8 251 - Celebi--386雪拉比:8B55974C78D847FC。
2022成才之路·人教B版数学·选修2-2练习：第2章知能基础测试
其次章知能基础测试时间120分钟，满分150分．一、选择题(本大题共12个小题，每小题5分，共60分．在每小题给出的四个选项中，只有一项是符合题目要求的．)1．k 棱柱有f (k )个对角面，则k ＋1棱柱的对角面个数f (k ＋1)为导学号05300577( )A ．f (k )＋k －1B ．f (k )＋k ＋1C ．f (k )＋kD ．f (k )＋k －2答案] A解析] 增加的一条侧棱与其不相邻的k －2条侧棱形成k －2个对角面，而过与其相邻的两条侧棱的截面原来为侧面，现在也成了一个对角面，故共增加了k －1个对角面，∴f (k ＋1)＝f (k )＋k －1.故选A.2．已知a >0，b >0，a 、b 的等差中项为12，且α＝a ＋1a ，β＝b ＋1b，则α＋β的最小值为导学号05300578( )A ．3B ．4C ．5D ．6答案] C解析] 由已知得a ＋b ＝1，∴α＋β＝a ＋1a ＋b ＋1b ＝1＋a ＋b a ＋a ＋b b ＝3＋b a ＋ab≥3＋2＝5.故选C.3．已知f (x )＝x 3＋x (x ∈R )，a 、b 、c ∈R ，且a ＋b >0，b ＋c >0，c ＋a >0，则f (a )＋f (b )＋f (c )的符号为导学号05300579( )A ．正B ．负C ．等于0D ．无法确定答案] A解析] ∵f ′(x )＝3x 2＋1>0， ∴f (x )在R 上是增函数．又a ＋b >0，∴a >－b .∴f (a )>f (－b )． 又f (x )＝x 3＋x 是奇函数， ∴f (a )>－f (b )，即f (a )＋f (b )>0. 同理：f (b )＋f (c )>0，f (c )＋f (a )>0，∴f (a )＋f (b )＋f (c )>0，故选A.4．下列代数式(其中k ∈N *)能被9整除的是导学号05300580( ) A ．6＋6·7k B ．2＋7k －1 C ．2(2＋7k ＋1) D ．3(2＋7k )答案] D解析] 特值法：当k ＝1时，明显只有3(2＋7k )能被9整除，故选D. 证明如下：当k ＝1时，已验证结论成立，假设当k ＝n (n ∈N *)时，命题成立，即3(2＋7n )能被9整除，那么3(2＋7n ＋1)＝21(2＋7n )－36. ∵3(2＋7n )能被9整除，36能被9整除， ∴21(2＋7n )－36能被9整除， 这就是说，k ＝n ＋1时命题也成立．故命题对任何k ∈N *都成立．5．已知1＋2×3＋3×32＋4×33＋…＋n ×3n －1＝3n (na －b )＋c 对一切n ∈N *都成立，那么a ，b ，c 的值为导学号05300581( )A ．a ＝12，b ＝c ＝14B ．a ＝b ＝c ＝14C ．a ＝0，b ＝c ＝14D ．不存在这样的a 、b 、c答案] A解析] 令n ＝1，得1＝3(a －b )＋c ，令n ＝2，得1＋2×3＝9(2a －b )＋c ， 令n ＝3，得1＋2×3＋3×32＝27(3a －b )＋c . 即⎩⎪⎨⎪⎧3a －3b ＋c ＝118a －9b ＋c ＝781a －27b ＋c ＝34，∴a ＝12，b ＝c ＝14.故选A.6．观看下列各式：a ＋b ＝1，a 2＋b 2＝3，a 3＋b 3＝4，a 4＋b 4＝7，a 5＋b 5＝11，…，则a 10＋b 10＝导学号05300582( )A ．28B ．76C ．123D ．199答案] C解析] 法一：由a ＋b ＝1，a 2＋b 2＝3得ab ＝－1，代入后三个等式中符合，则a 10＋b 10＝(a 5＋b 5)2－2a 5b 5＝123，故选C.法二：令a n ＝a n ＋b n ，则a 1＝1，a 2＝3，a 3＝4，a 4＝7，…得a n ＋2＝a n ＋a n ＋1，从而a 6＝18，a 7＝29，a 8＝47，a 9＝76，a 10＝123，故选C.7．观看下列各式：55＝3125,56＝15625,57＝78125，…，则52021的末四位数字为导学号05300583( )A ．3125B ．5625C ．0625D ．8125答案] D解析] ∵55＝3125,56＝15625,57＝78125， 58末四位数字为0625,59末四位数字为3125， 510末四位数字为5625,511末四位数字为8125， 512末四位数字为0625，…，由上可得末四位数字周期为4，呈规律性交替消灭， ∴52021＝54×502＋7末四位数字为8125.8.已知函数f (x )满足f (0)＝0，导函数f ′(x )的图象如图所示，则f (x )的图象与x 轴围成的封闭图形的面积为导学号05300584( )A.13 B ．43C ．2D ．83答案] B解析] 由f ′(x )的图象知，f ′(x )＝2x ＋2，设f (x )＝x 2＋2x ＋c ，由f (0)＝0知，c ＝0，∴f (x )＝x 2＋2x ，由x 2＋2x ＝0得x ＝0或－2.故所求面积S ＝－⎠⎛－2(x 2＋2x )dx ＝⎪⎪－(13x 3＋x 2)0－2＝43. 9．平面上有n 个圆，其中每两个都相交于两点，每三个都无公共点，它们将平面分成f (n )块区域，有f (1)＝2，f (2)＝4，f (3)＝8，则f (n )的表达式为导学号05300585( )A ．2nB ．n 2－n ＋2C ．2n －(n －1)(n －2)(n －3)D ．n 3－5n 2＋10n －4 答案] B解析] 四个选项的前三项是相同的，但第四项f (4)＝14(如图)就只有B 符合，从而否定A ，C ，D ，选B ，一般地，可用数学归纳法证明f (n )＝n 2－n ＋2.故选B.10．已知等比数列a n ＝13n －1，其前n 项和为S n ＝∑k ＝1na k ，则S k ＋1与S k 的递推关系不满足导学号05300586( )A ．S k ＋1＝S k ＋13k ＋1B ．S k ＋1＝1＋13S kC ．S k ＋1＝S k ＋a k ＋1D ．S k ＋1＝3S k －3＋a k ＋a k ＋1答案] A解析] S k ＋1＝a 1＋a 2＋…＋a k ＋a k ＋1 ＝S k ＋a k ＋1.C 真． S k ＋1＝1＋13＋…＋13k＝1＋13×⎝ ⎛⎭⎪⎫1＋13＋…＋13k －1＝1＋13S k .B 真． 3S k ＝3×⎝ ⎛⎭⎪⎫1＋13＋…＋13k －1＝3＋1＋13＋…＋13k －2＝3＋⎝ ⎛⎭⎪⎫1＋13＋…＋13k －2＋13k －1＋13k －a k －a k ＋1＝3＋S k ＋1－a k －a k ＋1.D 真．事实上，S k ＋1＝S k ＋a k ＋1＝S k ＋13k .A 不真．故选A.11．下列结论正确的是导学号05300587( ) A ．当x >0且x ≠1时，lg x ＋1lg x≥2 B ．当x >0时，x ＋1x≥2 C ．当x ≥2时，x ＋1x 的最小值为2D ．当0<x ≤2时，x －1x 无最大值答案] B解析] A 错在lg x 的正负不清；C 错在等号成立的条件不存在；依据函数f (x )＝x －1x 的单调性，当x ＝2时，f (2)max ＝32，故D 错．故选B.12．如图(1)，在△ABC 中，AB ⊥AC 于点A ，AD ⊥BC 于点D ，则有AB 2＝BD ·BC ，类似地有命题：如图(2)，在三棱锥A －BCD 中，AD ⊥面ABC ，若A 在△BCD 内的射影为O ，则S 2△ABC ＝S △BCO ·S △BCD ，那么上述命题导学号05300588( )A ．是真命题B ．增加条件“AB ⊥AC ”后才是真命题 C ．是假命题D ．增加条件“三棱锥A －BCD 是正三棱锥”后才是真命题 答案] A解析] 由已知垂直关系，不妨进行如下类比：将题图(2)中的△ABC ，△BCO ，△BDC 分别与题图(1)中的AB ，BD ，BC 进行类比即可．严格推理如下：连结DO 并延长交BC 于点E ，连结AE ，则DE ⊥BC ，AE ⊥BC .由于AD ⊥面ABC ，所以AD ⊥AE .又由于AO ⊥DE ，所以AE 2＝EO ·ED ，所以S 2△ABC＝(12BC ·EA )2＝(12BC ·EO )·(12BC ·ED )＝S △BCO ·S △BCD .故选A.二、填空题(本大题共4个小题，每小题4分，共16分．将正确答案填在题中横线上)13．(2022·全国卷Ⅱ理，15)有三张卡片，分别写有1和2,1和3,2和3. 甲，乙，丙三人各取走一张卡片，甲看了乙的卡片后说：“我与乙的卡片上相同的数字不是2”，乙看了丙的卡片后说：“我与丙的卡片上相同的数字不是1”，丙说：“我的卡片上的数字之和不是5”，则甲的卡片上的数字是________.导学号 05300589答案] 1和3解析] 为便利说明，不妨将分别写有1和2,1和3,2和3的卡片记为A ，B ，C .从丙动身，由于丙的卡片上的数字之和不是5，则丙只可能是卡片A 或B ，无论是哪一张，均含有数字1，再由乙与丙的卡片上相同的数字不是1可知，乙所拿的卡片必定是C ，最终由甲与乙的卡片上相同的数字不是2，知甲所拿的卡片为B ，此时丙所拿的卡片为A .14．在平面上，我们用始终线去截正方形的一个角，那么截下的一个直角三角形，按如图所标边长，由勾股定理有c 2＝a 2＋b 2.设想正方形换成正方体，把截线换成如图截面，这时从正方体上截下三条侧棱两两垂直的三棱锥O －LMN ，假如用S 1、S 2、S 3表示三个侧面面积，S 表示截面面积，那么类比得到的结论是________．导学号05300590答案] S 2＝S 21＋S 22＋S 23解析] 类比如下：正方形↔正方体；截下直角三角形↔截下三侧面两两垂直的三棱锥；直角三角形斜边平方↔三棱锥底面面积的平方；直角三角形两直角边平方和↔三棱锥三个侧面面积的平方和，结论S 2＝S 21＋S 22＋S 23.证明如下：如图，作OE ⊥平面LMN ，垂足为E ，连接LE 并延长交MN 于F ， ∵LO ⊥OM ，LO ⊥ON ， ∴LO ⊥平面MON ， ∵MN ⊂平面MON ，∴LO ⊥MN ，∵OE ⊥MN ，∴MN ⊥平面OFL ，∴S △OMN ＝12MN ·OF ，S △MNE ＝12MN ·FE ，S △MNL ＝12MN ·LF ，OF 2＝FE ·FL ，∴S 2△OMN＝(12MN ·OF )2＝(12MN ·FE )·(12MN ·FL )＝S △MNE ·S △MNL ，同理S 2△OML ＝S △MLE ·S △MNL ，S 2△ONL ＝S △NLE ·S △MNL ，∴S 2△OMN ＋S 2△OML＋S 2△ONL ＝(S △MNE ＋S △MLE ＋S △NLE )·S △MNL ＝S 2△MNL ，即S 21＋S 22＋S 23＝S 2.15．对于大于1的自然数m 的n 次幂可用奇数进行如图所示的“分裂”，仿此，记53的“分裂”中的最小数为a ，而52的“分裂”中最大的数是b ，则a ＋b ＝________.导学号05300591答案] 30解析] 类比规律∴a ＝21，b ＝9故a ＋b ＝30.16．(2022·四川文，15)在平面直角坐标系中，当P (x ，y )不是原点时，定义P 的“伴随点”为P ′(yx 2＋y 2，－xx 2＋y 2)；当P 是原点时，定义P 的“伴随点”为它自身．现有下列命题：导学号 05300592 ①若点A 的“伴随点”是点A ′，则点A ′的“伴随点”是点A ； ②单位圆上的点的“伴随点”仍在单位圆上；③若两点关于x 轴对称，则它们的“伴随点”关于y 轴对称； ④若三点在同一条直线上，则它们的“伴随点”肯定共线． 其中的真命题是________(写出全部真命题的序号)． 答案] ②③解析] 对于①，设A (0,3)，则A 的“伴随点”为A ′(13，0)，但是A ′(13，0)的“伴随点”为(0，－3)，与A 不同，所以①错误；对于②，设单位圆C ：x 2＋y 2＝1上的点P (x ，y )，点P 的“伴随点”为P ′(x ′，y ′)，则有⎩⎨⎧x ′＝yx 2＋y 2y ′＝－xx 2＋y2，所以x ′2＋y ′2＝y 2(x 2＋y 2)2＋(－x )2(x 2＋y 2)2＝1x 2＋y2＝1，所以②正确；对于③，设P (x ，y )的“伴随点”为P ′(yx 2＋y 2，－x x 2＋y 2)，P 1(x ，－y )的“伴随点”为P ′1(－y x 2＋y 2，－xx 2＋y 2)，易知P ′(yx 2＋y 2，－xx 2＋y 2)与P ′1(－y x 2＋y 2，－xx 2＋y 2)关于y 轴对称，所以③正确；对于④，设原直线的解析式为Ax ＋By ＋C ＝0，其中A ，B不同时为0，且P (x 0，y 0)为该直线上一点，P (x 0，y 0)的“伴随点”为P ′(x ′，y ′)，其中P ，P ′都不是原点，且⎩⎨⎧x ′＝y 0x 20＋y 2y ′＝－x 0x 20＋y2，则x 0＝－(x 20＋y 20)y ′，y 0＝(x 20＋y 20)x ′，将P (x 0，y 0)代入原直线方程，得－A (x 20＋y 20)y ′＋B (x 20＋y 20)x ′＋C ＝0，则－Ay ′＋Bx ′＋C x 20＋y 20＝0，由于x 20＋y 20的值不确定，所以“伴随点”不肯定共线，所以④错误．三、解答题(本大题共6个小题，共74分．解答应写出文字说明、证明过程或演算步骤)17．(本题满分12分)已知a 、b 、c 是互不相等的非零实数．用反证法证明三个方程ax 2＋2bx ＋c ＝0，bx 2＋2cx ＋a ＝0，cx 2＋2ax ＋b ＝0至少有一个方程有两个相异实根．导学号05300593证明] 假设三个方程中都没有两个相异实根， 则Δ1＝4b 2－4ac ≤0，Δ2＝4c 2－4ab ≤0， Δ3＝4a 2－4bc ≤0.相加有a 2－2ab ＋b 2＋b 2－2bc ＋c 2＋c 2－2ac ＋a 2≤0， 即(a －b )2＋(b －c )2＋(c －a )2≤0.由题意a 、b 、c 互不相等，∴①式不能成立．∴假设不成立，即三个方程中至少有一个方程有两个相异实根．18．(本题满分12分)在圆x 2＋y 2＝r 2(r >0)中，AB 为直径，C 为圆上异于A 、B 的任意一点，则有k AC ·k BC＝－1.你能用类比的方法得出椭圆x 2a 2＋y 2b2＝1(a >b >0)中有什么样的结论？并加以证明．导学号05300594解析] 类比得到的结论是：在椭圆x 2a 2＋y 2b 2＝1(a >b >0)中，A 、B 分别是椭圆长轴的左右端点，点C (x ，y )是椭圆上不同于A 、B 的任意一点，则k AC ·k BC ＝－b 2a2证明如下：设A (x 0，y 0)为椭圆上的任意一点，则A 关于中心的对称点B 的坐标为B (－x 0，－y 0)，点P (x ，y )为椭圆上异于A ，B 两点的任意一点，则k AP ·k BP ＝y －y 0x －x 0·y ＋y 0x ＋x 0＝y 2－y 20x 2－x 20.由于A 、B 、P 三点在椭圆上，∴⎩⎨⎧x 2a 2＋y 2b 2＝1，x 20a 2＋y20b 2＝1.两式相减得，x 2－x 20a 2＋y 2－y 20b 2＝0，∴y 2－y 20x 2－x 20＝－b 2a 2，即k AP ·k BP ＝－b 2a 2.故在椭圆x 2a 2＋y 2b 2＝1(a >b >0)中，长轴两个端点为A 、B 、P 为异于A 、B 的椭圆上的任意一点，则有k AB ·k BP＝－b 2a2.19．(本题满分12分)已知a 、b ∈R ，求证：|a |＋|b |1＋|a |＋|b |≥证明] 设f (x )＝x1＋x，x ∈0，＋∞)．设x 1、x 2是0，＋∞)上的任意两个实数，且0≤x 1<x 2，则f (x 2)－f (x 1)＝x 21＋x 2－x 11＋x 1＝x 2－x 1(1＋x 1)(1＋x 2). 由于x 2>x 1≥0，所以f (x 2)>f (x 1)．所以f (x )＝x1＋x 在0，＋∞)上是增函数．(大前提)由|a |＋|b |≥|a ＋b |≥0(小前提) 知f (|a |＋|b |)≥f (|a ＋b |) 即|a |＋|b |1＋|a |＋|b |≥|a ＋b |1＋|a ＋b |成立．20．(本题满分12分)设a ，b ∈R ＋，且a≠b ，求证：a 3＋b 3>a 2b ＋ab 2证明] 证法1：用分析法． 要证a 3＋b 3>a 2b ＋ab 2成立，只需证(a ＋b )(a 2－ab ＋b 2)>ab (a ＋b )成立．又因a ＋b >0， 只需证a 2－ab ＋b 2>ab 成立．只需证a 2－2ab ＋b 2>0成立． 即需证(a －b )2>0成立．而依题设a ≠b ，则(a －b )2>0明显成立． 由此命题得证． 证法2：用综合法． a ≠b ⇒a －b ≠0⇒(a －b )2>0 ⇒a 2－2ab ＋b 2>0⇒a 2－ab ＋b 2>ab .留意到a ，b ∈R ＋，a ＋b >0，由上式即得(a ＋b )(a 2－ab ＋b 2)>ab (a ＋b )． ∴a 3＋b 3>a 2b ＋ab 2.21．(本题满分12分)(2021·甘肃省会宁一中高二期中)用数学归纳法证明等式：12－22＋32－42＋…＋(2n －1)2－(2n )2＝－n (2n ＋1)(n ∈N *)证明] (1)当n ＝1时，左边＝12－22＝－3，右边＝－1×(2＋1)＝－3， 故左边＝右边，∴当n ＝1时，等式成立； (2)假设n ＝k 时，等式成立，即12－22＋32－…＋(2k －1)2－(2k )2＝－k (2k ＋1)成立， 那么n ＝k ＋1时，左边＝12－22＋32－…＋(2k ＋1)2－(2k ＋2)2 ＝－k (2k ＋1)＋(2k ＋1)2－4(k ＋1)2 ＝(2k ＋1)(2k ＋1)－k ]－4(k ＋1)2 ＝(k ＋1)(－2k －3) ＝－(k ＋1)2(k ＋1)＋1]，综合(1)、(2)可知等式12－22＋32－42＋…＋(2k －1)2－(2n )2＝－n (2n ＋1)对于任意正整数都成立．22．(本题满分14分)(2021·湖北理，22)已知数列{a n }的各项均为正数，b n ＝n ⎝⎛⎭⎫1＋1n n a n (n ∈N ＋)，e 为自然(1)求函数f (x )＝1＋x －e x 的单调区间，并比较⎝⎛⎭⎫1＋1n n 与e 的大小； (2)计算b 1a 1，b 1b 2a 1a 2，b 1b 2b 3a 1a 2a 3，由此推想计算b 1b 2…b n a 1a 2…a n的公式，并给出证明；(3)令c n ＝(a 1a 2…a n )1n ，数列{a n }，{c n }的前n 项和分别记为S n ，T n ，证明：T n ＜e S n .解析] (1)f (x )的定义域为(－∞，＋∞)，f ′(x )＝1－e x.当f ′(x )＞0，即x ＜0时，f (x )单调递增； 当f ′(x )＜0，即x ＞0时，f (x )单调递减．故f (x )的单调递增区间为(－∞，0)，单调递减区间为(0，＋∞)．当x ＞0时，f (x )＜f (0)＝0，即1＋x ＜e x . 令x ＝1n ，得1＋1n ＜e 1n ，即(1＋1n )n ＜e.①(2)b 1a 1＝1·(1＋11)1＝1＋1＝2； b 1b 2a 1a 2＝b 1a 1·b 2a 2＝2·2(1＋12)2 ＝(2＋1)2＝32； b 1b 2b 3a 1a 2a 3＝b 1b 2a 1a 2·b 3a 3＝32·3(1＋13)3＝(3＋1)3＝43.由此推想：b 1b 2…b na 1a 2…a n ＝(n ＋1)n .②下面用数学归纳法证明②.(1)当n ＝1时，左边＝右边＝2，②成立． (2)假设当n ＝k 时，②成立，即 b 1b 2…b ka 1a 2…a k＝(k ＋1)k .当n ＝k ＋1时，b k ＋1＝(k ＋1)(1＋1k ＋1)k ＋1a k ＋1，由归纳假设可得b 1b 2…b k b k ＋1a 1a 2…a k a k ＋1＝b 1b 2…b k a 1a 2…a k ·b k ＋1a k ＋1＝(k ＋1)k (k ＋1)(1＋1k ＋1)k ＋1＝(k ＋2)k ＋1. 所以当n ＝k ＋1时，②也成立．依据(1)(2)，可知②对一切正整数n 都成立．(3)由c n 的定义，②，算术－几何平均不等式， b n 的定义及①得 T n ＝c 1＋c 2＋c 3＋…＋c n＝(a 1)11＋(a 1a 2)12＋(a 1a 2a 3)13＋…＋(a 1a 2…a n )1n＝(b 1)112＋(b 1b 2)123＋(b 1b 2b 3)134＋…(b 1b 2…b n )1n n ＋1≤b 11×2＋b 1＋b 22×3＋b 1＋b 2＋b 33×4＋…＋b 1＋b 2＋…＋b n n (n ＋1)＝b 111×2＋12×3＋…＋1n (n ＋1)]＋b 212×3＋13×4＋…＋1n (n ＋1)]＋…＋b n ·1n (n ＋1)＝b 1(1－1n ＋1)＋b 2(12－1n ＋1)＋…＋b n (1n －1n ＋1)＜b 11＋b 22＋…＋b nn＝(1＋11)1a 1＋(1＋12)2a 2＋…＋(1＋1n )n a n＜e a 1＋e a 2＋…＋e a n ＝e S n . 即T n ＜e S n .。
贴片B系列三极管参数
NQ I NQ N N P I N N N N N N P I E C P I N I N N N N P I N N N N P P I N N N N I P N N N N P I DL
SOT143 SOD323 SOT343 SOT23 SOT23 SOT89 SOD323 SOT23 SOT23 SOT23 SOT23 SOT23 SOT23 SOT89 SOD323 SOT23 SOT23 SOT89 SOD323 SOT23 SOD323 SOT23 SOT23 SOT23 SOT23 SOT89 SOD323 SOT23 SOT23 SOT23 SOT23 SOT223 SOT89 SOD323 SOT23 SOT23 SOT23 SOT23 SOD323 SOT223 SOT23 SOT23 SOT23 SOT23 SOT89 SOD323 SOT363
Dual pin shunt switch 5.1V 0.3W zener Dual pin shunt switch BCY78-ix BCY78-ix npn hfe100 5.6V 0.3W zener BCY78-ix BCY78-ix BCY78-x BCY78-x BCY78-x BCY78-x npn hfe160 comp BCX51-16 6.2V 0.3W zener 40V 0.4A schottky diode schottky sw diode npn AF 60V comp BCX52 6.8V 0.3W zener low noise BCW61 7.5V 0.3W zener BCY79-vii BCY79-vii BCY79-vii BCY79-vii npn hfe 100 8.2V 0.3W zener BCY79-viii BCY79-viii BCY79-viii BCY79-viii npn amp 80V 150mA npn AF 80V 9.1V 0.3W zener i BCY79-ix BCY79-ix BCY79-ix BCY79-ix 10V 0.3W zener npn amp 80V 150mA BCY79 BCY79 BCY79 BCY79 npn hfe 100 11V 0.3W zener 2x schottky detector diodes
LSI SAS 9311-8i PCI Express 12Gb s SAS HBA 用户指南说明书
LSI® SAS 9311-8i PCI Express® to 12Gb/s Serial Attached SCSI (SAS) Host Bus AdapterUser GuideVersion 1.3March 2015DB15-000903-03LSI SAS 9311-8i PCI Express to 12Gb/s SAS Host Bus Adapter User GuideMarch 2015For a comprehensive list of changes to this document, see the Revision History.Corporate Headquarters Email WebsiteSan Jose, CA*******************************Avago, Avago Technologies, the A logo, LSI, Storage by LSI, and Fusion-MPT are trademarks of Avago Technologies inthe United States and other countries. All other brand and product names may be trademarks of their respectivecompanies.Data subject to change. Copyright © 2013–2015 Avago Technologies. All Rights Reserved.LSI® SAS 9311-8i PCI Express® to 12Gb/s Serial Attached SCSI (SAS) Host Bus Adapter User Guide1OverviewThe LSI® PCI Express® (PCIe®)-to-Serial Attached SCSI (SAS) host bus adapter (HBA), referred to as the LSI 12Gb/s SASHBA, provides high-performance internal storage connectivity for servers and workstations. The LSI 12Gb/s SAS HBAprovides eight lanes of 12Gb/s SAS connectivity and is matched with eight lanes of PCIe 3.0 8Gb/s performance. Thelow-profile design of the SAS HBA includes a full-height bracket and low-profile mounting bracket that create auniversal fit for any server. The LSI 12Gb/s SAS HBA is based on the Fusion-MPT™-architected LSI SAS 3008 controllerthat integrates the latest enhancements in PCIe 3.0 technology and 12Gb/s SAS technology.The LSI 12Gb/s SAS HBA has onboard Flash memory for the firmware, and BIOS and NVSRAM for RAID support (RAID 0,RAID 1, RAID10, and RAID 1E).2FeaturesThis section lists the LSI 12Gb/s SAS HBA features.⏹Implements LSI SAS 3008 eight-port 12Gb/s SAS to PCIe 3.0 controller⏹Supports eight-lane, full-duplex PCIe 3.0 performance⏹Supports eight internal 12Gb/s SATA+SAS ports⏹Supports SATA link rates of 3Gb/s and 6Gb/s⏹Supports SAS link rates of 3Gb/s, 6Gb/s, and 12Gb/s⏹Provides two x4 internal mini-SAS HD connectors (SFF-8643)⏹Supports passive copper cable, active copper cable, and optical cable⏹Supports Integrated RAID (RAID 0, RAID 1, RAID 10, and RAID 1E)⏹Supports up to 1024 SATA or SAS end devices⏹Offered with a full-height bracket and a low-profile vented bracket⏹Provides one heartbeat LED3Functional Descriptions3.1PCI Express InterfacePCIe is a high-speed standard local bus for point-to-point interfacing of I/O components to the processor and thememory subsystems in high-end computers and servers. The LSI SAS 3008 controller chip contains the PCIefunctionality for the LSI 12Gb/s SAS HBA. The LSI SAS 3008 controller chip connects to the PCIe bus and generatestiming and protocol in compliance with the PCIe specifications.The LSI 12Gb/s SAS HBA supports eight-lane PCIe performance up to 64Gb/s single direction and 128Gb/sdual direction.3.2SAS-3 InterfaceThe LSI SAS 3008 controller chip contains the SATA+SAS functionality for the LSI 12Gb/s SAS HBA. The following tableshows the LSI SAS 12Gb/s SAS performance.Half Duplex Full DuplexNarrow port (one lane), 1200 MB/s Narrow port (one lane), 2400 MB/sWide port (four lanes), 4800 MB/s Wide port (four lanes), 9600 MB/s3.3LED ManagementThe LSI 12Gb/s SAS HBA offers LED management support for your backplane implementation. This configurationoption lets you use the LSI 12Gb/s SAS HBA with backplanes configured for the SGPIO interface. The LSI 12Gb/s SASHBA is in accordance with SFF-8485: Specification for Serial GPIO (SGPIO) Bus, Revision0.7.4Operating System SupportThe LSI 12Gb/s SAS HBA supports all major operating systems: Windows®, Linux® Red Hat®, Linux SUSE® EnterpriseServer (SLES), and VMware®. The HBA also supports Solaris® 11 Update 2. Refer to /hbas for details on the software versions and device driver support. For Solaris support, contact the Avago® Technical Support team.5LSI SAS 9311-8i HBA Characteristics5.1MemoryThe LSI 12Gb/s SAS HBA provides one 4-M × 16-bit Flash ROM to store the firmware and the BIOS. The LSI 12Gb/s SASHBA can provide up to 32 K × 8-bit NVSRAM for storing nonvolatile RAID information when a system failure occurs orto reflash the board to run IR firmware.5.2LEDThe LSI 12Gb/s SAS HBA Heartbeat LED, CR1, blinks green to indicate the HBA is capable of general activity.5.3ConnectorsPCIe Connector (EC1). The LSI 12Gb/s SAS HBA supports a x8 interface. The PCIe host interface connection is throughthe edge connector, EC1, which provides connections on both the top (EC1 B) and bottom (EC1 A) of the board. Thesignal definitions and pin numbers conform to the PCIe specification.SATA+SAS Connector (J1). The LSI 12Gb/s SAS HBA supports SATA and SAS connectors through connectors that areSFF-8643 mini-SAS HD, internal connectors.5.4Physical CharacteristicsThe LSI 12Gb/s SAS HBA is a 6.0-in. × 2.7-in., low-profile board. The component height on the top and bottom of theLSI 12Gb/s SAS HBA is in accordance with the PCIe specification. The following figure shows the HBA board layout.Figure⏹EC1⏹CR1 – Heartbeat LED⏹J1 – SFF-8643 mini-SAS HD, internal, right-angle connectors5.5Electrical CharacteristicsThe power requirements for the LSI SAS 9311-8i HBA under normal operation are as follows:⏹PCIe 12.0 V = 1.59A⏹Power values:—Nominal = 13.0W—Worst case = 19.04W5.6Thermal and Atmospheric LimitsThe atmospheric limits for the LSI 12Gb/s SAS HBA are as follows:⏹Temperature range: 0 °C to 55 °C (32 °F to 131 °F) (dry bulb)⏹Relative humidity range: 5% to 90% noncondensing⏹Maximum dew point temperature: 32 °C (89.6 °F)⏹Minimum airflow: 200 linear feet per minute at 55 °C inlet temperatureThe following limits define the storage and transit environment for the LSI 12Gb/s SAS HBA:⏹Temperature range: –45 °C to +105 °C (–49 °F to +221 °F) (dry bulb)⏹Relative humidity range: 5% to 90% noncondensing6LSI 12Gb/s SAS HBA Certifications and Safety CharacteristicsAll LSI 12Gb/s SAS HBAs meet or exceed the requirements of UL flammability rating 94V-0. Each bare board is markedwith the supplier’s name or trademark, type, and UL flammability rating. Because these boards are installed in a PCIebus slot, all voltages are less than the SELV 42.4-V limit.The design and implementation of the LSI 12Gb/s SAS HBA minimizes electromagnetic emissions, susceptibility toradio frequency energy, and the effects of electrostatic discharge.The LSI 12Gb/s SAS HBA meets the following integrated electromagnetic interference (EMI) compliance labels:⏹CE mark⏹RCM mark⏹Canadian Compliance Statement⏹FCC Class B, marked with the FCC Self-Certification logo⏹UL Listed Mark for Canada/U.S.⏹Japan VCCI⏹Korean KCC⏹Taiwan BSMIThe LSI 12Gb/s SAS HBA meets the following environmental directives:⏹Restriction of Hazardous Substances (RoHS)⏹Waste of electrical and electronic equipment (WEEE)7Hardware Installation InstructionsTo install the LSI 12Gb/s SAS HBA, follow these steps:1.Unpack the HBA, and inspect it for damage. Unpack the HBA in a static-free environment. Remove the HBA fromthe antistatic bag, and carefully inspect the device for damage. If you notice any damage, contact Avago or yourreseller support representative.ATTENTION To avoid the risk of data loss, back up your data before changing yoursystem configuration.2.Prepare the computer. Turn off the computer, and disconnect the power cord from the rear of the power supply.CAUTION Disconnect the computer from the power supply and from anynetworks to which you will install the HBA, or you risk damaging thesystem or experiencing electrical shock.3.Remove the cover from the chassis.4.Check the mounting bracket on the HBA (system-dependent). If required for your system, replace thefull-height mounting bracket that ships on the HBA with the low-profile bracket supplied.5.Insert the HBA into an available PCIe slot. Locate an empty x8 PCIe slot. Remove the blank bracket panel on therear of the computer that aligns with the empty PCIe slot. Save this bracket screw, if applicable. Align the HBA to aPCIe slot. Press down gently, but firmly, to seat the HBA correctly in the slot. The following figure shows how toinsert the HBA into a PCIe slot.NOTE The shape, size, and locations of the components on your HBA and itsbracket might vary from this illustration. The HBA requires a x8PCIe slot.Figure6.Secure the HBA bracket to the system’s chassis. Install the bracket screw, if applicable, or engage the systemretention mechanism to secure the HBA to the system’s chassis.7.Connect SAS cables between the HBA and the SAS backplane or any other SATA or SAS device. The LSI12Gb/s SAS HBA has two SFF-8643, internal x4, mini-SAS HD connectors. Use cables with an internal mini-SAS HDconnector on one end (to connect to the HBA) and the appropriate connector on the other end to attach to thebackplane or SAS/SATA devices.8.Replace the cover and any power cords, and power up the system. Replace the chassis’s cover, reconnect anypower cords, and reconnect any network cables. Turn on the power.The hardware installation of your LSI 12Gb/s SAS HBA is complete.8Technical SupportFor assistance installing, configuring, or running the LSI 12Gb/s SAS HBA, contact Technical Support:Email:*******************************Website:/support/pages/submit-support-request.aspxRevision HistoryVersion 1.3, March 2015The following document change was made:⏹Changed Solaris operating system support. Version 1.2, September 2014The following document changes were made:⏹Updated support contact information.⏹Template update.Version 1.1, December 2013The following document change was made:⏹Added RAID 1E support.Version 1.0, March 2013Initial document release.。
RT8252B 同步步进下降转换器数据手册说明书
DS8252B-02 March 2011Ordering InformationNote :Richtek products are :` RoHS compliant and compatible with the current require-ments of IPC/JEDEC J-STD-020.` Suitable for use in SnPb or Pb-free soldering processes.Pin Configurations(TOP VIEW)ApplicationszWireless AP/Router z Set-T op-Boxz Industrial and Commercial Low Power Systems z LCD Monitors and TVsz Green Electronics/Appliancesz Point of Load Regulation of High-Performance DSPsSOP-8 (Exposed Pad)2A, 23V, 1.2MHz Synchronous Step-Down ConverterGeneral DescriptionThe RT8252B is a high-efficiency, monolithic synchronous step-down DC/DC converter that can deliver up to 2A output current from a 4.5V to 23V input supply. The RT8252B's current mode architecture and external compensation allow the transient response to be optimized over a wide range of loads and output capacitors.Cycle-by-cycle current limit provides protection against shorted outputs and soft-start eliminates input current surge during start-up. The RT8252B also provides under voltage protection and thermal shutdown protection. The low current (<3μA) shutdown mode provides output disconnect, enabling easy power management in battery-powered systems. The RT8252B is available in a SOP-8 (Exposed Pad) package.Featuresz ±1.5% High Accuracy Feedback Voltagez 4.5V to 23V Input Voltage Range z 2A Output Currentz Integrated N-MOSFET Switches z Current Mode Controlz Fixed Frequency Operation : 1.2MHz z Adjustable Output from 0.8V to 20V z Up to 95% Efficiencyz Programmable Soft-Startz Stable with Low-ESR Ceramic Output Capacitors z Cycle-by-Cycle Over Current Protection z Input Under Voltage Lockout z Output Under Voltage Protection z Thermal Shutdown ProtectionzRoHS Compliant and Halogen FreeBOOT VINSW GNDSS EN FBCOMPMarking InformationRT8252BGSP : Product Numberx : H or LYMDNN : Date CodePackage TypeSP : SOP-8 (Exposed Pad-Option 1)RT8252BLead Plating SystemG : Green (Halogen Free and Pb Free)H : UVP Hiccup L : UVP Latch-OffTypical Application CircuitOUTDS8252B-02 March 2011Function Block DiagramElectrical Characteristics(V IN= 12V, T A = 25°C, unless otherwise specified)Absolute Maximum Ratings (Note 1)z Supply Voltage, V IN -------------------------------------------------------------------------------------------------−0.3V to 25Vz Input Voltage, SW ---------------------------------------------------------------------------------------------------−0.3V to (V IN + 0.3V)z V BOOT − V SW ----------------------------------------------------------------------------------------------------------−0.3V to 6V z Other Pin Voltages --------------------------------------------------------------------------------------------------−0.3V to 6V zPower Dissipation, P D @ T A = 25°CSOP-8 (Exposed Pad)---------------------------------------------------------------------------------------------1.333W zPackage Thermal Resistance (Note 2)SOP-8 (Exposed Pad), θJA ----------------------------------------------------------------------------------------75°C/W SOP-8 (Εxposed Pad), θJC ---------------------------------------------------------------------------------------15°C/W z Lead Temperature (Soldering, 10 sec.)-------------------------------------------------------------------------260°C z Junction T emperature -----------------------------------------------------------------------------------------------150°Cz Storage T emperature Range --------------------------------------------------------------------------------------−65°C to 150°C zESD Susceptibility (Note 3)HBM (Human Body Mode)----------------------------------------------------------------------------------------2kV MM (Machine Mode)------------------------------------------------------------------------------------------------200VRecommended Operating Conditions (Note 4)z Supply Voltage, V IN -------------------------------------------------------------------------------------------------4.5V to 23V z Junction T emperature Range --------------------------------------------------------------------------------------−40°C to 125°C zAmbient T emperature Range --------------------------------------------------------------------------------------−40°C to 85°CTo be continuedDS8252B-02 March 2011Note 1. Stresses listed as the above "Absolute Maximum Ratings " may cause permanent damage to the device. These are forstress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability.Note 2. θJA is measured in natural convection at T A = 25°C on a high effective thermal conductivity four-layer test board ofJEDEC 51-7 thermal measurement standard. The measurement case position of θJC is on the exposed pad for SOP-8 (Exposed Pad) package.Note 3. Devices are ESD sensitive. Handling precaution is recommended.Note 4. The device is not guaranteed to function outside its operating conditions.Typical Operating CharacteristicsReference Voltage vs. Input Voltage0.7800.7850.7900.7950.8000.8050.8100.8150.8204681012141618202224Input Voltage (V)R e f e r e n c e V o l t a g e (V)Output Voltage vs. Output Current3.203.223.243.263.283.303.323.343.363.383.400.00.20.40.60.81.01.21.41.61.82.0Output Current (A)O u t p u t V o l t a g e (V )Frequency vs. Temperature1.001.051.101.151.201.251.301.351.40-50-25255075100125Temperature (°C)F r e q u e n c y (M H z )Frequency. vs. Input Voltage1.001.051.101.151.201.251.301.351.404681012141618202224Input Voltage (V) F r e q u e n c y(M H z )Reference Voltage vs. Temperature0.7800.7850.7900.7950.8000.8050.8100.8150.820-50-25255075100125Temperature (°C)R e f e r e n c e V o l ta g e (V )Efficiency vs. Output Current01020304050607080901000.010.1110Output Current (A)E f f i c i e n c y (%)DS8252B-02 March 2011Current Limit vs. Duty Cycle3.03.54.04.55.05.56.001020304050607080Duty Cycle (%)C u r r e n t L i m i t (A)Current Limit VS. Temperature3.03.54.04.55.05.56.0-50-25255075100125Temperature (°C)C u r r e n t L i m i t (A)Output Current Limit vs. Input Voltage0.00.51.01.52.02.53.03.54.04.55.05.56.04681012141618202224Input Voltage (V)O u t p u t C u r r e n t L i m i t (A)Load Transient ResponseTime (100μs/Div)V IN = 12V, V OUT = 3.3V, I OUT = 0.2A to 2AI OUT (2A/Div)V OUT (50mV/Div)Load Transient ResponseTime (100μs/Div)V OUT (50mV/Div)I OUT (2A/Div)V IN = 12V, V OUT = 3.3V, I OUT = 1A to 2ASwitchingTime (500ns/Div)V IN = 12V, V OUT = 3.3V, I OUT = 2AI L (1A/Div)V OUT (10mV/Div)V SW (10V/Div)SwitchingTime (500ns/Div)V IN = 12V, V OUT = 3.3V, I OUT = 1A V OUT (10mV/Div)V SW (10V/Div)I L (1A/Div)Power On from VINTime (5ms/Div)V IN = 12V, V OUT = 3.3V, I OUT = 2AI L (2A/Div)V OUT (2V/Div)V IN (5V/Div)Power Off from VIN Time (5ms/Div)I L (2A/Div)V OUT (2V/Div)V IN (5V/Div)V IN = 12V, V OUT = 3.3V, I OUT = 2APower On from ENTime (5ms/Div)V OUT (2V/Div)V EN (5V/Div)I L (2A/Div)V IN = 12V, V OUT = 3.3V, I OUT = 2APower Off from ENTime (5ms/Div)V IN = 12V, V OUT = 3.3V, I OUT = 2AV OUT (2V/Div)V EN (5V/Div)I L (2A/Div)DS8252B-02 March 2011Application InformationThe RT8252B is a synchronous high voltage buck converter that can support the input voltage range from 4.5V to 23V while providing output current up to 2A.Output Voltage SettingThe resistive divider allows the FB pin to sense the output voltage as shown in Figure 1.Figure 1. Output Voltage SettingThe output voltage is set by an external resistive voltage divider according to the following equation :⎛⎞+⎜⎟⎝⎠OUT FB R1V = V 1R2Where V FB is the feedback reference voltage (0.8V typ.).External Bootstrap DiodeConnect a 100nF low ESR ceramic capacitor between the BOOT pin and SW pin. This capacitor provides the gate driver voltage for the high side MOSFET .It is recommended to add an external bootstrap diode between an external 5V and BOOT pin for efficiency improvement when input voltage is lower than 5.5V or duty ratio is higher than 65% .The bootstrap diode can be a low cost one such as IN4148 or BAT54. The external 5V can be a 5V fixed input from system or a 5V output of the RT8252B. Note that the external boot voltage must be lower than 5.5V.Figure 2. External Bootstrap DiodeSoft-StartThe RT8252B contains an external soft-start clamp that gradually raises the output voltage. The soft-start timing can be programmed by the external capacitor between SS pin and GND. The chip provides a 6μA charge current for the external capacitor. If 0.1μF capacitor is used to set the soft-start, it's period will be 13.5ms(typ.).Chip Enable OperationThe EN pin is the chip enable input. Pulling the EN pin low (<0.4V) will shutdown the device. During shutdown mode, the RT8252B quiescent current will drops below 3μA. Driving the EN pin high (>2.7V, < 5.5V) will turn on the device again. For external timing control (e.g.RC),the EN pin can also be externally pulled high by adding a R EN * resistor and C EN * capacitor from the VIN pin (see Figure 5).An external MOSFET can be added to implement digital control on the EN pin when no system voltage above 2.5V is available, as shown in Figure 3. In this case, a 100k Ωpull-up resistor, R EN , is connected between V IN and the EN pin. MOSFET Q1 will be under logic control to pull down the EN pin.V OUT100nFFigure 3. Enable Control Circuit for Logic Control withLow Voltage.To prevent enabling circuit when V IN is smaller than the V OUT target value, a resistive voltage divider can be placed between the input voltage and ground and connected to the EN pin to adjust IC lockout threshold, as shown in Figure 4. For example, if an 8V output voltage is regulated from a 12V input voltage, the resistor R EN2 can be selected to set input lockout threshold larger than 8V.OUTHaving a lower ripple current reduces not only the ESR losses in the output capacitors but also the output voltage ripple. High frequency with small ripple current can achieve highest efficiency operation. However, it requires a large inductor to achieve this goal.For the ripple current selection, the val ue of ΔI L = 0.24(I MAX )will be a reasonable starting point. The large st ripple current occurs at the highest V IN . To guarantee that theOUT OUT L(MAX)IN(MAX)V V L =1f I V ⎡⎤⎡⎤×−⎢⎥⎢⎥×Δ⎣⎦⎣⎦The inductor's current rating (caused a 40°C temperature rising from 25°C ambient) should be greater than the maximum load current and its saturation current should be greater than the short circuit peak current limit. Please see Table 2 for the inductor selection reference.Table 2. Suggested Inductors for TypicalRMS OUT(MAX)I = I This formula has a maximum at V IN = 2V OUT , where I RMS = I OUT /2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief.Choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design.For the input capacitor, one 10μF low ESR ceramic capacitors are recommended. For the recommended capacitor, please refer to Table 3 for more detail.The selection of C OUT is determined by the required ESR to minimize voltage ripple.Moreover, the amount of bulk capacitance is also a key for C OUT selection to ensure that the control loop is stable.Loop stability can be checked by viewing the load transientC IN and C OUT SelectionThe input capacitance, C IN, is needed to filter the trapezoidal current at the source of the high side MOSFET .To prevent large ripple current, a low ESR input capacitor sized for the maximum RMS current should be used. The RMS current is given by :V OUTFigure 4. The Resistors can be Selected to Set ICLockout Threshold.Hiccup ModeFor the RT8252BH, it provides Hiccup Mode Under Voltage Protection (UVP). When the FB voltage drops below half of the feedback reference voltage, V FB , the UVP function will be triggered and the RT8252BH will shut down for a period of time and then recover automatically. The Hiccup Mode UVP can reduce input current in short-circuit tch-Off ModeFor the RT8252BL, it provides Latch-Off Mode Under Voltage Protection (UVP). When the FB voltage drops below half of the feedback reference voltage, V FB , UVP will be triggered and the RT8252BL will shut down in Latch-Off Mode. In shut down condition, the RT8252BL can be reset by the EN pin or power input VIN.Inductor SelectionThe inductor value and operating frequency determine the ripple current according to a specific input and output voltage. The ripple current ΔI L increases with higher V IN and decreases with higher inductance.OUT OUT L IN V V I =1f L V ⎡⎤⎡⎤Δ×−⎢⎥⎢⎥×⎣⎦⎣⎦ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation :DS8252B-02 March 2011OUT L OUT 1V I ESR 8fC ⎡⎤Δ≤Δ+⎢⎣⎦The output ripple will be highest at the maximum input voltage since ΔI L increases with input voltage. Multiplecapacitors placed in parallel may be needed to meet the ESR and RMS current handling requirement. Dry tantalum,special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages.Special polymer capacitors offer very low ESR value. However, it provides lower capacitance density than other types. Although T antalum capacitors have the highest capacitance density, it is important to only use types that pass the surge test for use in switching power supplies.Aluminum electrolytic capacitors have significantly higher ESR. However, it can be used in cost-sensitive applications for ripple current rating and long term reliability considerations. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing.Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at theresponse as described in a later section.The output ripple, ΔV OUT , is determined by :input, V IN . At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at V IN large enough to damage the part.Checking Transient ResponseThe regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, V OUT immediately shifts by an amount equal to ΔI LOAD (ESR) also begins to charge or discharge C OUT generating a feedback error signal for the regulator to return V OUT to its steady-state value. During this recovery time, V OUT can be monitored for overshoot or ringing that would indicate a stability problem.EMI ConsiderationSince parasitic inductance and capacitance effects in PCB circuitry w ould cause a spike voltage on SW pin when high side MOSFET is turned-on /off, this spike voltage on SW may impact on EMI performance in the system. In order to enhance EMI performance, there are two methods to suppress the spike voltage. One is to place an R-C snubber between SW and GND and make them as close as possible to the SW pi n (see Figure 5). Another m ethod is adding a resistor in series with the bootstrap capacitor, C BOOT . But this method will decrease the driving capability to the high side MOSFET. It is strongly recommended to reserve the R-C snubber during PCB layout for EMI improvement. Moreover, reducing the SW trace area and keeping the main power in a small loop will be helpful on EMI performance. For detailed PCB layout guide, please refer to the section of Layout Consideration.Figure 5. Reference Circuit with Snubber and Enable Timing ControlV OUT 3.3V/2AFigure 7. Derating Curves for RT8252B Package(a) Copper Area = (2.3 x 2.3) mm 2, θJA = 75°C/W(b) Copper Area = 10mm 2, θJA = 64°C/W(c) Copper Area = 30mm 2 , θJA = 54°C/W0.00.20.40.60.81.01.21.41.61.82.02.20255075100125Ambient Temperature P o w e r D i s s i p a t i o n (W )(°C)Thermal ConsiderationsFor continuous operation, do not exceed the maximum operation junction temperature 125°C . The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient.The maximum power dissipation can be calculated by following formula :P D(MAX) = (T J(MAX) − T A ) / θJAWhere T J(MAX) is the maximum operation junction temperature , T A is the ambient temperature and the θJA is the junction to ambient thermal resistance.For recommended operating conditions specification of RT8252B, the maximum junction temperature is 125°C .The junction to ambient thermal resistance θJA is layout dependent. For PSOP-8 package, the thermal resistance θJA is 75°C /W on the standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at T A = 25°C can be calculated by following formula :P D(MAX) = (125°C − 25°C ) / (75°C /W) = 1.333W (min.copper area PCB layout)P D(MAX) = (125°C − 25°C ) / (49°C /W) = 2.04W (70mm 2copper area PCB layout)The thermal resistance θJA of SOP-8 (Exposed Pad) is determined by the package architecture design and the PCB layout design. However, the package architecture design had been designed. If possible, it's useful to increase thermal performance by the PCB layout copper design. The thermal resistance θJA can be decreased by a dding copper area under the exposed pad of SOP-8(Exposed Pad) package.As shown in Figure 6, the amount of copper area to which the SOP-8 (Exposed Pad) is mounted affects thermal performance. When mounted to the standard SOP-8 (Exposed Pad) pad (Figure 6.a), θJA is 75°C/W.Adding copper area of pad under the SOP-8 (Exposed Pad) (Figure 6.b) reduces the θJA to 64°C/W. Even further,increasing the copper area of pad to 70mm 2 (Figure 6.e)reduces the θJA to 49°C/W.The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θJA . For RT8252B package, the Figure 7 ofderating curves allows the designer to see the effect of rising ambient temperature on the maximum power dissipation allowed.DS8252B-02 March 2011(d) Copper Area = 50mm 2 , θJA = 51°C/W(e) Copper Area = 70mm 2 , θJA = 49°C/WFigure 6. Themal Resistance vs. Copper Area Layout DesignFigure 8. PCB Layout GuideTable 3. Suggested Capacitors for Cand CLayout ConsiderationFor best performance of the RT8252B, the follow layout guidelines must be strictly followed.`Input capacitor must be placed as close to the IC as possible.C `SW should be connected to inductor by wide and short trace. Keep sensitive components away from this trace.`The feedback components must be connected as close to the device as possibleInformation that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.Richtek Technology CorporationHeadquarter5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C.Tel: (8863)5526789 Fax: (8863)5526611Richtek Technology CorporationTaipei Office (Marketing)5F, No. 95, Minchiuan Road, Hsintien City Taipei County, Taiwan, R.O.C.Tel: (8862)86672399 Fax: (8862)86672377Email:*********************Outline DimensionHM(Bottom of Package)8-Lead SOP (Exposed Pad) Plastic Package。
贝索特安全公司 D8125MUX 双路复用总线接口说明书
u Multiplex bus controls two independent buses uAux Power terminals that can be used for remote devicesuProgrammed with D5060 Handheld Programmer (not required for "i" class modules)u Operation monitoring LED uConnect to Zonex 1 or Zonex 2The D8125MUX Multiplex Bus Interface Module and associated modules are used to expand the compatible Bosch control panels beyond theirstandard number of onboard initiating zones or points.The D8125MUX module is installed in the control panel enclosure, and is connected to either Zonex 1 or Zonex 2 on the control panel where it scans themultiplex (MUX) points connected to it and reports the points’ status to the control panel. Point indexprogramming then determines if an action on the part of the control panel is required (alarm response,trouble response, and so on).FunctionsTwo Independent BusesThe multiplex bus interface can control twoindependent buses. A fault on one MUX bus does not prevent the other from operating normally.Aux Power TerminalsThe D8125MUX has Aux Power terminals labeled Power A (+,-) and Power B (+,-) that can be used for remote devices that require an uninterrupted source of power. Up to 200 mA are available at these terminals.NoticeObserve correct polarity when connecting devices to these power terminals.D5060 Hand-held ProgrammerUse the D5060 Multiplex Point Programmer to program multiplex bus points. The D5060 is not required when programming "i" class modules. In addition to programming points, use the D5060 to view the MUX device point number.Certifications and approvalsCompatible Control Panels•B9512G/B9512G-E •B8512G/B8512G-E•D9412GV4/D7412GV4/D7212GV4•D9412GV3/D7412GV3/D7212GV3•D9412GV2/D7412GV2/D7212GV2•D9412G/D7412G/D7212G•D9124 Fire Alarm Control Panel •FPD-7024 Fire Alarm Control PanelCompatibility Multiplex Modules•DS7432 Series Eight-input Remote Modules •DS7457i Series Single-zone Input Modules •DS7460i Dual-zone Input Module •DS7461i Single-zone Input Module •DS7465i Input-output ModuleCompatible Programmers •D5060 Multiplex ProgrammerWiringMaximum Wire Impedance: 33 ΩThe recommended wiring from the control panel to the module is quad (four-wire) cable. Do not use shielded or twisted-pair cable. If used in fire applications,18 AWG wire is required.Maximum Impedance: 4.05 Ω at +20°C (+68°F) nominalUse non-shielded wire for data loops. Do not exceed 75 mA on each MUX Bus output.Parts includedQuantity Component1Multiplex Bus interface 1Hardware pack 1Literature packEnvironmental ConsiderationsPropertiesPower RequirementsTrademarksAll hardware and software product names used in this document are likely to be registered trademarks and must be treated accordingly.Ordering informationD8125MUX Multiplex Bus InterfaceControls two independent buses.Order number D8125MUXRepresented by:Europe, Middle East, Africa:North America:Asia-Pacific:Bosch Security Systems B.V.P.O. Box 800025600 JB Eindhoven, The Netherlands Phone: + 31 40 2577 284****************************** Bosch Security Systems, Inc.130 Perinton ParkwayFairport, New York, 14450, USAPhone: +1 800 289 0096Fax: +1 585 223 9180*******************.comRobert Bosch (SEA) Pte Ltd, Security Systems11 Bishan Street 21Singapore 573943Phone: +65 6571 2808Fax: +65 6571 2699*****************************© Bosch Security Systems 2016 | Data subject to change without notice 2537982603 | en, V7, 20. Jul 2016。
阳极氧化膜性能测试及国家标准
阳极氧化膜性能测试及国家标准阳极氧化膜性能测试方法1. 光泽1.1 目视法目视检测法：包含对颜色、色差、表面光泽和表面表面缺陷的检测。
其观察距离一般是0.5m；（GB/T14952.3-1994）1.2 光泽仪由于光泽目视时无法量化，所以采用了相应的仪器：光泽仪（目前的产品由于形状所限制，无法采用）；（GB/T5237.4-2000）2. 色泽2.1 目视法在自然散射光或标准光源D65用目视法检测，视力达到1.0，与产品垂直或呈45°角；（GB/T14952.3-1994）2.2 色差仪目视法受到产品、环境和人的因素影响，判断的偏差较大，所以一般采用色差仪，色差仪一般采用D65标准照明体，测量400~700nm的可见光波；（ISO7724.1~3-1984、ISO/TR8125-1984和GB/T11186.1~3-1989）3. 膜厚度（现有一个膜厚计）3.1 显微镜测量横断面厚度采用的方法是将产品截断，用金相显微镜测试，影响的因素有表面粗糙度、横断面的斜度、覆盖层变形和机加工缺陷；（GB/T6462-1986和ISO1463-1983）3.2 分光束显微镜测量法仅限于银色阳极氧化膜的测量；（ISO2128-1976、GB/T8014.3-200X）3.3 质量损失法适用于膜厚大于10μm（GB/T8014.2-200X、ISO2016-1982）3.4 涡流法（现有的膜厚计即为此种）采用涡流法有快速、方便、非破坏性，因此应用很广，原理是采用涡电流，并要求金属非磁性且表面不导电，当侧头与试样接触时，测头产生高频电流磁场，在基体金属中会感应出涡电流，此涡电流产生的附加电磁场会改变测头参数，而（GB/T4957-1994和ISO2360-1982）测头参数的改变取决于与氧化膜相关的测头到基体的距离，然后经芯片分析得到数值。
4. 阳极氧化膜封孔质量4.1 指印试验用橡胶“手指”模拟人的手指进行试验，“手指”放在试样的待测表面上5min，然后移去并用丙酮擦干净检查，有指印为不合格；（BS1615-1945）4.2 染色斑点试验适用于检验在大气曝晒与腐蚀的环境下使用的氧化膜，特别适用于对耐污染性有要求得氧化膜：将产品在25mL/L的硫酸和10g/L的氟化钾溶液中浸泡1min，擦干，再在23℃、PH=5±0.5的染色溶液中浸泡1min。
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UNISONIC TECHNOLOGIES CO., LTD81XX LINEAR INTEGRATED CIRCUITPOWER RESET ICDESCRIPTIONThe function of UTC 81XX is to accurately reset system afterdetecting the supply voltage at the time of switching power on and instantaneous power off in various CPU and other logic systems. Further, this IC, with its super low consumption current and high precision voltage detection capacity, is most suited as a voltage check circuit for a number of products which use batteries.FEATURES*High precision voltage detection. (V SS ±3% max) *low current consumption.(I CCH =15µA typ. I CCL =10µA typ.)*Low operating threshold voltage (0.65V typ.)*Hystresis voltage is provided as a detect voltage. (50mV typ.)*Large output current at the time ON (15mA typ.)*The detect voltage can be selected at your discretion at 0.1V step within the range of 1.9V to 4.6V by the following stipulation method.*Pb-free plating product number: 81XX LORDERING INFORMATIONOrder Number Pin AssignmentNormal Lead Free Plating Package 12 3 4 5Packing81XX-AB3-D-R 81XXL-AB3-D-R SOT-89I G O - - Tape Reel 81XX-AE3-2-R 81XXL-AE3-2-R SOT-23I O G - - Tape Reel 81XX-AE3-3-R 81XXL-AE3-3-R SOT-23O G I - - Tape Reel 81XX-AE3-5-R 81XXL-AE3-5-R SOT-23G O I - - Tape Reel 81XX-AF5-A-R 81XXL-AF5-A-R SOT-25NC NC G O I Tape Reel 81XX-AF5-B-R 81XXL-AF5-B-R SOT-25O I G NC NC Tape Reel 81XX-T92-D-B 81XXL-T92-D-B TO-92 I G O - - Tape Box 81XX-T92-D-K 81XXL-T92-D-K TO-92 I G O - - Bulk 81XX-T92-E-B 81XXL-T92-E-B TO-92 O I G - - Tape Box 81XX-T92-E-K 81XXL-T92-E-K TO-92 O I G - - Bulk Note: Pin Assignment: I: V CC O: V OUT G: GNDMARKING INFORMATIONBLOCK DIAGRAMV CCOUTGNDThe Pin2 this product is SUB, so connect the pin to Ground.ABSOLUTE MAXIMUM RATINGSPARAMETER SYMBOL RATINGS UNITPower supply voltage V CC -0.3~+10 V Operating temperature T OPR -20~+75 °C Storage temperature T STG -40~+125 °C Note Absolute maximum ratings are those values beyond which the device could be permanently damaged.Absolute maximum ratings are stress ratings only and functional device operation is not implied.ELECTRICAL CHARACTERISTICS(Ta=25°C, The unit of resistance is Ω unless otherwise indicated.)PARAMETER SYMBOL (*1)TEST CONDITIONS MIN TYP MAX UNITUTC 8150 4.850 5.000 5.150UTC 8146 4.462 4.600 4.738UTC 8145 4.365 4.500 4.635UTC 8144 4.268 4.400 4.532UTC 8143 4.171 4.300 4.429UTC 8142 4.074 4.200 4.326UTC 8141 3.977 4.100 4.223UTC 8140 3.880 4.000 4.120UTC 8139 3.783 3.900 4.017UTC 8138 3.686 3.800 3.914UTC 8137 3.589 3.700 3.811UTC 8136 3.492 3.600 3.708UTC 8135 3.395 3.500 3.605UTC 8134 3.298 3.400 3.502UTC 8133 3.201 3.300 3.399UTC 8132 3.104 3.200 3.296UTC 8131 3.007 3.100 3.193UTC 8130 2.910 3.000 3.090UTC 8129 2.813 2.900 2.987UTC 8128 2.716 2.800 2.884UTC 8127 2.619 2.700 2.781UTC 8126 2.522 2.600 2.678UTC 8125 2.425 2.500 2.575UTC 8124 2.328 2.400 2.472UTC 8123 2.231 2.300 2.369UTC 8122 2.134 2.200 2.266UTC 8121 2.037 2.100 2.163UTC 8120 1.940 2.000 2.060UTC 8119 1.843 1.900 1.957Detection Voltage V SS 1 R L =470ΩV CC =H->L V OUT =V CCUTC 8118 1.746 1.800 1.854VHysteresis Voltage ∆V SS 1R L =470Ω, V CC =L->H->L,V OUT =V CC30 50 100 mV Detection Voltage TemperatureCoefficient V SS /∆T 1 R L =470Ω, Ta=-20~+75°C V OUT =V CC±0.01 %/°CLow Level Output Voltage V OL 1V CC =V SS min.-0.05V,R L =470Ω0.2 0.4 V Output Leakage Current I OH 2 V CC =10V , V OUT =V CC ±0.1 µA Circuit Current at ON Time I CCL 3 V CC =V SS min.-0.05V, R L =∞ 3 5 µA Circuit Current at OFF Time I CCH 3 V CC =V SS typ./0.85, R L =∞ 3 5 µAELECTRICAL CHARACTERISTICS(Cont.)PARAMETER SYMBOL (*1)TEST CONDITIONS MIN TYP MAX UNIT“H” Transmission Delay Time TpLH (*2) 4 C L =100pF, R L =4.7K Ω 20 60 µS “L” Transmission Delay Time TpHL (*3) 4 C L =100pF, R L =4.7k Ω 20 60 µSOperating Threshold Voltage V OPL 1 R L =4.7k Ω, V OL ≦0.4V 0.65 0.85 V Output current at ON Time 1 I OL 1 2R L =0, V CC =Vs min.-0.05V,V OUT =0.4V 5 mA Output current at ON Time 2 I OL 2 2 Ta=-20~+75°CR L =0, V CC =V SS min.-0.15V V OUT =0.4V3 mANote:(*1) MEASUREMENT CIRCUIT(*2) TpLH: V CC =(V SS Typ. –0.4V) -> (V SS Typ. +0.4V) (*3) TpHL: V CC =(V SS Typ. +0.4V) -> (V SS Typ. -0.4V)MEASURING CIRCUITSV 1）V CC2）V OUTV CC3）PULSE5.0V4)NOTE: 1.) A: DC AMMETER V: DC VOLTMETER CRT: OSCILLOSCOPE 2.) INPUT PULSEVsTyp. +0.4V VsTyp. -0.4V0V。