AECQ信息汇总
aecq104 h组测试大纲
一、测试目的：1.1 确定产品的可靠性与稳定性，保证产品正常运行。
1.2 确定产品的安全性，保障用户使用过程中的安全。
1.3 确认产品的性能指标，保证产品达到设计要求。
二、测试范围：2.1 产品整体测试2.1.1 外观测试：检查产品外观是否完整，有无明显瑕疵。
2.1.2 尺寸测试：核对产品尺寸，确保符合设计要求。
2.1.3 结构测试：检测产品结构是否牢固，是否存在松动、裂痕等情况。
2.2 功能测试2.2.1 核心功能测试：测试产品核心功能是否正常运行。
2.2.2 辅助功能测试：测试产品附加功能是否正常运行。
2.3 安全性测试2.3.1 电气安全测试：检测产品电气部分是否符合安全标准。
2.3.2 热安全测试：测试产品在长时间工作下是否存在过热情况。
2.4 性能测试2.4.1 功能性能测试：测试产品在正常使用条件下的性能表现。
2.4.2 环境适应性测试：测试产品在不同环境下的适应能力。
三、测试方法：3.1 实验室测试3.1.1 采用专业测试设备进行各项测试，确保测试数据准确可靠。
3.1.2 固定测试条件，保证测试结果的可比性。
3.2 实地测试3.2.1 针对产品实际使用环境进行测试，模拟用户实际使用情况。
3.2.2 收集用户反馈意见，完善测试内容，确保测试结果真实可靠。
四、测试标准：4.1 相关国家标准：按照国家相关标准进行测试，确保产品符合国家标准要求。
4.2 行业标准：参照行业标准进行测试，确保产品符合行业标准要求。
4.3 公司内部标准：针对公司产品特点，制定公司内部测试标准，确保产品质量符合公司要求。
五、测试流程：5.1 制定测试计划5.1.1 确定测试时间、地点、人员等测试要素。
5.1.2 制定详细的测试方案，确保测试全面有效进行。
5.2 实施测试5.2.1 按照测试计划进行测试，保证测试过程规范有序。
5.2.2 完善测试记录，及时反馈测试结果。
5.3 分析总结5.3.1 对测试结果进行分析，找出存在的问题。
AEC_Q002_Rev_A
AEC - Q002 Rev AAugust 25, 2000GUIDELINESFORSTATISTICAL YIELDANALYSISComponent Technical CommitteeAutomotive Electronics CouncilAEC - Q002 Rev AAugust 25, 2000 Automotive Electronics CouncilComponent Technical CommitteeAcknowledgmentAny document involving a complex technology brings together material and skills from many sources. The Automotive Electronics Council would especially like to recognize the following significant contributors to the development of this revision of this document:Majdi Mortazavi DaimlerChrysler (256)464-2249 msm11@Brian Jendro DaimlerChrysler (256)464-2980 bj5@Robert V. Knoell Visteon Corporation (313)248-1116 rknoell@Gerald E. Servais Delphi Delco Electronics Systems (765)451-7923 gerald.e.servais@Kevin Hankins Delphi Delco Electronics Systems (765)451-7670 kevin.t.hankins@Nick Lycoudes Motorola (408)413-3343 raqa01@Philippe Briot PSA, Peugeot, Citroën 33 01 41 36 7849 p-briot@calvanet.calvacom.frMark Gabrielle On Semiconductor (602)244-3115 mark.gabrielle@Component Technical CommitteeGUIDELINES FOR STATISTICAL YIELD ANALYSIS Text enhancements and changes made since the last revision of thisdocument are shown as underlined areas1.SCOPEThis guideline is intended for use as a method for detecting and removing abnormal lots of material and thus ensuring the quality and reliability of the ICs supplied as meeting AEC - Q100 or 101. The principles described in this guideline are applicable to packaged or unpackaged die.1.1PurposeThis guideline describes a method, utilizing statistical techniques, of identifying a wafer, wafer lot or assembly lot that exhibits an unusually low yield or an unusually high bin failure rate. Experience has shown that wafer and assembly lots exhibiting these abnormal characteristics tend to havegenerally poor quality and can result in significant system reliability and quality problems.Note: For best statistical yield limits (SYL) and statistical bin limits (SBL) results, use test limitsbased on PAT Limits as described in AEC Q001.1.2 ReferencesAEC - Q001 Guidelines For Part Average TestingAEC - Q100 Stress Test Qualification For Integrated CircuitsAEC - Q101 Stress Test Qualification For Discrete Semiconductors2.DEFINITIONS2.1PAT LimitsPart average test limits established per AEC - Q001.3.METHOD FOR ESTABLISHING STATISTICAL YIELD LIMITS (SYL) AND STATISTICAL BINLIMITS (SBL)3.1Detailed Description For Basic Wafer / Wafer Lot / Assembly Lot Level Yield LimitsCollect data from at least six lots and determine the mean and sigma value for the percentage ofdevices passing per lot and the percentage of devices failing each bin-out per lot (lot as used here could mean each wafer, a wafer lot or an assembly lot). Early in production of a part, when dataComponent Technical Committeefrom six lots is not available, data from characterization/matrix lots may be used. This data shallbe updated as soon as production data is available. This early data shall be reviewed and updated using current data at least every 30 days during the first 6 months of production. The current data used shall include the data available since the last update or at least the last 8 lots. Older data shall not be used. After the first 6 months of production the limits shall be updated on a quarterly (every3 months) basis. With this data determine the SYL and SBL (both on a wafer, wafer lot andassembly lot basis) as follows:SYL1 = Mean - 3 SigmaSBL1 = Mean + 3 SigmaSYL2 =Mean - 4 SigmaSBL2 = Mean + 4 SigmaAny wafer or lots that fall below SYL1 or exceed SBL1 shall be held for engineering review. Inaddition, lots that fall below SYL2 or exceed SBL2 may be impounded and require customernotification before release, if specified in the applicable procurement document. Analysis shall be performed on failures to determine the failure mechanism(s) causing these abnormal failure rates.3.2RecordsThe supplier shall maintain records on all wafers, wafer lots and assembly lots that fall below SYL1 or exceed SBL1. This data shall include the root cause for the yield problem and corrective action taken to prevent reoccurrence of the problem. It should also include any special testing or screens that were performed on the wafer, wafer lot or assembly lot and the customer that approved theshipment of the parts in question.4. CUSTOMER NOTIFICATION4.1Procedure For Customer NotificationBefore the customer is notified, the supplier shall have determined the failure mechanism(s) and,based on his experience, determine the corrective action required to prevent a reoccurrence of the condition in future product. The supplier shall also present data on a reasonable expectation of the seriousness of the failure mechanism(s) and it’s impact on quality and reliability. Included in this data should be a plan for additional tests and screens which could provide the user with reasonable certainty that the product he receives will be at least equal to normal product.4.2Customer ResponseThe customer reserves the right to reject material that falls below SYL2 or exceeds SBL2 if thesupplier data does not satisfy his concerns about the quality and reliability of the product.4.3 If Customer Is Not KnownIf the supplier does not know who the customer is and customer approval can not be obtained, the parts from the lots in question (lots falling below SYL2 or exceeding SBL2) shall not be supplied to distributors as meeting AEC - Q100 or Q101.Component Technical CommitteeRevision HistoryRev #Date of change Brief summary listing affected paragraph-July 31, 1997Initial releaseA Aug. 25, 2000Added Paragraph 1.2, Paragraph 1, 2.1, and 4.3 revised.。
AECQ相关
标签：AECQAECQ信息汇总最近在整理元器件方面的资料，涉及ROSH与AECQ的信息，下面整理了AE CQ的信息。
克莱斯勒、福特和通用汽车为建立一套通用的零件资质及质量系统标准而设立了汽车电子委员会(AEC)，AEC 是“Automotive Electronics Council：汽车电子协会”之略，是主要汽车制造商与美国的主要部件制造商汇聚一起成立的、以车载电子部件的可靠性以及认定标准的规格化为目的的团体，AEC建立了质量控制的标准。
同时，由于符合AEC规范的零部件均可被上述三家车厂同时采用，促进了零部件制造商交换其产品特性数据的意愿，并推动了汽车零件通用性的实施，为汽车零部件市场的快速成长打下基础。
主要的汽车电子成员有：Autoliv, Co ntinental, Delphi, Johnson Controls 和Visteon。
AEC-Q100：主要用于预防产品可能发生各种状况或潜在的故障状态，引导零部件供货商在开发的过程中就能采用符合该规范的芯片。
AEC-Q100对每一个芯片个案进行严格的质量与可靠度确认，确认制造商所提出的产品数据表、使用目的、功能说明等是否符合最初需求的功能，以及在连续使用后个功能与性能是否能始终如一。
A EC-Q100标准的目标是提高产品的良品率，这对芯片供货商来说，不论是在产品的尺寸、合格率及成本控制上都面临很大的挑战。
AEC-Q100又分为不同的产品等级，其中第１级标准的工作温度范围在-40℃-1 25℃之间，最严格的第0级标准工作温度范围可达到-40℃-150℃。
0 等级：环境工作温度范围-40℃-150℃1 等级：环境工作温度范围-40℃-125℃2 等级：环境工作温度范围-40℃-105℃3 等级：环境工作温度范围-40℃-85℃4 等级：环境工作温度范围0℃-70℃AEC - Q100 Rev - G base: 集成电路的应力测试标准（不包含测试方法）AEC-Q100-001 邦线切应力测试AEC-Q100-002 人体模式静电放电测试AEC-Q100-003 机械模式静电放电测试AEC-Q100-004 集成电路闩锁效应测试AEC-Q100-005 可写可擦除的永久性记忆的耐久性、数据保持及工作寿命的测试AEC-Q100-006 热电效应引起的寄生闸极漏电流测试AEC-Q100-007 故障仿真和测试等级AEC-Q100-008 早期寿命失效率（ELFR）AEC-Q100-009 电分配的评估AEC-Q100-010 锡球剪切测试AEC-Q100-011 带电器件模式的静电放电测试AEC-Q100-012 12V 系统灵敏功率设备的短路可靠性描述AEC - Q101 Rev - C: 分立半导体元件的应力测试标准（包含测试方法）* AEC - Q101-001 - Rev-A: 人体模式静电放电测试* AEC - Q101-002 - Rev-A: 机械模式静电放电测试* AEC - Q101-003 - Rev-A: 邦线切应力测试* AEC - Q101-004 - Rev-: 同步性测试方法* AEC - Q101-005 - Rev-A: 带电器件模式的静电放电测试* AEC - Q101-006 - Rev-: 12V 系统灵敏功率设备的短路可靠性描述AEC - Q200 Rev - C: 半导体被动元件的应力测试标准（包含测试方法）* AEC - Q200-001 - Rev-A: 阻燃性能测试* AEC - Q200-002 - Rev-A: 人体模式静电放电测试* AEC - Q200-003 - Rev-A: 断裂强度测试* AEC - Q200-004 - Rev-: 自恢复保险丝测量程序* AEC - Q200-005 - Rev-: PCB板弯曲/端子邦线应力测试* AEC - Q200-006 - Rev-: 端子应力（贴片元件）/切应力测试* AEC - Q200-007 - Rev-: 电压浪涌测试AEC-Q001 零件平均测试指导原则提出了所谓的参数零件平均测试(PPAT)方法。
AEC_Q006_Rev_
Component Technical CommitteeAEC - Q006 - REV-QUALIFICATION REQUIREMENTS FOR COMPONENTS USING COPPER (Cu) WIRE INTERCONNECTIONSComponent Technical CommitteeAcknowledgmentAny document involving a complex technology brings together experience and skills from many sources. The Automotive Electronics Council would especially like to recognize the following significant contributors to the development of this document:Cu Wire Requirements Sub-Committee Members:Jeff Jarvis AMRDECJames Molyneaux Analog DevicesEarl Fischer AutolivBankim Patel AutolivMark Sears Bose CorporationXin Miao Zhao Cirrus LogicHadi Mehrooz Continental CorporationJohn Timms Continental CorporationRamon Aziz Delphi CorporationMark A. Kelly Delphi CorporationBruce Hood FreescaleNick Lycoudes FreescaleStephen Lee FreescaleSteve Sibrel HarmonWerner Kanert Infineon TechnologiesScott Daniels International RectifierJoe Lucia John DeereTom Lawler Lattice SemiconductorWarren Chen MacronixBob Knoell [Q006 Team Leader]NXP SemiconductorsZhongning Liang NXP SemiconductorsAndreas Pinkernelle NXP SemiconductorsRene Rongen NXP SemiconductorsPeter Turlo ON SemiconductorKiran Kumar Vanam QualcommFrancis Classe SpansionBassel Atala STMicroelectronicsLarry Ting Texas InstrumentsJames Williams Texas InstrumentsLarry Dudley TRW AutomotiveArthur Chiang VishayKrimo Sennaud XilinxComponent Technical CommitteeNOTICEAEC documents contain material that has been prepared, reviewed, and approved through the AEC Technical Committee.AEC documents are designed to serve the automotive electronics industry through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than AEC members, whether the standard is to be used either domestically or internationally.AEC documents are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action AEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the AEC documents. The information included in AEC documents represents a sound approach to product specification and application, principally from the automotive electronics system manufacturer viewpoint. No claims to be in Conformance with this document shall be made unless all requirements stated in the document are met. Inquiries, comments, and suggestions relative to the content of this AEC document should be addressed to the AEC Technical Committee on the link .Published by the Automotive Electronics Council.This document may be downloaded free of charge, however AEC retains the copyright on this material. By downloading this file, the individual agrees not to charge for or resell the resulting material.Printed in the U.S.A.All rights reservedCopyright © 2015 by the Automotive Electronics Council. This document may be freely reprinted with this copyright notice. This document cannot be changed without approval from the AEC Component Technical Committee.Component Technical CommitteeQUALIFICATION REQUIREMENTS FOR COMPONENTS USING COPPER(Cu) WIRE INTERCONNECTIONS1. SCOPEThis document contains a set of tests and defines the minimum requirements for qualification of copper (Cu) wire interconnections for components to be used in any automotive electronics application. While the set of tests highlighted here are replicated in AEC-Q100/Q101, this document details any different test conditions and/or durations plus the activity around these tests that are unique requirements for ensuring Cu wire reliability. Use of this document does not relieve the supplier of their responsibility to meet their own company's internal qualification program. In this document, "user" is defined as all customers using a component qualified per this specification. The user is responsible to confirm and validate all qualification data that substantiates conformance to this document.If a supplier has already qualified Cu wire and is in production with no Cu wire related issues, the supplier does not have to requalify those approved components again per this document.1.1 PurposeThe purpose of this specification is to determine that a component is capable of passing the specified stress tests and thus can be expected to give a certain level of quality/reliability in the application.1.2 Reference DocumentsCurrent revision of the referenced documents will be in effect at the date of agreement to the qualification plan. Subsequent qualification plans will automatically use updated revisions of these referenced documents.1.2.1 AutomotiveAEC-Q100 Failure Mechanism Based Stress Test Qualification for Integrated CircuitsAEC-Q101 Failure Mechanism Based Stress Test Qualification for Discrete Semiconductors inAutomotive Applications1.2.2 JEDECJESD22 Reliability Test MethodsJESD22-A104 Temperature Cycling (TC)JESD22-A110 Highly Accelerated Stress Test (HAST)JESD22-A101 Temperature Humidity Bias (THB) / High Humidity High Temperature Reverse Bias(H3TRB)JESD22-A105 Power Temperature Cycle (PTC)JESD22-A103 High Temperature Storage Life (HTSL) / High Temperature Gate Bias (HTGB)J-STD-035 Acoustic Microscopy for Non-Hermetic Encapsulated Electronic ComponentsJ-STD-020 Moisture/Reflow Sensitivity Classification for Nonhermetic Surface Mount Devices1.2.3 MilitaryMIL-STD-750, Method 1037 Intermittent Operation Life (IOL)MIL-STD-750, Method 1038 (condition A) High Temperature Reverse Bias (HTRB)Component Technical Committee2. EQUIPMENTNot applicable (see referenced documents)3. DATA SUBMISSION3.1 Certificate of Design and ConstructionFor qualification of components with Cu wire, a Certificate of Design and Construction per AEC-Q100/Q101 is required to determine whether available generic data can apply to the part in question for one or more of the required tests in this document.If applicable, supplier must document the definition of Cu wire product or technology family. This document should explain the selection of family (worst-case) test vehicle(s). In the following list, critical product, construction and material items for defining Cu wire product or technology families are given:Relevant items in Certificate of Design and Construction (referenced Q100 Appendix 2 item number shown in parentheses below):•(4) Wafer/Die Fab Location and process ID•(6) Assembly Location and process ID•(10a-c) Die Dimensions•(11c-d) Die Top Metallization and Thickness (including plating if applicable)•(12b) Die Passivation Material•(13) Die Overcoating Material•(17a) Die Attach Material•(19) Mold Compound Type (Material)•(20a-b) Wire Bond Material & Diameter•Either (21a-h) Leadframe material, plating and dimensionsOr (22a-b) Substrate material and thickness3.2 Test ResultsThe following data is to be submitted to the user for approval on request:•Cu wire stress test qualification results•Wire pull/ball shear – mean, min, max, standard deviation•CSAM images before/after stressing•Electrical/ATE functional/parametric test results before/after stress tests•Cross-sections of ball/wedge bonds (as needed per Section 5)4. QUALIFICATION TESTSThe required set of qualification stresses, test conditions and test durations are shown in the following sections, with an enhanced qualification flow described in Table 2.Qualification of Cu wire components to standard AEC-Q100/Q101 requirements for temperature cycling can be conducted if board level stress test (Section 4.5) was performed with no issues or fails observed. Otherwise, the supplier must perform the enhanced qualification flow described in Table 2 on a family/technology specific component at a minimum.If a supplier has already qualified Cu wire and is in production with no Cu wire related issues, the supplier does not have to requalify those approved components again per this document.Component Technical Committee4.1 Temperature Cycling (TC)This test highlights the differences in the coefficient of thermal expansion of package materials with Cu along with the increased hardness of Cu with respect to gold (Au).Perform per the requirements in AEC-Q100/Q101.4.2 Biased Humidity(HAST/THB/H3TRB)This test can exacerbate corrosion along the Cu/bond pad intermetallic compound (IMC) interfaces.Perform per the requirements in AEC-Q100/Q101.4.3 Power Temperature Cycle (PTC) / Intermittent Operation Life (IOL)This test can accelerate wearout by the combination of current/voltage and temperature.Perform per the requirements in AEC-Q100/Q101.4.4 High Temperature Storage Life(HTSL) / High Temperature Gate Bias (HTGB) / HighTemperature Reverse Bias (HTRB)This test can accelerate IMC growth along the Cu/Aluminum (Al) interface to yield an open bond failure. It can also degrade the mechanical performance of the stitch bond. This is especially important for high temperature applications.Perform per the requirements in AEC-Q100/Q101.4.5 Board Level Stress TestPerformance of this board-level temperature cycling test along with the test conditions, sample sizes and bill of materials to be used is to be agreed to between the user and supplier and justified by data.5. ANALYTICAL TESTS5.1 Delamination/CSAMDelamination of the mold compound over the Cu ball or stitch bond could lead to joint fatigue failure at either weld joint. The delamination criteria for various stages of qualification testing are shown in Table 1.Component Technical CommitteeTable 1: Delamination CriteriaNotes:(1) Agreement between the supplier and user would be achieved via the exchange of data thatdemonstrates that the form of delamination seen is not an issue for this part based on supporting data (field, monitor, in-process, etc.).(2) Method of evaluation to be determined by the user and supplier.(3) At 2x TC read point, passing production test means zero systematic Cu wire related issues. Forexample, if a failure was found to be related to solder ball or substrate, that is not considered a valid Cu wire failure.5.2 Wire Bond IntegrityThe tests described below and where they are performed are a good gauge of the bond strength and weld formation of the ball and stitch bonds. They are done to demonstrate no reliability risk. The location of the hook for bond pull should be over the contact of interest (i.e., over the ball and over the stitch/wedge).• Ball shear – ball bond area versus shear force (pre-packaged) • Wedge bond wire pull (pre-packaged)• Perform wire pull/ ball shear on first bond and wire pull for stitch bond (post packaged) • Pad cratering test (pre-packaged)Wire pull / ball shear is performed after stress testing and decapsulation. A recommended process flow is described below:1. Select components per the sample size specified in AEC-Q100/Q101 for wire pull and shear.Selecting worst-case components based on CSAM is desirable.2. Carefully decapsulate these components so as to not damage or adversely affect the wire bondsbut enough to be able to reliably conduct wire pulls and/or bond shears.Read PointMold Compound Delaminationacceptance criteria ElectricalQualification RequirementsT 0No delamination at first (ball) or second (stitch/wedge) bonds unless otherwiseagreed between supplier and user. (1)All components passing production testPost MSL PCNo delamination at first (ball) or second (stitch/wedge) bonds unless otherwiseagreed between supplier and user. (1)All components passing production test1X AEC grade XNo delamination at first (ball) bond. If any second (stitch/wedge) bond delamination found – no heel cracks or any other Cu-related fail mechanisms allowed.All components passing production test2X AEC grade X (TC included if no BLR performed)Evaluate the severity of any bond delamination found per Sections 5.2 and5.3. (2)All components passingproduction test (3)Minimum CSAM samples size: EITHER the same 11 components per lot through each readpoint (preferable) OR 22 random components per lot at each readpoint.Component Technical Committee3. The wire pull hook should be situated over the wedge bond for stitch bond pull and over the ballfor ball bond pull. Stitch bond pull force results after stress testing may not be a reliable gauge ofbond quality, as the act of pulling a wedge might not be repeatable and/or reproducible.4. Compare these results with production data (i.e., before mold) to see if there is a level ofdegradation in the distribution of the data that could reasonably point to a potential reliabilityissue. If there are positively biased wires required in the test, ensure that they are included in thisanalysis, as they are thought to be more susceptible to corrosion.5. In conjunction with pull/shear after decapsulation, a thorough inspection of the wedge bondsshould take place to look for heel cracks or precursors for failure.For temperature cycling, pulls and shears at corner locations of the die/package are preferable. For moisture stressing, selecting random balls/stitches is acceptable (uniform moisture penetration) but ensure that both biased and unbiased pins are selected. Determination of which wires per device undergo ball shear, ball pull or stitch pull is left to the supplier to determine as long as the intent of inspecting all types of bonds is adequately addressed.5.3 Cross-sectioning InspectionFor initial supplier qualification of a new die/package (interaction) family/technology, components from the CSAM after TC stressing showing both no delamination and delamination over a bond(s) are to be used for cross-sectioning. The sample sizes, test conditions and acceptance criteria are specified in the overall process qualification flow shown in Table 2.Criteria of examination:•Ball bond areao Amount and distribution of intermetallic - an alternative planar analysis method to evaluate ball bond IMC formation is also acceptableo Crack initiation/propagationo Corrosion after 1x•Wedge bond areao Amount of contacto Wire angle to wedgeo Crack initiation/propagationo Corrosion after 1xo Intermetallics formed in the bond area6. COMPONENT CHANGES6.1 Qualification Test Requirements for Cu Wire ChangesThe method of qualification of changes to already qualified and released components is outside the scope of this document. For those cases, AEC-Q100/Q101 is applicable and the qualification plan shall be based on an assessment of the tests needed for changes per Table 3 of AEC-Q100/Q101 and the relevant fail mechanisms, risk factors and best practices found in Appendix 1 of this document. If degradation models have been developed that can be technically justified via internal and external data to support the equivalent robustness of material and design changes to already-qualified Cu wire parts, this can be used with customer approval to then be allowed to perform AEC-Q100/Q101 testing. If there is limited knowledge or data on changes to already-qualified Cu wire parts, relevant tests should be performed per Q006 Table 2 conditions.Component Technical Committee7. QUALIFICATION REQUIREMENTS FOR Cu WIRE COMPONENTSThe table below describes the individual steps required in a qualification flow for Cu wire components and the sample sizes required for each stress test.The qualification can be performed on a technology basis (define technology family for the purpose of Cu wire). Passage of the technology family allows subsequent components in the family to be qualified using the enhanced requirements below and allow them to be qualified. Subsequent qualification of parts in the same technology but not in the same product family would require performance to this table up to and including sequence #10 only.Table 2a: Integrated Circuit Qualification Test Requirements based on AEC-Q100Notes:(1) Either 11 marked or 22 random parts per lot per Table 1 CSAM sample size criteria.(2) Performed only if board level reliability testing is NOT being performed.(3) Any failures beyond 1X must directly relate to the Cu wire bonding system for them to count as alegitimate failure requiring further evaluation (i.e., the projected lifetime of failure, effect of failmode on product lifetime, corrective/preventive action). The method of approval is determinedbetween the user and supplier.(4) Pull/shear as many as is possible per the number of wires per device to be qualified up to amaximum of 30 wires/balls from the total sample size specified.Component Technical CommitteeTable 2b: Discrete Qualification Test Requirements based on AEC-Q101Notes:(1) Either 11 marked or 22 random parts per lot per Table 1 CSAM sample size criteria.(2) Performed only if board level reliability testing is NOT being performed.(3) Any failures beyond 1X must directly relate to the Cu wire bonding system for them to count as alegitimate failure requiring further evaluation (i.e., the projected lifetime of failure, effect of fail mode on product lifetime, corrective/preventive action). The method of approval is determined between the user and supplier.(4) Pull/shear as many as is possible per the number of wires per device to be qualified up to amaximum of 30 wires/balls from the total sample size specified.Component Technical CommitteeAPPENDIX 1: Cu Wire Process and Technology Characterization GuidelineThis appendix is meant to be used as a guideline for users of components assembled using Cu wire for the internal interconnects. This guideline is a broad outline of generic items and issues suppliers should address to ensure a reliable Cu wire process in production.This guideline is meant to illustrate the technical items that need discussion between supplier and user to determine the level of competence in the supplier’s development process for Cu wire production. This discussion can involve data from design of experiments, stress tests, historical data, models, etc.A.1 Failure Mechanisms Related to Copper Wire and Causes/Risk Factors:•Chipout under ball bond (AEC Q100-001)o The pad and underlying structures have higher risk of damage/cracking due to the extra ball bonding force required for Cu wireo Bonding over layered active area circuitryo Thin passivation layer under bond pad•Corrosion along Cu/Al IMC interfaceo Trace contaminants/additives in mold compound in presence of moisture •Insufficient Cu/Al IMCo Al bondpad splash from overbonding forceo Poorly optimized bonding parameters for bonding temperature/frequency/force during thermosonic bondingo Oxidation of free air ball during ball bonding•Crack at wedge heelo Delamination at/near the lead tip where wedge locatedAdequate mold compound cureMold lock techniqueso Large CTE mismatch among package materialso Mismatch of material properties (e.g., Tg, CTE, elastic modulus) of component and with customer circuit boards•Wire neck severanceo Die/mold compound delamination near/at the ball bondA.2 Best Practices:•Inert environment around Cu wireo During wire storageo During free air ball formationo(Pd) Plated Cu wire•Tighter controls/limits for wire pull/shear metricso USL/UCL and LSL/LCLo Ball shear and wire pull near/over stitcho Production monitor using unmolded partso Pull/shear after stress testing and careful decapsulation•Capillaryo More frequent replacement/maintenanceo Designed specifically for Cu wire•Thermosonic bondingo Tighter parameters for frequency, temperature, forceo Reliability data collection at bond recipe corners of Force and Frequency •Mold Compound Material Requirementso Sufficiently high pH (generally greater than 5)o Cl extracted content (generally less than 15ppm)Component Technical Committee•Safe Launch (i.e., initial production period) period for new Qualification and Changes o Sample first lots for reliability test•Bond Pad Construction including active circuits under pad if applicableo Selecting the most sensitive bond pad known for analysis•Ball Bond: IMC contact area after wire bondingo Quantify smallest contact area below which there would be a bonding problem •Wedge Bond: delamination response after TCo Quantify the largest amount of delamination change allowedComponent Technical CommitteeRevision HistoryRev #-Date of changeJune 8, 2015Brief summary listing affected sectionsInitial Release.。
aec q标准
aec q标准
AEC-Q标准是一套车规元器件产品验证标准，由克莱斯勒、福特和通用汽
车为建立一套通用的零件资质及质量系统标准而设立的汽车电子委员会（AEC）制定。
AEC-Q标准包括多个子标准，如AEC-Q100（集成电路IC）、AEC-Q101（离散半导体元件，如二极管，三极管）、AEC-Q102（离散光电LED）、AEC-Q104（多芯片组件）和AEC-Q200（被动元器件）等。
AEC-Q标准是国际通用的车规元器件产品验证标准，通过AEC-Q认证意味着产品能够应用于汽车上。
供应商只有在通过元器件相应标准中规定的所有测试项目后，才能声称产品已通过AEC-Q认证。
完整的AEC-Q验证项目
数量众多，且周期较长，因此指定时间表是为了确保测试按计划进行。
此外，AEC-Q100的工作温度等级分4个等级（AEC_Q100_Rev_H规范），AEC-Q100要求器件能够承受2KV人体放电模式 (HBM)，在边角引脚上能承受750V的带电器件模式 (CDM)，而在所有其它引脚上则能承受500V
的电压。
以上内容仅供参考，如需了解更多信息，建议查阅AEC-Q标准相关文献或
咨询该标准业内人士。
AEC-Q001
AEC - Q001 - Rev-CJuly 18, 2003GUIDELINES FORPART AVERAGETESTINGComponent Technical CommitteeAutomotive Electronics CouncilComponent Technical CommitteeAcknowledgmentAny document involving a complex technology brings together experience and skills from many sources. The Automotive Electronics Counsel would especially like to recognize the following significant contributors to the development of this document:Majdi Mortazavi DaimlerChryslerBrian Jendro DaimlerChryslerRobert V. Knoell Visteon CorporationGerald E. Servais Delphi Delco Electronics Systems - RetiredKevin Hankins Formerly with Delphi Delco Electronics SystemsNick Lycoudes MotorolaMark Gabrielle ON SemiconductorComponent Technical CommitteeGUIDELINES FOR PART AVERAGE TESTINGText enhancements and differences made since the last revision of thisdocument are shown as underlined areas.1. SCOPEThis guideline presents a statistically based method, called part average testing (PAT), for removing parts with abnormal characteristics (outliers) from the semiconductors supplied per AEC - Q100 and AEC - Q101. The test limits used in PAT are established based on a sample of the electrical testresults for that particular part with its unique design and processing. Each part design and itsassociated processing will show a unique distribution of test results for each test requirement and this data is the basis for establishing PAT limits. The principles described in this guideline are applicable to packaged or unpackaged die. For a further discussion of PAT and its possible use to provideKnown Good Die, see Appendix 1.1.1 PurposeThis guideline is intended to provide a general method for removing abnormal parts and thus improve the quality and reliability of parts supplied per AEC - Q100 and AEC - Q101. PAT is not intended tobe a requirement, unless specified in the applicable procurement document or specifically approvedby the user as a substitute for ELFR. The failures from ELFR and PAT do not always show a 1:1correlation.Meeting the intent of this guideline, either by performing this method or some other similar method, is highly recommended. History has shown that parts with abnormal characteristics significantlycontribute to quality and reliability problems. Use of this technique will also flag process shifts andprovide a source of rapid feedback that should prevent quality accidents.1.2 References1.2.1 Automotive1. AEC - Q100: Stress Test Qualification For Integrated Circuits2. AEC - Q101: Stress Test Qualification For Discrete Semiconductors1.2.2 MiscellaneousIglewicz, B. and Hoaglin, D.C., ASQC Basic References in Quality Control: Statistical Techniques,Volume 16: How to Detect and Handle Outliers, ASQC Quality Press, 1993, ISBN 0-87389-247-X.DaimlerChrysler Date Delphi Delco Electronics Systems Date Visteon Corporation Date Majdi Mortazavi Detlef Griessman Robert V. KnoellCopyright © 2003 by DaimlerChrysler, Delphi Delco Electronics Systems, and Vi s teon Corporation. This document may be freely reprinted with this copyright notice. This document cannot be changed without approval by the AEC Component Technical Committee.Component Technical Committee2. DEFINITIONS2.1 Important CharacteristicsDevice characteristics that could impact product quality and reliability. Characteristics that providethe most significant information about a part’s capability of working properly. For examples ofimportant characteristics, see Appendix 2. These characteristics may not necessarily affect the part’s ability to operate in the application.2.2Known Good Die (KGD)Unpackaged semiconductor devices that are at least as good as an equivalent packaged part.2.3 Lower Specification Limit (LSL)Lower specification limit specified on the device specification.2.4 Robust Mean and Robust SigmaStatistics calculated excluding outlying data. Outlying data is generally considered to be data that is more than 6 standard deviations away from the mean of the main distribution.An example of one generalized method of doing this is as follows:Exclude outliers by estimating the location and spread of the main distribution of parts. The usualMean and Sigma can be poor statistics because they are very sensitive to outliers. The use of theterm “Robust” is to indicate statistics that are insensitive to outliers.Robust Mean = Q2 [the median]Note 1: Q2 (Quartile 2) is the middle data point, if the sample size is an odd number. If the sample size is an even number, Q2 is the average of the two middle numbers.Robust Sigma = (Q3 - Q1) / 1.35Note 2: The 1.35 number is inexact for sample sizes less than 20. Q1 is the point 1/4 of the way through the ranked data and Q3 is the point 3/4 the way through the ranked data.2.5 Upper Specification Limit (USL)Upper specification limit specified on the device specification.3. PROCEDURE3.1 Setting The Test LimitsTest limits may be set in either a static or dynamic manner. The static limits are established based on an available amount of test data and used without modification for some period of time. The dynamic test limits are based on the static limits, but are established for each lot (or wafer in a lot) andcontinually change as each lot (or wafer) is tested. New PAT limits (both static and dynamic) must be established when wafer level design changes, die shrinks or process changes have been made.Component Technical Committee3.1.1 Static PAT limitsCollect test data from at least six part lots that have passed the test limits as defined by the devicespecification. Determine the robust mean and sigma values per test by randomly selecting the test data from a minimum of 30 parts from each lot (see Figure 1). If test data is wafer level data, select data from at least 5 die located in different areas of each wafer (at least 30 die per lot). Early inproduction of a part, when data from six lots is not available, data from characterization lots may be used. This data shall be updated as soon as production data is available. Set the test limits asfollows:Static PAT Limits = Robust Mean ± 6 Robust SigmaFigure 1: Determining Static PAT Limits3.1.1.1PAT limits should be used for all electrical tests if possible, but shall be established for at least 8important characteristics (see Appendix 2). PAT test limits shall not exceed the device specification limits and shall be reviewed and updated as required using current data during the first 6 months of production or the last 8 wafer lots, whichever occurs first. Older data shall not be used.3.1.1.2After 6 months the static PAT limits shall be reviewed and updated as needed on a quarterly (every 3month) basis.3.1.2 Dynamic PAT limitsDynamic PAT Limits are preferred over Static PAT Limits because the reference population is thesame as the parts being tested. Dynamic PAT can provide tighter limits without causing rejection of good parts because it does not have to consider the lot-to-lot variation that is part of Static PATLimits. Before dynamic limits can be established, static limits, as defined in section 3.1.1, must beestablished. Dynamic PAT limits are determined in the same manner as static PAT limits except that the limits are established using the data from the current lot (or wafer) of parts under test that have passed the static limits. To use this method, after the lot (or wafer) of parts have been tested to the static limits they must be held in a manner that allows further statistical analysis of the test data. This analysis establishes new tighter test limits for that particular lot (or wafer) and removes additionaloutliers (see Figure 2). Set the test limits as follows:Dynamic PAT Limits = Mean± 6 SigmaNote 3: Statistical values calculated for the particular lot (or wafer) after the parts in the lot have passed the static PAT limits.Component Technical CommitteeFigure 2: Determining Dynamic PAT LimitsComponent Technical CommitteeAPPENDIX 1: PART AVERAGE TEST LIMITSA1.Part Average Test (PAT) Limits represent the application of statistical techniques for the removal of abnormal parts during part level testing (see Figure 3). A device specification defines therequirements needed for the part to work properly in the application. Every part (part as used hererefers to a supplier part number) is built with a particular design and SPC controlled process that, ifprocessed correctly, will yield a certain consistent set of characteristic test results. PAT usesstatistical techniques to establish the limits on these test results. These test limits are set up toremove outliers (parts whose parameters are statistically different from the typical part) and shouldhave minimal yield impact on correctly processed parts from an SPC controlled process. This testmethodology is not limited to the standard device specification tests, but may also include extended operating tests (tests beyond the device specification requirements) to improve the ability to detectspecial abnormal conditions and increase the sensitivity of this testing technique. The only restriction on extended operating tests is that the test shall not reduce the reliability of the parts that pass thetest.A1.1The intent of PAT is to increase the quality and reliability of AEC - Q100 and AEC - Q101 parts by removing abnormal parts as early in the part manufacturing sequence as possible (possibly at wafer test). This should minimize costs related to customer support and failure analysis, and provide early feedback to prevent the occurrence of quality accidents.A1.2This method, if utilized to its full capability (with statistical limits for all part level electrical tests and proper extended operating condition tests), is capable of providing “electrically” Known Good Die for most semiconductor technologies. It should also be remembered that Known Good Die (as defined in section 2) requires more than part level electrical testing. It requires careful control of all otherassembly processes such as wafer sawing, die handling, packaging, ESD, etc.Test LimitsFigure 3: Graphical Representation of Part Average Test Limits and OutliersComponent Technical CommitteeAPPENDIX 2: ELECTRICAL TESTSA2.1 Tests Required For All Devices TypesTo meet the requirements of this procedure, the following tests shall use PAT limits during ATEtesting.A2.1.1 Pin Leakage TestUse the following measurement approach to establish the PAT limits for pin leakage. This test will verify that the device pins have normal junction characteristics with respect to substrate and withrespect to V DD in the case of CMOS components.a. With all pins grounded except the pin under test (PUT):1. Force -10µA into each pin, measure the forward biased junction voltage (V F1).2. For CMOS, also force +10µA into each pin, measure the forward biased junction voltage(V F1).3. Test V DD (V CC) separately with respect to the substrate using -10µA, measure theforward biased junction voltage (V F2).4. Statistically analyze this data to determine the mean for V F1 and V F2.b. With all pins grounded except the pin under test (PUT), and using the V F1 and V F2 valuesdetermined above, measure the leakage current:1. Apply -0.8 V F1 (80% of forward bias voltage) to each pin, measure the leakage current.2. For CMOS, also apply +0.8 V F1 to each pin, measure the leakage currents.3. Apply -0.8 V F2 to V DD (V CC), measure the leakage current.4. Statistically analyze this data to determine the leakage current PAT limits.Notes:4. After the conclusion of the final ATE test and following powering down, perform this testmethod to detect any possible damage that could have occurred during testing.5. This method can utilize gang testing methods if the combination of pins have a PAT leakagelimit that does not exceed 600ηA.6. Devices with pins that have pull-up or pull-down loads are excluded from the above testmethods. However, their impedance values used for testing must be based on PAT limits. A2.1.2 Standby Power Supply Current (I DD or I CC)A2.2 Additional Tests Required For Certain Device TypesA2.2.1 CMOS DevicesCMOS devices shall be I DDQ tested with at least 70% transistor-level coverage (TLC). If the device design is not capable of being I DDQ tested, then this requirement does not apply.Component Technical CommitteeA2.2.2 Linear and BICMOS Devicesa. Output breakdown voltage (BV CES or BV DSS).b. Output leakage (I CES or I DDS), measured at 80% of the breakdown voltage value.c. Output current drive (I OUT) and output voltage levels (V OUT).d. The CMOS portion of BICMOS devices shall be tested per section A2.2.1.A2.3 Examples of Additional TestsThe following are examples of tests whose parameter variations have shown a correlation to poorcomponent quality and reliability in some integrated circuits. This is not a comprehensive list, and is offered only as a suggested list to be considered. Other tests deemed more important or morerelevant to a particular device should also be included in Part Average Testing.A2.3.1 Voltage Stress (V s)This test forces failures in silicon MOS type devices (e.g., NMOS, PMOS, CMOS, and DMOS, etc.) that have gate oxide and other related defects. To force failures that would occur within the power on time (t A) during the test time (t S), the test voltage stress (V S) must be greater than the maximumoperating voltage (V A). The supplier is encouraged to use his experience on his processes/designs to determine this voltage. One equation that could be used to determine this voltage is as follows (this equation does not consider temperature, gate-aided drain/source breakdown and other potentiallylimiting factors):V S= V A + (d ox / γ) * log10 (t A / t s) volts or= V A + 0.5 V A whichever is greater (see Note 7)where:d ox = nominal gate oxide thickness in Angstromsγ = electrical field acceleration coefficient= 700 Angstroms • log10 decade of time / voltst A = power on time in secondsV A = maximum operating voltaget S = test time in secondsFor example if:V A = 5 volts (max. operating voltage)d ox = 400 Angstromst A = 10 years (in seconds) with power on continuously (for an automotive application, 10 years of ignition-on in the field is equal to about 5,000 hours or approximately 18 x 106seconds of power on operation)t S = 0.1 secondthe suggested stress test voltage V s = 10.4 voltsNotes:7. This equation is a generalized equation applicable at room temperature and is not correctedfor elevated temperatures and other limiting factors.8. Fault coverage must be considered during voltage stress. For example, on CMOS devicesthe voltage is applied only to the transistors that are “on”. Two or more states may beComponent Technical Committeenecessary to force a stress voltage on a high proportion of gate oxides. The supply voltageshould be raised to V S for the duration t s in each of these states.9. The voltage stress test V S supply current must be limited to insure proper operation of thetest (1 ma is generally a good limit).10. The voltage stress test must be followed by functional and parametric tests using PAT limitsto detect the outlier parts.11. To avoid wear-out V S must be less than5 volts / 100 Angstroms.12. It must be demonstrated that the stress voltage does not adversely affect the reliability of thepart. The reliability of the ICs can be demonstrated by passing the HTOL, ESD and Latch-uptesting as specified in AEC - Q100 Tables 1 & 2. The reliability of discrete devices can bedemonstrated by passing ESD, and HTGB testing per AEC - Q101.A2.3.1.1 The following references provide the basis for the Voltage Stress Test guidelines contained above:a. D. L. Crook, “Method of Determining Reliability Screens for Time Dependent Breakdown”,Proceedings of The International Reliability Physics Symposium, 1979, pp. 1 - 7.b. A. Berman, “Time-Zero Dielectric Reliability Test by a Ramp Method”, Proceedings of TheInternational Reliability Physics Symposium, 1980, pp. 204 - 209.c. EIA/JEDEC Publication EIA/JEP122 “Failure Mechanisms and Models for SiliconSemiconductor Devices”.A2.3.2 Low Level Input Current (I I L)A2.3.3 High Level Input Current (I IH)A2.3.4 Propagation Delay or Output Response TimeA2.3.5 Rise/Fall TimesA2.3.6 Low Level Output Voltage (V OL)A2.3.7 High Level Output Voltage (V OH)A2.3.8 Extended Operating TestsExtended operating tests are tests beyond the device specification requirements intended to increase the effectiveness of PAT. These are the type of tests that, combined with PAT testing of more device characteristics, can make part level testing capable of providing parts with very high quality andreliability (Known Good Die). PAT limits shall be established for each extended operating test. The following are some examples of extended operating tests:• Low/High temperature• Low/High voltage operation• Dwell time at high voltage• Operating frequencies above/below specification requirements• For power devices, demonstration of safe operating capability (60% of safe operating limit) followed by leakage testing, etc.Note 13: The only restriction on these tests is that it must be demonstrated that the test does not adversely affect the reliability of the part. The reliability of the part can be demonstratedby passing the electrical qualification tests as specified in AEC - Q100 (for ICs) and AEC- Q101 (for discrete semiconductors).AEC - Q001 Rev-CJuly 18, 2003Component Technical Committee Automotive Electronics CouncilPage 9 of 9 Revision History Rev # - A B C Date of changeJuly 31, 1997Oct. 8, 1997Aug. 25, 2000July 18, 2003Brief summary listing affected sections Initial Release. Paragraph 2.1 revised, Figure 2 changed, Appendix 2 added new paragraph 2.1, added Appendix 3. Revised 1.2.2, 3.1, 3.1.2, Appendix 1, and Appendix 3. Corrected formatting errors. Removed Appendix 3 and references to DE Histograms.。
AEC_Q100-006_rev_D
Component Technical CommitteeATTACHMENT 6AEC - Q100-006 REV-DELECTRO-THERMALLY INDUCED PARASITIC GATE LEAKAGE TEST(GL)Component Technical CommitteeAcknowledgmentAny document involving a complex technology brings together experience and skills from many sources. The Automotive Electronics Counsel would especially like to recognize the following significant contributors to the development of this document:Mark A. Kelly Delphi Delco Electronics SystemsComponent Technical CommitteeChange NotificationThe following summary details the changes incorporated into AEC-Q100-006 Rev-D: • Sections 3.5, 3.5.1, and 3.5.2: Deleted section title 3.5, Detailed Procedure. Changed section 3.5.1 to section 3.5 and section 3.5.2 to section 3.6.Component Technical CommitteeMETHOD - 006ELECTRO-THERMALLY INDUCED PARASITICGATE LEAKAGE (GL) TESTText enhancements and differences made since the last revision of thisdocument are shown as underlined areas.1. SCOPE1.1 DescriptionThe purpose of this specification is to establish a reliable and repeatable procedure for determiningsurface mount integrated circuit susceptibility to Electro-Thermally Induced Parasitic Gate Leakage(GL). This specification may also be used as an evaluation tool for determining the susceptibility ofcircuit designs, molding compounds, fabrication processes, and post mold cure processes to GL.1.2 Reference DocumentsNot applicable.1.3 Terms and DefinitionsThe terms used in this specification are defined as follows:1.3.1 Device FailureA condition in which a device does not meet all the requirements of the acceptance criteria, asspecified in section 5, following the GL test.1.3.2 DUTAn electronic device being evaluated for its sensitivity to GL.1.3.3 Electro-Thermally Induced Parasitic Gate Leakage (GL)A trapped-charge phenomenon affecting plastic encapsulated integrated circuits in varying degreesdepending upon circuit design, fabrication technology, molding compound, and post mold cure profile.The phenomena occurs at high temperature when an electric field (E-field) is present. GL results inyield losses during high temperature processes, especially those with heated air flow (e.g., hightemperature handling and IR reflow solder operations). The phenomena can be detected as anincrease in Icc, input leakage, pin parametrics degradation, or functional failure. GL does not causepermanent damage and can be reversed by a 4 hour unbiased bake at a temperature of 125 °C (or 2hours at 150 °C).DaimlerChrysler Date Delphi Delco Electronics Systems Date Visteon Corporation DateMajdi Mortazavi Detlef Griessman Robert V. Knoell Copyright © 2003 by DaimlerChrysler, Delphi Delco Electronics Systems, and Visteon Corporation. This document may be freely reprinted with this copyright notice. This document cannot be changed without approval by the AEC Component Technical Committee.Component Technical Committee1.3.4 Electro-Thermally Induced Parasitic Gate Leakage (GL) SensitivityA GL level resulting in device failure. Sensitivity will vary depending upon the design, layout,process, and materials used.2. EQUIPMENT2.1 Test ApparatusThe apparatus required for this test consists of a GL test fixture, high voltage power supply, andthermal chamber. Figure 1 shows an equivalent test setup.Figure 1: GL Test Fixture and Set-up2.1.1 GL Test FixtureA test fixture as illustrated in Figure 1 and Appendix A. Other equivalent test fixture configurationsmay be used, but the actual fixture must meet the following requirements:1. The tungsten probe must be at a height of2.5 ± 0.5 inches above the conductive base platesurface and allow for vertical movement to facilitate voltage adjustment.2. To ensure consistent test results, all test devices must be able to be repeatably placedwith leads in contact with the conductive base plate surface by using milled recesses orequivalent markings and shall be equidistant from the high voltage tungsten probe.Component Technical Committee2.1.2 High Voltage Power SupplyA high voltage DC power supply capable of generating 20,000 volts at both positive (+) and negative(-) polarities.2.1.3 Thermal ChamberAn oven (Thermotron oven Model 51.C-B or equivalent) capable of controlled heating to atemperature of 155 °C and having adequate space to accommodate the GL test fixture.2.2 Measurement EquipmentEquipment shall include a digital voltmeter and high voltage probe to verify conformance of the GLtest fixture and resulting electric field (E-field) to the requirements of this document as specified inFigure 2, section 3.4, and Appendix A.2.2.1 Digital VoltmeterDigital voltmeter capable of accurately measuring 0 to 20,000 volts DC with a minimum sensitivity of± 1 mV.2.2.2 High Voltage ProbeHigh voltage probe capable of accurately measuring 0 to 20,000 volts DC with input resistance of1000 MΩ and ± 2% accuracy (Fluke Model 80 K-40 or equivalent).3. TEST PROCEDURE3.1 Sample SizeA total of six (6) devices shall be evaluated for GL sensitivity: a sample of three (3) devices shall bestressed at a positive (+) GL exposure and a new sample of three (3) devices shall be stressed at anegative (-) GL exposure. The use of a new sample group of three (3) devices for each GL exposurepolarity is required. Test samples must be representative of the normal process for deliverable devices;samples shall not be subjected to any additional testing or preconditioning (e.g., burn-in, etc.).Devices used for GL testing shall be discarded and shall not be retested or considered as deliverable product. GL is typically a non-destructive phenomena; however, the process of GL testing and thepost-test bake, used to verify recovery, often results in changes to the molding compound and/or lead solderability characteristics rendering the devices unsatisfactory for shipment.3.2Test TemperatureEach sample group shall be subjected to a GL exposure at 155 °C.3.3 MeasurementsPrior to GL testing, complete initial DC parametric and functional testing (initial ATE verification) shall be performed per applicable device specification. If the applicable part drawing specifies an allowable parametric shift as failure criteria, a data log of each device shall be made listing the applicableparameter measurement values (e.g., supply current, pin leakages, etc.). The data log will becompared to the parameters measured during final ATE verification to determine the failure criteria ofsection 4.Component Technical Committee3.4 GL Stress ConditionsEach sample shall be subjected to an E-field voltage potential of positive (+) or negative (-) 400 volts. A new sample of three (3) devices shall be used for each E-field voltage polarity.3.5Fixture Preparationa. Place the GL test fixture in the thermal chamber and verify both are at room temperature (seeFigure 1 and Appendix A).b Ensure the high voltage power supply is OFF and connect the positive lead to the high voltagetungsten probe. Set the height of the tungsten probe to a level of 2.5 ± 0.5 inches above theconductive base plate surface.c. Connect the negative lead of the high voltage power supply to the conductive base plate.d. Place a setup device in the fixture (located where the actual test samples will be placed) suchthat the device leads are in contact with the conductive base plate surface.e. Make sure the voltage control is set to the minimum level. Turn the high voltage power supplyto the ON position.f. Place the positive lead of the high voltage probe at the center of, and in direct contact with, thetop surface of the setup device. Connect the negative lead of the high voltage probe to theconductive base plate. The high voltage probe body should extend at a 45° ± 5° angle awayfrom the conductive base plate surface (as depicted in Figure 2). This angle is critical to themeasuring of the E-field voltage potential. As the high voltage probe body is raised (exceedingthe 45° angle requirement) or lowered (falling below the 45° angle requirement), the measuredE-field voltage potential will vary significantly.g. Monitor the setup device's E-field voltage potential using the digital voltmeter. Adjust thevoltage setting on the high voltage power supply to provide a positive (+) 400 volt E-field voltagepotential, or negative (-) 400 volt E-field voltage potential depending on the desired GLexposure, measured at the center of the setup device's top surface.h. Turn the high voltage power supply switch to the OFF position.i. Verify that the high voltage power supply is at zero (0) volts before touching the GL test fixture.j. Remove the setup device from the GL test fixture.Component Technical CommitteeFigure 2: Measurement Angle Used to Monitor E-field Voltage3.6 Detailed Test Procedurea. Ensure the high voltage power supply is OFF. Place a sample group of three (3) devices in theGL test fixture such that the device leads are in contact with the conductive base platesurface. All devices must be at the same distance from the high voltage tungsten probe as thesetup device used in section 3.5.1.b. Set the thermal chamber temperature to 155 °C. The use of a thermocouple placed in directcontact with the GL test fixture conductive base plate surface may be used to monitor thetemperature of the sample group devices.c. Verify the test sample devices are at the specified temperature. Allow the test fixture andsample group of three (3) devices to stabilize at the specified temperature for 15 minutes.d. Turn the high voltage power supply switch to the ON position.e. Allow the devices and GL test fixture (with the E Field voltage applied) to soak for a 2 minutedwell time as indicated in Figure 3.f. After 2 minutes of the total dwell time have elapsed, begin reducing the thermal chambertemperature to 100 °C or less with the E-field voltage still applied. This can beaccomplished by opening the thermal chamber door while the circulating fans are operating.Thermal chamber heating and cooling times will vary and a longer ramp-down time may berequired when reducing the thermal chamber temperature. The total ramp-down time (155°C to 100 °C) shall not exceed 10 minutes (see Figure 3).Component Technical Committeeg. Once the sample group of three (3) devices reaches a temperature of 100 °C, turn the highvoltage power supply switch to the OFF position. A thermocouple placed in direct contactwith the GL test fixture conductive base plate surface may be used to monitor thetemperature of the sample group devices.h. Verify the high voltage power supply is at zero (0) volts before touching the GL test fixture.i. After cooling to room temperature, remove the sample group of three (3) devices from the GLtest fixture.j. Submit the devices for complete DC parametric and functional testing (final ATE verification) per applicable device specification within 96 hours of GL exposure and determine whether the devices meets the acceptance criteria requirements specified in section 5. The storagetemperature between GL exposure and final ATE verification shall not exceed 30 °C.k. Subject all failing devices to an unbiased bake of 4 hours at a temperature of 125 °C (or 2 hours at 150 °C) and then submit for complete DC parametric and functional testing (ATE re-verification). GL failures will always recover when subjected to a 4 hour unbiased bake at 125 °C (or 2 hours at 150 °C). If the failing devices do not recover following the unbiased bake,then the devices may have been damaged (due to handling, EOS, ESD, etc.). Failing devices that do not recover shall be eliminated from the GL data.l. Record pass/fail and any other pertinent observations for each device.m. Reverse the high voltage power supply polarity, verify the E-field voltage potential (as specified in section 3.5.1), and repeat steps (a) through (l) above using a new sample group of three (3) devices.Figure 3: Dwell Time and Ramp-Down Time for GL TestComponent Technical Committee4. FAILURE CRITERIAA device will be defined as a failure if, after exposure to GL, the device fails any of the following criteria:1. The device exceeds the allowable shift value. Specific parameters and allowable shift valuesshall be as defined in the applicable device specification. During initial ATE verification, a datalog shall be made for each device listing the applicable parameter measurement values. Thedata log will be compared to the parameters measured during final ATE verification todetermine the shift value. Devices exceeding the allowable shift value will be defined as afailure.2. The device no longer meets the device specification requirements. Complete DC parametricand functional testing shall be performed per applicable device specification.5. ACCEPTANCE CRITERIAA device passes a GL exposure level if all devices in the sample group stressed at that GL level pass.All the devices and sample groups used must pass the measurement requirements specified in section3 and the failure criteria requirements specified in section4 following both positive (+) and negative (-)400 volt E-field exposures in order for the devices to be considered acceptable.Component Technical CommitteeAppendix A(suggested GL test fixture)This appendix provides suggested general construction features of the GL test fixture. Other equivalent test fixture configurations may be used, but the actual fixture must meet the requirements of section 2.1.1. The dimensions shown are approximate and are not critical to the test fixture construction. Figures A1 through A5 illustrate the GL test fixture assembly and major components.Note:Attach High VoltageWarning Label totest fixtureFigure A1: GL Test Fixture AssemblyComponent Technical CommitteeFigure A2: Conductive Base PlateThe base plate is constructed from electrically conductive material (e.g., .125 - .250 inch aluminum stock). The plate is approximately 6 inches square and serves to support and locate the devices under test and as one pole of the test voltage. Milled recesses may be used for repeatable device placement during GL testing (see Figures A1 and A2). The suggested recesses may be milled directly into the plate to ensure consistent device placement and orientation with respect to the tungsten probe center-line. The recesses, large enough to accommodate the largest device to be tested, are located 120 degrees apart and equidistant from the center of the base plate. The absolute distance from center (approximately one inch) is not critical.The lower left hand corner (dashed line section) is cut off on a diagonal to facilitate device handling and to reduce thermal mass. A lower post section, or leg, is added to the diagonal side for stability (see FigureA1).Note: The aluminum plate should be alodine coated for protection against corrosion and to retain electrical quality.Component Technical CommitteeFigure A3: Top Insulating PlateThe top insulating plate serves to support and locate the tungsten probe at the center of the GL test fixture. It establishes and maintains the probe to device distance during set-up and test. The top plate is fabricated from a triangular piece of .250 inch Teflon, Delrin, or other insulating material which is capable of withstanding an environment of 200 °C and ± 20,000 volts.A .049 inch diameter hole, used to position the tungsten probe, is centered on the diagonal side so as to be directly above the base plate center point after assembly. Clearance holes are drilled at each corner for assembly screws.Component Technical Committee60 degreeradius.049 "approximately 4 "Figure A4: Tungsten ProbeGrind a 60 degree point on a 4 inch length of 0.049 inch diameter tungsten wire (or a diameter of tungsten wire that is readily available; the diameter of the wire is not critical). This will provide an E-field potential at the specified test voltage, as measured on the top surface of the device approximately 2 inches from the tungsten probe point.Figure A5: Tungsten Probe Clamping MechanismComponent Technical CommitteeRevision HistoryRev #-A B C D Date of changeJune 9, 1994May 15, 1995Sept. 6, 1996Oct. 8, 1998July 18, 2003Brief summary listing affected sectionsInitial ReleaseAdded Copyright statement. Revised the following: Foreword; Sections2.1.2,3.1, 3.2.2 (d, f, and g), and 3.2.3 (a, b, c, f, g, and l); Figures 1, 2,and 3; Appendix A.Deleted old Sections 1.3.3, 1.3.4, 1.3.5, 1.3.6, 1.3.7, 2.1.1, 3.1, 3.2.1, 3.3,3.4, 3.5, and 3.6. Added new Sections 1.3.1, 1.3.4, 2.2, 2.2.1, 2.2.2, 3.1,3.2, 3.3, 3.4, and 5.0. Revised the following: Sections 1.1, 1.3, 1.3.2, 1.3.3,2.1, 2.1.1, 2.1.2,3.5.1 (a, e, f, g, h, and i), 3.5.2 (a, b, c, e, f, g, h, i, j, k, l,and m), 4.0, and Appendix A; Figures 1, 2, 3, A1, and A2.Revised the following: Sections 3.4, 3.5.1 (g), 5; Figure 1. Revisions reflecta change in E-field requirement from ±700 volt to ±400 volt.Revised the following: Sections 3.5, 3.5.1, and 3.5.2.。
aec-q103标准
aec-q103标准
AEQ-Q103标准是汽车电子质量可靠性评估标准的一部分。
它
是由汽车电子工程协会（Automotive Electronics Council，AEC）制定的，旨在确保汽车电子产品的质量和可靠性。
该标准主要适用于汽车电子产品的设计和制造过程中的质量保证。
它包含了一系列的要求和测试方法，以确保汽车电子产品在各种使用环境和条件下能够稳定运行并满足安全性和可靠性要求。
AEQ-Q103标准涵盖了多个方面，包括产品设计和开发规范、
可靠性测试方法、生产过程控制和验证要求等。
它要求汽车电子产品在设计阶段考虑到可靠性问题，并进行相应的验证和测试，以确保其满足可靠性要求。
同时，它还要求制造商建立严格的生产过程控制和质量管理体系，以确保产品在生产过程中的一致性和可靠性。
AEQ-Q103标准对汽车电子产品的可靠性测试也提出了详细的
要求，包括温度循环测试、湿热循环测试、机械冲击测试等。
这些测试旨在模拟汽车电子产品在使用过程中可能遇到的各种应力和环境条件，以评估其在实际使用中的可靠性。
AEQ-Q103标准的实施有助于提高汽车电子产品的质量和可靠性，减少故障率和维修成本，提升用户满意度。
同时，它也为汽车电子产品的设计和制造提供了一个统一的标准和指导，有助于提高产业的整体水平和竞争力。
ARC-QM-031《管理评审报告》●完成.(2010年四月)docx
4.3评价或初步结论
本公司服务质量的满意度和用户投诉处理情况有较大改善。目前，尚未发生质量事故和客户投诉情况。
5、质量管理体系对环境的适宜性、充分性、有效性的评价
5.1现状
a）本公司推行质量体系以来，公司内存在一些问题：与市场接轨意识不强，目的不明确，对文件控制不知如何操作，质量记录不知如何正确填写，程序不熟悉、不习惯，对质量方针、质量目标不理解等问题。
2、目前一段时间内，本公司的质量管理体系无重大变化或调整；
3、质量管理体系的过程及相应的文件体系是否需要修正按当时的实际情况处理；
4、质量方针、目标具有先进性，是适宜和有效的，正在努力实现暂时无需要更新；
5、资源配置目前基本适宜，但人力资源略显不足，需要进一步加强、引进或培训业务骨干，充实人力资源管理；
6、质量管理体系运行基本正常、有效；但还不够充分，距离目标还有一定的差距，责成质量管理部透过年度内/外审核抓紧落实并整改完毕；
7、2010年借公司流程优化和ISO9001：2008的推行，不断改进和落实，在运行中发现问题，解决问题，使职责更加明确，机构更加合理，流程更加规范，运行更加有效，从而为公司战略目标的实现打下坚实的基础。
b）通过内审，公司领导高度重视，结合考核办法，强行内部推广实施，使各部门贯标工作有了较大的改变。（见内审报告）
c）明确了各级人员各自的要求：
① 对每个员工的要求：在运行中，每个员工基本上都能熟悉并理解公司的质量方针，目标，所在部门职能，并明确了本人的质量职责和权限，清楚本人的工作所依据的文件，熟练撑握自己的工作技能。
2）还有很多工作还有不尽完善的地方，存在质量记录的使用，不完整，还有些历史遗留的表格没有统一的编号，我们的质量手册和程序文件在以后的工作中还有待进一步完善。
aecq标准关于高压组件
aecq标准关于高压组件AECQ标准是国际汽车电子协会的车规验证标准，包括多个子标准，其中与高压组件相关的标准是AEC-Q101。
AEC-Q101是针对离散组件的可靠性验证标准，其中涉及到高压组件的验证。
该标准要求高压组件在承受高电压、大电流等极端条件下，仍能保持稳定的性能和可靠性，以确保汽车电子系统的安全和可靠性。
具体来说，AEC-Q101对高压组件的验证包括以下几个方面：1. 耐压测试：测试高压组件在承受高电压时的稳定性和耐久性，以确保其在极端条件下不会发生击穿或短路等故障。
2. 绝缘测试：测试高压组件的绝缘性能，以确保其在高电压下不会产生漏电或电击等危险情况。
3. 热性能测试：测试高压组件在高温环境下的性能和稳定性，以确保其在高温下不会发生热失控或烧毁等故障。
4. 耐腐蚀测试：测试高压组件在恶劣环境下的耐腐蚀性能，以确保其在恶劣环境下不会发生腐蚀或老化等故障。
5.机械振动测试：高压组件在汽车电子系统中，需要承受各种机械振动，因此需要进行机械振动测试。
这一测试旨在验证高压组件在振动环境下性能的稳定性和可靠性，确保其在实际使用过程中不会因振动而导致故障。
6.电磁兼容性测试：汽车电子系统中的高压组件需要与其他电子元件共同工作，因此需要具备良好的电磁兼容性。
电磁兼容性测试旨在验证高压组件在电磁干扰环境下性能的稳定性和可靠性，确保其不会对其他电子元件产生干扰，也不会受到其他元件的干扰。
7.寿命周期测试：高压组件在汽车电子系统中的使用寿命至关重要。
寿命周期测试旨在模拟实际使用环境，验证高压组件在长时间运行过程中的性能稳定性和可靠性，确保其在使用寿命内保持良好的工作状态。
8.封装和材料测试：高压组件的封装和材料对其性能和可靠性具有重要影响。
封装和材料测试旨在验证高压组件的封装和材料是否具备足够的强度、耐热性、耐腐蚀性等性能，以确保其在极端环境下的稳定性。
9.失效模式分析：失效模式分析是对高压组件在各种工况下可能出现的失效模式进行研究，以便在设计阶段就消除潜在的故障隐患。
AEC-Q100简表
附加要求 仅用于表面贴器件
附加要求
ESD22-A108
附加要求
附加要求
附加要求
附加要求
附加要求
NVM）集成电路或带有NVM的集成电路进行预处理
的温度和极限参数范围内进行
故障分级 特性描述 电热效应引起的 栅漏 电磁兼容 短路特性描述 软错误率
FG CHAR GL EMC SC SER
E6 E7 E8 E9 E10 E11
6 1 10 3
-
见AECQ100-007 AEC-Q100-007 第4节 AEC-Q003 1 0 Fails 13 0 Fails 1AEC-Q100-006 SAE J1752/3-辐射 AEC-Q100-012 JEDEC 无加速：JESD89-1 加速：JESD89-2或 JESD89-3
Cpk〉1.33 Ppk>1.67
AEC-Q100 001
绑线拉力
WBP
C2
可焊性
SD
C3
Cpk〉 1.33 最少5个器件中 Ppk>1.67 的30个绑线 或温度循 环 （#A4） 后0 Fails >95%引脚 15 1 覆盖
MIL-STD883 method 2011
JEDEC JESD22B102
Group F Test(针对芯片产品测试过程的缺陷筛选指南) 每批样 应力测试 缩写 编号 批数 接受标准 遵循的测试规范 品个数 部件平均测试 PAT F1 AEC-Q001 统计良率分析 SBA F2 AEC-Q002 Group G Test(针对芯片产品封装过程后的封装完整性测试) 每批样 应力测试 缩写 编号 批数 接受标准 遵循的测试规范 品个数 JEDEC JESD22机械冲击 MS G1 39 3 0 Fails B104 JEDEC JESD22变频振动 VFV G2 39 3 0 Fails B103 MIL-STD883 恒加速应力 CA G3 39 3 0 Fails Method 2001 MIL-STD883 粗/细气漏 GFL G4 39 3 0 Fails Method 1014 跌落测试 DROP G5 5 1 0 Fails MIL-STD883 盖板扭力测试 LT G6 5 1 0 Fails Method 2024 MIL-STD883 芯片切断 DS G7 5 1 0 Fails Method 2019 MIL-STD883 内部水蒸气含量 IWV G8 3 1 0 Fails Method 1018
模拟温度传感器
目录
1 特性.......................................................................... 1 2 应用.......................................................................... 1 3 说明.......................................................................... 1 4 修订历史记录 ........................................................... 2 5 Device Comparison Tables................................... 3 6 Pin Configuration and Functions ......................... 3 7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings ..................................... 4 7.2 ESD Ratings – LMT85 .............................................. 4 7.3 ESD Ratings – LMT85-Q1 ........................................ 4 7.4 Recommended Operating Conditions....................... 5 7.5 Thermal Information .................................................. 5 7.6 Accuracy Characteristics........................................... 6 7.7 Electrical Characteristics .......................................... 6 7.8 Typical Characteristics ............................................. 7 8 Detailed Description .............................................. 9 8.1 Overview ................................................................... 9 8.2 Functional Block Diagram ......................................... 9
AEC-Q004
AEC-Q004概述AEC-Q004（汽车电子委员会质量说明标准Q004）是一项汽车行业标准，由汽车电子委员会（AEC）制定，用于评估和验证汽车电子产品的质量和可靠性。
AEC-Q004旨在确保汽车电子产品在极端环境和恶劣条件下的稳定性和可靠性，以满足严格的汽车行业要求。
AEC-Q004的重要性随着汽车行业的快速发展和电子技术在汽车中的广泛应用，电子产品的质量和可靠性对于汽车的性能和安全性愈发重要。
AEC-Q004的实施可以有效地确保汽车电子产品在高温、低温、湿度、机械振动和电磁干扰等各种极端条件下的稳定性和可靠性。
AEC-Q004的要求AEC-Q004包含了一系列对汽车电子产品质量的要求和测试方法，以下是该标准主要要求的概述：温度要求AEC-Q004对于汽车电子产品在各种温度条件下的运行和耐受能力提出了严格要求。
测试时，电子产品需要经受高温和低温环境的长时间暴露，并要求其功能、性能和可靠性在极端温度环境下也能得到保证。
湿度要求汽车电子产品通常会面临高湿度的工作环境，例如车辆进入雨天或者高湿度地区。
AEC-Q004要求相关电子产品应具备良好的湿度防护措施，能够在高湿度环境下保证正常运行，并能有效防止湿度引起的故障，以确保驾驶人员和乘客的安全。
机械振动要求汽车行驶时会受到各种不同频率和振幅的机械振动，因此，汽车电子产品需要能够在这些振动环境下稳定工作。
AEC-Q004对于汽车电子产品的机械振动性能进行了详细的测试和要求，以确保其在行驶过程中能够正常工作，并在振动环境下不会发生故障。
电磁干扰要求汽车内部存在着各种电磁干扰源，例如发动机系统、无线通信设备等。
AEC-Q004要求汽车电子产品具备抗电磁干扰的能力，并能在这些干扰源存在的环境下正常工作。
相关测试包括辐射干扰和传导干扰的评估，以保证汽车电子产品的可靠性和稳定性。
如何达到AEC-Q004的要求要达到AEC-Q004的要求，汽车电子产品制造商需要采取一系列措施和测试。
2023年3~4月国外消费品召回信息汇总
信息汇总此栏目内容由国家市场监督管理总局缺陷产品管理中心权威发布并分析● 2023年3月国外消费品召回及中国生产产品召回情况电子电器儿童用品家具家用日用百货其他交通运输设备日用纺织品和服装文教体育用品其他合计总次数559985888514255其他国产品213472276310110中国产品34651361224145总数量5807433287781104100810720843455390525303639413511341032其他国产品6521399012240080694084270464051915362921357346417中国产品51553032778808170037807575006150● 2023年3月国外消费品召回涉及伤害类别概况产品伤害类别触电危险火灾危险健康危险烧伤危险溺水危险受伤危险窒息危险中毒危险烫伤危险摔伤危险共计总数19301001526035118271其他国产品91630612520105113中国产品10147091351513158注：产品伤害类别中，同一召回存在多种类别危险的情况，统计总数大于召回次数。
● 2023年3月国外消费品召回次数统计电子电器儿童用品家具家用日用百货其他交通运输设备日用纺织品和服装文教体育用品其他合计美国9824532740欧盟38865530507194日本110000103澳大利亚7411302018合计55（22%）99（39%）8（3%）58（23%）8（3%）8（3%）5（2%）14（5%）255（100%）● 2023年3月国外消费品召回数量统计电子电器儿童用品家具家用日用百货其他交通运输设备日用纺织品和服装文教体育用品其他合计美国571230328588010410081072084345539056150639413511310465欧盟不详不详不详不详不详不详不详不详不详日本95131901000019153030567澳大利亚不详不详不详不详不详不详不详不详不详合计580743（5%）3287781（29%）104100（1%）810720（7%）84345（1%）53905（1%）25303（8%）6394135（56%）11341032（100%）信息汇总欧盟消费品召回● 2023年3月欧盟消费品召回及中国生产产品召回情况电子电器儿童用品家具家用日用百货日用纺织品和服装其他合计总次数38（28%）86（44%）5（2%）53（27%）5（3%）7（4%）194（100%）其他国产品11285184470中国产品27583513124日本消费品召回● 2023年3月日本消费品召回及中国生产产品召回情况电子电器儿童用品文教体育用品合计总次数1（34%）1（33%）1（33%）3（100%）总数量9513（31%）1901（6%）19153（63%）30567（100%）● 2023年3月按不符合欧盟标准统计中国生产产品和其他国产品召回情况对比EN 14682欧盟玩具安全指令欧盟REACH法规其他项总计总数17405780194中国产品6324442124其他国产品118133870● 2023年3月欧盟消费品召回涉及伤害类别情况触电危险火灾危险健康危险烧伤危险受伤危险窒息危险烫伤危险共计总数161393552241204中国产品9769332111132其他国产品76242201372注：产品伤害类别中，同一召回存在多种类别危险的情况，统计总数大于召回次数。
AECQ101中文标准规范
AECQ101中文标准规范本文介绍了AEC-Q101基于离散半导体元件应力测试认证的失效机理，旨在确保汽车电子元器件在极端条件下的可靠性。
以下是相关附录和测试方法。
附录1：认证家族的定义认证家族是指一组基于相同标准和测试方法的认证测试。
AEC-Q101认证家族包括多种测试，如人体模式静电放电测试和邦线切应力测试等。
附录2：Q101设计、构架及认证的证明该附录详细介绍了Q101认证的设计和构架，并提供了证明文件，以确保测试结果的准确性和可靠性。
附录3：认证计划该附录列出了AEC-Q101认证的计划，包括测试的时间表和所需的资源。
附录4：数据表示格式该附录定义了数据表示格式，以确保测试结果的一致性和可比性。
附录5：最小参数测试要求该附录列出了最小参数测试要求，以确保测试结果的准确性和可靠性。
附录6：邦线测试的塑封开启该附录介绍了邦线测试的塑封开启方法，以确保测试结果的准确性和可靠性。
附录7：AEC-Q101与健壮性验证关系指南该附录提供了AEC-Q101认证与健壮性验证之间的关系指南，以确保测试结果的一致性和可靠性。
附件：AEC-Q101-001：人体模式静电放电测试该测试方法用于评估元器件在人体模式静电放电条件下的耐受性。
AEC-Q101-003：邦线切应力测试该测试方法用于评估元器件在邦线切应力条件下的耐受性。
AEC-Q101-004：同步性测试方法该测试方法用于评估元器件在同步性条件下的耐受性。
AEC-Q101-005：静电放电试验–带电器件模型该测试方法用于评估元器件在静电放电条件下的耐受性。
AEC-Q101-006：12V系统灵敏功率设备的短路可靠性描述该测试方法用于评估12V系统灵敏功率设备在短路条件下的可靠性。
最后，我们感谢以下人员对该版文件的重大贡献：固定会员XXX Forster、Mark A。
Kelly、Drew Hoffman、XXX XXX、XXX和XXX XXX，以及技术成员XXX、XXX。
AEC-Q101中文标准规范
基于离散半导体元件应力测试认证的失效机理内容列表AEC-Q101 基于离散半导体元件应力测试认证的失效机理附录1: 认证家族的定义附录2: Q101 设计、构架及认证的证明附录3: 认证计划附录4: 数据表示格式附录5: 最小参数测试要求附录6: 邦线测试的塑封开启附录7: AEC-Q101与健壮性验证关系指南附件AEC-Q101-001: 人体模式静电放电测试AEC-Q101-002: 人体模式静电放电测试 (废止)AEC-Q101-003: 邦线切应力测试AEC-Q101-004: 同步性测试方法AEC-Q101-005: 静电放电试验–带电器件模型AEC-Q101-006: 12V系统灵敏功率设备的短路可靠性描述感谢任何涉及到复杂的技术文件都来自于各个方面的经验和技能。
为此汽车电子委员会由衷承认并感谢以下对该版文件有重大贡献的人：固定会员:Rick Forster Continental CorporationMark A. Kelly Delphi CorporationDrew Hoffman Gentex CorporationSteve Sibrel HarmanGary Fisher Johnson ControlsEric Honosowetz Lear Corporation技术成员:James Molyneaux Analog DevicesJoe Fazio Fairchild SemiconductorNick Lycoudes FreescaleWerner Kanert InfineonScott Daniels International RectifierMike Buzinski MicrochipBob Knoell NXP SemiconductorsZhongning Liang NXP SemiconductorsMark Gabrielle ON SemiconductorTom Siegel Renesas TechnologyTony Walsh Renesas TechnologyBassel Atallah STMicroelectronicsArthur Chiang VishayTed Krueger [Q101 Team Leader]Vishay其他支持者:John Schlais Continental CorporationJohn Timms Continental CorporationDennis L. Cerney International RectifierRene Rongen NXP SemiconductorsThomas Hough Renesas TechnologyThomas Stich Renesas Technology本文件是专门的纪念：Ted Krueger (1955-2013)Mark Gabrielle (1957-2013)注意事项AEC文件中的材料都是经过AEC技术委员会准备、评估和批准的。
AEC_Q101中文标准规范
組件技術委員會基于离散半导体元件应力测试认证的失效机理組件技術委員會内容列表AEC-Q101 基于离散半导体元件应力测试认证的失效机理附录1: 认证家族的定义附录2: Q101 设计、构架及认证的证明附录3: 认证计划附录4: 数据表示格式附录5: 最小参数测试要求附录6: 邦线测试的塑封开启附录7: AEC-Q101与健壮性验证关系指南附件AEC-Q101-001: 人体模式静电放电测试AEC-Q101-002: 人体模式静电放电测试 (废止)AEC-Q101-003: 邦线切应力测试AEC-Q101-004: 同步性测试方法AEC-Q101-005: 静电放电试验–带电器件模型AEC-Q101-006: 12V系统灵敏功率设备的短路可靠性描述組件技術委員會感谢任何涉及到复杂的技术文件都来自于各个方面的经验和技能。
为此汽车电子委员会由衷承认并感谢以下对该版文件有重大贡献的人：固定会员:Rick Forster Continental CorporationMark A. Kelly Delphi CorporationDrew Hoffman Gentex CorporationSteve Sibrel HarmanGary Fisher Johnson ControlsEric Honosowetz Lear Corporation技术成员:James Molyneaux Analog DevicesJoe Fazio Fairchild SemiconductorNick Lycoudes FreescaleWerner Kanert InfineonScott Daniels International RectifierMike Buzinski MicrochipBob Knoell NXP SemiconductorsZhongning Liang NXP SemiconductorsMark Gabrielle ON SemiconductorTom Siegel Renesas TechnologyTony Walsh Renesas TechnologyBassel Atallah STMicroelectronicsArthur Chiang VishayTed Krueger [Q101 Team Leader]Vishay其他支持者:John Schlais Continental CorporationJohn Timms Continental CorporationDennis L. Cerney International RectifierRene Rongen NXP SemiconductorsThomas Hough Renesas TechnologyThomas Stich Renesas Technology本文件是专门的纪念：Ted Krueger (1955-2013)Mark Gabrielle (1957-2013)組件技術委員會注意事项AEC文件中的材料都是经过AEC技术委员会准备、评估和批准的。
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AECQ信息汇总
标签: AECQ汇总2010-03-15 14:43
最近在整理元器件方面的资料，涉及ROSH与AECQ的信息，下面整理了AECQ的信息。
克莱斯勒、福特和通用汽车为建立一套通用的零件资质及质量系统标准而设立了汽车电子委员会(AEC)，AEC 是“Automotive Electronics Council：汽车电子协会”之略，是主要汽车制造商与美国的主要部件制造商汇聚一起成立的、以车载电子部件的可靠性以及认定标准的规格化为目的的团体，AEC建立了质量控制的标准。
同时，由于符合AEC规范的零部件均可被上述三家车厂同时采用，促进了零部件制造商交换其产品特性数据的意愿，并推动了汽车零件通用性的实施，为汽车零部件市场的快速成长打下基础。
主要的汽车电子成员有：Autoliv, Continental, Delphi, Johnson Controls 和 Visteon。
AEC-Q100：
主要用于预防产品可能发生各种状况或潜在的故障状态，引导零部件供货商在开发的过程中就能采用符合该规范的芯片。
AEC-Q100对每一个芯片个案进行严格的质量与可靠度确认，确认制造商所提出的产品数据表、使用目的、功能说明等是否符合最初需求的功能，以及在连续使用后个功能与性能是否能始终如一。
AEC-Q100标准的目标是提高产品的良品率，这对芯片供货商来说，不论是在产品的尺寸、合格率及成本控制上都面临很大的挑战。
AEC-Q100又分为不同的产品等级，其中第１级标准的工作温度范围在-40℃-125℃之间，最严格的第0级标准工作温度范围可达到-40℃-150℃。
0 等级：环境工作温度范围-40℃-150℃
1 等级：环境工作温度范围-40℃-125℃
2 等级：环境工作温度范围-40℃-105℃
3 等级：环境工作温度范围-40℃-85℃
4 等级：环境工作温度范围0℃-70℃
AEC - Q100 Rev - G base: 集成电路的应力测试标准（不包含测试方法） AEC-Q100-001 邦线切应力测试
AEC-Q100-002 人体模式静电放电测试
AEC-Q100-003 机械模式静电放电测试
AEC-Q100-004 集成电路闩锁效应测试
AEC-Q100-005 可写可擦除的永久性记忆的耐久性、数据保持及工作寿命的测试 AEC-Q100-006 热电效应引起的寄生闸极漏电流测试
AEC-Q100-007 故障仿真和测试等级
AEC-Q100-008 早期寿命失效率（ELFR）
AEC-Q100-009 电分配的评估
AEC-Q100-010 锡球剪切测试
AEC-Q100-011 带电器件模式的静电放电测试
AEC-Q100-012 12V 系统灵敏功率设备的短路可靠性描述
AEC - Q101 Rev - C: 分立半导体元件的应力测试标准（包含测试方法）
* AEC - Q101-001 - Rev-A: 人体模式静电放电测试
* AEC - Q101-002 - Rev-A: 机械模式静电放电测试
* AEC - Q101-003 - Rev-A: 邦线切应力测试
* AEC - Q101-004 - Rev-: 同步性测试方法
* AEC - Q101-005 - Rev-A: 带电器件模式的静电放电测试
* AEC - Q101-006 - Rev-: 12V 系统灵敏功率设备的短路可靠性描述
AEC - Q200 Rev - C: 半导体被动元件的应力测试标准（包含测试方法）
* AEC - Q200-001 - Rev-A: 阻燃性能测试
* AEC - Q200-002 - Rev-A: 人体模式静电放电测试
* AEC - Q200-003 - Rev-A: 断裂强度测试
* AEC - Q200-004 - Rev-: 自恢复保险丝测量程序
* AEC - Q200-005 - Rev-: PCB板弯曲/端子邦线应力测试
* AEC - Q200-006 - Rev-: 端子应力（贴片元件）/切应力测试
* AEC - Q200-007 - Rev-: 电压浪涌测试
AEC-Q001 零件平均测试指导原则
提出了所谓的参数零件平均测试(PPAT)方法。
PPAT是用来检测外缘半导体组件异常特性的统计方法，用以将异常组件从所有产品中剔除。
PPAT可分为静态PAT、动态PAT和地域性PAT。
地域性PAT即是为所有在晶圆上的裸晶加入邻近性权重，因此一些被不良裸晶包围或
邻近的良好裸晶，也可能会被剔除。
AEC-Q002 统计式良品率分析的指导原则
AEC-Q002基于统计原理，属于统计式良品率分析的指导原则。
AEC-Q002的统计性良品率分析(SYA)分为统计性良品率限制(SYL)和统计箱限制(SBL)两种。
这些方法通过对关键性测试参数建立一套分析和控制生产变量的系统，可用来检测出异常的材料区域，保证最终产品的质量和可靠性。
所有新组件或技术在制造程序前后的不同阶段都可进行统计分析，同时也能在晶圆测试及封装最后测试的阶段被用来进行电子参数测试。
AEC-Q002为组件制造商提供使用统计技巧来检测和剔除异常芯片组件的方法，让制造商能在晶圆及裸晶的阶段就能及早发现错误并将其剔除。
AEC-Q003 芯片产品的电性表现特性化的指导原则
产品及制程的特性表现对于开发新的芯片或对现有的芯片进行调整相当重要。
AEC-Q003是针对芯片产品的电性表现所提出的特性化指导原则，用来生成产品、制程或封装的规格与数据表，目的在于收集组件、制程的数据并进行分析，以了解此组件与制程的属性、表现和限制，检查这些组
件或设备的温度、电压、频率等参数特性表现。
AEC-Q004 零缺陷指导原则
定义芯片供货商或用户如何在产品生命周期中使用一些工具和制程来达成零缺陷的目标。
提出一系列的流程步骤，包括组件设计、制造、测试和使用，以及在这流程的各个阶段中采用何种呈零缺陷的工具或方法。
这些方法涵盖上述AEC的各种文件标准。
当零件或制程已实现最佳化，且成熟性在经过一段时间后被证实，此时只需用较少的工具就能改善或维持质
量和可靠性。
AEC-Q004并不是强制性的规范，而是提出用来降低缺陷的工具和方法。
不同的应用模式会需要不同的工具或生产方法，因此在此指导原则中提出了建议的做法。