BA3575中文资料
ASTM-D3574中文版
TEST D
Constant Deflection Compression Set Test
恒定压缩测试
前言
此项测试是事先将试样压缩到 规定的间距，进而将压制试样放 入特定氛围中保持一段时间后 将试样在特定环境中恢复形变，
测量试样前后的厚度变化
测试三个试样 最终数值应为三试样测试值的均值
Page 9
测试装置—— 压缩装置
该压缩装置由两块或者两块以上的平整面板并排组成， 板与板之间由螺栓固定而不至于产生相对滑动，平板 之间安放垫片保证相对的两块板是平行的状态。
Page 10
测试样品
1、试样的上表面和下表面应该是平行的，在试样边缘彼此 要互相垂直。
2、除非特殊要求，试样规格应为50*50*25mm，如果厚度不 够25mm的试样可以相互堆积起来，但是试样之间不能含有胶 水或者其他。
Page 5
测试方法
质量： 使用精确电子天平测量 试样质量，误差不超过1%
体积： 按照Section 8 试样测量
（见后表）中的方法准确 测量试样的尺寸，并计算体积
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Section 8——样品规格测量方法
1、使用标尺或者卷尺对试样的长度和宽度进行测量，注意测量时 不要挤压到泡棉；
6、之后取出压缩装置并将样品从中取出，将样品放在步骤1 中描述环境中让其自由恢复30-40min后（该时间也可按照客 户需要进行指定），按照Section8（TestA）测量试样的最 终厚度tf。
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计算
按照以下公式计算压缩残留形变值：
注：一般情况下，优先使用Ct的计算公式数值
Ct = [（to-tf）/to]*100 Cd = [（to-tf）/（to-
RO3075A;中文规格书,Datasheet资料
Electrical Characteristics CharacteristicSymNotesMinimumTypical MaximumUnitsCenter Frequency, +25 °C Absolute Frequency f C 2,3,4,5344.930345.07MHz Tolerance from 345.0 MHz∆f C ±70kHz Insertion Loss IL 2,5,6 1.3 1.7dBQuality Factor Unloaded Q Q U 5,6,7800050 Ω Loaded Q Q L 1000Temperature StabilityTurnover Temperature T O 6,7,8102540°C Turnover Frequencyf O f C Frequency Temperature CoefficientFTC 0.032ppm/°C 2Frequency AgingAbsolute Value during the First Year |f A |1≤10ppm/yr DC Insulation Resistance between Any Two Terminals51.0M ΩRF Equivalent RLC ModelMotional Resistance R M 5, 7, 914.1ΩMotional Inductance L M 57.7µH Motional Capacitance C M 4.11fF Shunt Static CapacitanceC O 5, 6, 9 4.2pF Test Fixture Shunt InductanceL TEST2, 749.8nHLid Symbolization (in addition to Lot and/or Date Codes)664 // YWWS•Designed for 345.0MHz Transmitters •Very Low Series Resistance •Quartz Stability•Surface-mount Ceramic Case•Complies with Directive 2002/95/EC (RoHS)The RO3075A is a true one-port, surface-acoustic-wave (SAW) resonator in a surface-mount, ceramic case. It provides reliable, fundamental-mode, quartz frequency stabilization of fixed-frequency transmittersoperating at 345MHz. This SAW is designed specifically for remote control and wireless security transmitters.Absolute Maximum Ratings RatingValueUnitsCW RF Power Dissipation (See: Typical Test Circuit)+0dBm DC Voltage Between Terminals (Observe ESD Precautions)±30VDC Case Temperature-40 to +85°C Soldering Temperature (10 seconds / 5 cycles maximum)260°C345.0 MHz SAW ResonatorRO3075ACAUTION: Electrostatic Sensitive Device. Observe precautions for handling.Notes:1.Frequency aging is the change in f C with time and is specified at +65 °C or less. Aging may exceed the specification for prolonged temperaturesabove +65 °C. Typically, aging is greatest the first year after manufacture, decreasing in subsequent years.2.The center frequency, f C , is measured at the minimum insertion loss point, IL MIN , with the resonator in the 50Ω test system (VSWR ≤ 1.2:1). The shunt inductance, L TEST , is tuned for parallel resonance with C O at f C . Typically, f OSCILLATOR or f TRANSMITTER is approximately equal to the resonator f C .3.One or more of the following United States patents apply: 4,454,488 and 4,616,197.4.Typically, equipment utilizing this device requires emissions testing and government approval, which is the responsibility of the equipment manufacturer.5.Unless noted otherwise, case temperature T C =+25±2°C.6.The design, manufacturing process, and specifications of this device are subject to change without notice.7.Derived mathematically from one or more of the following directly measured parameters: f C , IL, 3dB bandwidth, f C versus T C , and C O .8.Turnover temperature, T O , is the temperature of maximum (or turnover) frequency, f O . The nominal frequency at any case temperature, T C , may be calculated from: f =f O [1-FTC (T O -T C )2]. Typically oscillator T O is approximately equal to the specified resonator T O .9.This equivalent RLC model approximates resonator performance near the resonant frequency and is provided for reference only. The capacitance C O is the static (nonmotional) capacitance between the two terminals measured at low frequency (10MHz) with a capacitance meter. Themeasurement includes parasitic capacitance with "NC” pads unconnected. Case parasitic capacitance is approximately 0.05pF. Transducer parallel capacitance can by calculated as: C P ≈C O -0.05pF.10.Tape and Reel standard per ANSI / EIA 481.PbElectrical ConnectionsThe SAW resonator is bidirectional and may beinstalled with either orientation. The two terminalsare interchangeable and unnumbered. The calloutNC indicates no internal connection. The NC padsassist with mechanical positioning and stability.External grounding of the NC pads isrecommended to help reduce parasiticcapacitance in the circuit.Typical Test CircuitThe test circuit inductor, L TEST, is tuned to resonate with the static capacitance, C O, at F C.Typical Application Circuits Equivalent Model Temperature Characteristics The curve shown on the right accounts for resonator contribution only and does not include LC component temperature contributions.CaseDimensionsMillimeters InchesMin Nom Max Min Nom MaxA 4.87 5.00 5.130.1910.1960.201B 3.37 3.50 3.630.1320.1370.142C 1.45 1.53 1.600.0570.0600.062D 1.35 1.43 1.500.0400.0570.059E0.670.800.930.0260.0310.036 F0.370.500.630.0140.0190.024G 1.07 1.20 1.330.0420.0470.052H- 1.04--0.041-I- 1.46--0.058-J-0.50--0.019-K- 1.05--0.041-L- 1.44--0.057-M-0.71--0.028-PCB Land PatternTop View分销商库存信息: RFMRO3075A。
PB375A芯片说明书
3.1 引脚图
版本号：V1.1
第 3 页/共 21 页
深圳蓝色飞舞科技
PB375ADATASHEET
3.2 管脚描述
管脚号 管脚名
1
VDD33
7
VSS
12
VSS
14
VDD33
18
SDWP
19
SDCLK
20
SDCMD
21
SDDO
22
SDCD
23
RX
24
VSS
8.1 极限参数…………………………………………………………………………………17
8.2 电气参数…………………………………………………………………………………17
8.3. 时序参数 ………………………………………………………………………………18
9. 典型应用电路 ……………………………………………………………………………19
10.U 盘支持列表…………………………………………………………………………………20
11.技术支持 …………………………………………………………………………………20
版本号：V1.1
第 2 页/共 21 页
深圳蓝色飞舞科技
PB375ADATASHEET
1、 概述
当前信息化社会，U 盘（含闪盘、USB 闪存盘、USB 移动硬盘等）/SD 卡已经成为很常用 的移动存储设备，用来随身携带存储数据。所以在很多产品中需要读取或者保存数据，多数 采用方便快捷的存储方式。单片机系统可以直接采用 U 盘/SD 卡作为移动存储器，并且方便 与使用 WINDOWS 操作系统的计算机交换数据。由深圳蓝色飞舞科技独立开发的 PB375A U 盘 /SD 卡读写芯片作为一款高性价比的单芯片 U 盘/SD 卡读写解决方案，广泛应用于便携式仪 表设备的数据存储相关领域。
LTV-357T资料
FEATURES* Current transfer ratio( CTR : MIN. 50% at I F =5mA, V CE =5V )* High input-output isolation voltage( V iso =3,750Vrms )* High collector-emitter voltage( V CEO = 80V )* Employs double transfer mold technology* Subminiature type( The volume is smaller than that of conventional DIP type by as far as 30% ) * Mini-flat package :2.0mm profile : LTV-357T* UL approved ( No. E113898 )* CUL approved ( No. E113898 , 01SC19287 )* CSA approved ( No. 1243207 )* FIMKO approved ( No. FI-16420 )* NEMKO approved ( No. P0******* )* DEMKO approved ( No. 310475-01 )* SEMKO approved ( No. 0109173 / 01-08 )* VDE approved ( No. 138213 )* RoHS complianceAPPLICATIONS* Hybrid substrates that require high density mounting.* Programmable controllersABSOLUTE MAXIMUM RATING( Ta = 25°C ) PARAMETER SYMBOL RATING UNITForward Current I F50 mA INPUTReverse Voltage V R 6 VPower Dissipation P 70 mWCollector - Emitter Voltage V CEO80 VEmitter - Collector Voltage V ECO 6 V OUTPUTCollector Current I C50 mACollector Power Dissipation P C150 mW Total Power Dissipation P tot170 mW*1 Isolation Voltage V iso3,750 Vrms Operating Temperature T opr-55 ~ +110 °CStorage Temperature T stg-55 ~ +150 °C*2 Soldering Temperature T sol260 °C Junction Temperature Tj 125 °C*1. AC For 1 Minute, R.H. = 40 ~ 60%Isolation voltage shall be measured using the following method.(1) Short between anode and cathode on the primary side and between collector andemitter on the secondary side.(2) The isolation voltage tester with zero-cross circuit shall be used.(3) The waveform of applied voltage shall be a sine wave.*2. For 10 SecondsRANK TABLE OF CURRENT TRANSFER RATIO CTRMODEL NO. RANK MARK CTR ( % )A 80 ~ 160B 130 ~ 260C 200 ~ 400D 300 ~ 600E 50 ~ 150F 100 ~ 300LTV-357TA orB orC orD or No mark 50 ~ 600CONDITIONS I F = 5 mA V CE = 5 V Ta = 25 °Ctr Fig.9 Collector Dark Current vs.Ambient TemperatureFig.10 Response Time vs. LoadFig.11 Frequency Response 0C E Ambient temperature Ta ( C)Ambient temperature Ta ( C)Ambient temperature Ta ( C)Frequency f (kHz)e ( s )R e l a t i v e c u r r e n t t r a n s f e r r a t i o (%)V o l t a g e g a i n A v (d B )C o l l e c t o r -e m i t t e r s a t u r a t i o n v o l t a g e V (s a t ) (V )ooooo2040608010050100150 020408010020406080100501002005000.52010210100500Resistance0.020.040.060.080.1015205060C o l l e c t o r d a r k c u r r e n t I C E O (n A )V CE =20VI F =5mA V CE =2V I F =20mA I C =1mA V CE =2V I C =2mA Ta=25 CR L =10k Ω1k Ω100ΩV CE =2V I C =2mA Ta=25 C1101000010001000Ambient temperature T a ( C)R e l a t i v e c u r r e n t t r a n s f e r r a t i o (%)o2040608010050100150I F =5mAV CE =2VC E Ambient temperature Ta ( C)V (s a t ) (V )o2040801000.020.040.060.080.1060I F =20mAI C =1mATEMPERATURE PROFILE OF SOLDERING REFLOW(1)One time soldering reflow is recommended within the condition of temperature and timeprofile shown below.LITE-ON TECHNOLOGY CORPORATIONProperty of LITE-ON OnlyTEMPERATURE PROFILE OF SOLDERING REFLOW - Lite-On is continually improving the quality, reliability, function or design andLite-On reserves the right to make changes without further notices.- The products shown in this publication are designed for the general use in electronicapplications such as office automation equipment, communications devices,audio/visual equipment, electrical application and instrumentation.- For equipment/devices where high reliability or safety is required, such as spaceapplications, nuclear power control equipment, medical equipment, etc, pleasecontact our sales representatives.- When requiring a device for any ”specific” application, please contact our sales inadvice.- If there are any questions about the contents of this publication, please contact us atyour convenience.- The contents described herein are subject to change without prior notice.Do not immerse unit’s body in solder paste.Part No. :LTV-357T Page :11 of 11 BNS-OD-C131/A4。
KPC357中文资料
KPC357NT
UL 1577 (File No.E169586)
Outside Dimension : Unit (mm)
Applications
1. Hybrid substrates that reguire high density mounting. 2. Programmable controllers.
Fig.8 Collector Current vs. Collectoremitter Voltage
Fig.9 Relative Current Transfer Ratio vs. Ambient Temperature
Forward current IF (mA)
Collector-emitter voltage VCE (V)
Relative current transfer ratio (%)
Current transfer ratio CTR (%)
Collector current Ic (mA)
Ambient Temperature Ta (°C)
Fig.10 Collector-emitter Saturation Voltage vs. Ambient Temperature
1. Opaque type, mini-flat package. 2. Subminiature type (The volume is smaller than that of our conventional DIP type by as far as 30%). 3. Current transfer ratio (CTR:MIN.50% at IF=5mA, Vce=5V) 4. Isolation voltage between input and output (Viso:3750Vrms).
AK4545中文资料
424140393837MONO_OUT AVdd2NCLNLVL_OUT_LLNLVL_OUT_RAVss2TEST243TEST344NC 45NC 4647EAPD 148SPDIF_OUTLINE_OUT_L 3Dcap VRDA VRAD AFILTR AFILTL VrefOut Vref AVss1AVdd1LINE_OUT_R DVdd12XTL_IN3XTL_OUT4DVss15SDATA_OUT6BIT_CLK7SDATA_IN8DVdd29SYNC10RESET#1112DVss2PC_BEEP192021222324LINE_IN_R LINE_IN_L MIC2MIC1CD_R CD_GND 18CD_L 17VIDEO_R 16VIDEO_L 15AUX_R 14AUX_L 13PHONE363525262728293031323334PLLfilterPin/FunctionNo.Signal Name I/O Description1DVdd1-Digital power supply; 3.3V(DVdd1 = DVdd2)0.1uF + 4.7uF capacitors should be connected to digital ground.2XTL_IN (MCLKI)I 24.576MHz(512fs) Crystal is normally connected.If crystal is not connected, external clock can be used.3XTL_OUT(open)O 24. 576MHz(512fs) Crystal. If external clock is used, this pin should be open.4DVss1-Digital Ground; 0V. This pin should be directly connected to DVss2 on board.5SDATA_OUT I Serial 256-bit AC 97 data stream from digital controller 6BIT_CLK O 12.288MHz(256fs) serial data clock7DVss2-Digital Ground; 0V. This pin should be directly connected to DVss1 on board.8SDATA_IN O Serial 256-bit AC 97 data stream to digital controller 9DVdd2-Digital power supply; 3.3V(DVdd1 = DVdd2)0.1uF + 4.7uF capacitors should be connected to digital ground.10SYNC I AC 97 Sync Clock, 48kHz(1fs) fixed rate sampling rate 11RESET#I AC 97 Master Hardware Reset 12PC_BEEP I PC Speaker beep pass through13PHONE I From telephony subsystem speakerphone 14AUX_L I Aux Left Channel 15AUX_R I Aux Right Channel16VIDEO_L I Video Audio Left Channel 17VIDEO_R I Video Audio Right Channel 18CD_L I CD Audio Left Channel 19CD_GND I CD Audio analog groundCD_GND or analog ground should be connected through capacitor.20CD_R I CD Audio Right Channel 21MIC1I Desktop Microphone Input 22MIC2I Second Microphone Input 23LINE_IN_L I Line In Left Channel 24LINE_IN_R I Line In Right Channel25AVdd1-Power supply; 5.0V(AVdd1=AVdd2)0.1uF + 4.7uF capacitors should be connected to AVss1(analog ground).26AVss1-Analog Ground; 0V27Vref O Reference Voltage Output;0.1µF +4.7µF capacitors should be connected to Avss1(analog ground).28VrefOut O Reference Voltage Output (2.5V,1.25mA)29AFILTL O Anti-Aliasing Filter Cap; Connected to analog ground with 1nF capacitor.30AFILTR O Anti-Aliasing Filter Cap; Connected to analog ground with 1nF capacitor.31VRAD O Vref for ADC ; 0.1uF + 4.7uF capacitors should be connected to analog ground.32PLLfilter O Loop filter for PLL is connected; 36k resistor and 33nF capacitor in series and 390pF capacitor.33VRDA O Vref for DAC; 0.1uF + 4.7uF capacitors should be connected to analog ground.343DcapO 3D Enhancement Cap; 27nF capacitor should be connected to analog ground.35LINE_OUT_L O Line Out Left Channel 36LINE_OUT_R O Line Out Right Channel37MONO_OUT O To telephony subsystem speakerphone 38AVdd2-Power supply; 5.0V(AVdd1=AVdd2)0.1uF capacitor should be connected to AVss2(analog ground).39LNLVL_OUT_L O True Line Level Out Left Channel 40NC-No Connection41LNLVL_OUT_R O True Line Level Out Right Channel 42AVss2-Analog Ground43TEST2I Test pin (This pin should be open for normal operation):With internal pull-down.44TEST3I Test pin (This pin should be open for normal operation):With internal pull-down.45NC -No Connection 46NC -No Connection47EAPDO EAPD(External amplified powerdown)48SPDIF_OUTOSPDIF serial data outputAbsolute Maximum RatingAVss1, AVss2, DVss1, DVss2 =0V (Note 1)Parameter Symbol min max UnitsPower Supplies (Note 2) Analog(AVdd1 & AVdd2)Digital(DVdd1 & DVdd2)VAVD-0.3-0.36.06.0VVInput Current (any pins except for supplies)IIN-±10mA Analog Input Voltage VINA-0.3VA+0.3V Digital Input Voltage VIND-0.3VD+0.3V Ambient Temperature Ta-1070°C Storage Temperature Ta-65150°C Note 1: All voltages with respect to ground.AGND(AVss1, AVss2) and DGND(DVss1, DVss2) should be same voltage.Note 2: Supplying Digital Power, Analog Power should be supplied.Warning: Operation at or beyond these limits may results in permanent damage to the device.Normal operation is not guaranteed at these extremes.Recommended Operating ConditionAGND, DGND=0V (Note 1)Parameter Symbol min typ max UnitsPower Supplies AK4545AnalogDigital VAVD4.753.1355.03.35.253.465VVNote 1 : All voltages with respect to ground.AK4545 Analog CharacteristicsTa=25°C,AVdd=5.0V,DVdd=3.3V, fs=48kHz unless otherwise specified, Signal Frequency =1kHz All volume setting for ADC/DAC performance measurement is 0dB.Parameter min typ max Units Audio-ADC Resolution 18BitsS/N (A weight, fs=48kHz)8390dB S/N (A weight, fs=44.1kHz)87dB S/(N+D) (fs=48KHz, -1dB analog input)7082dBFS Inter Channel Isolation 7077dB Inter Channel Gain Mismatch 0.5dB Full Scale Input Voltage 0.88 1.0 1.12Vrms Power Supply Rejection 50dB Audio DAC: measured at AOUTL/AOUTR via MIXER path Resolution 18Bits S/N (A weighted, fs=48kHz): mixer+DAC measured at AOUT 8489dB S/N (A weighted, fs=44.1kHz): mixer+DAC measured at AOUT 88dB S/(N+D) (fs=48KHz, -1dB digital input)7280dBFS Inter Channel Isolation 7080dB Inter Channel Gain Mismatch 1.0dB Full Scale Output Voltage 0.88 1.0 1.12Vrms Total Out-of-Band Noise (28.8kHz - 100kHz)-70dB Power Supply Rejection 50dB MIC Amplifier / MUX Gain : 20dB is selected 182022dB Master volume (Mono, Stereo, True Line Level Out) : 1.5dB x 32 step Step Size -1.5dB Attenuation Control Range -46.50dB Load Resistance 10k ΩPC Beep : 3dB x 16 step Step Size -3.0dB Attenuation Control Range -450dB Analog Mixer : 1.5dB x 32 step Step Size -1.5dB Gain Control Range -34.5+12dB Record Gain : 1.5dB x 16 step Step Size +1.5dB Gain Control Range 0+22.5dB MixerInput Voltage (except for MIC) 1.0Vrms Input Voltage MIC : Gain = 0dB MIC : Gain = 20dB 10.1Vrms Vrms S/N(A weighed) : 0dB setting, 1 path is selected at Mixer CD to AOUT: Other analog input to AOUT 889595dB dB Input Impedance (Input gain=0dB,Rec_MUTE=off) PC_BEEP only Others(PHONE, LINE, CD, AUX, VIDEO)Input Impedance (MIC1 and MIC2)(10)(10)(10)764020k Ωk Ωk ΩOutput load Resistance (LINE_OUT_L/R, MONO_OUT, LNLVL_OUT_L/R)10k ΩVrefout Drivability 1.25mAParameter min typ max Units Power SuppliesAnalog Power Supply Current(AVdd1 & AVdd2) All ON mode(all PR_bits are 0)Cold Reset status(Reset#=L, Vref is ON)All OFF mode(all PR_bits are 1)383.75780.2mAmAmADigital Power Supply Current(DVdd1 & DVdd2) All ON mode(all PR_bits are 0) at DVDD=3.3V All OFF mode(all PR_bits are 1)6.9110.4mAmAFilter CharacteristicsTa=25°C,AVdd=5.0V±5%,DVdd=3.3V±5% , fs=48KHz(fixed)P arameter min typ Max Units ADC Digital Filter (Decimation LPF)Passband (±0.2dB) Note)019.2kHz Stopband28.8kHz Stopband Attenuation70dB Group Delay0.5ms ADC Digital Filter (HPF)Frequency Response; -3dB -0.5dB -0.1dB 7.52149HzDAC Digital FilterPassband (±0.2dB)019.2kHz Stopband28.8kHz Group Delay0.5ms Stopband Rejection70dB DAC Post filterPassband Frequency Response (0 - 19.2kHz)±0.1dB Note) This frequency scales with the sampling frequency (fs).AK4545 DC CharacteristicsTa=-10∼70°C, VD= 3.3V±5%, VA=5V±5%, 50pF external loadParameter Symbol min typ Max UnitsC-coupled VIH0.7xVD--V H level input voltage(XTAL_IN)direct VIH0.8xVD VC-coupled VIL--0.3xVD V L level input voltage(XTAL_IN)direct VIL0.2xVD VH level input voltage(RESET#, SYNC, SDATA_OUT)VIH0.7xVD--VL level input voltage( RESET#, SYNC, SDATA_OUT)VIL--0.3xVD VH level output voltage Iout= -1mA VOH VD-0.55--V L level output voltage Iout= 1mA VOL--0.55V Input leakage current(exclude pull up pins)Iin--±10µASwitching CharacteristicsTa=25°C, AVdd=5.0V±5%, DVdd=3.3V±5%, 50pF external loadParameter Symbol Min Typ max UnitsMaster Clock Frequency Note) If Crystal is not used.Fmclk-4524.57650-55MHz%AC link Interface TimingBIT_CLK frequencyBIT_CLK clock Period(Tbclk=1/Fbclk)BIT_BLK low pulse widthBIT_BLK low pulse widthBIT_CLK rise timeBIT_CLK fall time FbclkTbclkTclk_lowTclk_highTrise_clkTfall_clk-3636--12.28881.3840.740.7--454566MHznsnsnsnsnsSYNC frequency SYNC low pulse widthSYNC high pulse widthSYNC rise time SYNC fall time Tsync_lowTsync_highTrise_syncTfall_sync-----4819.5(240 cycle)1.3(16 cycle)-----66kHzµs(Tbclk)µs(Tbclk)nsnsSetup time(SYNC, SDATA_OUT) Hold time(SYNC, SDATA_OUT) SDATA_IN delay time from BIT_CLK rising edgeSDATA_IN rise timeSDATA_IN fall timeSDATA_OUT rise timeSDATA_OUT fall time TsetupTholdTdelayTrise_dinTfall_dinTrise_doutTfall_dout1025--------------156666nsnsnsnsnsnsnsCold Rest (SDATA_OUT=L, SYNC=L) RESET# active low pulse widthRESET# inactive to BIT_CLK delay Trst_lowTrst2clk1.0162.8(2 cycle)--µsns(Tbclk)Warm Rest TimingSYNC active low pulse widthSYNC inactive to BIT_CLK delay Tsync_highTsync2clk1.0162.8(2 cycle)1.3(16 cycle)-µs(Tbclk)ns(Tbclk)AC-link Low Power Mode TimingEnd of Slot 2 to BIT_CLK, SDATA_INLow Ts2_pdwn-- 1.0µsActivate Test Mode TimingSetup to trailing edge of RESET#Hold from RESET# rising edgeRising edge of RESET# to Hi-ZFalling edge of RESET# to L Tsetup2rstThold2rstToffTlow15.0100--------5050nsnsnsnsNote ) The use of a crystal is recommended. If master clock is supplied from controller (or if a external oscillator is used), Master Clock should be input to XTAL_IN, meanwhile XTAL_OUT should be open.Note that AK4545 must be in cold reset at power on and RESET# must be low until master c rystal clock becomes stable, or reset must be done once master clock is stable.BIT_CLKRESET#Vddn Cold Reset TimingNote that both SDATA_OUT and SYNC must be low at the rising edge of RESET# for cold reset.The AK4545 initializes all registers including the Powerdown Control Registers, BIT-CLK is reactivated and each analog output is in Hi-Z state except for PC Beep while RESET# pin is low. The PC Beep is directly routed to L & R line outputs when AK4545 is in Cold Reset.At the rising edge of RESET#, the AK4545 starts the initialization of ADC and DAC, which takes 1028TS cycles. After that, the AK4545 is ready for normal operation.Status bit in the slot 0 is 0 (not ready) when the AK4545 is in RESET period ( L ) or in initialization process. After initialization cycles, the status bit goes to 1 (ready).BIT_CLKRESET#The AK4545 initiates warm reset process by receiving a single pulse on the sync. The AK4545 clears PR4 bit and PR5 bit in the Powerdown Control Register. However, warm reset does not influence PR0∼PR3 or PR6,7 bits in Powerdown Control Register. Note that SYNC signal should synchronize with BIT_CLK after AK4545 starts to output BIT_CLK clock. And if an external clock is used, external clocks should be supplied before issuing a sync pulse for warm reset.ADC and DAC require 1028TS for the initialization.IHBIT_CLKSYNCnnV IHV ILn Setup and Hold TimingSDATA_IN SDATA_OUTSYNCIH V ILBIT_CLKV IHV ILV IHV ILn Signal Rise and Fall Times(50pF external load : from 10% 90% of DVdd)nBIT_CLKSDATA_INSDATA_OUTn Activate Test ModeIHIHSDATA_INBIT_CLKSDATA_OUTRESET#Notes:11. All AC-link signals are normally low through the trailing edge of RESET#. Bringing SDATA_OUT high for the rising edge of RESET# causes the AK4545 AC-link outputs to go high impedance which is suitable for ATE in circuit testing. Note that theAK4545 enters in the ATE test mode regardless SYNC is high or low.2. Once test modes have been entered, the only way to return to the normal operating state is to issue “cold reset” which issues RESET# with both SYNC and SDATA_OUT low.1 All the following sentences written with small italic font in this document quote the AC’97 component specification.General Descriptionn AC 97 Connection to the Digital AC 97 controller2AC ‘97 communicates with its companion AC ‘97 controller via a digital serial link, AC-link”. All digital audio streams, andcommand/status information are communicated over this point to point serial interconnect. A breakout of the signals connecting the two is shown in the following figure.AC 97ControllerAC 97n Digital InterfaceThe AK4545 incorporates a 5 pin digital serial interface that links it to the AC ’97 controller. AC-link is a bi-directional, fixed rate(48kHz), serial PCM digital stream. It handles multiple input, and output audio streams, as well as control register accesses employing a time division multiplexed (TDM) scheme. The AC-link architecture divides each audio frame into 12 outgoing and 12incoming data streams, each with 20-bit sample resolution. DAC and ADC resolution of the AK4545 is 18 bit resolution. The data streams currently defined by the AC ‘97 specification include:l PCM Playback 2 output slots 2 channel composite PCM output stream l PCM Record data 2 input slots 2 channel composite PCM input stream l Control 2 output slots Control register write port l Status 2 input slots Control register read port l S/PDIF output data 2 output slots 2 channel composite data output streamSYNC, fixed at 48 KHz, is derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed at 12.288 MHz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming time slots. AC-link serial data is transitioned on each rising edge of BIT_CLK. The receiver of AC-link data, the AK4545 for outgoing data and AC ’97 controller for incoming data,samples each serial bit on the falling edges of BIT_CLK.The AK4545 outputs BIT_CLK.The AC-link protocol provides for a special 16-bit slot (Slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. A “1” in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream, and contains valid data. If a slot is “Tagged” invalid, it is the responsibility of the source of the data, (The AK4545 for the input stream, AC ’97 controller for the output stream), to stuff all bit positions with 0’s during that slot’s active time.SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The portion of the audio frame where SYNC is high is defined as the “Tag Phase”. The remainder of the audio frame where SYNC is low is defined as the “Data Phase”.Note that SDATA_OUT and SDATA_IN data is delayed one BIT_CLK because A C 97 controller causes SYNC signal high at a rising edge of BIT_CLK which initiates a frame.Output stream means the direction from AC 97 controller to the AK4545, and Input stream means the direction from the AK4545 to AC 97 controller2All the following sentences written with small italic font in this document quote the AC’97 component specification.121110987654321Slot 0SYNCSDATA INSDATA OUTthe Tag phase, is 16bits, all other slots are 20bits in length. These slots are explained in later sections.AC-link Audio Output Frame (SDATA_OUT)a) S lot 0SYNC SDATA_OUTBIT_CLK The AK4545 checks bit15 (valid frame bit). Note that when the valid frame bit is 1 , at least one bit14-7 (slot 1-8)must be valid, bit6-0 will be 0 and should be ignored.If bit15 is 0 , the AK4545 ignores all following information in the frame.The AK4545 then checks the validity of each bit in the TAG phase (slot 0).Bit14-11,8,7 are valid bits for slot1-4,7,8.If each bit is 0 , the AK4545 ignores the slot indicated by 0 . On the other hand, if each bit is 1 , the slot is valid.A new audio output frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the AK4545 samples the assertion of SYNC. This falling edge marks the time when both sides of AC-link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC ’97 controller transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is presented to AC-link on a rising edge of BIT_CLK, and subsequently sampled by the AK4545 on the following falling edge of BIT_CLK. This sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned.Data should be sent to the AC 97 codec with MSB first through the SDATA_OUT.The following table shows the relationship of bit14&13 and the Read/Write operation depending on codec ID configuration.Bit 15Valid FrameBit 14: Slot1 Valid Bit (Command Address)Bit 13: Slot 2 Valid Bit (Command Data)Read/Write Operation ofAK4545111Read/Write(Normal Operation)101Ignore11Read: Normal Operation Write: Ignore100IgnoreAK4545 Addressing: Slot0 Tag Bitsb)Slot1:Command Address PortSlot1 gives the address of the command data, which is given in the slot 2. The AK4545 has 26 valid registers of 16bitBIT_CLKSDATA_OUTBit 19:Bit 18:12Control Register Index (see Mixer Registers for the detail)Bit 11:0Reserved ( 0 )Bit 18 of this slot1 is equivalent to the most significant bit of the index r egister address.The AK4545 ignores from bit11 to bit0. These bits will be reserved for future enhancement and must be staffed with 0 s by the AC 97 controller.BIT_CLKSDATA_OUTBit19:4Bit3:0Reserved( 0 )If bit19 in slot1 is 0 , the AC 97 controller must output Command Data Port data in slot 2 of the same frame. If the bit19 in slot1 is 1 , the AK4545 will ignore any Command Data Port data in slot2.Bit19 of this slot2 is equivalent to D15 bit of mixer register value.d)Slot3 PCM Playback Left Channel (18bits)The AK4545 uses the playback(DAC) data format in slot3 for left channel.Playback data format is MSB first. Data format is 18bits 2 s complement. AC 97 controller should stuff bit1-0 with 0 . If valid bit (slot3) in the slot 0 is invalid ( 0 ), the AK4545 interprets the data as all 0 .Bit19:2Playback dataBit 1:0 0If Slot3 and 4 of SDATA_OUT are selected for S/PDIF output data, this 18bits data is output through channel1 of S/PDIF out besides DAC.e)Slot4 PCM Playback Right Channel (18bits)The AK4545 uses the playback(DAC) data format in the slot4 for right channel. Playback data format is MSB first. Data format is 18bits 2 s complement. AC 97 controller should stuff bit1-0 with 0 . If valid bit (slot 4) in the slot 0 is invalid ( 0 ), the AK4545 interprets the data as all 0 .Bit19:2Playback dataBit 1:0 0If Slot3 and 4 of SDATA_OUT are selected for S/PDIF output data, this 18bits data is output through channel2 of S/PDIF out besides DAC.f)Slot5,6 Not implemented in the AK4545The AK4545 ignores these data slots.g)Slot7 S/PDIF output data channel1(16bits)In case of selecting slot7 and 8 of SDATA_OUT for S/PDIF output data, the AK4545 uses data format in the slot7 for channel1 of S/PDIF output data. This data format is MSB first. Data format is16bits 2 s complement. AC 97 controller should stuff bit3-0 with 0 . If valid bit (slot7) in the slot 0 is invalid ( 0 ), the AK4545 interprets the data as all 0 .Bit19:4Output dataBit 3:0 0h)Slot8 S/PDIF output data channel2(16bits)In case of selecting slot7 and 8 of SDATA_OUT for S/PDIF output data, the AK4545 uses data format in the slot8 for channel2 of S/PDIF output data. This data format is MSB first. Data format is16bits 2 s complement. AC 97 controller should stuff bit3-0 with 0 . If valid bit (slot8) in the slot 0 is invalid ( 0 ), the AK4545 interprets the data as all 0 .Bit19:4Output dataBit 3:0 0i)Slot9-12 Not implemented in the AK4545The AK4545 ignores these data slots.AC-link Input Frame(SDATA_IN)Each AC-link frame consists of one 16bit tag phase and twelve 20bit slots used for data and control.a) S lot0Slot0 is a special time frame, and consists of 16bit s. Slot0 is also named the Tag phase. The AK4545 supports Bits 15-11. Each bit indicates 1 =valid(normal operation) or ready, 0 =invalid(abnormal operation) or not ready.If the first bit in the slot 0 (Bit15) is valid, the AK4545 is ready for normal operation. 3If the Codec Ready bit is invalid, the following bits and remaining slots are all 0 . AC 97 controller should ignore the following bits in the slot 0 and all other slots. When the ADC sampling rate is set for less than 48kHz, then Bits 12and 11 in slot 0( corresponds to slot3 and slot4 respectively ) will be 1 s when valid data is transferred in SDATA_IN, and will be 0 s when no data is transmitted. ( On-demand ) base data transaction )The next is the extracted description from AC 97 Rev.2.1 ;For variable sample rate input, the tag bit for each input slot indicates whether valid data is present or not. Thus,even in variable sample rate mode, the Codec is always the master: for SDATA_IN (Codec to Controller), the Codec sets the TAG bit; for SDATA_OUT (Controller to Codec), the Codec sets the SLOTREQ bit and then checks for the TAG bit in the next frame. AK4545 expects Controller will reply TAG bit in the next frame correctly.Bit 14 means that Slot 1(Status Address) output is valid or invalid. And Bit 13 means that Slot 2(Status Data ) is valid or invalid.The following table shows the relationship between Bit 14,13 and each Status of the AK4545.Bit 15(Codec Ready)Bit 14(Status Address)Bit 13(Status Data)Status111There is a Read Command in the previous frame.Then both Slot 1 and Slot 2 output normal data.If the access to non-implemented register or odd register is requested, the AK4545 returns valid 7-bit register address in slot 1 and returns valid 0000h data in slot 2 on the next AC-link frame.110Prohibited or non-existing 100There is no Read Command in the previous frame.Bits 19-12 and Bits 9-0 in Slot 1 are set to 0 . And Slot2 outputs All 0 .101Prohibited or non-existingNote 1). The above Read sequence is done as response for previous frames read command. That is, if the previousframe is the Write Command, AK4545 outputs bit14 = 0 , bit13 = 0 and slot 1&2 = All 0 , if there is no SLOTREQ.2). The Bits 14 and 13 in Slot 0 is independent of the SLOTREQ Bits 11 and 10 in Slot 1 which the AK4545supports.Bit12 means the output of Slot 3(PCM(ADC) Left) is valid or invalid. And Bit 11 means the output of Slot 4(PCM(ADC)Right) is valid or invalid. Bits10-0 are occupied with 0 .A new audio input frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the AK4545 samples the assertion of SYNC. This falling edge marks the time when both sides of AC-link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AK4545 transitions SDATA_IN into the first bit position of slot 0 (“Codec Ready” bit). Each new bit position is presented to AC-link on a rising edge of BIT_CLK,and subsequently sampled by the AC ’97 controller on the following falling edge of BIT_CLK. This sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned.SYNC SDATA_INBIT_CLK 3When the AC’97 is not ready for normal operation, output bits are not specified and should be ignored.b)S lot1Status Address PortAudio input frame slot1’s stream echoes the control register index, for historical reference, for the data to be returned in slot2.BIT_CLKSDATA_INThis address shows register index for which data is being returned in the slot2.This address port is the copy of slot1 of the output frame, and index address input to SDATA_OUT is loop ed back to the AC 97 controller through SDATA_IN even for non-supported register.For On Demand base data transaction, when the DAC sampling rate is set less than 48kHz, then AK4545 will request new audio data as required by setting the SLOTREQ bits 11 and 10 in Slot1 to 0 s. When no data is required to support the selected sampling rate, these bits will be 1 s. When SLOTREQ bits are asserted as send data request during the current frame on SDATA_IN, AC 97 digital controller should send data onto the corresponding slot in the next frame on SDATA_OUT.If VRA is set 0 , SLOTREQ bits show always 0 and sample rate is forced to 48ksps.SLOTREQ Bit Description19Reserved ( Set to 0 )18 12Control Register Index ( Set to 0 s if tagged invalid )11Slot 3 Request : PCM Left channel0 : send data request, 1 : do not send10Slot 4 Request : PCM Right channel0 : send data request, 1 : do not send9Reserved ( Set to 0 )8Slot 6 Request : AK4545 doesn t use slot6. ( Set to 0 )7Slot 7 Request : Slot 7 can t be used at except 48KHz.Set to 0 .6Slot 8 Request : Slot 8 can t be used at except 48KHz.Set to 0 .5Slot 9 Request : AK4545 doesn t use slot9. ( Set to 0 )4 0Reserved ( Set to 0 )c)Slot2:Status Data PortStatus data addressed by command address port of Output Stream is output through SDATA_IN pin.Bit19:4Control Register Read Data (the contents of indexed address in the slot 1)Bit3:0 0Note that the address of Status Data Port data are consistent with Status Address Port data of the slot 1 in the same frame. If the read operation is issued in the frame N by AC 97 controller, Status Data Port data is output through SDATA_IN in the frame N+1. Note that data is output in only this frame, only one time and that the following frames are invalid if the next read operation is not issued.d)Slot3PCM Record Left ChannelRecord(ADC) data format is MSB first. Data format is 2 s complement. As the resolution of the AK4545 is 18bit, lower 2 bits are ignored. If ADC block is powered down, slot-3 valid bit in the slot 0 is invalid ( 0 ), and data is output as all 0 .Bit19:2Audio ADC left channel outputBit1:0 0e)Slot4PCM Record Right ChannelRecord(ADC) data format is MSB first. Data format is 2 s complement. As the resolution of the AK4545 is 18bit, lower 2 bits are ignored. If ADC block is powered down, slot-4 valid bit in the slot 0 is invalid ( 0 ), and data is output as all 0 .Bit19:2Audio ADC right channel outputBit1:0 0f)Slot5Modem Line CodecAs the AK4545 does not incorporate modem codec, all bits are stuffed with 0 .Bit19:0 0g)Slot6Microphone Record DataAs the AK4545 does not incorporate 3rd ADC codec, all bits are stuffed with 0 .Bit19:0 0h)Slots7-12Reserved for future enhancementBits19:0 0n S/PDIF outputa) Electrical CharacteristicsSame as other digital output pins (CMOS level).S/PDIFout pin is supposed to be connected to optical component only.b) Outline of S/PDIF Spec.(1) The channel status of the AK4545 supports consumer mode only. The AK4545 has three-16 bit registerswhich keep Copyrights-bit, Category-code bits, Generation-bit, etc. These bits can be changed through AC-link I/F.(2) SDATA_IN data or SDATA_OUT data is encoded to appropriate bi-phase signal by internal digital audiotransmitter (DIT) circuit, and is output through S/PDIFout pin. One of the following audio data streams can be selected as the input signal to DIT circuit by the setting of internal register.(a) D/A data from SDATA_OUT (slot3/4)(b) A/D data to SDATA_IN (slot 3/4)(c) Slot 7/8 data from SDATA_OUT (In this case, we assume that slot7/8 is original AC-3 encoded data,and that slot 3/4 is down-mixed AC-3 audio data Therefore, the device supposes data rate of slot 7/8and slot 3/4 to be same and to be 48kHz. )(3) Even if A/D and D/A sampling frequency (fs) are different, S/PDIFout circuit works correctly.AK4545BIT_CLKSYNCSDATA_OUTSDATA_INRESET#S/PDIF OUTI/O ASLT Data Select00SDATA_OUT : slot 3, 401SDATA_OUT : slot 7, 8 Note1X SDATA_IN : slot 3, 4Note) DAC rate and S/PDIF rate should be same (48kHz).。
TLC3578中文资料
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ASTM D3574-I3中文版
这是因为 对实验数 据的分析 表明，它 能够减少 结果的不 确定性。 通常使用 的百分比 损失通过 以下公式 与绝对损 失相关 联：
百分 比硬度降 低 = 100 x (H1H2)/H1 8 测试报 告
测试 报告应该 包括以下 信息：
a) 该国际标 准的参考 文件
b) 材料的描 述
c) 所用的测 试条件
该国 际标准定 义了一种 测定软质 泡沫材料 的厚度减 少和硬度 降低的方 法，该材 料 被用在室 内装饰业 。
这种 测试方法 提供了一 种评估乳 胶和聚醚 氨基甲酸 酯类软质 泡沫聚合 材料使用 性 能的手 段，该材 料被用在 需要承受 一定重量 的家具上 。
所测 出的厚度 减少和硬 度降低与 使用中可 能发生的 损失有 关，但两 者不一定 相同。
以下 公式给出 了减少的 厚度百分 比
△d = 100 x (d1d2)/d1
这里 d1 代表初始 厚度 d2 代表最终 厚度
从这 三个测试 件的测量 值中取其 中间值作 为测量结 果。 7.2 硬度 降低
以下 公式给出 了降低的 硬度
△ H=H1-H2
这里 H1 代表初始 硬度 H2 代表最终 硬度 从这 三个测试 件的测量 值中取其 中间值作 为测量结 果。 注意 --现在一 般采用这 种用绝对 损失而不 用百分比 损失来表 达硬度降 低的方 法，
冲击 头支撑装 置竖直朝 向两者中 的另一个 振动。震 荡幅度应 该能够调 节。 4.3 冲击 头支撑装 备：除非 在该装备 和台板由 于撞击而 距离最近 时，冲击 头的力量 都
由其 承载。在 撞击时， 冲击头的 作用力全 部加在测 试件上。 冲击头在 该装备中 可
以自 由上升， 以防止测 试件过载 。在撞击 时，冲击 头施加全 部作用 力，无论 何时
MSDS物质危险有害特性识别表184种
184种物质危险有害特性识别表MSDS大全目录表1－001 乙炔气 (1)表1－002 氧气 (2)表1－003 二氧化碳 (3)表1－004 氢气 (4)表1－005 氩气 (5)表1－006 甲烷 (6)表1－007 四氢噻吩 (7)表1－008 活性炭 (8)表1－009 三乙胺 (9)表1－010 硫代磷酰氯 (10)表1－011 硫黄 (11)表1－012 甲胺磷 (12)表1－013 多聚甲醛 (13)表1－014（附表1－3）甲缩醛 (14)表1－015 黄磷 (15)表1－016 氯 (16)表1－017 三氯化磷 (17)表1－018 甲醇 (19)表1－019 液碱 (20)表1－020 氨水 (21)表1－021 硫酸二甲酯 (22)表1－022 甲胺磷 (23)表1－023 液氨 (24)表1－024 氯仿 (25)表1－025 二氯乙烷 (26)表1－026 二硫化碳 (27)表1－027 甲苯 (28)表1－028 盐酸 (29)表1－029 氯甲烷 (30)表1－030 硫酸 (31)表1－031 二甲苯 (33)表1－032 醋酸酐 (34)表1－033 多聚甲醛 (35)表1－034 草甘膦 (36)表1－035 稻瘟灵 (37)表1－036 异丙胺 (38)表1－037 漂白粉 (39)表1－038 氯化氢 (40)表1－039 氰化氢 (41)表1－040 氰化钠 (42)表1－041 氯乙酸 (43)表1－043 丙烯腈 (45)表1－044 氧化亚铜 (46)表1－045 四氯化锡 (47)表1－046 四氧化三铅 (48)表1－047 三氯化铝（无水） (49)表1－048 松香水 (50)表1－049红丹油性防锈漆 (51)表1－050 酚醛树脂 (52)表1－051 硫磺粉(补充) (53)表1－052 一乙胺 (54)表1－053三聚氯氰 (55)表1－054 三氯乙烯 (57)表1－055 磷酸 (58)表1－056 四丁基锡 (59)表1－057 柴油 (60)表1－058 对氨基苯酚 (61)表1－059 醋酸乙酯 (62)表1－060 对氯硝基苯 (63)表1－061 氮气 (64)表1－062莠去津 (65)表1－063 扑草净 (66)表1－064 八氯二丙醚 (67)表1－065 硫化钠 (68)表１－066 异丙醇 (69)表１－067 丙酮 (70)表１－068 二氯丙烷 (71)表１－069 环己酮 (72)表１－070 乙酸异戊酯 (73)表1－071 锌粉 (74)表1－072 乙醇 (75)表1－073 次氯酸钠溶液 (76)表1－074 石脑油 (77)表1－075 双环戊二烯 (78)表1－076 乙酸丁酯 (79)表1－077 双氧水 (80)表1－078 丙烯酸丁酯 (81)表1－079 丙烯酸 (82)表1－080 苯乙烯 (83)表1－081 过硫酸铵 (84)表1－082 过硫酸钾 (85)表1－083 丙烯酰胺 (86)表1－084 甲醛 (87)表1－085 甲基丙烯酸甲酯 (88)表1－087 汽油 (90)表1－088 乙酸 (91)表1－089 丙烯酸树脂 (92)表1－090 丙烯酸清漆 (93)表1－091 丙烯酸漆稀释剂 (94)表1－092 丙烯酸磁漆 (95)表1－093 二乙醇胺 (97)表1－094 煤油 (98)表1－095 漂白粉 (99)表1－096 漂粉精 (100)表1－097 三氯异氰尿酸 (101)表1－098 松香 (102)表1－099 松节油 (103)表1－100 硫化钠 (104)表1－101 保险粉 (105)表1－102 7385聚氨酯清漆（分装） (106)表1－103 甲酸 (107)表1－104 乙酸乙二醇乙醚 (108)表1－105 H－3聚氨酯漆固化剂 (109)表1－106 聚氨酯漆稀释剂 (110)表1－107 263醇酸树脂 (111)表1－108 异噻唑啉酮 (112)表1－109 N-乙基苯胺 (113)表1－110苯胺 (114)表1－111 乙酰甲胺磷 (115)表1－112 亚磷酸 (117)表1－113 亚磷酸二甲酯 (118)表1－114 氯甲烷 (119)表1－115 乙醚 (120)表1－116 丙烯酸甲酯 (121)表1－117 一甲胺 (122)表1－118 硝酸镁 (123)表1－119 硫化氢 (124)表1－120 硫化铵 (125)表1－121 一甲胺水溶液 (126)表1－122 兔宝宝面漆 (127)表1－123 兔宝宝稀释剂 (128)表1－124 硫氢化钠 (129)表1－125丙酸 (130)表1－126乙酰氯 (131)表1－127丙酰氯 (132)表1－128 丁醇 (133)表1－129 醇酸调合漆（未列名） (134)表1－130 硝酸钠 (136)表1－131 溴甲烷 (137)表1－132 磷化铝 (138)表１－133 正丁醇 (139)表１－134 硝基木器漆 (140)表１－135 硝化棉（含氮≤12.6％） (141)表１－136 单丁醚 (142)表1－137 砷 (143)表1－138 碘化汞 (144)表1－139 氯化汞 (145)表1－140 叠氮化钠 (146)表1－141 重铬酸钠 (147)表1－142 高锰酸钾 (148)表1－143 氰化金钾 (149)表1－144丙烯酸 (150)表1－145甲基丙烯酸甲酯 (151)表1－146苯乙烯 (152)表1－147丙烯酸丁酯 (153)表1－148丁醇 (154)表1－149偶氮二异丁腈 (155)表1－150甲基丙烯酸异丁酯 (156)表1－151 甲基丙烯酸（正）丁酯 (157)表1－152 乙酰丙酮 (158)表1－153 2－丁酮 (160)表1－154 生松香 (161)表1－155 硫酸铜 (162)表1－155 硝酸 (163)表1－155 氰化钾 (164)表1－156硝基苯 (165)表1－157 氟化钠 (166)表1－158 氢氟酸 (167)表1－159蓄电池（注有酸液） (168)表1－160 环氧树脂 (169)表1－161 氯苯 (170)表1－162 乙苯 (171)表1－163 樟脑 (172)表1－164 赛璐珞 (173)表1-165 氢氧化钾 (174)表1-166 乙酸丁酯 (175)表1－001 乙炔气表1－002 氧气表1－003 二氧化碳表1－004 氢气表1－005 氩气表1－006 甲烷表1－007 四氢噻吩表1－008 活性炭活性炭 C 12.0Active carbon别名：Activated chlarcoal危规分类及编号：自燃物品。
EN 868-5中文翻译版
EN 868-5：1999待灭菌医疗器械包装材料和系统第5部分：纸与塑料膜组合的热封和自封袋和卷要求和试验方法引言本系列欧洲标准的第1部分规定了预期用作医疗器械包装的包装材料和系统的通用要求和试验方法。
这些医疗器械最终在其包装内灭菌。
1 范围EN 868的本部分规定了用符合EN 868-3规定的纸和符合本部分第4章规定的塑料膜制造的热封和自封袋的专用要求和试验方法。
4.2至4.7中的专用要求可用以证实符合第1部分的一项或多项要求，但不是其全部要求。
本标准规定的热封和自封袋和卷适用于包装最终灭菌的医疗器械。
热封和自封袋和卷用作初包装能使使用者用前方便地无菌观察内装物，这一点非常重要。
2 规范性引用文件EN 285 灭菌蒸汽灭菌大型灭菌器EN 867-2 灭菌器中使用的非生物学系统第2部分：过程批示物（A级）EN 868-1待灭菌医疗器械包装材料和系统第1部分：通用要求和试验方法EN 868-3待灭菌医疗器械包装材料和系统第3部分：袋（EN868-4所规定的）袋和卷（EN868-5所规定的）生产用纸要求和试验方法EN 1422 医用灭菌器环氧乙烷灭菌器要求和试验方法EN 28601数据元和交换格式信息交换日期和时间表示法（ISO 8601：1988和技术修改单1：1991）GB/T 7408-1994数据元和交换格式信息交换日期和时间表示法EQV ISO 8601-88 EQV ISO 8601-88ASTM D 882：1995 塑料膜抗张性能试验方法3定义EN868-1的定义适用于本部分。
4 要求4.1 总则EN868-1的要求适用。
注：下列专用要求和试验方法可用于证实EN868-1的一项或多项要求，但不是全部要求。
4.2 材料4.2.1 纸纸应符合EN 868-3的要求。
4.2.2 塑料膜4.4.2.1 塑料膜应是由两层或多层复合而成。
按附录A试验时，塑料结合层（interplybond）应不发生分离或发白。
危险化学品理化性质及危险特性表
表7.6-1苯的理化性质及危险特性表表7。
6—7粗苯的理化性质及危险特性表表7。
6-82—丁氧基乙醇的理化性质及危险特性表表7.6-111，4－二甲苯的理化性质和危险特性表表7。
6-12二甲苯异构体混合物的理化性质及危险特性表表7。
6—14 二甲醚的理化性质及危险特性表7.6—15 二甲氧基甲烷的理化性质及危险特性表7.6-22 环辛烷的理化性质及危险特性表7.6-23 1,2—环氧丙烷的理化性质及危险特性表7。
6-24 环氧乙烷的理化性质及危险特性表7。
6-25甲苯的理化性质及危险特性表表7。
6-26甲醇的理化性质及危险特性表表7。
6-272－甲基－1－丙醇的理化性质及危险特性表表7.6—28 2—甲基—2—丙醇的理化性质及危险特性表7.6-29 2—甲基丁烷的理化性质及危险特性表7。
6-30甲基叔丁基醚的理化性质及危险特性表表7.6-31 甲醛溶液的理化性质及危险特性表7。
6—32 煤焦沥青的理化性质及危险特性表7.6—33 煤油的理化性质及危险特性表7。
6—36 溶剂苯的理化性质及危险特性表7.6-37 溶剂油的理化性质及危险特性表7。
6-381，2，3－三甲基苯的理化性质及危险特性表表7.6—391,2,4－三甲基苯的理化性质及危险特性表表7.6-41石脑油的理化性质及危险特性表表7.6-42石油醚的理化性质及危险特性表7。
6—43 石油原油的理化性质及危险特性表7.6-44叔丁基苯的理化性质及危险特性表表7.6-451，2，4,5－四甲苯的理化性质及危险特性表表7.6-46松焦油的理化性质及危险特性表7。
6-47 天然气的理化性质及危险特性表7.6-48 液化石油气的理化性质及危险特性表7。
6—49乙苯的理化性质及危险特性表表7。
6-50 异丁烯的理化性质及危险特性表7。
6-51异辛烷的理化性质及危险特性。
3577;中文规格书,Datasheet资料
PC QUICK-FIT FEMALE TERMINALSACCEPTS .110(2.8)TABVERTICAL ENTRYVERTICAL ENTRYACCEPTS .187(4.8)TABVERTICAL ENTRYACCEPTS .110(2.8)TAB HORIZONTAL ENTRYACCEPTS .187(4.8),.205(5.2),.250(6.4)TABSACCEPTS .110(2.8)×.032(.81)TABHORIZONTAL ENTRYMounting DetailMATERIAL:.012(.30)Brass,Tin-Nickel PlateMounting DetailMATERIAL:.016(.41)Brass,Tin-Nickel PlateMATERIAL:Brass,Tin-Nickel PlateMounting DetailMounting DetailMATERIAL:.016(.41)Brass,Tin-Nickel Plate CAT.NO.ACCEPTS TAB 3525.205(5.2)×.020(.51)3575.205(5.2)×.032(.81)CAT.NO.ACCEPTS TAB 3528.250(6.4)×.032(.81).400[10.1].046[1.15] DIA..076[1.9] DIA..400[10.1].067[1.70]DIA..104[2.6]DIA..146[3.7].232[5.9]W (Ref).420[10.7].150[3.8].050[1.25].200[5.1].200[5.1].052[1.30]DIA.CAT.NO.ACCEPTS TAB 3545.110(2.8)×.020(.51)3549.110(2.8)×.032(.81).212[5.4].062[1.55].100[2.5].075[1.90].400[10.2].040[1.00].070[1.80].156[4.0].280[7.1].070 [1.80].125 [3.2].281 [7.1].437[11.1].076[1.90].271 [6.9].120 [3.0].250[6.3]Tel (718)956-8900•Fax (718)956-9040(800)221-5510•kec@31-0720th Road –Astoria,NY 11105-2017RoHS COMPLIANT ~ISO 9001CERTIFIED®Mounting Detail.200[5.1].100[2.54]DIA.Mounting Detail.200[5.1].089[2.3]Mounting Detail.328[8.35].152[3.86]DIA.MATERIAL:.016(.41)Brass,Tin-Nickel PlateACCEPTS .205(5.2)TAB VERTICAL ENTRYACCEPTS .250(6.4)TABCAT.NO.ORIENTATION 3557top &side entry 3577bottom &side entryMATERIAL:.016(.41)Brass,Tin-Nickel PlateMATERIAL:.020(.51)Copper,Tin-Nickel PlateACCEPTS ALL TABS.110(2.8)TO.250(6.4)×.020(.50)TO.032.(.80)VERTICAL OR HORIZONTAL ENTRYSMT -HORIZONTAL ENTRYSMT -VERTICAL OR HORIZONTAL ENTRYACCEPTS .312(7.9)TABOVER SIZED.032[0.8].062[1.6].400[10.2].134[3.4].150[3.8].150[3.8].185[4.7]Underwriters Laboratories,Inc.Recognized Component Program —UL File Number E201546CAT.MATL NO.ACCEPTS TAB “W”“A”THICK 3571.187(4.8)×.020(.51).222(5.6).162(4.1).012(.30)3572.187(4.8)×.032(.81)3546.205(5.2)×.020(.51).240(6.1).180(4.6).012(.30)3550.205(5.2)×.032(.81)3547.250(6.4)×.032(.81).291(7.4).205(5.2).016(.41).392[10.0].180[4.6].422[10.7].375[9.5].109[2.8].106[2.7].578[14.7].180[4.6].144[3.7].065[1.30]DIA.Mounting Detail Cat.No.3557.134[3.4].067[1.7]DIA.(2)PLS.Mounting Detail Cat.No.3577.067[1.7]DIA.(2)PLS.TERMINAL CLEARENCE.040[1.0].134[3.4].062[1.6].212[5.4].062[1.55]W.100[2.5]A.098[2.5].400[10.2].062[1.55].250[6.4]MATERIAL:.012(.30)Brass,Tin-Nickel Plate.050[1.3].125[3.2].281[7.1].437[11.1].091[2.3].291[7.4].110[2.8].250[6.3].086[2.2].062[1.55]W (Ref).440[11.2].156[4.0].144[3.7].125[3.2].196[5.0]CAT.NO.ACCEPTS TAB W 3534.110(2.8)×.020(.51).070(1.80)3544.110(2.8)×.032(.81).075(1.92).312[7.9].090[2.3].250[6.4].100[2.54].075[1.9].105[2.7].156[4.0].150[3.8].242[6.2].282[7.2].062[1.6].100[2.5].185[4.7].250[6.4].176[4.5].067[1.7].252[6.4].067[1.7]TYP..105[2.7]Mounting Detail.100[2.6].105[2.7].312[7.9]Mounting DetailSPECIFICATIONSMaterial:.012(.30)Brass,Tin-Nickel Plate Current Rating:15Amps @500V ACSPECIFICATIONSMaterial:.016(.40)Brass,Tin-Nickel Plate Current Rating:15Amps @500V ACTape &Reel Spec’s:16mm wide,12mm pitch,13inch reel (750pieces per reel)*Low insertion force designTape &Reel Spec’s:24mm wide,8mm pitch,13inch reel (2000pieces per reel)CAT.NO.ACCEPTS TAB “W”3548.187(4.8)×.020(.51).093(2.36)3578*.187(4.8)×.020(.51).093(2.36)3551.187(4.8)×.032(.81).102(2.59)CAT.NO.3569(Bulk)CAT.NO.3569TR (Tape &Reel)CAT.NO.3586TR (Tape &Reel)CAT.NO.3586(Bulk)FEMALE PC QUICK-FIT TERMINALS55ACCEPTS ALL TABS.110(2.8)TO.250(6.4)×.020(.50)TO.032.(.80)CAT.NO.ACCEPTS TAB3555.312(7.9)×.032(.81)35573577/分销商库存信息: KEYSTONE-ELECTRONICS 3577。
2SK3575-ZK资料
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.DATA SHEETDocument No. D16261EJ2V0DS00 (2nd edition)Date Published September 2002 NS CP(K)Printed in Japan©2002The mark ! shows major revised points.DESCRIPTIONThe 2SK3575 is N-channel MOS FET device that features a low on-state resistance and excellent switching characteristics, designed for low voltage high current applications such as DC/DC converter with synchronous rectifier.FEATURES•4.5V drive available •Low on-state resistanceR DS(on)1 = 4.5 m Ω MAX. (V GS = 10 V, I D = 42 A)•Low gate chargeQ G = 70 nC TYP. (V DD = 24 V, V GS = 10 V, I D = 83 A)•Avalanche capability ratings •Surface mount device availableABSOLUTE MAXIMUM RATINGS (T A = 25°C)Drain to Source Voltage (V GS = 0 V)V DSS 30V Gate to Source Voltage (V DS = 0 V)V GSS ±20V Drain Current (DC) (T C = 25°C)I D(DC)±83A Drain Current (pulse)Note1I D(pulse)±332A Total Power Dissipation (T A = 25°C)P T1 1.5W Total Power Dissipation (T C = 25°C)P T2105W Channel Temperature T ch 150°C Storage Temperature T stg–55 to +150°C Single Avalanche Current Note2I AS 57A Single Avalanche EnergyNote2E AS325mJNotes 1. PW ≤ 10 µs, Duty Cycle ≤ 1%2. Starting T ch = 25°C, V DD = 15 V, R G = 25 Ω, V GS = 20 → 0 VORDERING INFORMATIONPART NUMBER PACKAGE2SK3575TO-220AB 2SK3575-S TO-2622SK3575-ZK TO-2632SK3575-ZTO-220SMD NoteNote TO-220SMD package is produced only in Japan.5Data Sheet D16261EJ2V0DS2ELECTRICAL CHARACTERISTICS (T A = 25°C)CHARACTERISTICSSYMBOL TEST CONDITIONSMIN.TYP.MAX.UNITZero Gate Voltage Drain Current I DSS V DS = 30 V, V GS = 0 V 10µA Gate Leakage Current I GSS V GS = ±20 V, V DS = 0 V ±100nA Gate Cut-off Voltage V GS(off)V DS = 10 V, I D = 1 mA 1.5 2.5V Forward Transfer Admittance | y fs|V DS = 10 V, I D = 42 A 27S Drain to Source On-state ResistanceR DS(on)1V GS = 10 V, I D = 42 A 3.3 4.5mΩR DS(on)2V GS = 4.5 V, I D = 42 A 4.3 6.4mΩInput Capacitance C iss V DS = 10 V 3700pF Output CapacitanceC oss V GS = 0 V 1430pF Reverse Transfer Capacitance C rss f = 1 MHz500pF Turn-on Delay Timet d(on)V DD = 15 V, I D = 42 A 26ns Rise Timet r V GS = 10 V 27ns Turn-off Delay Time t d(off)R G = 10 Ω110ns Fall Timet f 40ns Total Gate Charge Q G V DD = 24 V 70nC Gate to Source Charge Q GS V GS = 10 V 12nC Gate to Drain Charge Q GD I D = 83 A20nC Body Diode Forward Voltage V F(S-D)I F = 83 A, V GS = 0 V 1.0V Reverse Recovery Time t rr I F = 83 A, V GS = 0 V 61ns Reverse Recovery ChargeQ rr di/dt = 100 A/µs94nCTEST CIRCUIT 3 GATE CHARGEV GS = 20 → 0 VPG.TEST CIRCUIT 1 AVALANCHE CAPABILITYL DDTEST CIRCUIT 2 SWITCHING TIMEL DDτ = 1 µsDuty Cycle ≤ 1%5Data Sheet D16261EJ2V0DS3TYPICAL CHARACTERISTICS (T A = 25°C)DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREATOTAL POWER DISSIPATION vs.CASE TEMPERATUREd T - Pe r c e n t a g e of R a t e d P o w e r -%0204060801001200255075100125150175T C - Case Temperature - °C P T - T o t a l P o w e r D i s s i p a t i o n -W020406080100120255075100125150175T C - Case Temperature - °CFORWARD BIAS SAFE OPERATING AREAI D - D r a i n C u r r e n t - A0.111010010000.1110100V DS - Drain to Source Voltage - VTRANSIENT THERMAL RESISTANCE vs. PULSE WIDTHr t h (t ) - T r a n s i e n t T h e r m a l R e s i s t a n c e - °C /W0.010.1110100PW - Pulse Width - s10 µ100 µ 1 m 10 m 100 m 1101001000Data Sheet D16261EJ2V0DS4DRAIN CURRENT vs.DRAIN TO SOURCE VOLTAGEFORWARD TRANSFER CHARACTERISTICSI D - D r a i n C u r r e n t - A0501001502002503003500.511.52V DS - Drain to Source Voltage - V I D - D r a i n C u r r e n t - A0.010.11101001000V GS - Gate to Source Voltage - VGATE CUT-OFF VOLTAGE vs.CHANNEL TEMPERATUREFORWARD TRANSFER ADMITTANCE vs.DRAIN CURRENTV G S (o f f ) - G a t e Cu t -o f f V o l t a g e - V00.511.522.53-5050100150T ch - Channel Temperature - °C| y f s | - F o r w a r d T r a n s f e r A d m i t t a n c e - S0.1110100I D - Drain Current - ADRAIN TO SOURCE ON-STATE RESISTANCE vs.DRAIN CURRENTDRAIN TO SOURCE ON-STATE RESISTANCE vs.GATE TO SOURCE VOLTAGER D S (o n ) - D r a i n t o S o u r c e O n -s t a t e R es i s t a n c e - m Ω1101001000I D - Drain Current - A R D S (o n ) - D r a i n t o S o u r c e O n -s t a t e R e s is t a n c e - m Ω02468102468101214161820V GS - Gate to Source Voltage - VData Sheet D16261EJ2V0DS5DRAIN TO SOURCE ON-STATE RESISTANCE vs.CHANNEL TEMPERATURECAPACITANCE vs. DRAIN TO SOURCE VOLTAGER D S (o n ) - D r a i n t o S o u r c e O n -s t a t e R e s i s t a n c e - m Ω-5050100150T ch - Channel Temperature - °C C i s s , Co s s , Cr s s - C a p a c i t a n c e - p F101001000100000.1110100V DS - Drain to Source Voltage - VSWITCHING CHARACTERISTICSDYNAMIC INPUT/OUTPUT CHARACTERISTICSt d (o n ), t r , t d (o f f ), t f - S w i t c h i n g T i m e - n s11010010000.1110100I D - Drain Current - A V D S - D r a i n t o S o u r c e V o l t a g e - V5101520253002040608024681012Q G - Gate Change - nCV G S - G a t e t o S o u r c e V o l t a g e - VSOURCE TO DRAIN DIODE FORWARD VOLTAGEREVERSE RECOVERY TIME vs.DRAIN CURRENTI F - D i o d e F o r w a r d C u r r e n t - A0.010.11101001000V F(S-D) - Source to Drain Voltage - V t r r - R e v e r s e R e c o v e r y T im e - n s11010010000.1110100I D - Drain Current - AData Sheet D16261EJ2V0DS6SINGLE AVALANCHE CURRENT vs.INDUCTIVE LOADSINGLE AVALANCHE ENERGY DERATING FACTORI A S - S i n g l e A v a l a n c h e C u r r e n t - A11010010000.010.1110L - Inductive Load - mH E n e r g y D e r a t i n g F a c t o r - %20406080100120255075100125150Starting T ch - Starting Channel Temperature - °CData Sheet D16261EJ2V0DS7PACKAGE DRAWINGS (Unit: mm)1) TO-220AB(MP-25)2) TO-262(MP-25 Fin Cut)Note This package is produced only in Japan.Remark Strong electric field, when exposed to this device, cancause destruction of the gate oxide and ultimatelydegrade the device operation. Steps must be taken to stop generation of static electricity as much as possible,and quickly dissipate it once, when it has occurred.5EQUIVALENT CIRCUITBody DiodeM8E 00. 4The information in this document is current as of September, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information.No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others.Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information.While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features.NEC semiconductor products are classified into the following three quality grades:"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application."Standard":Computers, office equipment, communications equipment, test and measurement equipment, audioand visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots"Special":Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disastersystems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support)"Specific":Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, lifesupport systems and medical equipment for life support, etc.The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application.(Note)(1)"NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.(2)"NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).••••••。
1879285资料
Extract from the onlinecatalogEMCV 1,5/ 2-GF-3,81Order No.: 1879285The figure shows a 10-position version of the producthttp://eshop.phoenixcontact.de/phoenix/treeViewClick.do?UID=1879285Header, nominal current: 8 A, rated voltage: 160 V, pitch: 3.81 mm, no. of positions: 2, mounting: Press inhttp://Please note that the data givenhere has been taken from theonline catalog. For comprehensiveinformation and data, please referto the user documentation. TheGeneral Terms and Conditions ofUse apply to Internet downloads. Technical dataDimensions / positionsPitch 3.81 mmNumber of positions2Pin dimensions0,8 x 0,8 mmHole diameter 1.45 mmTechnical dataInsulating material group IIIaRated surge voltage (III/3) 2.5 kVRated surge voltage (III/2) 2.5 kVRated surge voltage (II/2) 2.5 kVRated voltage (III/2)160 VRated voltage (II/2)250 VConnection in acc. with standard EN-VDENominal current I N8 ANominal voltage U N160 VMaximum load current8 AInsulating material PBTInflammability class acc. to UL 94V0Certificates / ApprovalsApproval logoCULNominal voltage U N300 VNominal current I N8 AULNominal voltage U N300 VNominal current I N8 ACertification CUL, GOST, ULAccessoriesItem Designation DescriptionAssembly1877258EMC 1,5-SH Stamp holder, for upper and lower stamp1877274EMCV 1,5-SS 1Stamp set, consisting of upper and lower stamp for 3.81 mm pitch,2 to 16-pos.Marking0804109SK 3,81/2,8:FORTL.ZAHLEN Marker card, printed horizontally, self-adhesive, 10-section markerstrip, 14 identical decades marked 1-10, 11-20 etc. up to 91-(99)100, sufficient for 140 terminal blocksPlug/Adapter1734634CP-MSTB Coding profile, is inserted into the slot on the plug or invertedheader, red insulating materialAdditional productsItem Designation DescriptionGeneral1851232FK-MCP 1,5/ 2-STF-3,81Plug, with screw flange, nominal current: 8 A, rated voltage: 160V, pitch: 3.81 mm, no. of positions: 2, type of connection: Spring-cage connection1850851FRONT-MC 1,5/ 2-STF-3,81Plug component, nominal current: 8 A, rated voltage: 160 V, pitch:3.81 mm, no. of positions: 2, type of connection: Screw connection 1827703MC 1,5/ 2-STF-3,81Plug component, nominal current: 8 A, rated voltage: 160 V, pitch:3.81 mm, no. of positions: 2, type of connection: Screw connection 1852367MCC 1/ 2-STZF-3,81Plug component, nominal current: 8 A, rated voltage: 160 V, pitch:3.81 mm, no. of positions: 2, type of connection: Crimp connection 1828346MCVR 1,5/ 2-STF-3,81Plug component, nominal current: 8 A, rated voltage: 160 V, pitch:3.81 mm, no. of positions: 2, type of connection: Screw connection 1828498MCVW 1,5/ 2-STF-3,81Plug component, nominal current: 8 A, rated voltage: 160 V, pitch:3.81 mm, no. of positions: 2, type of connection: Screw connection 1897542QC 0,5/ 2-STF-3,81Plug, nominal current: 6 A, rated voltage: 320 V, pitch: 3.81mm, number of positions: 2, connection method: Insulationdisplacement connection QUICKONDrawingsDrilling diagramDimensioned drawingAddressPHOENIX CONTACT GmbH & Co. KGFlachsmarktstr. 832825 Blomberg,GermanyPhone +49 5235 3 00Fax +49 5235 3 41200http://www.phoenixcontact.de© 2008 Phoenix ContactTechnical modifications reserved;。
80535资料
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ASTM-D3574中文版
Tensile Test
Page 2
ASTM —— 美国材料与试验协会
简介
美国材料与试验协会 （American Society for Testing and
Materials,ASTM） 前身是国际材料试验协会（International Association for Testing Materials, IATM）。 19世纪80年代，为解决采购商与供货商在购 销工业材料过程中产生的意见和分歧，有人 提出建立技术委员会制度，由技术委员会组 织各方面的代表参加技术座谈会，讨论解决 有关材料规范、试验程序等方面的争议问题。 IATM首次会议于1882年在欧洲召开，会上 组成了工作委员会。
TEST D Constant Deflection Compression Set Test 恒定压缩测试
前言
此项测试是事先将试样压缩到 规定的间距，进而将压制试样放 入特定氛围中保持一段时间后 将试样在特定环境中恢复形变，
测量试样前后的厚度变化
测试三个试样 最终数值应为三试样测试值的均值
Page 9
（见后表）中的方法准确 测量试样的尺寸，并计算体积
Page 6
Section 8——样品规格测量方法
1、使用标尺或者卷尺对试样的长度和宽度进行测量，注意测量时 不要挤压到泡棉；
2、测试厚度≤25mm的试样使用底座面积≥650m㎡带有转盘刻度的 厚度仪，按住转盘刻度控制装置使指针指向170±35Pa（注：由于 柔性泡棉的压缩强度低于1.65KPa，所以柔性泡棉的调整为100Pa） 厚度＞25mm的试样可以用转盘厚度仪测试，也可以用游标卡尺或 者步骤1中所述测试工具。使用游标卡尺测量时，请将游标卡尺附 于试样上进行测量，事先将试样放于仪器中再进行仪器调整，注意 测量时只需让仪器测量部分轻触试样表面，不能挤压试样。
镀锌板国家新标准
注：其他锌层代号的锌层重量及相当锌层厚度，可按表列值以“内插法”求出，或由供需双方协商确定。
表A.2
计算顺序计算方法结果的位数
基板的基本重量/（kg/(mm*㎡)）7.85（厚度1mm，面积1㎡的重量）——
基板的单位重量/（kg/㎡）基板基本重量（kg/(mm*㎡)）X基板公称厚度（mm）修约到有效数字4位镀锌后单位重量/（kg/㎡）基板单位重量（kg/㎡）+锌层计算重量（kg/㎡）修约到有效数字4位
镀锌后钢板的面积/㎡宽度（mm）X长度(m)修约到有效数字4位
镀锌后1块钢板的重量/kg镀锌后的单位重量（kg*M-2）X面积（㎡）修约到有效数字3位
1捆的重量/kg1块的重量（kg）X同一尺寸1捆中的块数修约到kg的个位
总重量/kg各捆的重量之和（kg）Kg的整数
注1：基板公称厚度为订货公称厚度减去订货锌层代号相应的相当锌层厚度。
注2。
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BA3575FS
FElectrical characteristics curves
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BA3575FS
FExternal dimensions (Units: mm)
883
5) Internal standby switch. 6) Internal mute switch. 7) Internal ripple filter. 8) No output coupling capacitor required. 9) Internal beep circuit. 10) SSOP-A20 package.
FApplications Portable CD players
FFeatures 1) Low current consumption (when VCC = 2.4 V, the quiescent current is 4.9mA). 2) Suitable for use in digital audio equipment (voltage gain: GV = 11.8dB, output noise voltage: VNO = –102dBm typ.). 3) ATT circuit (gain switch). 4) AVC (Auto Volume Control) circuit, for output limiting.
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FMeasurement circuit
BA3575FS
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FMeasurement circuit switch table (Fig.1)
BA3575FS
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FApplication example
BA3575FS
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BA3575FS
FApplication notes (1) “Pop” sound By operating the BA3575FS according to the timing chart shown in Fig.3, it is possible to suppress generation of “pop” noise in the headphone output.
FAbsolute maximum ratings (Ta = 25_C)
FRecommended operating conditions (Ta = 25_C)
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FBlock diagram
BA3575FS
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(3) The PCB pattern for the external components should be designed carefully to prevent oscillation and degradation of the circuit characteristics. Keep the wiring tracks as short as possible, and ensure that there is no impedance between the common connections. The ripple filter pins (1 and 2) and the bias amplifier pins (3 and 4) cannot be used for external power supplies or reference voltages
BA3575FS
FElectrical characteristics(unless otherwis noted, Ta = 25_C, VCC = 2.4V, RL = 16Ω, f = 1kHz, DIN AUDIO, PWSW = ON, MUTE = OFF, ATT = OFF, and AVC = OFF)
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(4) Recommended operating conditions The curves in Fig.4 below show the maximum allowable power output (PO (Max.) / ch) plotted against the supply voltage (VCC) for different values of ambient temperature (Ta). When VCC y 3.6 V, operate the IC in the region below the dotted line, and do not exceed it. If the maximum allowable power output for each channel (PO (Max.) / ch) is exceeded, the internal power consumption will exceed the power dissipation capacity of the package, and destroy the IC.
(2) Application circuits Provided the recommended circuit constants are used, the application circuits should function correctly. However, we recommend that you confirm the characteristics of the circuits in actual use. If you change the circuit constants, check both the static and transient characteristics of the circuit, and allow sufficient margin to accommodate variations between both ICs and external components. In particular, the capacitors connected to the OUT 1, OUT 2, and VREF pins must have low impedance at high frequency, and have sufficient margin in their temperature characteristics. Also, use an electrolytic or tantalum capacitor for the capacitor connected to the BIASOUT terminal.
元器件交易网 Audio ICs
Low-current audio headphone driver
BA3575FS
The BA3575FS is a headphone driver with an AVC circuit that keeps the output below a fixed level. It features low current consumption, and low output noise, and is ideal for use in portable digital audio equipment.
FPin descriptions
BA3575FS
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BA3575FS
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BA3575FS
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BA3575FS