MAX6408BS中文资料

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MAXIM MAX364 MAX365 数据手册

MAXIM MAX364 MAX365 数据手册

________________General DescriptionThe MAX364/MAX365 are precision, quad, single-pole single-throw (SPST) analog switches. The MAX364 has four normally closed (N C), and the MAX365 has four normally open (N O) switches. Both parts offer low-channel on -resistance (less than 85Ω), guaranteed to match within 2Ω between channels and to remain flat over the analog signal range (∆9Ω max). Both parts also offer low leakage (less than 500pA at +25°C and less than 4nA at +85°C) and fast switching (turn-on time less than 250ns and turn-off time less than 170ns).The MAX364/MAX365 are fabricated with Maxim’s new improved 44V silicon-gate process. Design improve-ments guarantee extremely low charge injection (10pC), low power consumption (35µW), and electro-static discharge (ESD) greater than 2000V. The 44V maximum breakdown voltage allows rail-to-rail analog signal handling capability.These monolithic switches operate with a single positive supply (+10V to +30V) or with split supplies (±4.5V to ±20V) while retaining CMOS-logic input compatibility and fast switching. CMOS inputs provide reduced input loading.________________________ApplicationsSample-and-Hold Circuits Communication Systems Guidance and Control Systems Battery-Operated Systems Heads-Up Displays PBX, PABX Test EquipmentMilitary Radios____________________________Features♦ Low On-Resistance: < 45Ω Typical (85Ω Max)♦ Guaranteed Matched On-Resistance Between Channels: < 2Ω♦ Guaranteed Flat On-Resistance over Full Analog Signal Range: ∆9ΩMax♦Guaranteed Charge Injection: < 10pC♦Guaranteed Off-Channel Leakage: < 4nA at +85°C ♦ESD Guaranteed > 2000V per Method 3015.7♦Single-Supply Operation (+10V to +30V)Bipolar-Supply Operation (±4.5V to ±20V)♦TTL-/CMOS-Logic Compatible♦Rail-to-Rail Analog Signal Handling CapabilityOrdering InformationMAX364/MAX365Precision, Quad, SPST Analog Switches_____________________ Pin Configurations/Functional Diagrams/Truth Tables19-0181; Rev 2; 6/04________________________________________________________________Maxim Integrated Products 1For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at .* Contact factory for dice specifications.M A X 364/M A X 365Precision, Quad, SPST Analog SwitchesABSOLUTE MAXIMUM RATINGSELECTRICAL CHARACTERISTICS—Dual Supplies(V+ = 15V, V- = -15V, VL = 5V, GND = 0V, V INH = 2.4V, V INL = 0.8V, T A = T MIN to T MAX , unless otherwise noted.)Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Voltage Referenced to V-V+........................................................................................44V GND....................................................................................25V VL..................................................(GND - 0.3V) to (V+ + 0.3V)IN_, COM_, NO_, or NC_..........(V- - 2V) to (V+ + 2V) or 30mA (whichever occurs first)Continuous Current (any terminal)......................................30mA Peak Current COM_, NO_, or NC_(pulsed at 1ms, 10% duty cycle max)...........................100mA ESD....................................................................................2000V Note 1: All leads are soldered or welded to PC board.Continuous Power Dissipation (T A = +70°C) (Note 1)Plastic DIP (derate 10.53mW/°C above +70°C )............842mW Thin QFN (derate 33.3mW/°C above +70°C )..............2667mW Narrow SO (derate 8.70mW/°C above +70°C) .............696mW Operating Temperature Ranges:MAX36_C_ _ ........................................................0°C to +70°C MAX36_E_ _......................................................-40°C to +85°C Storage Temperature Range.............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°CMAX364/MAX365Precision, Quad, SPST Analog Switches_______________________________________________________________________________________3ELECTRICAL CHARACTERISTICS—Dual Supplies (continued)(V+ = 15V, V- = -15V, VL = 5V, GND = 0V, V INH = 2.4V, V INL = 0.8V, T A = T MIN to T MAX , unless otherwise noted.)M A X 364/M A X 365Precision, Quad, SPST Analog Switches 4_______________________________________________________________________________________ELECTRICAL CHARACTERISTICS—Single Supply(V+ = 12V, V- = 0V, VL = 5V, GND = 0V, V INH = 2.4V, V INL = 0.8V, T A = T MIN to T MAX , unless otherwise noted.)Note 2:The algebraic convention, where the most negative value is a minimum and the most positive value a maximum, is used inthis data sheet.Note 3:Guaranteed by design.Note 4:Note 5:See Figure 2. Off Isolation = 20 log 10COM = output, V NO or V NC = input to off switch.Note 6:Between any two switches. See Figure 5.MAX364/MAX365Precision, Quad, SPST Analog Switches_______________________________________________________________________________________5__________________________________________Typical Operating Characteristics(T A = +25°C, unless otherwise noted.)ON LEAKAGE CURRENTSI C O M (n A )-2-112-1515V NC , V NO , V COM (V)OFF LEAKAGE CURRENTSI N C o r I N O (n A )-101-1515V NC , V NO, V COM (V)SWITCHING THRESHOLD vs. BIPOLAR SUPPLY VOLTAGEV I N (V )0.51.52.02.53.03.5±5±10±15±20BIPOLAR SUPPLY VOLTAGE (V)ON RESISTANCE vs. V COM AND UNIPOLAR SUPPLY VOLTAGE02550751001255101520V COM (V)R O N (Ω)150ON RESISTANCE vs. V COM , UNIPOLAR SUPPLY VOLTAGE AND TEMPERATURE255075100125150R O N (Ω)4812VCOM (V)ON RESISTANCE vs. V COM AND BIPOLAR SUPPLY VOLTAGER O N (Ω)306090120-20-1001020V COM(V)0ON RESISTANCE vs. V COM ,BIPOLAR SUPPLY VOLTAGE AND TEMPERATURER O N (Ω)20406080100-14-70714V COM (V)SWITCHING TIME vs. BIPOLAR SUPPLY VOLTAGET I ME (n s )04080120160±5±10±15±20BIPOLAR SUPPLY VOLTAGE (V)SWITCHING TIMES vs. UNIPOLAR SUPPLY VOLTAGET I M E (n s )05010015020010152024UNIPOLAR SUPPLY VOLTAGE (V)M A X 364/M A X 365Precision, Quad, SPST Analog Switches 6_________________________________________________________________________________________________________________________________Typical Operating Characteristics(T A = +25°C, unless otherwise noted.)Q (p C )-20020-14-1001014V COM (V)Q (p C )-1051012V COM (V)10______________________________________________________________Pin DescriptionCHARGE INJECTION vs.V COM VOLTAGECHARGE INJECTION vs.V COM VOLTAGE__________Applications InformationApplication Hints1. Switches are open when power is off.2. IN_, COM_, NO_, and NC_ should not exceed V+ orV-, even with the power off.3. Switch leakage is from each analog switch terminalto V+ or V-, not to the other switch terminal.Operation with Supply VoltagesOther than ±15V O The main limitation of supply voltages other than ±15V is reduction in the analog signal range. The MAX364/MAX365 switches operate with ±5V to ±20V bipolar supplies. The Typical Operating Characteristics graphs show typical on resistance for ±15V, ±10V, and ±5V supplies. Switching times increase by a factor of two or more for ±5V opera-tion. The MAX364/MAX365 operate from unipolar sup-plies of +10V to +24V. Both parts can be powered from a single +10V to +24V supply, as well as from unbalanced supplies, such as +24V and -5V. Connect V- to 0V when operating with a single supply. VL must be connected to +5V to be TTL compatible or to V+ for CMOS logic input levels.Overvoltage Protection Proper power-supply sequencing is recommended for all CMOS devices. It is important not to exceed the absolute maximum ratings, because stresses beyond those listed may cause permanent damage to the devices. Always sequence V+ on first, followed by VL, V-, and logic inputs. If power-supply sequencing is not possible, protect the devices from overvoltage bypins (Figure 1). Adding the diodes reduces the analogsignal range to 1V below V+ and 1V below V-, but low switch resistance and low leakage characteristics are unaffected. Device operation is unchanged, and the difference between V+ to V- should not exceed +44V.MAX364/MAX365Precision, Quad, SPST Analog Switches _______________________________________________________________________________________7M A X 364/M A X 365Precision, Quad, SPST Analog Switches 8_______________________________________________________________________________________Figure 3. Charge-Injection Test Circuit______________________________________________Test Circuits/Timing DiagramsMAX364/MAX365Precision, Quad, SPST Analog Switches_______________________________________________________________________________________9FREQUENCY TESTED SIGNAL GENERATORANALYZER100Hz to 13MHzAUTOMATIC SYNTHESIZERSPECTRUM ANALYZERFigure 6. COM_, NC_, NO_ Off CapacitanceFigure 7. COM_, NC_, NO_ On Capacitance_________________________________Test Circuits/Timing Diagrams (continued)M A X 364/M A X 365Precision, Quad, SPST Analog Switches 10____________________________________________________________________________________________Pin Configurations/Functional Diagrams (continued)MAX364/MAX365Precision, Quad, SPST Analog Switches______________________________________________________________________________________11Package Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to /packages .)M A X 364/M A X 365Precision, Quad, SPST Analog Switches 12______________________________________________________________________________________Package Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to /packages .)MAX364/MAX365Precision, Quad, SPST Analog SwitchesMaxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________13©2004 Maxim Integrated ProductsPrinted USAis a registered trademark of Maxim Integrated Products.Package Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to /packages .)。

MAX13085EESA-T中文资料

MAX13085EESA-T中文资料

General DescriptionThe MAX13080E–MAX13089E +5.0V, ±15kV ESD-protect-ed, RS-485/RS-422 transceivers feature one driver and one receiver. These devices include fail-safe circuitry,guaranteeing a logic-high receiver output when receiver inputs are open or shorted. The receiver outputs a logic-high if all transmitters on a terminated bus are disabled (high impedance). The MAX13080E–MAX13089E include a hot-swap capability to eliminate false transitions on the bus during power-up or hot insertion.The MAX13080E/MAX13081E/MAX13082E feature reduced slew-rate drivers that minimize EMI and reduce reflections caused by improperly terminated cables, allowing error-free data transmission up to 250kbps. The MAX13083E/MAX13084E/MAX13085E also feature slew-rate-limited drivers but allow transmit speeds up to 500kbps. The MAX13086E/MAX13087E/MAX13088E driver slew rates are not limited, making transmit speeds up to 16Mbps possible. The MAX13089E slew rate is pin selectable for 250kbps,500kbps, and 16Mbps.The MAX13082E/MAX13085E/MAX13088E are intended for half-duplex communications, and the MAX13080E/MAX13081E/MAX13083E/MAX13084E/MAX13086E/MAX13087E are intended for full-duplex communica-tions. The MAX13089E is selectable for half-duplex or full-duplex operation. It also features independently programmable receiver and transmitter output phase through separate pins.The MAX13080E–MAX13089E transceivers draw 1.2mA of supply current when unloaded or when fully loaded with the drivers disabled. All devices have a 1/8-unit load receiver input impedance, allowing up to 256transceivers on the bus.The MAX13080E/MAX13083E/MAX13086E/MAX13089E are available in 14-pin PDIP and 14-pin SO packages.The MAX13081E/MAX13082E/MAX13084E/MAX13085E/MAX13087E/MAX13088E are available in 8-pin PDIP and 8-pin SO packages. The devices operate over the com-mercial, extended, and automotive temperature ranges.ApplicationsUtility Meters Lighting Systems Industrial Control Telecom Security Systems Instrumentation ProfibusFeatures♦+5.0V Operation♦Extended ESD Protection for RS-485/RS-422 I/O Pins±15kV Human Body Model ♦True Fail-Safe Receiver While Maintaining EIA/TIA-485 Compatibility ♦Hot-Swap Input Structures on DE and RE ♦Enhanced Slew-Rate Limiting Facilitates Error-Free Data Transmission(MAX13080E–MAX13085E/MAX13089E)♦Low-Current Shutdown Mode (Except MAX13081E/MAX13084E/MAX13087E)♦Pin-Selectable Full-/Half-Duplex Operation (MAX13089E)♦Phase Controls to Correct for Twisted-Pair Reversal (MAX13089E)♦Allow Up to 256 Transceivers on the Bus ♦Available in Industry-Standard 8-Pin SO PackageMAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers________________________________________________________________Maxim Integrated Products 1Ordering Information19-3590; Rev 1; 4/05For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at .Selector Guide, Pin Configurations, and Typical Operating Circuits appear at end of data sheet.Ordering Information continued at end of data sheet.M A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers 2_______________________________________________________________________________________ABSOLUTE MAXIMUM RATINGSDC ELECTRICAL CHARACTERISTICS(V CC = +5.0V ±10%, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = +5.0V and T A = +25°C.) (Note 1)Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.(All Voltages Referenced to GND)Supply Voltage (V CC ).............................................................+6V Control Input Voltage (RE , DE, SLR,H/F , TXP, RXP)......................................................-0.3V to +6V Driver Input Voltage (DI)...........................................-0.3V to +6V Driver Output Voltage (Z, Y, A, B).............................-8V to +13V Receiver Input Voltage (A, B)....................................-8V to +13V Receiver Input VoltageFull Duplex (A, B)..................................................-8V to +13V Receiver Output Voltage (RO)....................-0.3V to (V CC + 0.3V)Driver Output Current.....................................................±250mAContinuous Power Dissipation (T A = +70°C)8-Pin SO (derate 5.88mW/°C above +70°C).................471mW 8-Pin Plastic DIP (derate 9.09mW/°C above +70°C).....727mW 14-Pin SO (derate 8.33mW/°C above +70°C)...............667mW 14-Pin Plastic DIP (derate 10.0mW/°C above +70°C)...800mW Operating Temperature RangesMAX1308_EC_ _.................................................0°C to +75°C MAX1308_EE_ _..............................................-40°C to +85°C MAX1308_EA_ _............................................-40°C to +125°C Junction Temperature......................................................+150°C Storage Temperature Range.............................-65°C to +150°C Lead Temperature (soldering, 10s).................................+300°CMAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers_______________________________________________________________________________________3DC ELECTRICAL CHARACTERISTICS (continued)(V CC = +5.0V ±10%, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = +5.0V and T A = +25°C.) (Note 1)M A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers 4_______________________________________________________________________________________DRIVER SWITCHING CHARACTERISTICSMAX13080E/MAX13081E/MAX13082E/MAX13089E WITH SRL = UNCONNECTED (250kbps)(V CC = +5.0V ±10%, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = +5.0V and T A = +25°C.)RECEIVER SWITCHING CHARACTERISTICSMAX13080E/MAX13081E/MAX13082E/MAX13089E WITH SRL = UNCONNECTED (250kbps)(V CC = +5.0V ±10%, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = +5.0V and T A = +25°C.)MAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers_______________________________________________________________________________________5DRIVER SWITCHING CHARACTERISTICSMAX13083E/MAX13084E/MAX13085E/MAX13089E WITH SRL = V CC (500kbps)(V CC = +5.0V ±10%, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = +5.0V and T A = +25°C.)RECEIVER SWITCHING CHARACTERISTICSMAX13083E/MAX13084E/MAX13085E/MAX13089E WITH SRL = V CC (500kbps)(V CC = +5.0V ±10%, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = +5.0V and T A = +25°C.)M A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers 6_______________________________________________________________________________________DRIVER SWITCHING CHARACTERISTICSMAX13086E/MAX13087E/MAX13088E/MAX13089E WITH SRL = GND (16Mbps)(V CC = +5.0V ±10%, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = +5.0V and T A = +25°C.)RECEIVER SWITCHING CHARACTERISTICSMAX13086E/MAX13087E/MAX13088E/MAX13089E WITH SRL = GND (16Mbps)(V CC = +5.0V ±10%, T A = T MIN to T MAX , unless otherwise noted. Typical values are at V CC = +5.0V and T A = +25°C.)Note 2:∆V OD and ∆V OC are the changes in V OD and V OC , respectively, when the DI input changes state.Note 3:The short-circuit output current applies to peak current just prior to foldback current limiting. The short-circuit foldback outputcurrent applies during current limiting to allow a recovery from bus contention.MAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers_______________________________________________________________________________________70.800.901.501.101.001.201.301.401.60-40-10520-253550958011065125SUPPLY CURRENT vs. TEMPERATURETEMPERATURE (°C)S U P P L Y C U R R E N T (m A )0201040305060021345OUTPUT CURRENTvs. RECEIVER OUTPUT-HIGH VOLTAGEM A X 13080E -89E t o c 02OUTPUT HIGH VOLTAGE (V)O U T P U T C U R R E N T (m A )20104030605070021345OUTPUT CURRENTvs. RECEIVER OUTPUT-LOW VOLTAGEM A X 13080E -89E t o c 03OUTPUT LOW VOLTAGE (V)O U T P U T C U R R E N T (m A )4.04.44.24.84.65.25.05.4RECEIVER OUTPUT-HIGH VOLTAGEvs. TEMPERATURETEMPERATURE (°C)O U T P U T H I G H V O L T A G E (V )-40-10520-2535509580110651250.10.70.30.20.40.50.60.8RECEIVER OUTPUT-LOW VOLTAGEvs. TEMPERATURETEMPERATURE (°C)O U T P U T L O W V O L T A G E (V )-40-10520-25355095801106512502040608010012014016012345DRIVER DIFFERENTIAL OUTPUT CURRENT vs. DIFFERENTIAL OUTPUT VOLTAGEDIFFERENTIAL OUTPUT VOLTAGE (V)D I F FE R E N T I A L O U T P U T C U R R E N T (m A )2.02.82.43.63.24.44.04.8DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs. TEMPERATURED I F FE R E N T I A L O U T P U T V O L T A G E (V )-40-10520-253550958011065125TEMPERATURE (°C)40201008060120140180160200-7-5-4-6-3-2-1012354OUTPUT CURRENT vs. TRANSMITTEROUTPUT-HIGH VOLTAGEOUTPUT HIGH VOLTAGE (V)O U T P U T C U R R E N T (m A )60402080100120140160180200042681012OUTPUT CURRENT vs. TRANSMITTEROUTPUT-LOW VOLTAGEOUTPUT-LOW VOLTAGE (V)O U T P U T C U R R E N T (m A )Typical Operating Characteristics(V CC = +5.0V, T A = +25°C, unless otherwise noted.)M A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers 8_______________________________________________________________________________________21543679810SHUTDOWN CURRENT vs. TEMPERATUREM A X 13080E -89E t o c 10S H U T D O W N C U R R E N T (µA )-40-10520-253550958011065125TEMPERATURE (°C)600800700100090011001200DRIVER PROPAGATION DELAY vs. TEMPERATURE (250kbps)D R I VE R P R O P A G A T I O N D E L A Y (n s )-40-10520-253550958011065125TEMPERATURE (°C)300400350500450550600DRIVER PROPAGATION DELAY vs. TEMPERATURE (500kbps)D R I VE R P R O P A G A T I O N D E L A Y (n s )-40-10520-253550958011065125TEMPERATURE (°C)1070302040506080DRIVER PROPAGATION DELAY vs. TEMPERATURE (16Mbps)D R I VE R P R O P A G A T I O N D E L A Y (n s )-40-10520-253550958011065125TEMPERATURE (°C)40201008060120140160180RECEIVER PROPAGATION DELAYvs. TEMPERATURE (250kpbs AND 500kbps)R E C E I V E R P R O P A G A T I O N D E L A Y (n s )-40-10520-253550958011065125TEMPERATURE (°C)40201008060120140160180RECEIVER PROPAGATION DELAYvs. TEMPERATURE (16Mbps)R EC E I V E R P R O P A G AT I O N D E L A Y (n s )-40-10520-253550958011065125TEMPERATURE (°C)2µs/div DRIVER PROPAGATION DELAY (250kbps)DI 2V/divV Y - V Z 5V/divR L = 100Ω200ns/divRECEIVER PROPAGATION DELAY(250kbps AND 500kbps)V A - V B 5V/divRO 2V/divTypical Operating Characteristics (continued)(V CC = +5.0V, T A = +25°C, unless otherwise noted.)MAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers_______________________________________________________________________________________9Test Circuits and Waveforms400ns/divDRIVER PROPAGATION DELAY (500kbps)DI 2V/divR L = 100ΩV Y - V Z 5V/div10ns/div DRIVER PROPAGATION DELAY (16Mbps)DI 2V/divR L = 100ΩV Y 2V/divV Z 2V/div40ns/divRECEIVER PROPAGATION DELAY (16Mbps)V B 2V/divR L = 100ΩRO 2V/divV A 2V/divTypical Operating Characteristics (continued)(V CC = +5.0V, T A = +25°C, unless otherwise noted.)Figure 2. Driver Timing Test CircuitM A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers 10______________________________________________________________________________________Test Circuits and Waveforms (continued)Figure 4. Driver Enable and Disable Times (t DHZ , t DZH , t DZH(SHDN))DZL DLZ DLZ(SHDN)MAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversTest Circuits and Waveforms (continued)Figure 6. Receiver Propagation Delay Test CircuitM A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversMAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversMAX13080E/MAX13083E/MAX13086EMAX13081E/MAX13084E/MAX13086E/MAX13087EFunction TablesM A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers MAX13082E/MAX13085E/MAX13088EFunction Tables (continued)MAX13089EDetailed Description The MAX13080E–MAX13089E high-speed transceivers for RS-485/RS-422 communication contain one driver and one receiver. These devices feature fail-safe circuit-ry, which guarantees a logic-high receiver output when the receiver inputs are open or shorted, or when they are connected to a terminated transmission line with all dri-vers disabled (see the Fail-Safe section). The MAX13080E/MAX13082E/MAX13083E/MAX13085E/ MAX13086E/MAX13088E/MAX13089E also feature a hot-swap capability allowing line insertion without erroneous data transfer (see the Hot Swap Capability section). The MAX13080E/MAX13081E/MAX13082E feature reduced slew-rate drivers that minimize EMI and reduce reflec-tions caused by improperly terminated cables, allowing error-free data transmission up to 250kbps. The MAX13083E/MAX13084E/MAX13085E also offer slew-rate limits allowing transmit speeds up to 500kbps. The MAX13086E/MAX13087E/MAX13088Es’ driver slew rates are not limited, making transmit speeds up to 16Mbps possible. The MAX13089E’s slew rate is selectable between 250kbps, 500kbps, and 16Mbps by driving a selector pin with a three-state driver.The MAX13082E/MAX13085E/MAX13088E are half-duplex transceivers, while the MAX13080E/MAX13081E/ MAX13083E/MAX13084E/MAX13086E/MAX13087E are full-duplex transceivers. The MAX13089E is selectable between half- and full-duplex communication by driving a selector pin (H/F) high or low, respectively.All devices operate from a single +5.0V supply. Drivers are output short-circuit current limited. Thermal-shutdown circuitry protects drivers against excessive power dissi-pation. When activated, the thermal-shutdown circuitry places the driver outputs into a high-impedance state.Receiver Input Filtering The receivers of the MAX13080E–MAX13085E, and the MAX13089E when operating in 250kbps or 500kbps mode, incorporate input filtering in addition to input hysteresis. This filtering enhances noise immunity with differential signals that have very slow rise and fall times. Receiver propagation delay increases by 25% due to this filtering.Fail-Safe The MAX13080E family guarantees a logic-high receiver output when the receiver inputs are shorted or open, or when they are connected to a terminated transmission line with all drivers disabled. This is done by setting the receiver input threshold between -50mV and -200mV. If the differential receiver input voltage (A - B) is greater than or equal to -50mV, RO is logic-high. If (A - B) is less than or equal to -200mV, RO is logic-low. In the case of a terminated bus with all transmitters disabled, the receiv-er’s differential input voltage is pulled to 0V by the termi-nation. With the receiver thresholds of the MAX13080E family, this results in a logic-high with a 50mV minimumnoise margin. Unlike previous fail-safe devices, the-50mV to -200mV threshold complies with the ±200mVEIA/TIA-485 standard.Hot-Swap Capability (Except MAX13081E/MAX13084E/MAX13087E)Hot-Swap InputsWhen circuit boards are inserted into a hot or powered backplane, differential disturbances to the data buscan lead to data errors. Upon initial circuit board inser-tion, the data communication processor undergoes itsown power-up sequence. During this period, the processor’s logic-output drivers are high impedanceand are unable to drive the DE and RE inputs of these devices to a defined logic level. Leakage currents up to±10µA from the high-impedance state of the proces-sor’s logic drivers could cause standard CMOS enableinputs of a transceiver to drift to an incorrect logic level. Additionally, parasitic circuit board capacitance couldcause coupling of V CC or GND to the enable inputs. Without the hot-swap capability, these factors could improperly enable the transceiver’s driver or receiver.When V CC rises, an internal pulldown circuit holds DElow and RE high. After the initial power-up sequence,the pulldown circuit becomes transparent, resetting thehot-swap tolerable input.Hot-Swap Input CircuitryThe enable inputs feature hot-swap capability. At theinput there are two NMOS devices, M1 and M2 (Figure 9). When V CC ramps from zero, an internal 7µstimer turns on M2 and sets the SR latch, which alsoturns on M1. Transistors M2, a 1.5mA current sink, andM1, a 500µA current sink, pull DE to GND through a5kΩresistor. M2 is designed to pull DE to the disabledstate against an external parasitic capacitance up to100pF that can drive DE high. After 7µs, the timer deactivates M2 while M1 remains on, holding DE low against three-state leakages that can drive DE high. M1 remains on until an external source overcomes the required input current. At this time, the SR latch resetsand M1 turns off. When M1 turns off, DE reverts to a standard, high-impedance CMOS input. Whenever V CCdrops below 1V, the hot-swap input is reset.For RE there is a complementary circuit employing two PMOS devices pulling RE to V CC. MAX13080E–MAX13089E+5.0V, ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversM A X 13080E –M A X 13089EMAX13089E ProgrammingThe MAX13089E has several programmable operating modes. Transmitter rise and fall times are programma-ble, resulting in maximum data rates of 250kbps,500kbps, and 16Mbps. To select the desired data rate,drive SRL to one of three possible states by using a three-state driver: V CC , GND, or unconnected. F or 250kbps operation, set the three-state device in high-impedance mode or leave SRL unconnected. F or 500kbps operation, drive SRL high or connect it to V CC .F or 16Mbps operation, drive SRL low or connect it to GND. SRL can be changed during operation without interrupting data communications.Occasionally, twisted-pair lines are connected backward from normal orientation. The MAX13089E has two pins that invert the phase of the driver and the receiver to cor-rect this problem. F or normal operation, drive TXP and RXP low, connect them to ground, or leave them uncon-nected (internal pulldown). To invert the driver phase,drive TXP high or connect it to V CC . To invert the receiver phase, drive RXP high or connect it to V CC . Note that the receiver threshold is positive when RXP is high.The MAX13089E can operate in full- or half-duplex mode. Drive H/F low, leave it unconnected (internal pulldown), or connect it to GND for full-duplex opera-tion. Drive H/F high for half-duplex operation. In full-duplex mode, the pin configuration of the driver and receiver is the same as that of a MAX13080E. In half-duplex mode, the receiver inputs are internally connect-ed to the driver outputs through a resistor-divider. This effectively changes the function of the device’s outputs.Y becomes the noninverting driver output and receiver input, Z becomes the inverting driver output and receiver input. In half-duplex mode, A and B are still connected to ground through an internal resistor-divider but they are not internally connected to the receiver.±15kV ESD ProtectionAs with all Maxim devices, ESD-protection structures are incorporated on all pins to protect against electro-static discharges encountered during handling and assembly. The driver outputs and receiver inputs of the MAX13080E family of devices have extra protection against static electricity. Maxim’s engineers have devel-oped state-of-the-art structures to protect these pins against ESD of ±15kV without damage. The ESD struc-tures withstand high ESD in all states: normal operation,shutdown, and powered down. After an ESD event, the MAX13080E–MAX13089E keep working without latchup or damage.ESD protection can be tested in various ways. The transmitter outputs and receiver inputs of the MAX13080E–MAX13089E are characterized for protec-tion to the following limits:•±15kV using the Human Body Model•±6kV using the Contact Discharge method specified in IEC 61000-4-2ESD Test ConditionsESD performance depends on a variety of conditions.Contact Maxim for a reliability report that documents test setup, test methodology, and test results.Human Body ModelFigure 10a shows the Human Body Model, and Figure 10b shows the current waveform it generates when dis-charged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest,which is then discharged into the test device through a 1.5k Ωresistor.IEC 61000-4-2The IEC 61000-4-2 standard covers ESD testing and performance of finished equipment. However, it does not specifically refer to integrated circuits. The MAX13080E family of devices helps you design equip-ment to meet IEC 61000-4-2, without the need for addi-tional ESD-protection components.+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversThe major difference between tests done using the Human Body Model and IEC 61000-4-2 is higher peak current in IEC 61000-4-2 because series resistance is lower in the IEC 61000-4-2 model. Hence, the ESD with-stand voltage measured to IEC 61000-4-2 is generally lower than that measured using the Human Body Model. Figure 10c shows the IEC 61000-4-2 model, and Figure 10d shows the current waveform for IEC 61000-4-2 ESD Contact Discharge test.Machine Model The machine model for ESD tests all pins using a 200pF storage capacitor and zero discharge resis-tance. The objective is to emulate the stress caused when I/O pins are contacted by handling equipment during test and assembly. Of course, all pins require this protection, not just RS-485 inputs and outputs.Applications Information256 Transceivers on the BusThe standard RS-485 receiver input impedance is 12kΩ(1-unit load), and the standard driver can drive up to 32-unit loads. The MAX13080E family of transceivers has a1/8-unit load receiver input impedance (96kΩ), allowingup to 256 transceivers to be connected in parallel on one communication line. Any combination of these devices,as well as other RS-485 transceivers with a total of 32-unit loads or fewer, can be connected to the line.Reduced EMI and ReflectionsThe MAX13080E/MAX13081E/MAX13082E feature reduced slew-rate drivers that minimize EMI and reduce reflections caused by improperly terminated cables, allowing error-free data transmission up to250kbps. The MAX13083E/MAX13084E/MAX13085Eoffer higher driver output slew-rate limits, allowing transmit speeds up to 500kbps. The MAX13089E withSRL = V CC or unconnected are slew-rate limited. WithSRL unconnected, the MAX13089E error-free data transmission is up to 250kbps. With SRL connected toV CC,the data transmit speeds up to 500kbps. MAX13080E–MAX13089E+5.0V, ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversM A X 13080E –M A X 13089ELow-Power Shutdown Mode (Except MAX13081E/MAX13084E/MAX13087E)Low-power shutdown mode is initiated by bringing both RE high and DE low. In shutdown, the devices typically draw only 2.8µA of supply current.RE and DE can be driven simultaneously; the devices are guaranteed not to enter shutdown if RE is high and DE is low for less than 50ns. If the inputs are in this state for at least 700ns, the devices are guaranteed to enter shutdown.Enable times t ZH and t ZL (see the Switching Characteristics section) assume the devices were not in a low-power shutdown state. Enable times t ZH(SHDN)and t ZL(SHDN)assume the devices were in shutdown state. It takes drivers and receivers longer to become enabled from low-power shutdown mode (t ZH(SHDN), t ZL(SHDN))than from driver/receiver-disable mode (t ZH , t ZL ).Driver Output ProtectionTwo mechanisms prevent excessive output current and power dissipation caused by faults or by bus contention.The first, a foldback current limit on the output stage,provides immediate protection against short circuits over the whole common-mode voltage range (see the Typical Operating Characteristics ). The second, a thermal-shut-down circuit, forces the driver outputs into a high-imped-ance state if the die temperature exceeds +175°C (typ).Line LengthThe RS-485/RS-422 standard covers line lengths up to 4000ft. F or line lengths greater than 4000ft, use the repeater application shown in Figure 11.Typical ApplicationsThe MAX13082E/MAX13085E/MAX13088E/MAX13089E transceivers are designed for bidirectional data commu-nications on multipoint bus transmission lines. F igures 12 and 13 show typical network applications circuits. To minimize reflections, terminate the line at both ends in its characteristic impedance, and keep stub lengths off the main line as short as possible. The slew-rate-lim-ited MAX13082E/MAX13085E and the two modes of the MAX13089E are more tolerant of imperfect termination.Chip InformationTRANSISTOR COUNT: 1228PROCESS: BiCMOS+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversFigure 11. Line Repeater for MAX13080E/MAX13081E/MAX13083E/MAX13084E/MAX13086E/MAX13087E/MAX13089E in Full-Duplex Mode+5.0V, ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversMAX13080E–MAX13089EM A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 TransceiversPin Configurations and Typical Operating CircuitsMAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers______________________________________________________________________________________21Pin Configurations and Typical Operating Circuits (continued)M A X 13080E –M A X 13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers 22______________________________________________________________________________________Ordering Information (continued)MAX13080E–MAX13089E+5.0V , ±15kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceivers______________________________________________________________________________________23Package Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,go to /packages .)。

PSX643技术说明书

PSX643技术说明书

规约转换器PSX640(COM板)软件使用说明国电南京自动化股份有限公司2001.08一、硬件概述本规约转换器分为PSX640和COM板两种类型。

其中PSX640为独立设备,它具有一个以太网接口,一个RS232/422/485接口,一个6位指拨开关;COM板为插件式模块,借用PSR650或PSX600电源,它具有三个以太网接口,两个RS232/422/485接口,一个8位指拨开关。

1、以太网的使用接至设备端时,应采用交叉线,接至HUB时,应采用直通线。

COM板三个接口的网络号部分不能相同。

目前子网掩码保留为255.255.0.0。

2、RS232/422/485的使用✓RS232管脚:2=收,3=发,5=公共地;RS422/485管脚:1=OUT-,2=OUT+,3=IN+,4=IN-。

✓方式选择由指拨开关决定,1、2号开关用于串口1,其中,1、2在OFF位置为232方式;1在ON位置为422方式;2在ON位置为485方式。

3、4号开关用于串口2(COM 板),方法类推。

方式选择是一种软跳线,最终由软件决定,改变开关设置后,只有在设备再次上电后才会有效。

✓COM板串口硬件接线分别由JP5-JP6(串口1)和JP7-JP8(串口2)设置,当工作在422/485方式时,需短接1-2;工作在232方式时, 需短接2-3。

PSX640采用了电子切换方式,只需使用相应的插座,无需设置硬件接线。

3、参数设置✓将COM板指拨开关7/8(PSX640:5/6)置于ON位置,使用串口线连接PC机和COM 板串口1/2(需设置为232接线方式)或PSX640的RS232口,上电。

✓启动Windows超级终端,设置PC串口波特率9600,数据位8,无校验,1位停止位, 【ASCII码发送】选项选中【以换行符作为发送行末尾】,【ASCII码接收】选项选中【将超过终端宽度的行自动换行】,按回车键,输入用户名(sac)和用户密码(1234),将显示选择菜单,可进行相应参数的设置。

Belimo MFT配置软件(V3.X)及相关配件说明书

Belimo MFT配置软件(V3.X)及相关配件说明书

203-791-8396 LATIN AMERICA/CARIBBEAN
Valve Accessories
Butterfly Valves
WEATHER SHIELDS
ZS-BFV-20* GM series for F6, F7 HD, HDU, VIC
ZS-BFV-30* AF series for F6, F7 HD, HDU, VIC
EXT-NSV-B23-230 Battery backup system, SY4 - SY6 230 VAC, on/off actuators
EXT-NSV-B24-230 Battery backup system, SY4 - SY6 230 VAC, MFT actuators
EXT-NSV-B25-230 Battery backup system, SY7 - SY12 230 VAC, on/off actuators
F6100HD+HND02 4” HD series valve with manual handle ductile iron, 200 psi close-off, Cv 600
F6125HD+HND02 5” HD series valve with manual handle ductile iron, 200 psi close-off, Cv 1022







ZK1-GEN Cable for use with ZTH US to connect to new generation non-spring return actuator via diagnostic/programming socket

MB85RC64中文

MB85RC64中文

铁电存储器MB85RC64(8K×8)1.概述MB85RC64了FRAM(铁电随机存取记忆体)独立芯片配置了8192×8位,形成铁电工艺和硅栅CMOS工艺技术非易失性内存中的细胞。

MB85RC64采用两线串行接口(与世界标准的I2C总线兼容)。

与SRAM不同的MB85RC64是无需使用数据备份电池,能够保留数据。

MB85RC64的读写次数10亿次,与EPROM和FLASH相比,有显著的改善。

而且不在向写完存储器后,不需要查询序列。

2.特性●位操作:8192×8位●工作电压:2.7V—3.3V●工作频率:400KHz●两串行总线:I2C总线2.1标准版,支持标准模式和快速模式,由SCL和SDA控制。

●工作温度范围:-40℃—85℃●数据保持:10年(55℃)●读写寿命:至少每位10亿次●封装:Plastic / SOP, 8-pin (FPT-8P-M02)●低电压消耗:工作电流0.15mA,待机电流5uA3.管脚分配3.管脚功能描述管教编号管脚名功能描述1—3 A0/A1/A2 器件地址一个I2C总线可以连接8个和MB85RC64类似的器件。

通过将A0/A1/A2与VDD和VSS连接,确定每个器件的地址。

如果A0/A1/A2未连接,默认为0。

CPU通过SDA线输出一个地址与器件进行匹配。

4 VSS 数字地5 SDA 数据IO串口这是双向通信的数据IO口,用来读写铁电存储器的阵列数据,这是开漏极输出,可能是与其它漏极开路(或者集电极开路信号总线)进行线或运算,因此需要一个上拉电阻连接到外部电路。

6 SCL 时钟串口这是时钟输入口,时钟上升沿进行数据采样,下降沿进行数据输出。

7 WP 写保护WP是H电平,禁止写入。

WP是L电平,可进行写数据,如果WP没有置位,默认为L电平。

而读数据操作,不受WP 管脚的限制。

8 VDD 电源电压4.模块框图5.I2C电路MB85RC64有两线串行接口,支持I2C总线,并作为从器件工作。

数据表面板PS6800WC产品说明书

数据表面板PS6800WC产品说明书

AC Model 100 to 240 Vac
Standard DC Model 12-24 Vdc ±20 % When using
AC Model 100 to 240 Vac
Input voltage limits
18...31.2 Vdc
85...264 Vac
18...31.2 Vdc
85...264 Vac
Ambient Air Temperature
Panel (Landscape) mounting: 0...55 °C (32...131 °F) with/without FAN kit (for 19” Wide, 0...50 °C (32...122 °F) with/without FAN kit), Panel (Portrait) mounting: 0...50 °C (32...122 °F) with/without FAN kit
260-pin SODIMM socket x 2, DDR4-2133 (Up to 16 GB/socket, up to 32 GB for 2 sockets)
260-pin SODIMM socket x 2, DDR4-2400 (Up to 16 GB/socket, up to 32 GB for 2 sockets)
19"
100-240 Vac 24 Vdc
Buial Specifications PS6800 19" Display with choice of box unit
Rated Input Voltage
Advanced DC Model 12-24 Vdc ±20 % When using

MAX6818中文资料

MAX6818中文资料
o Pin-Compatible with ’LS573 (MAX6818)
Ordering Information
PART
TEMP. RANGE
PIN-
SOT
PACKAGE TOP MARK
MAX6816EUS-T -40°C to +85°C 4 SOT143
KABA
MAX6817EUT-T -40°C to +85°C 6 SOT23-6
OUT Short-Circuit Duration (One or Two Outputs to GND)....................................Continuous
Continuous Power Dissipation (TA = +70°C) 4-Pin SOT143 (derate 4.0mW/°C above +70°C)..........320mW 6-Pin SOT23 (derate 8.7mW/°C above +70°C)............691mW 20-Pin SSOP (derate 8.0mW/°C above +70°C) ...........640mW
Input Threshold
Input Hysteresis Input Pull-Up Resistance IN Input Current Input Voltage Range Undervoltage-Lockout Threshold
SYMBOL VCC ICC
tDP
VIL
VIH
CONDITIONS
Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering, 10sec) .............................+300°C

Pro Max数字混合插卡拼接矩阵

Pro Max数字混合插卡拼接矩阵

Pro Max数字混合插卡拼接矩阵产品概述:PRO-MAX系列混合拼接矩阵切换器是一款配置灵活的拼接与无缝矩阵信号切换器。

采用高性能的硬件设计,完美支持各类高清晰数字/模拟信号切换处理,为各行业的多种视频及控制信号分配切换处理提供一站式解决方案,可广泛应用于广播电视工程、多媒体会议厅、大屏幕显示工程、电视教学、智能交通管理中心、指挥控制中心等场所。

PRO-MAX系列混合拼接矩阵切换器包含0808、1616、3636、7272、144144、288288等型号切换器,它的信号输入输出接口包括HDMI、DVI、VGA、HDBaseT、SDI、光纤等视频接口。

领先的全数字信号处理技术可保证信号无失真处理,将最优质的画面送至显示终端。

通过定制配置各类相同或不同的输入输出卡可以组成单一接口类型或多接口类型的矩阵,如光纤矩阵,HDMI矩阵,DVI矩阵,CAT5矩阵,VGA矩阵,YUV矩阵,Video矩阵等。

PRO-MAX系列混合拼接矩阵切换器提供多种控制模式,具有遥控器操作,RS-485扩展键盘操作,还提供2路标准RS-232通讯接口和网络端口,方便用户与各种远端控制设备配合使用。

功能特点:●全数字化切换,每种输出卡都能实现真正实时的无缝切换;●支持1080p分辨率;●支持DVI 1.0协议,符合HDCP1.3标准,兼容HDMI 1.3a;●支持热插拔,支持音视频信号一起切换,支持音频AUTO DELAY;●DVI-D接口,3.5mm音频座,支持模拟音频输入;●支持EDID读取,PC软件控制切换与EDID管理;●控制方式灵活,具有红外遥控,RS485,RS-232通讯接口和网络端口;●支持固件在线升级;●支持智能控制矩阵风扇的运行;●插卡式结构设计,可灵活配置输入输出信号类型及信号通道数。

●输出板卡支持自定义分辨率;●HDMI、DVI前驱35m;●输入端口字幕设置功能;●最大支持分辨率:HDPC:1920x1200P@60;HDTV:1920x1080P@60。

MAX1978中文数据手册

MAX1978中文数据手册

用于Peltier模块的集成温度控制器概论MAX1978 / MAX1979是用于Peltier热电冷却器(TEC)模块的最小, 最安全, 最精确完整的单芯片温度控制器。

片上功率FET和热控制环路电路可最大限度地减少外部元件, 同时保持高效率。

可选择的500kHz / 1MHz开关频率和独特的纹波消除方案可优化元件尺寸和效率, 同时降低噪声。

内部MOSFET的开关速度经过优化, 可降低噪声和EMI。

超低漂移斩波放大器可保持±0.001°C的温度稳定性。

直接控制输出电流而不是电压, 以消除电流浪涌。

独立的加热和冷却电流和电压限制提供最高水平的TEC保护。

MAX1978采用单电源供电, 通过在两个同步降压调节器的输出之间偏置TEC, 提供双极性±3A输出。

真正的双极性操作控制温度, 在低负载电流下没有“死区”或其他非线性。

当设定点非常接近自然操作点时, 控制系统不会捕获, 其中仅需要少量的加热或冷却。

模拟控制信号精确设置TEC 电流。

MAX1979提供高达6A的单极性输出。

提供斩波稳定的仪表放大器和高精度积分放大器, 以创建比例积分(PI)或比例积分微分(PID)控制器。

仪表放大器可以连接外部NTC或PTC热敏电阻, 热电偶或半导体温度传感器。

提供模拟输出以监控TEC温度和电流。

此外, 单独的过热和欠温输出表明当TEC温度超出范围时。

片上电压基准为热敏电阻桥提供偏置。

MAX1978 / MAX1979采用薄型48引脚薄型QFN-EP 封装, 工作在-40°C至+ 85°C温度范围。

采用外露金属焊盘的耐热增强型QFN-EP封装可最大限度地降低工作结温。

评估套件可用于加速设计。

应用光纤激光模块典型工作电路出现在数据手册的最后。

WDM, DWDM激光二极管温度控制光纤网络设备EDFA光放大器电信光纤接口ATE特征♦尺寸最小, 最安全, 最精确完整的单芯片控制器♦片上功率MOSFET-无外部FET♦电路占用面积<0.93in2♦回路高度<3mm♦温度稳定性为0.001°C♦集成精密积分器和斩波稳定运算放大器♦精确, 独立的加热和冷却电流限制♦通过直接控制TEC电流消除浪涌♦可调节差分TEC电压限制♦低纹波和低噪声设计♦TEC电流监视器♦温度监控器♦过温和欠温警报♦双极性±3A输出电流(MAX1978)♦单极性+ 6A输出电流(MAX1979)订购信息* EP =裸焊盘。

MAX4080TASA+中文资料

MAX4080TASA+中文资料
5V/V (MAX4080F/MAX4081F) 20V/V (MAX4080T/MAX4081T) 60V/V (MAX4080S/MAX4081S) ♦ ±0.1% Full-Scale Accuracy ♦ Low 100µV Input Offset Voltage ♦ Independent Operating Supply Voltage ♦ 75µA Supply Current (MAX4080) ♦ Reference Input for Bidirectional OUT (MAX4081) ♦ Available in a Space-Saving 8-Pin µMAX Package
元器件交易网
MAX4080/MAX4081
19-2562; Rev 0; 10/02
EVAALVUAAILTAIOBNLEKIT
76V, High-Side, Current-Sense Amplifiers with Voltage Output
General Description
General System/Board-Level Current Sensing
Precision High-Voltage Current Sources
Features
♦ Wide 4.5V to 76V Input Common-Mode Range ♦ Bidirectional or Unidirectional ISENSE ♦ Low-Cost, Compact, Current-Sense Solution ♦ Three Gain Versions Available
(MAX4081 Only)....-0.3V to the lesser of +18V or (VCC + 0.3V) Output Short Circuit to GND.......................................Continuous Differential Input Voltage (VRS+ - VRS-) ...............................±80V Current into Any Pin..........................................................±20mA

MaxDOS8[1].0工具箱简介

MaxDOS8[1].0工具箱简介

MaxDOS 8.0|最强的MaxDOS工具箱集成DM/PQ版,U盘版,PXE版,光盘等其它的MaxDos8版本,请关注我们的网站,感谢您的使用.MaxDOS 8 更新如下:1.全面支持WINDOWS 2000,WINXP,WIN2003,VTISTA,WIN2008,WIN7 以及Win 64位操作系统.2.新版本采用一体包方式,即一个安装包支持所有操作系统,不再区分VISTA版或XP版.3.增加全自动一键备份还原功能,可直接在WINDOWS上实现备份及还原操作,以及支持还原自定义GHOST镜像功能(可实现在WIN上直接重装系统),自动进入DOS,自动完成操作.详细功能,请使用"开始菜单"-->"程序"-->"一键备份还原系统"4.新版本采相对稳定的GHOST 11.0.2,支持GHOST11.5镜像,丢弃GHOST 8.2版.5.更新常用程序及驱动至最新版增加HDDREG,SFDISK,DISKGEN3(支持NTFS 分区中文文件复制删除操作),AMI和AWORD BIOS刷新程序.6.新增在启动时选择引导方式,去掉原始的需要在进入WIN后在控制台更换的麻烦.7.增加新的常见网卡驱动10余种,以及修正一些原有发现的小BUG, 新版本增加原V6版之前的自动指定IP功能,以便解决有些用户遇到在GHOST客户端无法获取DHCP 服务端IP现像.8.对多个批处理文件进行人性化整理增加人性化功能及修复有些脚本存在的小问题.9.新版本会同时有三种的网刻模式,可配合其它的DHCP服务端网刻,或者使用生成IP网刻.10.增加热键F7 直接启动MAXDOS,就算系统挂掉,或BOOTMGR,BOOT.INI损坏,一样可启动.11.增加直接启动硬盘存在的指定CDISO镜像,由于程序限制非所有ISO都可启动.12.原IE纠错插件不再强制,用户可选择性安装.13.全新控制台程序,实现程序更加自动化.增加自动纠错备份路径及目标错误问题.14.改进原有全自动备份还原默认为备份第一分区,改为默认备份当前系统盘.============================================================= ==================软件特色功能如下:1, 为装好的Win2K/XP/2K3/VISTA/2008/7 系统加入DOS,方便维护与备份还原.2, 支持进入DOS时设置密码,密码采用MD5加密,支持启动时热键F7 启动.3, 内置约300种网卡驱动,实现GHOST自动网克及DOS下访问局域网的共享资源.4, 全中文的菜单式操作方式,易上手,支持DOS下显示中文及五笔拼音=输入.5, 完全傻瓜化的网刻模式,懂的基本WINDOWS操作,就能快速实现网络刻隆.6, 支持引导自已制作DOS IMG镜像,以及支持直接启动硬盘上的光盘ISO镜像.7, 全中文全自动化一键备份还原程序,可直接在WINDOWS上操作备份及还原.8, 支持系统盘为NTFS分区,支持读取,修改,删除,复制或操作NTFS分区内容.9, 内置软件如:WIN系统密码清除,DISKGEN,SPFDISK,Ghost11,Memtset等软件.10,支持DOS下驱动SATA,SCSI,1394,USB,PCMCIA等设备,可直接DOS下访问.11,首家全面支持nVIDIA全系列网卡网刻,更多精采内容请查阅“说明文件”. ============================================================= ==================MaxDOS 8 使用前注意事项及常见问题:重要: 网刻前请先下载网刻服务端,并且设置好服务端后方能进入客户端网刻,服务端下载及网刻教程地址/bbs/read.php?tid=50400网刻前请先关闭局域网中的其它DHCP服务器,以免出现IP分配冲突,造成连接不上服务端.重要: GHOST11依然存在着不会自动分卷问题,这将导致GHOSTSRV上出现不是有效镜像问题如果你使用手动备份镜像时请加上-split=2000 参数,格式如Ghost -split=2000 . 重要: 如果您的机器运行GHOST时出现进入不了,或者后要等待很久才能出现操作界面问题,请尝试在运行前加上-no1394 -nousb -noide参数,格式如Ghost -no1394 -nousb -noide重要: GHOST11制作出的镜像,GHOST83和GHOST82不能识别,也就是说如果你客户机上依然使用的是GHOST82,您制作网刻镜像时就必须使用GHOST82制作全盘镜像.当您使用MaxDOS的一键备份还原系统或还原我的镜像功能时,如果执行了"备份或还原系统或还原我的镜像",在重启计算机时未进入DOS中完成操作,并且手动选择启动到了WINDOWS,那么请使用开始菜单->程序->迈思工作室->恢复系统默认启动项,来修复默认启动项为WINDOWS,否则可能每次都默认启动到MAXDOS.并且可以清空刚才未完成的操作,避免程序出错.1.使用前请务必认真的查阅说明文件,否则造成使用问题,作者不负任何责任.2.MaxDOS在安装时可以自由的设定密码,安装后无法修改,修改需重新安装,默认的密码为空.3.MaxDOS支持WIN 2K/XP/2003/VISTA/2008/Win7,不支持WIN9X/ME.4.安装MaxDOS时请在解压RAR压缩包后安装,并关闭其它无关程序,避免引起未知的错误.5.当安装时将启动等待时间设为:0 时,则启动时不会出现MaxDOS的入口选项,相对的系统启度也会快些,需要进入MaxDOS,请在启动时狂按F8键,等出现WINDOWS菜单时,再按ESC键.6.安装MaxDOS后请勿使用NTFS磁盘压缩功能,否则将损坏MaxDOS,使用时请关闭该功能.7.如果安装后出现不能启动或者启动一半时定住,请尝试进入BIOS载入默认高级设置后尝试.8.GHOST手动操作备份/还原系统,使用教程/bbs/read.php?tid=264239.GHOST备份后占用空间,找不到备份文件/bbs/read.php?tid=2369910.GHOST不是有效的GHO镜像解决方法/bbs/read.php?tid=1453511.GHOST网络克隆常见问题及经验分享/bbs/read.php?tid=158512.制作GHOST镜像到网络服务器/bbs/read.php?tid=1070513.GHOST全盘镜像制作(全盘备份)教程/bbs/read.php?tid=2643514.更多常见问题及使用帮助请参见/bbs/read.php?tid=850515.卸载本软件,请在"控制面板->添加删程序->找到MaxDOS点删除!============================================================= ==================MaxDOS 8 安装启动后首菜单有7个主选项.首菜单主选项 A. MaxDOS 工具箱MaxDOS内置的工具,建议都在此项运行.以下为内置的所有命令及工具的简要介绍.12.bat 将第一硬盘的资料通过ghost复制到第二硬盘.21.bat 将第二硬盘的资料通过ghost复制到第一硬盘.Chang.bat 在命令行模式下加载长文件名称的显示支持. Chang /q 退出.CDM.bat 在任何菜单下调用光驱驱动菜单,快速实现加载光驱驱动.Exlan.bat 如果要手动网刻的话.请运行这个解压出dos的pack网卡驱动.Gh.bat MaxDOS下的自动一键备份与还原菜单.Spfdisk.exe 启动管理器+分区管理器,功能强大Help.bat MaxDOS程序帮助文件. 我在这^_^ .Idecd.bat 任何菜单任何位置下快速加载ide光驱驱动.Satacd.bat 任何菜单任何位置下快速加载SATA光驱驱动. Loadiso.bat Dos下载入iso光盘镜像.只能读取.不能引导.但可装2k/xp/2k3系统.先切换到存放iso的目录.输入Loadiso Xx.iso (xx为镜像文件名).Uniso.bat 卸载上条命令加载的iso命令.M.bat MaxDOS工具箱的主菜单.Mouse.bat 鼠标驱动程序,如果需要鼠标操作请先运行. Mouse /q 退出支持.Ndisgo.bat 用于旧版本的命令行模式全盘网刻,格式: Ndisgo Xx Ndisgx.bat 用于旧版本的命令行模式单分区网刻,格式: Ndisgx Xx Ngo.bat Ndis2网卡驱动选项下的主网刻菜单.PWD.exe Dos下清除2k/xp/2k3/Vista/2008系统用户密码.支持NTFS分区.Pgo.bat Packet网卡驱动选项下的主网刻菜单.Sngo.bat 手动选择加载NDIS网卡驱动进行网刻.3c90xgo.bat 3com90x系列pack驱动旧版命令行模式全盘网刻批处理. 3c90xgx.bat 3com90x系列pack驱动旧版命令行模式单分区网刻批处理.8029go.bat Realtek瑞昱8029系列pack驱动旧版命令行模式全盘网刻批处理.8029gx.bat Realtek瑞昱8029系列pack驱动旧版命令行模式单分区网刻批处理.8139go.bat Realtek瑞昱8139系列pack驱动旧版命令行模式全盘网刻批处理.8139gx.bat Realtek瑞昱8139系列pack驱动旧版命令行模式单分区网刻批处理.Dcn530go.bat Dcn-530tx系列pack驱动旧版命令行模式全盘网刻批处理. Dcn530gx.bat Dcn-530tx系列pack驱动旧版命令行模式单分区网刻批处理.Dfe530go.bat D-link Dfe-530tx系列pack驱动旧版命令行模式全盘网刻批处理.Dfe530gx.bat D-link Dfe-530tx系列pack驱动旧版命令行模式单分区网刻批处理.Dle530go.bat *****dle530系列pack驱动旧版命令行模式全盘网刻批处理.Dle530gx.bat *****dle530系列pack驱动旧版命令行模式单分区网刻批处理.Ip100go.bat Ic Plus Ip100系列pack驱动旧版命令行模式全盘网刻批处理.Ip100gx.bat Ic Plus Ip100系列pack驱动旧版命令行模式单分区网刻批处理.Pro100go.bat Intel Pro100系列pack驱动旧版命令行模式全盘网刻批处理.Pro100gx.bat Intel Pro100系列pack驱动旧版命令行模式单分区网刻批处理.Sis900go.bat Sis900系列pack驱动旧版命令行模式全盘网刻批处理. Sis900gx.bat Sis900系列pack驱动旧版命令行模式单分区网刻批处理. T8139go.bat 腾达8139d网卡pack驱动系列旧版命令行模式全盘网刻批处理.T8139gx.bat 腾达8139d网卡pack驱动系列旧版命令行模式分区网刻批处理.Via1go.bat Via 其它网卡系列pack驱动系列旧版命令行模式全盘网刻批处理.Via1gx.bat Via 其它网卡系列pack驱动系列旧版命令行模式分区网刻批处理.Viagbgo.bat Via Rhine Iii系列pack驱动系列旧版命令行模式全盘网刻批处理.Viagbgx.bat Via Rhine Iii系列pack驱动系列旧版命令行模式分区网刻批处理.Viago.bat Via Rhine 1/2系列pack驱动系列旧版命令行模式全盘网刻批处理.Viagx.bat Via Rhine 1/2系列pack驱动系列旧版命令行模式分区网刻批处理.Tw.bat 天汇中文支持程序,tw /s加载dos的中文输入法,tw /q退出中文支持.Usbcd.bat 任何菜单任何位置下快速加载usb光驱驱动. 完全复制文件和目录,包括长文件名及属性.运行前建议运行smartdrv 文件/文件夹属性设置命令. 选择命令,返回按键的errorlevel值. 一个清除cmos密码和设置的程序. 同时删除目录,子目录及文件的工具.操作时请注意. 用命令行模式加载.sys 驱动. 卸载上条命令加载的.sys驱动. 判断驱动器状态,检查光驱中是否有光盘. 软盘是否写保护. 相当于记事本. 用来解压.img镜像.Find.exe 文本找加工具. 格式化fat32分区命令. 弹出或关闭光驱门. 内存清空程序,必须先运行驻留,再运行其它程序,使用ri /cls清空 非常小巧的修改磁盘卷标的工具. 磁盘mbr信息备份与还原工具. 关闭计算机. Zip解压工具. 重新启动计算机. 磁盘映射工具. 传输msdos 7.01 的引导文件到c盘.使用c盘可以引导到dos. 目录树显示工具.Debug.exe 强大的dos下编程命令.Diskge2.exe 强大的dos下中文分区软件,2.0版Diskgen.bat 强大的dos下中文分区软件,3.0版,支持NTFS分区及格式化.Fdisk.exe 早期的dos分区命令.Ghost.exe 系统备份还原工具.如果运行了ntfsdos.请用exit退出后再运行.Go.exe 直接跳转至目录,如Go C:\windows.Mem.exe Dos查看内存占用情况.Mousclip.exe 鼠标剪切板程序.NtfsDOS.bat Ntfs分区读写支持.使用exit退出.Pctool.exe Dos下的类似于win资源管理器Smartdrv.exe Dos下磁盘缓存程序.加载一下可大提高dos安装系统. Xcopy.exe 强大的复制程序,可复制带文件夹的目录,加载tw后,使用xcopy /?Xdel.exe 类似于winnt下的rd,可删除目录和子目录里文件. Ezcopy.exe 一个国产的免制作镜像直接网刻工具,第一台运行此程序为服务端.Memtest.exe Dos下内存测试程序,请在选项"F 纯DOS模式" 下运行. Crdisk.exe Dos下硬件还原卡通用破解程序. (限加强版) 分区表修复工具,用于修复受损的分区程序.============================================================= ==================首菜单主选项 B. 全自动网络克隆为了实现全自动化网刻,程序将在5秒内默认执行此选项,并且自动加载网卡驱动,自动进入GHOST界面等待服务端发送网刻及其它指令(前提是必须准备并设置好网刻服务端)请先下载网刻服务端,并且设置准备好服务端后方能进行客户端网刻,网刻服务端下载地址/bbs/read.php?tid=50400关于5.5S版本的以前使用的命令行网刻模式,依然是存在的.详细请参见此/bbs/read.php?tid=26430友情提醒:您也可以使用新版的网刻模式和旧版网刻模式结合,实现两批机器一起网刻.此项支持的网卡100M及1000M的共约300种,上面并无一一列出,如果您未知您的网卡型号,或者不确定是否支持您的网卡,请选择此项.MaxDOS会帮您自动辨认出网卡以及自动加载驱动.============================================================= ==================首菜单主选项 C. 手动网络克隆子菜单选项A. Packet网卡驱动请先下载网刻服务端,并且设置准备好服务端后方能进行客户端网刻,网刻服务端下载地址/bbs/read.php?tid=50400解: MaxDOS 内置PACKET的DOS网卡驱动选项.由于有些网卡使用自动识别网卡功能后无法识别出网卡或识别不正确,所以此项特意使用为手动选择模式.--------------------------------------------------------------------------------子菜单选项B. NDIS网卡驱动手动选择NDIS2网卡驱动进行网刻,主要用于驱动某些网卡不能识别问题.--------------------------------------------------------------------------------子菜单选项C/D/E/F/G/H. nVIDIA 1/2/3/4/5/6网卡驱动网刻理论上本选项支持nVIDIA全部集成的软网卡,但由于本人没有这些条件测试,所以无法确认.本选项共包含了6个版本的nVIDIA网卡驱动,都是由Max一个一个收集并制作. 我们建议,所有使用nVIDIA主板芯片的用户,如果您使用NDIS无法认出您的网卡或者认出无法正常网刻的话,请使用此六个选项一个一个测试是否可用.排列顺序按兼容性排列的,V1-V6,相对来说V1支持大部份的NF4及NF5系列网卡.V2则支持NF1-NF4系列网卡,其它V3-V5支持一些较特殊的PHY软网卡.您可以一个一个切换测试看哪个与您的主板兼容,则使用哪个.操作方式全部一样的.============================================================= ==================首菜单主选项 D. 备份/还原系统用于全自动备份与还原系统,安装MaxDOS时会提示您指定一个存放GHOST镜像的文件夹,指定后会在您指定的位置创建一个MaxBAK的系统隐藏文件夹,如果您删除了该分区的MaxBAK文件夹将造成全自动备份与还原功能失效.另:该功能默认自动备份为硬盘的第一分区,如果您想修改备份/还原源或目标,请使用开始菜单-程序-迈思工作室-"MaxDOS控制台"进行设置.============================================================= ==================首菜单主选项 E. 访问网络资源进入此项后,系统会自动帮您加载好网卡驱动,并且设置好连接的协议,而且是全中文菜单,您可以在进入此项后,直接获得局域网里WINDOWS主机上的共享资源,而且支持读写操作当然这前提您要开启权限.才能实现写操作,您可以根据菜单里的提示操作,也可以使用如NT主机上的NET命令来实现连接到共享目录,命令行如: net use z: \\max\f此命令的意思是将Z: 盘,映射到"Max"主机上的"f"为名称的共享目录.您可以参考NT的NET命令在NT主机上使用NET /? 或NET USE /? 获得帮助,当然可能有个别命令不支持.友情提醒:您只能通过机器名称来访问您的共享主机,而不能使用IP地址来连接您的主机.而且您还能使用此项进行网刻操作,映射好如Z:盘,然后在GHOST中选择Z:盘共享目录中的".GHO" 镜像还原或备份进去.注意:被访问的机器必须安装IPX协议,已经开启GUEST用户.============================================================= ==================首菜单主选项 F. 驱动USB/1394/SATA/CD/PCMCIA/SCSI设备用来驱动USB/1394/SATA/CD/PCMCIA/SCSI设备,驱动后就可以在DOS下访问设备的内容!============================================================= ==================首菜单主选项G. 纯DOS模式用于刷BIOS或运行其它特殊软件,不加载任何驱动,无HIMEM,无虚拟盘,不包含常用软件包.============================================================= ==================关于迈思(Max)工作室:迈思(Max)工作室是一个致力于网吧技术及电脑技术研究,探讨,创新的技术交流社区,成立于2003年至今已有30多万位会员,日访问量数万,提供最新,最全的网吧专用软件,如:游戏菜单,游戏更新软件,还原软件,网络克隆软件,网吧服务器软件等网吧常用软件,以及IT业网吧业的资讯,且是MaxDOS的官方站点.拥有较大的技术团队,我们以最高的热情欢迎。

MAX6409BS40+中文资料

MAX6409BS40+中文资料

General DescriptionThe MAX6406–MAX6411 is a family of ultra-low power circuits used for monitoring battery, power-supply, and regulated system voltages. Each detector contains a precision bandgap reference comparator and is trimmed to specified trip threshold voltages. These devices provide excellent circuit reliability and low cost by eliminating external components and adjustments when monitoring system voltages from 2.5V to 5.0V. A manual reset input is also included.The MAX6406–MAX6411 assert a signal whenever the V CC supply voltage falls below a preset threshold.These devices are differentiated by their output logic configurations and preset threshold voltages. The MAX6406/MAX6409 (push-pull) and the MAX6408/MAX6411 (open-drain) have an active-low output (OUT is logic low when V CC is below V TH ). The MAX6407/MAX6410 have an active-high push-pull output (OUT is logic high when V CC is below V TH ). All parts are guaranteed to be in the correct output logic state for V CC down to 1V. The detector is designed to ignore fast transients on V CC . The MAX6406/MAX6407/MAX6408 have voltage thresholds between 2.20V and 3.08V in approximately 100mV increments. The MAX6409/MAX6410/MAX6411 have voltage thresholds between 3.30V and 4.63V in approximately 100mV increments.Ultra-low supply current of 500nA (MAX6406/MAX6407/MAX6408) makes these parts ideal for use in portable equipment. These devices are available in 4-bump chip-scale packages (UCSP ).ApplicationsPortable/Battery-Powered Equipment Cell Phones PDAs MP3 Players PagersFeatureso Tiny 4-Bump (2 X 2) Chip-Scale Package, (Package Pending Full Qualification—Expected Completion Date 6/30/01. See UCSP Reliability Section for More Details.)o 70% Smaller Than SC70 Packages o Ultra-Low 500nA Supply Current (MAX6406/MAX6407/MAX6408)o Factory-Trimmed Reset Thresholds from 2.20V to 4.63V in Approximately 100mV Increments o ±2.5% Threshold Accuracy (-40°C to +85°C)o Manual Reset Inputo Guaranteed OUT Valid to V CC = 1.0Vo Three Reset Output Logic Options: Active-Low Push-Pull, Active-High Push-Pull, and Active-Low Open-Drain o Immune to Short V CC Transients o No External ComponentsMAX6406–MAX6411Voltage Detectors in 4-Bump (2 X 2)Chip-Scale PackageMaxim Integrated Products 119-2041; Rev 1; 8/01For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at .The MAX6406–MAX6411 are available in factory-set V CCdetector thresholds from 2.20V to 4.63V, in approximately 0.1V increments. Choose the desired threshold suffix from Table 1and insert it in the blank space following “S”. There are 21standard versions with a required order increment of 2500pieces. Sample stock is generally held on the standard ver-sions only (Table1). Required order increment is 10,000 pieces for nonstandard versions (Table 2). Contact factory for avail-ability. All devices available in tape-and-reel only.UCSP reliability is integrally linked to the user’s assemblymethods, circuit board material, and environment. Refer to the UCSP Reliability Notice in the UCSP Reliability section of this data sheet for more information.Pin Configuration appears at end of data sheet.UCSP is a trademark of Maxim Integrated Products, Inc.Ordering InformationSelector GuideM A X 6406–M A X 6411Voltage Detectors in 4-Bump (2 X 2) Chip-Scale PackageABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.All voltages measured to GND unless otherwise noted.VCC..........................................................................-0.3V to +6V OUT/OUT ...................................................-0.3V to (V CC + 0.3V)OUT (open-drain).....................................................-0.3V to +6V MR ..............................................................-0.3V to (V CC + 0.3V)Input/Output Current into Any Pin.......................................20mAContinuous Power Dissipation (T A = +70°C)4-Pin/Bump UCSP (derate 3.8mW/°C above +70°C)....303mW Operating Temperature Range ..........................-40°C to +85°C Junction Temperature......................................................+150°C Storage Temperature Range ............................-65°C to +160°C Bump Reflow Temperature .............................................+235°CELECTRICAL CHARACTERISTICS(V CC = 1.0V to 5.5V, T A = -40°C to +85°C, unless otherwise noted. Typical values are at V CC = 3V and T A = +25°C.) (Note1)MAX6406–MAX6411Voltage Detectors in 4-Bump (2 X 2)Chip-Scale Package_______________________________________________________________________________________3Note 2:Guaranteed by design.ELECTRICAL CHARACTERISTICS (continued)(V CC = 1.0V to 5.5V, T A = -40°C to +85°C, unless otherwise noted. Typical values are at V CC = 3V and T A = +25°C.) (Note1)Typical Operating Characteristics(T A = +25°C, unless otherwise noted.)00.30.20.10.50.40.90.80.70.61.0-40-2020406080SUPPLY CURRENT vs. TEMPERATURETEMPERATURE (°C)S U P P L Y C U R R E N T (µA )050100200150250-40-2020406080PROPAGATION DELAY (V CC FALLING)vs. TEMPERATURETEMPERATURE (°C)P R O P A G A T I O N D E L A Y (µs )M A X 6406–M A X 6411Voltage Detectors in 4-Bump (2 X 2) Chip-Scale Package 4_______________________________________________________________________________________Typical Operating Characteristics (continued)(T A = +25°C, unless otherwise noted.)040206012010080140-40-2020406080PROPAGATION DELAY (V CC RISING)vs. TEMPERATURETEMPERATURE (°C)P R O P A G A T I O N D E L A Y (µs )01100010010MAXIMUM TRANSIENT DURATION vs. THRESHOLD OVERDRIVE500200100400300THRESHOLD OVERDRIVE V TH - V CC (mV)M A X I M U M T R A N S I E N T D U R A T I O N (µs )MAX6406–MAX6411Voltage Detectors in 4-Bump (2 X 2)Chip-Scale Package_______________________________________________________________________________________5M A X 6406–M A X 6411Detailed DescriptionManual Reset InputMany µP-based products require manual reset capabil-ity, allowing the operator, a test technician, or external logic circuit to initiate a reset. A logic low on MR asserts OUT/OUT . OUT/OUT remains asserted while MR is low.This input has an internal 50k Ωpullup resistor, so it can be left open if it is not used. MR can be driven with TTL or CMOS logic levels, or with open-drain/collector out-puts. Connect a normally open momentary switch from MR to GND to create a manual reset function. If MR is driven from long cables or if the device is used in a noisy environment, connect a 0.1µF capacitor from MR to ground to provide additional noise immunity.Applications InformationInterfacing to Different LogicVoltage ComponentsThe MAX6408/MAX6411 have an active-low, open-drain output. This output structure will sink current when OUT is asserted. Connect a pullup resistor from OUT to any supply voltage up to 5.5V (Figure 1). Select a resistor value large enough to allow a valid logic low (see Electrical Characteristics ), and small enough to register a logic high while supplying all input currents and leakage paths connected to the OUT line.Voltage Detectors in 4-Bump (2 X 2) Chip-Scale Package 6_______________________________________________________________________________________Negative-Going V CC TransientsThese devices are relatively immune to short-duration,negative-going V CC transients (glitches).The Typical Operating Characteristics show the Maximum Transient Duration vs. Threshold Overdrive graph, for which output pulses are not generated. The graph shows the maximum pulse width that a negative-going V CC transient may typically have before the devices issue output signals. As the amplitude of the transient increases, the maximum allowable pulse width decreases.UCSP ReliabilityThe chip-scale package (UCSP) represents a unique packaging form factor that may not perform equally to a packaged product through traditional mechanical reliabil-ity tests. CSP reliability is integrally linked to the user ’s assembly methods, circuit board material, and usage environment. The user should closely review these areas when considering use of a CSP package. Performance through Operating Life Test and Moisture Resistance remains uncompromised as it is primarily determined by the wafer-fabrication process.Mechanical stress performance is a greater considera-tion for a CSP package. CSPs are attached through direct solder contact to the user ’s PC board, foregoing the inherent stress relief of a packaged product lead frame. Solder joint contact integrity must be rmation on Maxim ’s qualification plan, test data, and usage recommendations are detailed in the UCSP appli-cation note, which can be found on Maxim ’s website at .Chip InformationTRANSISTOR COUNT: 512PROCESS: BiCMOSMAX6406–MAX6411Voltage Detectors in 4-Bump (2 X 2)Chip-Scale Package_______________________________________________________________________________________7Figure 1. Interfacing to Different Logic Voltage ComponentsPin ConfigurationM A X 6406–M A X 6411Voltage Detectors in 4-Bump (2 X 2) Chip-Scale Package Package InformationMaxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.8_____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600©2001 Maxim Integrated ProductsPrinted USAis a registered trademark of Maxim Integrated Products.。

TCA6408中文资料

TCA6408中文资料

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
• I2C to Parallel Port Expander • Low Standby Current Consumption of 1 µA • Schmitt-Trigger Action Allows Slow Input
Transition and Better Switching Noise Immunity at the SCL and SDA Inputs
state machine. The RESET pin causes the same reset/initialization to occur without depowering the part.
The TCA6408 open-drain interrupt (INT) output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed.
The system master can reset the TCA6408 in the event of a timeout or other improper operation by asserting a low in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C/SMBus

Pro-face SP-5B90 eXtreme Box Module数据手册说明书

Pro-face SP-5B90 eXtreme Box Module数据手册说明书

AUX Output Interface
Alarm output/Buzzer output, Rated voltage 24Vdc, Rated current, 50 mA, Connector 2-piece terminal block (AUX) x1
*1 Amount of memory you can use depends on your screen editing software. For information refer to the manual of your screen editing software. *2 For 1000BASE-T communication, use twisted pair Ethernet cables with a rating of category 5e or higher.
©2020 Pro-face. All rights reserved. Specifications may change without notice.
External Dimensions Easy Maintenance and Modularity
Datasheet
Ordering Information
Cooling Method
Natural air circulation
Weight
0.9kg[1.98lb] or less
External Dimensions
W188 x H131 xD45mm [W7.4 x H5.16 x D1.77 in.]
Warranty
Two (2) years
Note: Box Module environmental specifications follow those of the connected Display Module.

GS8640Z36GT-250V中文资料

GS8640Z36GT-250V中文资料

GS8640Z18/36T-xxxV72Mb Pipelined and Flow ThroughSynchronous NBT SRAM 250 MHz –167 MHz 1.8 V or 2.5 V V DD 1.8 V or 2.5 V I/O100-Pin TQFP Commercial Temp Industrial Temp Features• NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization; Fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs• 1.8 V or 2.5 V core power supply • 1.8 V or 2.5 V I/O supply• User-configurable Pipeline and Flow Through mode • LBO pin for Linear or Interleave Burst mode• Pin compatible with 4Mb, 9Mb, 18Mb and 36Mb devices • Byte write operation (9-bit Bytes)• 3 chip enable signals for easy depth expansion • ZZ Pin for automatic power-down• JEDEC-standard 100-lead TQFP package• RoHS-compliant 100-lead TQFP package availableFunctional DescriptionThe GS8640Z18/36T-xxxV is a 72Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.The GS8640Z18/36T-xxxV may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, meaning that in addition to the rising edge triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock.The GS8640Z18/36T-xxxV is implemented with GSI's high performance CMOS technology and is available in a JEDEC-standard 100-pin TQFP package.Parameter Synopsis-250-200-167Unit Pipeline 3-1-1-1t KQ tCycle 3.04.0 3.05.0 3.56.0ns ns (x18)Curr (x32/x36)410350305mA Flow Through 2-1-1-1t KQ tCycle 6.56.57.57.58.08.0ns ns (x18)Curr (x32/x36)280250240mA807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B FT V DD NC V SS DQ B DQ B V DDQ V SS DQ B DQ B DQP BV SS V DDQ V DDQ V SS DQ A DQ A V SS V DDQ DQ A DQ A V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0N C N C V S SV D DA A A A A A A AA A E 1E 2 N C N C B BB AE 3C K W C K E VD DV S SG A D V A A A AA 2M x 18Top View DQP A A NC NC NC NC NC NC NC NCNC NC NC NC NC NC NCNC NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950GS8640Z18/36T-xxxVGS8640Z18T-xxxV Pinout (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C DQ C V SS V DDQ DQ C DQ C FT V DD NC V SS DQ D DQ D V DDQ V SS DQ D DQ D DQ D V SS V DDQ V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0N C N C V S SV D DA A A A A A A AA A E 1E 2 B DB CB BB AE 3C K W C K E VD DV S SG A D V A A A AA 1M x 36Top View DQB DQP B DQ B DQ B DQ B DQ A DQ A DQ A DQ A DQP ADQ C DQ C DQ C DQ D DQ D DQ D DQP DDQ C DQP C 100999897969594939291908988878685848382813132333435363738394041424344454647484950GS8640Z18/36T-xxxVGS8640Z36T-xxxV Pinout (Package T)TQFP Pin DescriptionsSymbolTypeDescriptionA 0, A 1In Burst Address Inputs; Preload the burst counterA In Address Inputs CK In Clock Input SignalB A In Byte Write signal for data inputs DQ A1-DQ A9; active low B B In Byte Write signal for data inputs DQ B1-DQ B9; active low BC In Byte Write signal for data inputs DQ C1-DQ C9; active low BD In Byte Write signal for data inputs DQ D1-DQ D9; active lowW In Write Enable; active low E 1In Chip Enable; active lowE 2In Chip Enable; Active High. For self decoded depth expansion E 3In Chip Enable; Active Low. For self decoded depth expansionG In Output Enable; active lowADV In Advance/Load; Burst address counter control pinCKE In Clock Input Buffer Enable; active low DQ A I/O Byte A Data Input and Output pins DQ B I/O Byte B Data Input and Output pins DQ C I/O Byte C Data Input and Output pins DQ D I/O Byte D Data Input and Output pins ZZ In Power down control; active high FT In Pipeline/Flow Through Mode Control; active lowLBO In Linear Burst Order; active lowV DD In Core power supplyV SS In GroundV DDQ In Output driver power supplyNC—No ConnectGS8640Z18/36T-xxxVKS A 1S A 0B u r s t Co u nt e rL B OA D VM e m o r y A r r a yE 3E 2E 1GWB DB CB BB AC KC K ED QF TD Q a –D Q nKS A 1’S A 0’D QM a t c hW r i t e A d d r e s sR e g i s t e r 2W r i t e A d d r e s sR e g i s t e r 1W r i t e D a t aR e g i s t e r 2W r i t e D a t aR e g i s t e r 1KKKKKKS e n s e A m p sW r i t e D r i v e r sR e a d , W r i t e a n dD a t a C o h e r e n c yC o n t r o l L o g i cF TA 0–A nGS8640Z18/36T-xxxVGS8640Z18/36T-xxxV NBT SRAM Functional Block DiagramGS8640Z18/36T-xxxVFunctional DetailsClockingDeassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.Pipeline Mode Read and Write OperationsAll inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E 1, E 2 and E 3). Deassertion of any one of the Enable inputs will deactivate the device. Function W B A B B B C B D Read H X X X X Write Byte “a”L L H H H Write Byte “b”L H L H H Write Byte “c”L H H L H Write Byte “d”L H H H L Write all Bytes L L L L L Write Abort/NOPLHHHHRead operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted Low, all three chip enables (E 1, E 2, and E 3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (B A , B B , B C, & B D ) determine which bytes will be written. All or none may be activated. A write cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock.Flow Through Mode Read and Write OperationsOperation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode.Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock.Synchronous Truth TableOperationType Address CK CKE ADV W Bx E 1E 2E 3G ZZDQNotesRead Cycle, Begin Burst R External L-H L L H X L H L L L Q Read Cycle, Continue Burst B Next L-H L H X X X X X L L Q 1,10NOP/Read, Begin Burst R External L-H L L H X L H L H L High-Z 2Dummy Read, Continue Burst B Next L-H L H X X X X X H L High-Z 1,2,10Write Cycle, Begin Burst W External L-H L L L L L H L X L D 3Write Cycle, Continue Burst B Next L-H L H X L X X X X L D1,3,10Write Abort, Continue Burst B Next L-H L H X H X X X X L High-Z 1,2,3,10Deselect Cycle, Power Down D None L-H L L X X H X X X L High-Z Deselect Cycle, Power Down D None L-H L L X X X X H X L High-Z Deselect Cycle, Power Down D None L-H L L X X X L X X L High-Z Deselect Cycle D None L-H L L L H L H L X L High-Z 1Deselect Cycle, Continue DNone L-H L H X X X X X X L High-Z 1Sleep ModeNone X X X X X X X X X H High-Z Clock Edge Ignore, StallCurrentL-HHXXXXXXXL-4Notes:1.Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-lect cycle is executed first.2.Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the Wpin is sampled low but no Byte Write pins are active so no write operation is performed.3.G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off duringwrite cycles.4.If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the buswill remain in High Z.5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Writesignals are Low6.All inputs, except G and ZZ must meet setup and hold times of rising clock edge.7.Wait states can be inserted by setting CKE high.8.This device contains circuitry that ensures all outputs are in High Z during power-up.9. A 2-bit burst counter is incorporated.10.The address counter is incriminated for all Burst continue cycles.GS8640Z18/36T-xxxVGS8640Z18/36T-xxxVDeselectNew ReadNew WriteBurst ReadBurst WriteWRBRBWDDBBWRD BWRDDCurrent State (n)Next State (n+1)TransitionƒInput Command CodeKeyNotes:1. The Hold command (CKE Low) is notshown because it prevents any state change.2. W, R, B and D represent input commandcodes ,as indicated in the Synchronous Truth Table.Clock (CK)CommandCurrent StateNext Stateƒnn+1n+2n+3ƒƒƒCurrent State and Next State Definition for Pipeline and Flow Through Read/Write Control State DiagramWRPipeline and Flow Through Read Write Control State DiagramGS8640Z18/36T-xxxVIntermediateIntermediateIntermediateIntermediateIntermediateIntermediateHigh Z (Data In)Data Out (Q Valid)High Z B W B R B DRW RWDDCurrent State (n)TransitionƒInput Command CodeKeyTransitionIntermediate State (N+1)Notes:1. The Hold command (CKE Low) is notshown because it prevents any state change.2. W, R, B, and D represent input command codes as indicated in the Truth Tables.Clock (CK)CommandCurrent StateIntermediate ƒn n+1n+2n+3ƒƒƒCurrent State and Next State Definition for Pipeline Mode Data I/O State DiagramNext StateStatePipeline Mode Data I/O State DiagramGS8640Z18/36T-xxxVHigh Z (Data In)Data Out (Q Valid)High Z B W B R B DRW RWDDCurrent State (n)Next State (n+1)TransitionƒInput Command CodeKeyNotes1. The Hold command (CKE Low) is notshown because it prevents any state change.2. W, R, B and D represent input command codes as indicated in the Truth Tables.Clock (CK)CommandCurrent StateNext Stateƒnn+1n+2n+3ƒƒƒCurrent State and Next State Definition for: Pipeline and Flow Through Read Write Control State DiagramFlow Through Mode Data I/O State DiagramGS8640Z18/36T-xxxVBurst CyclesAlthough NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode.Burst OrderThe burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have beenaccessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables below for details.Mode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down ControlZZL or NC Active HStandby, I DD = I SBNote:There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above table.Note:The burst counter wraps to initial state on the 5th clock.Note:The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110Interleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100Burst Counter SequencesBPR 1999.05.18GS8640Z18/36T-xxxVSleep ModeDuring normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time.Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I SB 2. The duration of Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I SB 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a deselect or read commands may be applied while the SRAM is recovering from Sleep mode.Sleep Mode Timing DiagramtZZRtZZHtZZStKLtKHtKCCKZZDesigning for CompatibilityThe GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal found on Pin 14. Not all vendors offer this option, however most mark Pin 14 as V DD or V DDQ on pipelined parts and V SS on flow through parts. GSI NBT SRAMs are fully compatible with these sockets.Absolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 4.6V V DDQ Voltage on V DDQ Pins –0.5 to V DDV V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 4.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 4.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125oCGS8640Z18/36T-xxxVNote:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges (1.8 V/2.5 V Version)ParameterSymbolMin.Typ.Max.UnitNotes1.8 V Supply Voltage V DD1 1.7 1.82.0V 2.5 V Supply Voltage V DD2 2.3 2.5 2.7V 1.8 V V DDQ I/O Supply Voltage V DDQ1 1.7 1.8V DD V 2.5 V V DDQ I/O Supply VoltageV DDQ22.32.5V DDVNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS8640Z18/36T-xxxVV DDQ2 & V DDQ1 Range Logic LevelsParameterSymbolMin.Typ.Max.UnitNotesV DD Input High Voltage V IH 0.6*V DD —V DD + 0.3V 1V DD Input Low VoltageV IL–0.3—0.3*V DDV1Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.Recommended Operating TemperaturesParameterSymbolMin.Typ.Max.UnitNotesAmbient Temperature (Commercial Range Versions)T A 02570°C 2Ambient Temperature (Industrial Range Versions)T A–402585°C2Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.20% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DD ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pFNote:These parameters are sample tested.(T A = 25= 2.5 V)AC Test ConditionsParameterConditionsDQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceFigure 1Input high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 11.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. GS8640Z18/36T-xxxVDC Electrical CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA FT, ZZ Input Current I IN V DD ≥ V IN ≥ 0 V –100 uA 100 uA Output Leakage CurrentI OLOutput Disable, V OUT = 0 to V DD–1 uA1 uADC Output Characteristics (1.8 V/2.5 V Version)ParameterSymbolTest ConditionsMinMax1.8 V Output High Voltage V OH1I OH = –4 mA, V DDQ = 1.6 V V DDQ – 0.4 V —2.5 V Output High Voltage V OH2I OH = –8 mA, V DDQ = 2.375 V1.7 V —1.8 V Output Low Voltage V OL1I OL = 4 mA —0.4 V2.5 V Output Low VoltageV OL2I OL = 8 mA—0.4 VOperating CurrentsParameterTest ConditionsModeSymbol-250-200-167Unit0to 70°C –40 to 85°C 0to 70°C –40to 85°C 0 to 70°C –40to 85°C Operating CurrentDevice Selected; All other inputs ≥V IH o r ≤ V IL Output open(x32/x36)Pipeline I DD I DDQ 360503805031040330402703529035mA Flow Through I DD I DDQ 255252752523020250202202024020mA (x18)PipelineI DD I DDQ 315253352527020290202402026020mA Flow Through I DD I DDQ 230152501520515225151951521515mA Standby Current ZZ ≥ V DD – 0.2 V —PipelineI SB 100120100120100120mA Flow Through I SB 100120100120100120mA Deselect CurrentDevice Deselected; All other inputs ≥ V IH or ≤ V IL—Pipeline I DD 140155130146125140mA Flow ThroughI DD125140120135120135mAGS8640Z18/36T-xxxVNotes:1.I DD and I DDQ apply to any combination of V DD and V DDQ operation.2.All parameters listed are worst case scenario.AC Electrical CharacteristicsParameter Symbol -250-200-167Unit Min Max Min Max Min Max PipelineClock Cycle Time tKC 4.0— 5.0— 6.0—ns Clock to Output ValidtKQ — 3.0— 3.0— 3.5ns Clock to Output Invalid tKQX 1.5— 1.5— 1.5—ns Clock to Output in Low-ZtLZ 1 1.5— 1.5— 1.5—ns Setup time tS 1.5— 1.5— 1.5—ns Hold time tH 0.2—0.4—0.5—ns Flow ThroughClock Cycle Time tKC 6.5—7.5—8.0—ns Clock to Output ValidtKQ — 6.5—7.5—8.0ns Clock to Output Invalid tKQX 3.0— 3.0— 3.0—ns Clock to Output in Low-ZtLZ 1 3.0— 3.0— 3.0—ns Setup time tS 1.5— 1.5— 1.5—ns Hold time tH 0.5—0.5—0.5—ns Clock HIGH Time tKH 1.3— 1.3— 1.3—ns Clock LOW Time tKL 1.7— 1.7— 1.7—ns Clock to Output inHigh-Z tHZ 1 1.5 2.5 1.5 3.0 1.5 3.0ns G to Output Valid tOE — 2.5— 3.0— 3.5ns G to output in Low-Z tOLZ 10—0—0—ns G to output in High-Z tOHZ 1— 2.5— 3.0— 3.0ns ZZ setup time tZZS 25—5—5—ns ZZ hold time tZZH 21—1—1—ns ZZ recoverytZZR20—20—20—nsGS8640Z18/36T-xxxVNotes:1.These parameters are sampled and are not 100% tested.2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.GS8640Z18/36T-xxxVPipeline Mode Timing (NBT)Begin Read A Cont Cont Deselect Write B Read C Read C+1Read C+2Read C+3ContDeselecttHZtKQX tKQtLZtHtStOHZtOEtHtStHtStHtStHtStHtStStHtStHtStHtSBurst ReadtKCtKL tKH Single Write Single ReadQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCDeselected with E1E1 masks ADSPE2 and E3 only sampled with ADSP and ADSCADSC initiated readCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdGS8640Z18/36T-xxxVFlow Through Mode Timing (NBT)Begin Read A ContCont Write B Read C Read C+1Read C+2Read C+3Read C Cont DeselecttHZtKQXtKQ tLZtH tStOHZtOEtHtS tHtS tHtStHtS tHtS tHtStHtS tHtS tH tS tHtS tKCtKL tKHABCQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)Q(C)E2 and E3 only sampled with ADSCADSC initiated readDeselected with E1Fixed HighCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdGS8640Z18/36T-xxxVTQFP Package Drawing (Package T) D1D E1EPin 1be cLL1A2A1YθNotes:1.All dimensions are in millimeters (mm).2.Package width and length do not include mold protrusion.SymbolDescriptionMin.Nom.MaxA1Standoff 0.050.100.15A2Body Thickness 1.35 1.40 1.45b Lead Width 0.200.300.40c Lead Thickness 0.09—0.20D Terminal Dimension 21.922.022.1D1Package Body 19.920.020.1E Terminal Dimension 15.916.016.1E1Package Body 13.914.014.1e Lead Pitch —0.65—L Foot Length 0.450.600.75L1Lead Length —1.00—Y Coplanarity 0.10θLead Angle0°—7°Ordering Information —GSI NBT Synchronous SRAMOrgPart Number1TypeVoltage OptionPackageSpeed 2(MHz/ns)T A 3Status 44M x 18GS8640Z18T-250V NBT 1.8 V or 2.5 V TQFP 250/6.5C PQ 4M x 18GS8640Z18T-200V NBT 1.8 V or 2.5 V TQFP 200/7.5C PQ 4M x 18GS8640Z18T-167V NBT 1.8 V or 2.5 V TQFP 167/8C PQ 2M x 36GS8640Z36T-250V NBT 1.8 V or 2.5 V TQFP 250/6.5C PQ 2M x 36GS8640Z36T-200V NBT 1.8 V or 2.5 V TQFP 200/7.5C PQ 2M x 36GS8640Z36T-167V NBT 1.8 V or 2.5 V TQFP 167/8C PQ 4M x 18GS8640Z18T-250IV NBT 1.8 V or 2.5 V TQFP 250/6.5I PQ 4M x 18GS8640Z18T-200IV NBT 1.8 V or 2.5 V TQFP 200/7.5I PQ 4M x 18GS8640Z18T-167IV NBT 1.8 V or 2.5 V TQFP 167/8I PQ 2M x 36GS8640Z36T-250IV NBT 1.8 V or 2.5 V TQFP 250/6.5I PQ 2M x 36GS8640Z36T-200IV NBT 1.8 V or 2.5 V TQFP 200/7.5I PQ 2M x 36GS8640Z36T-167IV NBT 1.8 V or 2.5 V TQFP167/8I PQ 4M x 18GS8640Z18GT-250V NBT 1.8 V or 2.5 V RoHS-compliant TQFP 250/6.5C PQ 4M x 18GS8640Z18GT-200V NBT 1.8 V or 2.5 V RoHS-compliant TQFP 200/7.5C PQ 4M x 18GS8640Z18GT-167V NBT 1.8 V or 2.5 V RoHS-compliant TQFP 167/8C PQ 2M x 36GS8640Z36GT-250V NBT 1.8 V or 2.5 V RoHS-compliant TQFP 250/6.5C PQ 2M x 36GS8640Z36GT-200V NBT 1.8 V or 2.5 V RoHS-compliant TQFP 200/7.5C PQ 2M x 36GS8640Z36GT-167V NBT 1.8 V or 2.5 V RoHS-compliant TQFP 167/8C PQ 4M x 18GS8640Z18GT-250IV NBT 1.8 V or 2.5 V RoHS-compliant TQFP 250/6.5I PQ 4M x 18GS8640Z18GT-200IV NBT 1.8 V or 2.5 V RoHS-compliant TQFP 200/7.5I PQ 4M x 18GS8640Z18GT-167IV NBT 1.8 V or 2.5 V RoHS-compliant TQFP 167/8I PQ 2M x 36GS8640Z36GT-250IV NBT 1.8 V or 2.5 V RoHS-compliant TQFP 250/6.5I PQ 2M x 36GS8640Z36GT-200IV NBT 1.8 V or 2.5 V RoHS-compliant TQFP 200/7.5I PQ 2M x 36GS8640Z36GT-167IVNBT1.8 V or2.5 VRoHS-compliant TQFP167/8IPQNotes:1.Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8640Z36T-167IVT.2.The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Eachdevice is Pipeline/Flow Through mode-selectable by the user.3.T A = C = Commercial Temperature Range. T A = I = Industrial Temperature Range.4.PQ = Pre-Qualification.5.GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which arecovered in this data sheet. See the GSI Technology web site () for a complete listing of current offeringsGS8640Z18/36T-xxxV。

6408hd-s说明书

6408hd-s说明书

6408hd-s说明书
解码器操作
该解码器需要一个12倍的数据速率的工作时钟输入在DC引脚。

曼彻斯特I编码的数据可以以两种方式提供给解码器。

BOI和BZI将从一个差分输出的比较器接收数据。

UDI的输入只能接收反向的曼彻斯特I编码数据(例如,从一个编码器的BOO经过反相器输入到UDI)。

解码器是自动运行的,持续将收到的数据显示在总线上,当收到有效的同步字符和两个有效的曼彻斯特数据位则启动一个输出周期。

当识别到一个有效的同步(1位置),CDS则动作显示接受到得是命令还是数据。

如果同步字符是一个命令,在位置(2)输出将为持续高并且保持16个DSC期到(3)位置,否则将保持为低。

当解码器通过SDO 发送解码数据的时候,TD的输出将为高电平并在(2)-(3)周期内保持高。

在SDO解码输出的数据是在一个NRZ格式。

在DSC作用下,使得解码器在上升沿的时候将解码数据位移位到外部的寄存器(2)-(3)。

需要注意的是当TD变为高电平的时候,解码器时钟DSC可能调整它的脉冲变高。

Synopsys TestMAX XLBIST 产品说明说明书

Synopsys TestMAX XLBIST 产品说明说明书

DATASHEETOverviewSynopsys TestMAX XLBIST delivers a solution for in-system self-test of digital designs where functional safety is critical, such as in automotive, medical, and aerospaceapplications, and is the industry’s first X-tolerant architecture (Figure 1 ) that eliminates all Xs in a design. The result is smaller impact on test costs and faster time to market.IEEE 1500 I/FFigure 1: TestMAX XLBIST architecture overviewKey Benefits• Addresses ISO 26262 automotive functional safety and other in-system test requirements• Predictably achieves target test coverage within given run time, clock frequency, and power constraints• X-tolerant logic BIST eliminates designer effort to address unknown logic values (Xs)In-system self-test for safety critical designs including automotive, medical, and aerospaceTestMAX XLBISTX-Tolerant Logic Built-in Self-Test (BIST)2Key Features• Supports standard and high X-tolerance architectures• In combination with TestMAX ATPG, supports deterministic compressed patterns• Intelligent re-seeding with on-chip pattern generation and response analysis that can be stored on-chip or applied from external sources• Diagnosis using MISR signature analysis supported for manufacturing test using TestMAX DiagnosisTraditional and X-tolerant logic BISTStandard logic BIST requires designs to be free of unknown (i.e., X) simulation values for correct operation. However, with aggressive design practices and new technologies, predicting post-silicon logic values is challenging when considering factors such as sophisticated fault models, design initialization, timing marginalities, and operating parameter variations.TestMAX XLBIST performs optimally on X-clean designs but provides the ability to handle designs with X values via selective masking of scan chains. This ability ensures that self-test will operate on the manufactured device with little impact to the operational time and fault coverage for most scenarios.Deterministic ATPG compression supported with XLBIST logicThe TestMAX XLBIST architecture also supports deterministic pattern generation with TestMAX ATPG, eliminating the need forseparate codec logic and additional area overhead. TestMAX XLBIST also has the ability to generate hardware to enable power-aware patterns that limits switching activity for both self-test and deterministic pattern generation modes.X-tolerant logic BIST pattern generationWith the ability to re-seed the pseudo-random pattern generator (PRPG), dynamic x-tolerant logic, and lower power sequencer in an automatic, intelligent manner, TestMAX XLBIST achieves significant increases in fault coverage in less time compared to traditional logic BIST solutions. Figure 2 shows an example comparison of coverage versus pattern count for a given number of pattern seeds.95.00%94.00%93.00%92.00%91.00%90.00%89.00%5,000t e s t c o v e r a g ePattern count10 seeds5 seeds 1 seed10,00015,00020,00025,00030,00050,00075,000100,000Figure 2: TestMAX XLBIST achieves high coverage with multiple seedsSince the number of bits required for a seed and associated response is in the order of 100s of bits, TestMAX XLBIST supports multiple seeds stored on-chip for in-system test or supplied externally.Design FormatsTestMAX XLBIST supports the following data formats:• Design: VHDL, Verilog (RTL or netlist), SystemVerilog• Constraints: SDC and SpyGlass SGDC, Tcl• Power: UPF• Assertions: OVL, SV• Verification: SAIF, VCD, FSDBFor more information about Synopsys products, support services or training, visit us on the web at: , contact your local sales representative or call 650.584.5000.©2019 Synopsys, Inc. All rights reserved. Synopsys is a trademark of Synopsys, Inc. in the United States and other countries. A list of Synopsys trademarks isavailable at /copyright.html . All other names mentioned herein are trademarks or registered trademarks of their respective owners.03/08/19.CS324588893_TestMAX XLBIST_DS.。

设备树及基本信息需求说明

设备树及基本信息需求说明

设备树及基本信息需求说明一、业务说明本系统为设备信息管理平台,已有系统框架,ibatis架构,数据库与数据库基本操作文件都已写出,现需要做的模块是设备树和设备基本信息维护页面。

二、数据库表说明表名:MIP_Product三、现有文件列表及其说明四、需要完成的文件列表页面文件名可修改,文件路径都为WebLib.Web\BaseInfo\Product五、 任务需求说明1. 设备树通过层次编码,把设备分为一级系统、二级系统等,三位编码表示一个层次,例如001表示一级系统,001001表示二级系统,等等。

设备树各层次可以展开折叠,其形式可参见下图(部门树在本系统已具有)。

页面说明左侧设备树,右侧是与设备相关的信息,右侧的信息采用Coolite 中的Tab 控件来实现,目前只需要实现“设备信息”即可,Tab 中的每一个按钮对应一个独立的页面,页面初始化时,这些页面不载入,当点击Tab 中的按钮,如设备信息,该页面通过Ajax 方式载入。

2.设备树的显示与维护●此部分功能与部门管理模块相似。

1.设备具有编号,根据设备编号来生成设备树结构2.点击“选择编号”按钮,会下拉一个页面(此下拉功能直接使用coolite的控件即可方便实现),从页面中获得设备所属系统的代码,此页面可以先不做,先模拟返回一个编号即可,此编号对应系统数据表“MIP_System”中的“Serial”字段,当点击返回后,重新根据“Serial”编码生成设备树结构。

3.点击“查看信息”按钮,会跳转到另一个页面——系统信息页面,此页面开发工作后期做,需要传递的参数为通过“选择编号”按钮所获取的“Serial”数值。

当点击某一个设备节点时,节点参数传递到右侧的Tab页面中,对应的页面也同步更新,注意“系统基本页面”不必更新,此页面仅仅当选择了“选择编号”这个按钮,并且编号发生变更时才需要更新●应具有与部门树类似的功能:模糊查询、添加设备、删除设备,上下移动,1)模糊查询功能在设备树上方设置模糊查询功能,输入设备名称的某几个关键字,点击“查询”按钮,设备树中包含关键字的设备将展开并以亮色显示,若有多个设备包含关键字,则这些所有设备都以亮色显示,并通过“下一个”或“上一个”按钮进行切换选中状态。

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General DescriptionThe MAX6406–MAX6411 is a family of ultra-low power circuits used for monitoring battery, power-supply, and regulated system voltages. Each detector contains a precision bandgap reference comparator and is trimmed to specified trip threshold voltages. These devices provide excellent circuit reliability and low cost by eliminating external components and adjustments when monitoring system voltages from 2.5V to 5.0V. A manual reset input is also included.The MAX6406–MAX6411 assert a signal whenever the V CC supply voltage falls below a preset threshold.These devices are differentiated by their output logic configurations and preset threshold voltages. The MAX6406/MAX6409 (push-pull) and the MAX6408/MAX6411 (open-drain) have an active-low output (OUT is logic low when V CC is below V TH ). The MAX6407/MAX6410 have an active-high push-pull output (OUT is logic high when V CC is below V TH ). All parts are guaranteed to be in the correct output logic state for V CC down to 1V. The detector is designed to ignore fast transients on V CC . The MAX6406/MAX6407/MAX6408 have voltage thresholds between 2.20V and 3.08V in approximately 100mV increments. The MAX6409/MAX6410/MAX6411 have voltage thresholds between 3.30V and 4.63V in approximately 100mV increments.Ultra-low supply current of 500nA (MAX6406/MAX6407/MAX6408) makes these parts ideal for use in portable equipment. These devices are available in 4-bump chip-scale packages (UCSP ).ApplicationsPortable/Battery-Powered Equipment Cell Phones PDAs MP3 Players PagersFeatureso Tiny 4-Bump (2 X 2) Chip-Scale Package, (Package Pending Full Qualification—Expected Completion Date 6/30/01. See UCSP Reliability Section for More Details.)o 70% Smaller Than SC70 Packages o Ultra-Low 500nA Supply Current (MAX6406/MAX6407/MAX6408)o Factory-Trimmed Reset Thresholds from 2.20V to 4.63V in Approximately 100mV Increments o ±2.5% Threshold Accuracy (-40°C to +85°C)o Manual Reset Inputo Guaranteed OUT Valid to V CC = 1.0Vo Three Reset Output Logic Options: Active-Low Push-Pull, Active-High Push-Pull, and Active-Low Open-Drain o Immune to Short V CC Transients o No External ComponentsMAX6406–MAX6411Voltage Detectors in 4-Bump (2 X 2)Chip-Scale PackageMaxim Integrated Products 119-2041; Rev 1; 8/01For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at .The MAX6406–MAX6411 are available in factory-set V CCdetector thresholds from 2.20V to 4.63V, in approximately 0.1V increments. Choose the desired threshold suffix from Table 1and insert it in the blank space following “S”. There are 21standard versions with a required order increment of 2500pieces. Sample stock is generally held on the standard ver-sions only (Table1). Required order increment is 10,000 pieces for nonstandard versions (Table 2). Contact factory for avail-ability. All devices available in tape-and-reel only.UCSP reliability is integrally linked to the user’s assemblymethods, circuit board material, and environment. Refer to the UCSP Reliability Notice in the UCSP Reliability section of this data sheet for more information.Pin Configuration appears at end of data sheet.UCSP is a trademark of Maxim Integrated Products, Inc.Ordering InformationSelector GuideM A X 6406–M A X 6411Voltage Detectors in 4-Bump (2 X 2) Chip-Scale PackageABSOLUTE MAXIMUM RATINGSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.All voltages measured to GND unless otherwise noted.VCC..........................................................................-0.3V to +6V OUT/OUT ...................................................-0.3V to (V CC + 0.3V)OUT (open-drain).....................................................-0.3V to +6V MR ..............................................................-0.3V to (V CC + 0.3V)Input/Output Current into Any Pin.......................................20mAContinuous Power Dissipation (T A = +70°C)4-Pin/Bump UCSP (derate 3.8mW/°C above +70°C)....303mW Operating Temperature Range ..........................-40°C to +85°C Junction Temperature......................................................+150°C Storage Temperature Range ............................-65°C to +160°C Bump Reflow Temperature .............................................+235°CELECTRICAL CHARACTERISTICS(V CC = 1.0V to 5.5V, T A = -40°C to +85°C, unless otherwise noted. Typical values are at V CC = 3V and T A = +25°C.) (Note1)MAX6406–MAX6411Voltage Detectors in 4-Bump (2 X 2)Chip-Scale Package_______________________________________________________________________________________3Note 2:Guaranteed by design.ELECTRICAL CHARACTERISTICS (continued)(V CC = 1.0V to 5.5V, T A = -40°C to +85°C, unless otherwise noted. Typical values are at V CC = 3V and T A = +25°C.) (Note1)Typical Operating Characteristics(T A = +25°C, unless otherwise noted.)00.30.20.10.50.40.90.80.70.61.0-40-2020406080SUPPLY CURRENT vs. TEMPERATURETEMPERATURE (°C)S U P P L Y C U R R E N T (µA )050100200150250-40-2020406080PROPAGATION DELAY (V CC FALLING)vs. TEMPERATURETEMPERATURE (°C)P R O P A G A T I O N D E L A Y (µs )M A X 6406–M A X 6411Voltage Detectors in 4-Bump (2 X 2) Chip-Scale Package 4_______________________________________________________________________________________Typical Operating Characteristics (continued)(T A = +25°C, unless otherwise noted.)040206012010080140-40-2020406080PROPAGATION DELAY (V CC RISING)vs. TEMPERATURETEMPERATURE (°C)P R O P A G A T I O N D E L A Y (µs )01100010010MAXIMUM TRANSIENT DURATION vs. THRESHOLD OVERDRIVE500200100400300THRESHOLD OVERDRIVE V TH - V CC (mV)M A X I M U M T R A N S I E N T D U R A T I O N (µs )MAX6406–MAX6411Voltage Detectors in 4-Bump (2 X 2)Chip-Scale Package_______________________________________________________________________________________5M A X 6406–M A X 6411Detailed DescriptionManual Reset InputMany µP-based products require manual reset capabil-ity, allowing the operator, a test technician, or external logic circuit to initiate a reset. A logic low on MR asserts OUT/OUT . OUT/OUT remains asserted while MR is low.This input has an internal 50k Ωpullup resistor, so it can be left open if it is not used. MR can be driven with TTL or CMOS logic levels, or with open-drain/collector out-puts. Connect a normally open momentary switch from MR to GND to create a manual reset function. If MR is driven from long cables or if the device is used in a noisy environment, connect a 0.1µF capacitor from MR to ground to provide additional noise immunity.Applications InformationInterfacing to Different LogicVoltage ComponentsThe MAX6408/MAX6411 have an active-low, open-drain output. This output structure will sink current when OUT is asserted. Connect a pullup resistor from OUT to any supply voltage up to 5.5V (Figure 1). Select a resistor value large enough to allow a valid logic low (see Electrical Characteristics ), and small enough to register a logic high while supplying all input currents and leakage paths connected to the OUT line.Voltage Detectors in 4-Bump (2 X 2) Chip-Scale Package 6_______________________________________________________________________________________Negative-Going V CC TransientsThese devices are relatively immune to short-duration,negative-going V CC transients (glitches).The Typical Operating Characteristics show the Maximum Transient Duration vs. Threshold Overdrive graph, for which output pulses are not generated. The graph shows the maximum pulse width that a negative-going V CC transient may typically have before the devices issue output signals. As the amplitude of the transient increases, the maximum allowable pulse width decreases.UCSP ReliabilityThe chip-scale package (UCSP) represents a unique packaging form factor that may not perform equally to a packaged product through traditional mechanical reliabil-ity tests. CSP reliability is integrally linked to the user ’s assembly methods, circuit board material, and usage environment. The user should closely review these areas when considering use of a CSP package. Performance through Operating Life Test and Moisture Resistance remains uncompromised as it is primarily determined by the wafer-fabrication process.Mechanical stress performance is a greater considera-tion for a CSP package. CSPs are attached through direct solder contact to the user ’s PC board, foregoing the inherent stress relief of a packaged product lead frame. Solder joint contact integrity must be rmation on Maxim ’s qualification plan, test data, and usage recommendations are detailed in the UCSP appli-cation note, which can be found on Maxim ’s website at .Chip InformationTRANSISTOR COUNT: 512PROCESS: BiCMOSMAX6406–MAX6411Voltage Detectors in 4-Bump (2 X 2)Chip-Scale Package_______________________________________________________________________________________7Figure 1. Interfacing to Different Logic Voltage ComponentsPin ConfigurationM A X 6406–M A X 6411Voltage Detectors in 4-Bump (2 X 2) Chip-Scale Package Package InformationMaxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.8_____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600©2001 Maxim Integrated ProductsPrinted USAis a registered trademark of Maxim Integrated Products.。

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