In the time slot replacement device the memory sup
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专利名称：In the time slot replacement device the memory supervisory mode
发明人：KABAYA EIICHI,蒲谷 衛一
申请号：JP特願昭63-318851
申请日：19881216
公开号：JP第2730109号B2
公开日：
19980325
专利内容由知识产权出版社提供
摘要：PURPOSE:To attain the alternating monitor of three temporary memories by preparing these memories and using these memories in a write/read/pause cycle in the case an idle time slot is available every second cycle only for the input data. CONSTITUTION:The data input is applied to a 1st selection circuit 2 together with a monitor pattern received from a monitor signal generating circuit 1. The circuit 2 selects the monitor pattern via an idle time slot of the data input. These data inputs are inputted to the 1st-3rd temporary memory circuits 31-33 and written there with an instruction of a write counter 41. Then the data are read out of the circuits 31-33 with an instruction of a read counter 51 and outputted after selection undergone via a 2nd selection circuit 6. These read data are collated with the monitor pattern via a pattern collation circuit 7. Thus it is possible to alternately monitor the circuits 31-33.
申请人：NIPPON DENKI KK,日本電気株式会社
地址：東京都港区芝5丁目7番1号
国籍：JP
代理人：井ノ口 壽
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