Parasiticextraction：寄生参数提取

Overview
Synopsys’ Star-RCXT™ is the electronic design automation (EDA) industry’s gold standard for parasitic extraction. It provides a single solution for ASIC, system-on-chip (SoC), digital custom,
memory and analog designs. Trusted by over 250 semiconductor companies and proven in thousands of production designs, Star-RCXT delivers fast and sub-femtofarad accurate technology. The Star-RCXT solution offers advanced capabilities needed for sub-65-nanometer (nm) designs, including variation-aware parasitic extraction, chemical-mechanical polishing (CMP) based and litho-aware extraction, inductance extraction and analog mixed signal design flow. Its seamless integration with industry leading physical verification, circuit simulation, timing, signal integrity, power, reliability and RTL2GDSII flows enables unmatched ease-of-use, increased productivity and reduced time-to-market. Star-RCXT is used by leading foundries to solve process modeling challenges at 65-nm and 45-nm.
Star-RCXT
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Parasitic extraction
Star-RCXT Parasitic Extraction Solution
Semiconductor process technology has been continually scaling down for the past four decades and the trend continues. In the early days of integrated circuits (ICs), the speed bottleneck was at the circuit level, whereas interconnects were treated as ideal connections with the parasitic effects ignored. With shrinking process technologies, increasing die size and clock frequency, interconnect parasitic effects have begun to manifest themselves in signal delay and noise. Consequently, interconnects now play an important role in the design flow. Today, IC design is interconnect-limited and the design flow is interconnect-driven. A trusted parasitic extraction tool that models advanced process effects and has the capacity to handle large designs with tens of millions of transistors and cells is required to enable designers to quickly achieve their sign-off goals.
Star-RCXT has the capacity and accuracy for sign-off extraction on the world’s largest SoC designs. Star-RCXT’s proprietary, advanced technology extracts full-chip designs extremely fast and provides accurate results within 5 percent or 0.2 femto-farad of industry-standard field solvers. Star-RCXT achieves its high accuracy by performing detailed modeling of every capacitive interaction. While, other extraction tools attempt to increase speed by modeling only a subset of the capacitive interactions, Star-RCXT extracts billions of capacitors for a typical design and by using a proprietary parasitic reduction capability, generates the smallest possible netlist, to achieve accurate results. Figure 2 shows excellent correlation between Star-RCXT and Raphael-NXT and demonstrates the accuracy of Star-RCXT.
Star-RCXT provides parasitic extraction solution for full-chip gate-level implementation and sign-off as well as for transistor-level custom, memory, analog-mixed-signal (AMS) and radio-frequency (RF) designers, as shown in Figure 1.
Gate-level Extraction
Star-RCXT is easily integrated into all industry standard design flows – Synopsys’ Galaxy™ Design Platform, and other third party implementation platforms – using Synopsys’ Milkyway™, LEF/DEF or GDSII interfaces. Galaxy users benefit from the increased productivity of Milkyway as well as the integration and faster convergence and flexibility of full-chip extraction at any time during the design cycle. In addition, Star-RCXT’s tight binary interface with PrimeTime®, PrimeTime SI, PrimeTime PX and integration with PrimeRail enables accurate post-layout optimization and timing, noise and power network sign-off.
Transistor-level Extraction
Star-RCXT is integrated with the EDA industry’s leading layout-versus-schematic verification tools and simulation tools – Hercules™, Calibre, HSIM plus, NanoSim™ , HSPICE® and NanoTime for high-seed productive design. Star-RCXT also reads connectivity, cross-reference, and device information from a generated data-base and integrates with third-party analysis tools through industry standard SPICE, DSPF and SPEF netlist formats. For the highest throughput, Star-RCXT offers hierarchical and in-context modes of extraction.
Virtuoso Custom Design Platform Integration
Star-RCXT is integrated with Virtuoso® Analog Design Environment (ADE) for AMS and RF design. Star-RCXT generates Design Framework II (DFII) database parasitic views for netlisting and simulation, compatible with common netlisting interfaces used within ADE. A probing utility is also provided
to probe parasitics either within the parasitic view or within the matching schematic view. The parasitic prober also provides the ability to output probed parasitics to an ASCII report file, and to annotate parasitic view total capacitance values to an associated schematic view.
Reluctance (Inductance) Extraction
Inductance effect becomes more and more prominent as the resistance (both device and interconnect) decreases and
the operating frequency increases. At low frequencies, RC modeling is sufficient and inductance can safely be ignored.
As clock frequencies increase, however, modeling global interconnects such as RC circuits are no longer adequate and inductance must be included in the modeling. Ignoring the inductance effect can underestimate signal integrity problems as well.
Star-RCXT provides a novel approach to modeling on-chip inductance effects, called partial reluctance extraction. Reluc-tance is defined as the inverse of inductance. Reluctance effects are localized just like capacitance and unlike inductance, resulting in a much sparser matrix compared to inductance. This enables Star-RCXT to produce the smallest netlist without losing any accuracy – overall achieving orders of magnitude faster extraction and simulation.
Variation-aware extraction
With shrinking technology, parametric yield due to variations
in critical device and interconnect process parameters has become the dominant factor in yield loss. In order to improve silicon predictability it is mandatory that extraction tools model the process variation accurately. Also, as the uncertainty grows,
Figure 1: Star-RCXT provides comprehensive solution for gate-level and transistor-level extraction
the traditional corner-based methodologies requiring multiple process technology files and time-consuming multiple extraction and simulation runs are becoming impractical. Statistical techniques are needed to model these process variation effects. Star-RCXT offers advanced statistical solution that enables sensitivity based parasitic extraction for interconnect process and temperature variation-aware designs at 65-nm and beyond. The variation of each process parameter, such as conductor or dielectric thickness, is available through the variation-aware process technology file and is used to compute sensitivities of parasitic values based on each of the process variations. Star-RCXT’s sensitivity-based extraction solution offers unique benefits to traditional STA flow users as well as to the variation-aware STA flow users, as shown in figure . It enhances the productivity of the traditional flow designers by eliminating the need to do multiple corner extractions, instead providing a single run sensitivity based extraction and multiple netlisting to feed into the traditional analysis – overall, providing 2X faster solution than traditional 5-corner extraction. On the other hand, for variation-aware STA, it generates a single sensitivity-based netlist for fast and robust sign-off. Star-RCXT Key Features
Comprehensive Process Modeling Conformal dielectric process support Support of Air Gap Via cap extraction Layer ETCH
Nonlinear RPSQ variation in function of Silicon width Temperature dependent resistance modeling for conducting layers and vias
••••••Support of background dielectric Nonlinear via resistance modeling 45-degree routing support
Support of multiple inter-layer dielectric Support of multiple intra-layer dielectric Support for co-vertical conductors Support for non-planarized metal
Multiple cap accuracy mode for different technology (MODE100/MODE200/MODE400) Advanced Process Modeling Sensitivity Extraction CMP simulator interface Litho-aware extraction
Single run multi-corner extraction Reluctance extraction Substrate extraction
Accurate D interconnect modeling
Width and Spacing dependent Thickness variation Bottom Thickness variation Density-based thickness variation Multiple density-based variation
Width and Spacing dependent RPSQ variation RPSQ variation in function of Silicon width Nonlinear RPSQ variation Trapezoidal polygon support Dielectric damage modeling Automatic Field Solver Flow
Copper interconnect, local interconnect modeling Low-K dielectric, silicon on insulator (SOI) modeling
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Over 99% of nets within 5% or 200aF
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Figure 2: Star-RCXT is strongly correlated with Raphael-NXT (field solver)
Figure 3: Star-RCXT’s sensitivity based extraction solution supports traditional corner-based and variation-aware STA and simulation flows
Gate-level Flow Gray-Box Extraction
Direct interface with Milkyway Database Direct interface with LEF/DEF 5.6Flexibility of Instance port handling Reading of gzip compressed LEF/DEF files Reduction of netlist size
Support metal fill polygons from GDSII file.Support GDS inputs for LEF macros.Support hierarchical LEF/DEF inputs.Power net extraction Transistor-level Flow
Flexibility of cap threshold handling Resistance threshold handling
Ability to add probe texts to the final netlist Support coupling capacitance to bulk layers
Support all device types including user-defined devices and generic devices
Interface to Hercules physical verification
Interface to Calibre physical verification through CCI Flexibility to control netlist type Support multiple cross-reference flow
Flexibility of ignoring the parameter parasitic presented in spice model
Support parasitic with model names
Ability to extract device of shrunk design parasitic for actual drawn design
••••••••••••••••••••••Productivity and Ease of Use Incremental Extraction Distributed Processing License Queuing ADE integration Hierarchical Extraction Selective net extraction
Support of multiple netlist formats (SBPF/SPF/SPEF) Ability to control a number of characters in a line of netlist Ability to write device parameter in parasitic netlist Ability to split power net parasitic into a separate netlist Ability to extract device parameters such as width/length and report in parasitic netlist
Ability to output original design coordinates of instance.Ability to extract a design in a given temperature Ability to read time capacitance or designed cap during extraction
Ability to extract multiple corners simultaneously Ability to merge multiple extraction result to one file Flexibility to control of ground capacitance
Ability to write parasitic diode to parasitic capacitance User-control reduction of parasitic netlists Multiple reduction mode for different application Validated silicon models available from leading foundries including TSMC, UMC, Chartered
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Synopsys, Inc.
700 East Middlefield Road Mountain View, CA 9404
Specifications File Format Support
Star-RCXT supports the following industry-standard formats and interfaces:
Layout data in: GDSII, LEF/DEF, Milkyway, Hercules,CalibreOutput formats: DSPF, SPICE, SPEF, SSPEF Binary interface: Direct binary interface to PrimeTime SI System Requirements
DRAM: 512MB, recommend 1GB Swap Space: 512MB, recommend 2GB
Installation disk space: 250MB baseline plus 250MB per platform
Design disk space depends on the circuit size, recommended minimum 500MB
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For more information about this product, sales, support services or training, please contact your local Synopsys representative or call 1-800-388-9125.。