MEMORY存储芯片MT45W4MW16PCGA-70LWT中文规格书

Figure 116: READ Preamble Training
CMD DQs
DQS_t WRITE Postamble
Whether the 1t CK or 2t CK WRITE preamble mode is selected, the WRITE postamble re-
mains the same at ½t CK.
Figure 117: WRITE Postamble
2t CK Mode
1t CK Mode
READ Postamble
Whether the 1t CK or 2t CK READ preamble mode is selected, the READ postamble re-
mains the same at ½t CK.
8Gb: x4, x8, x16 DDR4 SDRAM Programmable Preamble Modes and DQS Postambles
Table 114: Single-Ended Output Levels (Continued)
Note: 1.The swing of ±0.15 × V DDQ is based on approximately 50% of the static single-ended
output peak-to-peak swing with a driver impedance of R ZQ /7 and an effective test load
of 50˖ to V TT = V DDQ .
Using the same reference load used for timing measurements, output slew rate for fall-
ing and rising edges is defined and measured between V OL(AC) and V OH(AC) for single-
ended signals.
Table 115: Single-Ended Output Slew Rate Definition
Figure 232: Single-ended Output Slew Rate Definition
TR se
V OH(AC)V OL(AC)
S i n g l e -E n d e d O u t p u t V o l t a g e (D Q )8Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Output Measurement Levels
Figure 146: READ (BC4) OTF to WRITE (BC4) OTF with 2t CK Preamble in Same or Different Bank Group
Command DQ CK_t CK_c
DQS_t,
DQS_c
Bank Group
Address Address Notes: 1.BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 2t CK, WL = 10 (CWL = 9 + 1 [see Note
5], AL = 0), WRITE preamble = 2t CK.
2.DO n = data-out from column n ; DI b = data-in from column b .
3.DES commands are shown for ease of illustration; other commands may be valid at
these times.
4.BC4 (OTF) setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0
and WRITE commands at T6.
5.When operating in 2t CK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting.
6.CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
Figure 147: READ (BC4) Fixed to WRITE (BC4) Fixed with 1t CK Preamble in Same or Different Bank
Group
Command DQ
CK_t CK_c
DQS_t,
DQS_c
Bank Group
Address Address Notes: 1.BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 1t CK, WL = 9 (CWL = 9, AL = 0),
WRITE preamble = 1t CK.
2.DO n = data-out from column n ; DI b = data-in from column b .
8Gb: x4, x8, x16 DDR4 SDRAM READ Operation。