MEMORY存储芯片MT47J128M8HQ-37E中文规格书

c.DQS should function normally.
4.REF commands may NOT be issued at anytime while in PPT mode.
5.Issue PRE after t PGM time so that the device can repair the target row during t PGM time.
a.Wait t PGM_Exit after PRE to allow the device to recognize the repaired target row address.
6.Issue MR4[13] 0 command to hPPR mode disable.
a.Wait t PGMPST for hPPR mode exit to complete.
b.After t PGMPST has expired, any valid command may be issued.
The entire sequence from hPPR mode enable through hPPR mode disable may be re-peated if more than one repair is to be done.
After completing hPPR mode, MR0 must be re-programmed to a prehPPR mode state if the device is to be accessed.
After hPPR mode has been exited, the DRAM controller can confirm if the target row was repaired correctly by writing data into the target row and reading it back.
Figure 77: hPPR WR – Entry
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Figure 78: hPPR WR – Repair and Exit
Don’t Care
8Gb: x4, x8, x16 DDR4 SDRAM Hard Post Package Repair
Current Specifications – Limits
Table 148: I DD , I PP , and I DDQ Current Limits; Die Rev. A (0° ื T C ื 85°C)
8Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Limits
18.When CA parity is enabled for I DD4W , current changes by approximately +12% (x8),
+12% (x16).
19.When 2X REF is enabled for I DD5R , current changes by approximately –14%.
20.When 4X REF is enabled for I DD5R , current changes by approximately –33%.
21.I PP0 test and limit is applicable for I DD0 and I DD1 conditions.
22.I PP3N test and limit is applicable for all I DD2x , I DD3x , I DD4x and I DD8 conditions; that is, test-
ing I PP3N should satisfy the I PP s for the noted I DD tests.
23.DDR4-1600 and DDR4-1866 use the same I DD limits as DDR4-2133.
24.The I DD values must be derated (increased) when operated outside of the range 0°C ื T C
ื 85°C:
When T C < 0°C: I DD2P , and I DD3P must be derated by 6%; I DD4R and I DD4W must be derated by 4%; I DD6, I DD6ET , and I DD7 must be derated by 11%.
When T C > 85°C: I DD0, I DD1, I DD2N , I DD2NT , I DD2Q , I DD3N , I DD3P , I DD4R , I DD4W , and I DD5R must be derated by 3%; I DD2P must be derated by 40%. These values are verified by design and characterization, and may not be subject to production test.
25.I PP6x is applicable to I DD6N , I DD6E , I DD6R and I DD6A conditions.
Table 150: I DD , I PP , and I DDQ Current Limits; Die Rev. D (0° ื T C ื 85°C)
8Gb: x4, x8, x16 DDR4 SDRAM Current Specifications – Limits。