74LVC2G126DC-G资料
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It is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.
plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm
SOT902-1
4. Marking
Table 2. Marking codes Type number 74LVC2G126DP 74LVC2G126DC 74LVC2G126GT 74LVC2G126GD 74LVC2G126GM
1A 2
7 2OE
2Y 3
6 1Y
GND 4
5 2A
001aab741 Transparent top view
Fig 4. Pin configuration SOT833-1 (XSON8)
1OE 1
8 VCC
1A 2 2Y 3
74LVC2G126
7 2OE 6 1Y
GND 4
5 2A
001aah949 Transparent top view
Fig 5. Pin configuration SOT996-2 (XSON8U)
8 VCC
terminal 1 index area
74LVC2G126
2OE 1
7 1OE
1Y 2
6 1A
2A 3
5 2Y
GND 4
001aaf056 Transparent top view
Fig 6. Pin configuration SOT902-1 (XQFN8U)
Tamb = −40 °C to +125 °C
-
+100
mA
−100
-
mA
[3] -
300
mW
−65
+150
°C
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
74LVC2G126_8
N JESD8-7 (1.65 V to 1.95 V) N JESD8-5 (2.3 V to 2.7 V) N JESD8-B/JESD36 (2.7 V to 3.6 V) I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I ±24 mA output drive (VCC = 3.0 V) I CMOS low power consumption I Latch-up performance exceeds 250 mA I Direct interface with TTL levels I Inputs accept voltages up to 5 V I Multiple package options I Specified from −40 °C to +85 °C and −40 °C to +125 °C
Product data sheet
Rev. 08 — 5 May 2008
Description
output enable input (active HIGH) data input data output ground (0 V) data input
© NXP B.V. 2008. All rights reserved.
Symbol Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
VO
output voltage
VI < 0 V
VO > VCC or VO < 0 V Active mode Power-down mode
3 of 17
NXP Semiconductors
74LVC2G126
Dual bus buffer/line driver; 3-state
Table 3. Symbol
1Y 2OE VCC
Pin description …continued Pin SOT505-2, SOT765-1, SOT833-1 and SOT996-2 6 7 8
X
Output nY L H Z
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
8. Limiting values
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
74LVC2G126DP −40 °C to +125 °C TSSOP8
74LVC2G126DC −40 °C to +125 °C VSSOP8
74LVC2G126GT −40 °C to +125 °125 °C XSON8U
74LVC2G126GM −40 °C to +125 °C XQFN8U
−0.5 −50 [1] −0.5 [1] −0.5 [1][2] −0.5
+6.5
V
-
mA
+6.5
V
±50
mA
VCC + 0.5 V
+6.5
V
IO
output current
VO = 0 V to VCC
-
±50
mA
ICC IGND Ptot Tstg
supply current ground current total power dissipation storage temperature
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [3] For TSSOP8 packages: above 55 °C the value of Ptot derates linearly at 2.5 mW/K.
NXP Semiconductors
74LVC2G126
Dual bus buffer/line driver; 3-state
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC2G126 as a translator in a mixed 3.3 V and 5 V environment.
For VSSOP8 packages: above 110 °C the value of Ptot derates linearly at 8.0 mW/K. For XSON8, XSON8U and XQFN8U packages: above 45 °C the value of Ptot derates linearly at 2.4 mW/K.
6.1 Pinning
74LVC2G126
1OE 1 1A 2 2Y 3
GND 4
8 VCC 7 2OE 6 1Y 5 2A
001aab740
Fig 3. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)
74LVC2G126
1OE 1
8 VCC
5. Functional diagram
Marking code V26 V26 V26 V26 V26
1A
1Y
1OE
2A
2Y
2OE
Fig 1. Logic symbol
001aah787
nA
nY
nOE
Fig 2. Logic diagram (one gate)
mna234
74LVC2G126_8
6.2 Pin description
Table 3. Symbol
1OE 1A 2Y GND 2A
Pin description Pin SOT505-2, SOT765-1, SOT833-1 and SOT996-2 1 2 3 4 5
SOT902-1
7 6 5 4 3
74LVC2G126_8
Description
Version
plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm
SOT902-1
2 1 8
7. Functional description
Description
data output output enable input (active HIGH) supply voltage
Table 4. Function table[1]
Input
nOE
nA
H
L
H
H
L
Product data sheet
Rev. 08 — 5 May 2008
© NXP B.V. 2008. All rights reserved.
2 of 17
NXP Semiconductors
74LVC2G126
Dual bus buffer/line driver; 3-state
6. Pinning information
2. Features
I Wide supply voltage range from 1.65 V to 5.5 V I 5 V tolerant input/output for interfacing with 5 V logic I High noise immunity I Complies with JEDEC standard:
74LVC2G126
Dual bus buffer/line driver; 3-state
Rev. 08 — 5 May 2008
Product data sheet
1. General description
The 74LVC2G126 is a dual non-inverting buffer/line driver with 3-state outputs. Each 3-state output is controlled by an output enable input (pin nOE). A LOW-level at pin nOE causes the output to assume a high-impedance OFF-state. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.
plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 × 1.95 × 0.5 mm
plastic extremely thin small outline package; no leads; SOT996-2 8 terminals; UTLP based; body 3 × 2 × 0.5 mm
plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm
SOT902-1
4. Marking
Table 2. Marking codes Type number 74LVC2G126DP 74LVC2G126DC 74LVC2G126GT 74LVC2G126GD 74LVC2G126GM
1A 2
7 2OE
2Y 3
6 1Y
GND 4
5 2A
001aab741 Transparent top view
Fig 4. Pin configuration SOT833-1 (XSON8)
1OE 1
8 VCC
1A 2 2Y 3
74LVC2G126
7 2OE 6 1Y
GND 4
5 2A
001aah949 Transparent top view
Fig 5. Pin configuration SOT996-2 (XSON8U)
8 VCC
terminal 1 index area
74LVC2G126
2OE 1
7 1OE
1Y 2
6 1A
2A 3
5 2Y
GND 4
001aaf056 Transparent top view
Fig 6. Pin configuration SOT902-1 (XQFN8U)
Tamb = −40 °C to +125 °C
-
+100
mA
−100
-
mA
[3] -
300
mW
−65
+150
°C
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
74LVC2G126_8
N JESD8-7 (1.65 V to 1.95 V) N JESD8-5 (2.3 V to 2.7 V) N JESD8-B/JESD36 (2.7 V to 3.6 V) I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I ±24 mA output drive (VCC = 3.0 V) I CMOS low power consumption I Latch-up performance exceeds 250 mA I Direct interface with TTL levels I Inputs accept voltages up to 5 V I Multiple package options I Specified from −40 °C to +85 °C and −40 °C to +125 °C
Product data sheet
Rev. 08 — 5 May 2008
Description
output enable input (active HIGH) data input data output ground (0 V) data input
© NXP B.V. 2008. All rights reserved.
Symbol Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
VO
output voltage
VI < 0 V
VO > VCC or VO < 0 V Active mode Power-down mode
3 of 17
NXP Semiconductors
74LVC2G126
Dual bus buffer/line driver; 3-state
Table 3. Symbol
1Y 2OE VCC
Pin description …continued Pin SOT505-2, SOT765-1, SOT833-1 and SOT996-2 6 7 8
X
Output nY L H Z
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
8. Limiting values
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
74LVC2G126DP −40 °C to +125 °C TSSOP8
74LVC2G126DC −40 °C to +125 °C VSSOP8
74LVC2G126GT −40 °C to +125 °125 °C XSON8U
74LVC2G126GM −40 °C to +125 °C XQFN8U
−0.5 −50 [1] −0.5 [1] −0.5 [1][2] −0.5
+6.5
V
-
mA
+6.5
V
±50
mA
VCC + 0.5 V
+6.5
V
IO
output current
VO = 0 V to VCC
-
±50
mA
ICC IGND Ptot Tstg
supply current ground current total power dissipation storage temperature
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [3] For TSSOP8 packages: above 55 °C the value of Ptot derates linearly at 2.5 mW/K.
NXP Semiconductors
74LVC2G126
Dual bus buffer/line driver; 3-state
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC2G126 as a translator in a mixed 3.3 V and 5 V environment.
For VSSOP8 packages: above 110 °C the value of Ptot derates linearly at 8.0 mW/K. For XSON8, XSON8U and XQFN8U packages: above 45 °C the value of Ptot derates linearly at 2.4 mW/K.
6.1 Pinning
74LVC2G126
1OE 1 1A 2 2Y 3
GND 4
8 VCC 7 2OE 6 1Y 5 2A
001aab740
Fig 3. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)
74LVC2G126
1OE 1
8 VCC
5. Functional diagram
Marking code V26 V26 V26 V26 V26
1A
1Y
1OE
2A
2Y
2OE
Fig 1. Logic symbol
001aah787
nA
nY
nOE
Fig 2. Logic diagram (one gate)
mna234
74LVC2G126_8
6.2 Pin description
Table 3. Symbol
1OE 1A 2Y GND 2A
Pin description Pin SOT505-2, SOT765-1, SOT833-1 and SOT996-2 1 2 3 4 5
SOT902-1
7 6 5 4 3
74LVC2G126_8
Description
Version
plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm
SOT902-1
2 1 8
7. Functional description
Description
data output output enable input (active HIGH) supply voltage
Table 4. Function table[1]
Input
nOE
nA
H
L
H
H
L
Product data sheet
Rev. 08 — 5 May 2008
© NXP B.V. 2008. All rights reserved.
2 of 17
NXP Semiconductors
74LVC2G126
Dual bus buffer/line driver; 3-state
6. Pinning information
2. Features
I Wide supply voltage range from 1.65 V to 5.5 V I 5 V tolerant input/output for interfacing with 5 V logic I High noise immunity I Complies with JEDEC standard:
74LVC2G126
Dual bus buffer/line driver; 3-state
Rev. 08 — 5 May 2008
Product data sheet
1. General description
The 74LVC2G126 is a dual non-inverting buffer/line driver with 3-state outputs. Each 3-state output is controlled by an output enable input (pin nOE). A LOW-level at pin nOE causes the output to assume a high-impedance OFF-state. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.
plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 × 1.95 × 0.5 mm
plastic extremely thin small outline package; no leads; SOT996-2 8 terminals; UTLP based; body 3 × 2 × 0.5 mm