在对cyclone3配置时遇到的问题及配置的相关内容

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在对cyclone3配置时遇到的问题及配置的相关内容Cyclone III 器件的 AS 配置引脚与其他FPGA不同,其他FPGA 的 DA TA、DCLK、CSn、ASDO等引脚都是专用的,Cyclone III会使用另外的一些IO作为 EPCS 连接脚?有点晕!
对cyclone3配置时,程序就是写不进去!目前来说问题出在
一、核电压没有加上(vccint=1.2v)。

二、PLL的供电电压也没有加上(vcca=2.5v)。

三、配置引脚所用的BANK对应的电压也没有加上(vccio=3.3v)。

于是我注定写不进程序啊!!!
DATASHEET中发现,这三个引脚一个不能少,这样子才能配置成功!
另外的一些收获也记录一下吧。

一、有若干种配置模式,比如FAST AS,STANDARD AS等等,这个由MSEL【3:0】来设定。

二、VCCA is the analog power to the phase-locked loop (PLL).
三、When using a JTAG configuration scheme or a serial configuration device in an AS configuration scheme, you must connect a 25ou series resistor at the near end of the TDO and TDI pin or the serial configuration device for the DATA[0]pin.
四、After POR, the Cyclone III device family releases nSTATUS, pull-up resistor and enters which is pulled high by an external 10-k configuration mode.
When nCONFIG goes high, the device exits reset and releases the open-drain
nSTATUS pin, which pull-up resistor. After Ωis then pulled high by an external 10-k nSTATUS is released, the device is ready to receive configuration data and the configuration stage begins.
五、Configuration
Configuration data is latched into the Cyclone III device family at each DCLK cycle.
However, the width of the data bus and the configuration time taken for each scheme
are different. After the device receives all the configuration data, the device releases
the open-drain pull-up ΩCONF_DONE pin, which is pulled high by an external 10-k
resistor. A low-to-high transition on the CONF_DONE pin indicates that configuration
is complete and initialization of the device can begin. The CONF_DONE pin must have
pull-up resistor for the device to initialize.Ωan external 10-k
You can begin reconfiguration by pulling the nCONFIG pin low. The nCONFIG pin
must be low for at least 500 ns. When nCONFIG is pulled low, the
Cyclone III device
family is reset. The Cyclone III device family also pulls nSTATUS and CONF_DONE low
and all I/O pins are tri-stated. When nCONFIG returns to a logic-high level and
nSTATUS is released by the Cyclone III device family, reconfiguration begins.
六、User Mode
An optional INIT_DONE pin is available that signals the end of initialization and the
start of user mode with a low-to-high transition. The Enable INIT_DONE Output
option is available in the Quartus II software from the General tab of the Device and
Pin Options dialog box. If you use the INIT_DONE pin, it is high due to an external
10-k pull-up resistor when nCONFIG is low and during the beginning of
configuration. After the option bit to enable INIT_DONE is programmed into the
device (during the first frame of configuration data), the INIT_DONE pin goes low.
When initialization is complete, the INIT_DONE pin is released and pulled high. This
low-to-high transition signals that the device has entered user mode. In user mode,
the user I/O pins function as assigned in your design and no longer have weak
pull-up resistors.
七、整个过程应该是program>>configuration>>initialiaition.进入user mode。

八、A configuration scheme with different configuration voltage standards is selected by
driving the MSEL pins either high or low, as listed in Table 9–7.
The MSEL pins are powered by VCCINT . The MSEL[3..0] pins have internal 9-k
pull-down resistors that are always active.
九、The configuration voltage standard is applied to the VCCIO supply of the bank in which the configuration pins reside.You must follow specific requirements when interfacing Cyclone III device family with
2.5-,
3.0-, and 3.3-V configuration voltage standards.
十、In the AS configuration scheme, the serial configuration device latches input and
control signals on the rising edge of DCLK and drives out configuration
data on the
falling edge. Cyclone III device family drives out control signals on the falling edge of
DCLK and latch configuration data on the falling edge of DCLK.
In configuration mode, the Cyclone III device family enables the serial configuration
device by driving the nCSO output pin low, which connects to the nCS pin of the
configuration device. The Cyclone III device family uses the DCLK and DATA[1]pins
to send operation commands and read address signals to the serial configuration
device. The configuration device provides data on its DATA pin, which connects to the
DATA[0] input of the Cyclone III device family.
After all the configuration bits are received by the Cyclone III device family, it releases
the open-drain CONF_DONE pin, which is pulled high by an external resistor. 10-k
Initialization begins only after the CONF_DONE signal reaches a
logic-high level. All
AS configuration pins (DATA[0], DCLK, nCSO, and DATA[1]) have
weak internal
pull-up resistors that are always active. After configuration, these pins are set as input
tri-stated and are driven high by weak internal pull-up resistors. The CONF_DONE pin
must have an external pull-up resistor for the device to initialize. 10-k The timing parameters for AS mode are not listed here because the
tCF2CD, tCF2ST0, tCFG,
tSTATUS, tCF2ST1, and tCD2UM timing parameters are identical to the timing parameters for PS
mode listed in Table 9–13 on page 9–39.
十一、AS模式下的四个引脚:DCLK DATA[0] DATA[1](ASDI) NCS(NCSO) 中DCLK是由FPGA产生。

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