74HCT74N中文资料

元器件交易网
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
FEATURES • Wide supply voltage range from 2.0 to 6.0 V • Symmetrical output impedance • High noise immunity • Low power dissipation • Balanced propagation delays • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V.
2003 Jul 10
2
元器件交易网
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
FUNCTION TABLES Table 1 See note 1 INPUT SD L H L Table 2 See note 1 INPUT SD H H Note 1. H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH CP transition; Qn+1 = state after the next LOW-to-HIGH CP transition. ORDERING INFORMATION PACKAGE TYPE NUMBER 74HC74N 74HCT74N 74HC74D 74HCT74D 74HC74DB 74HCT74DB 74HC74PW 74HCT74PW 74HC74BQ 74HCT74BQ TEMPERATURE RANGE −40 to +125 °C −40 to +125 °C −40 to +125 °C −40 to +125 °C −40 to +125 °C −40 to +125 °C −40 to +125 °C −40 to +125 °C −40 to +125 °C −40 to +125 °C PINS 14 14 14 14 14 14 14 14 14 14 PACKAGE DIP14 DIP14 SO14 SO14 SSOP14 SSOP14 TSSOP14 TSSOP14 DHVQFN14 DHVQFN14 RD H H CP ↑ ↑ D L H RD H L L CP X X X D X X X
74HC74; 74HCT74
handbook, halfpage handbook, halfpage
1RD 1
VCC 14 13 12 2RD 2D 2CP 2SD 2Q
1RD 1D 1CP 1SD 1Q 1Q GND
1 2 3 4 5 6 7
MNA417
14 VCC 13 2RD 12 2D
1D 1CP 1SD 1Q
2003 Jul 10
3
元器件交易网
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
PINNING PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SYMBOL 1RD 1D 1CP 1SD 1Q 1Q GND 2Q 2Q 2SD 2CP 2D 2RD VCC data input clock input (LOW-to-HIGH, edge-triggered) asynchronous set-direct input (active LOW) true flip-flop output complement flip-flop output ground (0 V) complement flip-flop output true flip-flop output asynchronous set-direct input (active LOW) clock input (LOW-to-HIGH, edge-triggered) data input asynchronous reset-direct input (active LOW) positive supply voltage DESCRIPTION asynchronous reset-direct input (active LOW)
元器件交易网
INTEGRATED CIRCUITS
DATA SHEET
74HC74; 74HCT74 Dual D-type flip-flop with set and reset; positive-edge trigger
Product specification Supersedes data of 1998 Feb 23 2003 Jul 10
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/tPLH PARAMETER propagation delay nCP to nQ, nQ nSD to nQ, nQ nRD to nQ, nQ fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. For 74HC74 the condition is VI = GND to VCC. For 74HCT74 the condition is VI = GND to VCC − 1.5 V. maximum clock frequency input capacitance power dissipation capacitance per flip-flop notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 14 15 16 76 3.5 24 15 18 18 59 3.5 29 ns ns ns MHz pF pF HCT UNIT
Product specification
Dual D-type flip-flop with set and reset; positive-edge trigger
74HC74; 74HCT74
OUTPUT Q H L H Q L H H
OUTPUT Qn+1 L H Qn+1 H L
MATERIAL plastic plastic plastic plastic plastic plastic plastic plastic plastic plastic
CODE SOT27-1 SOT27-1 SOT108-1 SOT108-1 SOT337-1 SOT337-1 SOT402-1 SOT402-1 SOT762-1 SOT762-1
2 3 4 5 6 7 Top view GND 8 2Q
74
11 2CP 10 2SD
GND(1)
11 10 9
9
2Q 1Q
8 2Q
MNB038
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
MNA418
handbook, halfpage
4 3 2
S C1 1D R
5
5 9
1
6
6 8
10 11 12 13
S C1 1D R
MNA419
9
8
Fig.3 Logic symbol.
Fig.4 IEC logic symbol.
handbook, halfpage
4
1SD SD D CP FF Q RD 1Q 6 Q
74HC74; 74HCT74
GENERAL DESCRIPTION The 74HC/HCT74 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT74 are dual positive-edge triggered, D-type flip-flops with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

Dual D-type flip-flop with set and reset; positive-edge trigger
74HC74; 74HCT74
handbook, halfpage
4 10 1SD 2SD 2 12 3 11 SD 1Q 1D Q D 2D 2Q 1CP CP 2CP FF 1Q Q 2Q RD 1RD 2RD 1 13
2 3
1D 1CP
1Q
5
1 10
1RD 2SD SD D CP FF Q RD 2Q 8 Q
12 11
2D 2CP
2Q
9
13
2RD
MNA420
Fig.5 Functional diagram.
2003 Jul 10
5
元器件交易网
Philips Semiconductors
Fig.1
Pin configuration DIP14, SO14 and (T)SSOP14.
Fig.2 Pin configuration DHVQFN14.
2003 Jul 10
4
元器件交易网
Philips Semiconductors
Product specification