FPGA可编程逻辑器件芯片XC6SLX45T-2FGG484C中文规格书

Date Version Revision
10/07/09 1.0Initial Xilinx release.
11/09/09 1.1•Updated Figure1-17 and Figure1-23.
•Changed speed grade from -2 to -3.
•Miscellaneous typographical edits.
02/01/10 1.1.1Minor typographical edits to Table1-24 and Table1-25.
05/18/10 1.2Updated Figure1-2. Added Note 6 to Table1-11. Updated board connections for
SFP_TX_DISABLE in Table1-12. Added note about FMC LPC J63 connector in 18. VITA
57.1 FMC LPC Connector. Updated U1 FPGA Pin column for FMC_LA00_CC_P/N in
Table1-28. Updated description of PMBus Pod and TI Fusion Digital Power Software
GUI in Onboard Power Regulation. Updated Appendix B, VITA 57.1 FMC LPC
Connector Pinout, and Appendix C, Xilinx Design Constraints.
06/16/10 1.3Updated 2. 128 MB DDR3 Component Memory. Added note 1 to Table1-30.
09/24/10 1.4Updated description of Fusion Digital Power Software in Onboard Power Regulation. 02/16/11 1.5Revised oscillator manufacturer information from Epson to SiTime in Table1-1. Revised
oscillator manufacturer information from Epson to SiTime on page page26. Deleted note
on page 44 referring to J55: “Note: This header is not installed on the SP605 as built.”
Revised values for R50 and R216 in Figure1-12. Revised oscillator manufacturer
information from Epson to SiTime on page page69.
Detailed Description
Table 1-5 shows the connections and pin numbers for the DDR3 Component Memory.MEM1_ODT 4.7K Ω to GND
–MEM1_DQ[15:0]
–ODT MEM1_UDQS[P,N], MEM1_LDQS[P,N] –ODT MEM1_UDM, MEM1_LDM –
ODT MEM1_CK[P,N]
100Ω differential at memory
component
–
Notes:
1.Nominal value of V TT for DDR3 interface is 0.75V.
Table 1-4:FPGA On-Chip (OCT) Termination External Resistor Requirements
U1 FPGA Pin
FPGA Pin Number
Board Connection for OCT
ZIO M7No Connect RZQ
K7
100Ω to GROUND
Table 1-5:DDR3 Component Memory Connections U1 FPGA Pin
Schematic Net Name
Memory U42
Pin Number
Pin Name
K2MEM1_A0N3A0K1MEM1_A1P7A1K5MEM1_A2P3A2M6MEM1_A3N2A3H3MEM1_A4P8A4M3MEM1_A5P2A5L4MEM1_A6R8A6K6MEM1_A7R2A7G3MEM1_A8T8A8G1MEM1_A9R3A9J4MEM1_A10L7A10/AP E1MEM1_A11R7A11F1MEM1_A12N7A12/BCN J6MEM1_A13T3NC/A13H5MEM1_A14T7NC/A14J3MEM1_BA0M2BA0J1MEM1_BA1N8BA1H1
MEM1_BA2
M3
BA2
Table 1-3:Termination Resistor Requirements (Cont’d)
Signal Name
Board Termination
On-Die Termination
Chapter 1:SP605 Evaluation Board
See the Winbond Serial Flash Memory Data Sheet for more information. [Ref 16] See the XPS Serial Peripheral Interface Data Sheet (DS570) for more information. [Ref 4]
Figure 1-4:SPI Flash Interface Topology
Table 1-6:SPI x4 Memory Connections U1 FPGA Pin Schematic Net Name SPI MEM U32SPI HDR J17Pin #
Pin Name
Pin #Pin Name
AB2FPGA_PROG_B – –1–T14FPGA_D2_MISO31IO3_HOLD_B 2 –R13FPGA_D1_MISO2_R
9IO2_WP_B
3 – AA3SPI_CS_B
– –4TMS AB20FPGA_MOSI_CSI_B_MISO015DIN 5TDI AA20FPGA_D0_DIN_MISO_MISO1
8IO1_DOUT
6TDO Y20
FPGA_CCLK
16
CLK
7TCK
– – – –
8GND – – – –9VCC3V3
J46.2(1)
SPIX4_CS_B
7
CS_B
–
–
Notes:
1.Not a U1 FPGA pin
U1 FPGA Pin
Schematic Net Name
U25 BPI FLASH Pin Number
Pin Name
N22FLASH_A029A1N20FLASH_A125A2M22FLASH_A224A3M21FLASH_A323A4L19FLASH_A422A5K20FLASH_A521A6H22FLASH_A620A7H21FLASH_A719A8L17FLASH_A88A9K17FLASH_A97A10G22FLASH_A106A11G20FLASH_A115A12K18FLASH_A124A13K19FLASH_A133A14H20FLASH_A142A15J19FLASH_A151A16E22
FLASH_A16
55
A17。