FPGA可编程逻辑器件芯片XC3S400-5FTG256I中文规格书

Chapter 19
Address Maps
The global address map is based around the NoC interconnect and provides a high-level view.The PMC and PS occupy the first 4 GBs of memory space. From a PS perspective, the address maps include:
•Global Address Map
• 4 GB Address Space
Note : Not all devices have the locations listed in these maps. The address maps might vary by device series and device within a series. For a comprehensive list, see the product Versal ACAP data sheets .
Global Address Map
The global address map is based on the NoC and spans 0 to 16 T erabytes (TB) as shown in the following table.
Table 37: Global Address Map (0 to 16 TB)
Destination
Size (GB)Address Range Notes Start End 0 to 4 GB
40x0000_0000_00000x0000_FFFF_FFFF See High-level 4 GB Address Map -
40x0001_0000_00000x0001_FFFF_FFFF reserved AI Engine
0x0002_0000_0000AI Engine memory space M_AXI_FPD
80x0004_0000_00000x0005_FFFF_FFFF High address 0PCIe
80x0006_0000_00000x0007_FFFF_FFFF PCIe region 1DDR
320x0008_0000_00000x000F_FFFF_FFFF DDR channel 0 region 1-
4480x0010_0000_00000x007F_FFFF_FFFF reserved PCIe
2560x0080_0000_00000x00BF_FFFF_FFFF PCIe region 2DDR
2560x00C0_0000_00000x00FF_FFFF_FFFF DDR channel 0 region 2DDR
7340x0100_0000_00000x01B7_7FFF_FFFF DDR channel 0 region 3-
2900x01B7_8000_00000x01FF_FFFF_FFFF reserved AI Engine
10x0200_0000_00000x0200_3FFF_FFFF AI Engine interface tiles -
30710x0200_4000_00000x04FF_FFFF_FFFF reserved DDR_CH{1:3}30720x0500_0000_00000x07FF_FFFF_FFFF DDR channels 1, 2, 3
Section IV: Address Maps and Programming Interfaces
Chapter 19: Address Maps
AM011 (v1.1) November 30, 2020Versal ACAP TRM
The helper data and the encrypted user key must be stored in the same location (i.e., both in eFUSE or both in the boot image). When the device powers on, the RCU examines the boot
image header (the boot image header is authenticated when authentication is enabled). The boot image header contains information on whether the PUF is used, where the encrypted key is stored (eFUSE or boot image), and where the helper data is stored (eFUSE or boot image). The RCU then initializes the PUF, loads the helper data, and regenerates the KEK. This process is called regeneration. After the KEK is regenerated, the RCU can use it to decrypt the user key,which is then used to decrypt the rest of the boot image.
Key Management Summary
The following table provides a key management summary for BBRAM, eFUSE, and boot image.Table 36: Key Management Summary
Features
BBRAM eFUSE Boot Image Programming method •Internal via XilNVM software library •Internal via XilNVM software library
•External via JTAG PUF registration software •Bootgen •Bootgen + PUF registration software
Program verification
CRC32 only CRC32 only N/A Key state during storage
Red or black Red or black Black In-use protections •Temporary storage in registers, not RAM •Transferred in parallel not serial
•DPA countermeasures
User Access to Xilinx Hardware Cryptographic Accelerators
The Versal ACAP flexibility allows for many ways to implement cryptographic functions. The most common is software using the Arm ® cryptographic extensions and custom accelerators
built in the programmable logic (PL). The Versal ACAP built-in cryptographic accelerators can also be used to secure the device configuration. These cryptographic accelerators are available post-boot:
•AES-GCM
•RSA/ECDSA
•SHA3-384
•True Random Number Generator
Section III: Platform Boot, Control, and Status
Chapter 18: Platform Management
AM011 (v1.1) November 30, 2020Versal ACAP TRM
Soft Error Mitigation
The Versal ACAP PMC hardware supports the ability to validate the integrity of the device configuration and perform readback of configuration data (in the background) using the Xilinx soft error mitigation library.
The Xilinx Soft Error Mitigation (XilSEM) library is a pre-configured, pre-verified solution to detect and optionally correct soft errors in the configuration memory of Versal ACAPs. A soft error is caused by ionizing radiation and is extremely uncommon in commercial terrestrial operating environments. While a soft error does not damage the device, it carries a small statistical possibility of transiently altering the device behavior.
The XilSEM library does not prevent soft errors; however, it provides a method to better manage the possible system-level effect. Proper management of a soft error can increase reliability and availability, and reduce system maintenance and downtime. In most applications, soft errors can be ignored. In applications where a soft error cannot be ignored, see the Versal ACAP System Software Developers Guide (UG1304) for additional information about the XilSEM library prior to configuring it for use through the CIPS IP core.
Section III: Platform Boot, Control, and Status
Chapter 18: Platform Management
AM011 (v1.1) November 30, 2020Versal ACAP TRM。