计算机组成与系统结构
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m −1
m−2
∑
i=0
2i ai
+
∑
n−2 i=0
2 ai = −2
m−2 i = n −1
+
m−2
∑
i=0
2i ai
2 n −1 + 1+
∑
2 i a i = 2 m −1
m−2
∑
n−2 i=0
2 +
i
m−2 i = n −1
∑
2 ai = 1 +
i
∑
2 = 1+
i
i=0
∑
n−2 i=0
2 +
i
m−2 i = n −1
• 3 n-bit registers:Q,M,A; one 1-bit register:C;initially set A,C to 0 • Control logic reads the bits of the multiplier one at a time • If Q0=1,then the multiplicand is added to the A and the results is stored in the A • Then, all of the bits of C,A,and Q are shifted right one bit, Q0 is lost • If Q0=0,just right shift • The resulting 2n-bit product is in the A and Q
– Controller,registers, memory,I/O
• Handles integers, floating point (real) numbers • May be separate FPU (maths co-processor) • May be on chip separate FPU
– Need to consider both sign and magnitude in arithmetic – Two representations of zero (+0 and -0)
• Rarely used
Two’s Complement Representation ’
• • • • • • • +3 = 00000011 +2 = 00000010 +1 = 00000001 +0 = 00000000 A = − 2 -1 = 11111111 -2 = 11111110 -3 = 11111101
Division of Unsigned Binary Integers
00001101 1011 10010011 1011 001110 Partial 1011 Remainders 001111 1011 100 Divisor Dividend
Remainder
Flowchart for Unsigned Binary Division
– Overflow Rule:如果两个正数或两个负数相加，当 且仅当结果的符号位变反才出现上溢
• Subtraction Rule:Take complement of subtrahend and add to minuend
– i.e. a - b = a + (-b)
• No subtracter in a computer • So we only need addition and complement circuits
2 ai =
i
∑
n−2 i=0
2 ai +
m−2 i = n −1
∑
∑
2i ai = 0,
ai = 0,
i ∈ [ n − 1, m − 2 ]
Proof （2） ）
若A是负数，a n-1=1扩展前后的数必须相等，有：
A = − 2 n −1 a n −1 + − 2
n −1
∑
i
n−2 i=0
2 i a i = − 2 m −1 a m −1 +
2 i (a i + a i ) + 1
= − 2 n −1 +
∑
n−2 i= 0
2i + 1 = 0
Addition & Subtraction
•
Example for Subtraction
Comment on Addition and Subtraction
• Normal binary addition • Monitor sign bit for overflow
Example from Fig.8.7
Flowchart for Unsigned Binary Multiplication
Multiplying Negative Numbers
• Straightforward multiplication does not work!
• • • • • 1001 x 0011 1001 1001 11011 (-7) (3)
∑
2i
m−2 i = n −1
∑
2i ai =
m−2 i = n −1
∑
2i,
a i = 1, i ∈ [ n − 1, m − 2 ]
Negation(整数取负 整数取负) 整数取负
• Sign-magnitude: invert the sign bit • Complement: 取反+1
– E.g. – – – – – – – 18= 00010010 11101101 + 1 11101110 -18=11101110 00010001 + 1 00010010
1001 A=A-M 1001 shift right
1001 shift right 1001 A=A+M 1001 shift right 1001 shift right
Example of Booth’s Algorithm (3) ’
Division
• More complex than multiplication • Based on long division
(27) (-5)
• Solution 1
– Convert to positive if required – Multiply as above – If signs were different, negate answer
• Solution 2
– Booth’s algorithm
Booth’s Algorithm ’
• 一个n位序列，可表示-2n-1这个负数，但不能表 示2n-1这个正数
proof
•
A = − 2 n −1 a n −1 +
∑
n−2 i= 0
2 iai
B = −2 A + B = −2
n −1
n −1
a
n −1
+
n −1
∑
n−2 i=0
2iai + 1
( a n −1 + a
)+
∑
n−2 i= 0
• 16 bit 2s complement
+32767 = 011111111 11111111 = 215 - 1 -32768 = 100000000 00000000 = -215
Conversion Between Different Bit Lengths
• • • • • • • Positive number pack with leading zeros +18 = 00010010 +18 = 00000000 00010010 Negative numbers pack with leading ones -18 = 11101110 -18 = 11111111 11101110 补码整数的扩展规则：左填充符号位 左填充符号位
Multiplication--Pencil-and-paper
• 1011 Multiplicand (11 dec) • x 1101 Multiplier (13 dec) • 1011 Partial products • 0000 Note: if multiplier bit is 1 copy • 1011 multiplicand (place value) • 1011 otherwise zero • 10001111 Product (143 dec) • Note: need double length result
Negation Special Case 1
• • • • • • 0= 00000000 Bitwise not 11111111 Add 1 to +1 Result 1 00000000 Overflow is ignored, so: 0=0√
Negation Special Case 2
William Stallings Computer Organization and Architecture
Chapter 8 Computer Arithmetic
Arithmetic & Logic Unit
• Does the calculations • Everything else in the computer is there to service this unit
Multiplication--computer
• More efficient • Addition on partial product rather than waiting until the end
– No need for storage all the partial products,fewer registers are needed – Save some time
• • • • -128 = 10000000 bitwise not 01111111 Add 1 to +1 Result 10000000 (overflow)
Range of Numbers
• 8 bit 2’s complement
+127 = 01111111 = 27 -1 -128 = 10000000（补码） = -27
Proof （1） ）
• 对于数A的二进制序列： an-1an-2….a1a0
A = − 2 n −1 a n −1 +
n−2 i= 0
∑
2 iai
• 若A是正数，a n-1=0, 有：
A =
∑
n−2 i= 0
2 iai =
i
m−2
∑
i= 0
2i ai 2 iai
∑
m−2 i = n −1
n−2 i=0
A =
∑
n −1 i= 0
2 ia
i
Sign-Magnitude Representation
• • • • • • Left most bit is sign bit 0 means positive 1 means negative +18 = 00010010 -18 = 10010010 Problems
n −1
a n −1 +
∑
n−2 i=0
2 iai
• 正数的补码是原码，负数的补码是对原码的求 求 反+1
Geometric Depiction of Twos Complement Integers
Benefits
• One representation of zero • Arithmetic works easily
Example of Booth’s Algorithm (1) ’
Example of Booth’s Algorithm (2) ’
• A Q Q-1
0 0 1 1 1 0 0
M
1001 initial values
0000 0011 0111 0011 0011 1001 0001 1010 1101 1110 1100 1100 0110 1011
• For each 1 on the multiplier,an addition and a shift operation are required,but for each 0, only a shift is required
Block Diagram of Multiplier
Specification for fig8.6a
ALU Inputs and Outputs
Integer Representation
• Only have 0 & 1 to represent everything • Positive numbers stored in binary
– e.g. 41=00101001
• No minus sign • No period(.) • n-bit binary digits an-1an-2….a1a0 denotes an unsigned integer A
m−2
∑
i=0
2i ai
+
∑
n−2 i=0
2 ai = −2
m−2 i = n −1
+
m−2
∑
i=0
2i ai
2 n −1 + 1+
∑
2 i a i = 2 m −1
m−2
∑
n−2 i=0
2 +
i
m−2 i = n −1
∑
2 ai = 1 +
i
∑
2 = 1+
i
i=0
∑
n−2 i=0
2 +
i
m−2 i = n −1
• 3 n-bit registers:Q,M,A; one 1-bit register:C;initially set A,C to 0 • Control logic reads the bits of the multiplier one at a time • If Q0=1,then the multiplicand is added to the A and the results is stored in the A • Then, all of the bits of C,A,and Q are shifted right one bit, Q0 is lost • If Q0=0,just right shift • The resulting 2n-bit product is in the A and Q
– Controller,registers, memory,I/O
• Handles integers, floating point (real) numbers • May be separate FPU (maths co-processor) • May be on chip separate FPU
– Need to consider both sign and magnitude in arithmetic – Two representations of zero (+0 and -0)
• Rarely used
Two’s Complement Representation ’
• • • • • • • +3 = 00000011 +2 = 00000010 +1 = 00000001 +0 = 00000000 A = − 2 -1 = 11111111 -2 = 11111110 -3 = 11111101
Division of Unsigned Binary Integers
00001101 1011 10010011 1011 001110 Partial 1011 Remainders 001111 1011 100 Divisor Dividend
Remainder
Flowchart for Unsigned Binary Division
– Overflow Rule:如果两个正数或两个负数相加，当 且仅当结果的符号位变反才出现上溢
• Subtraction Rule:Take complement of subtrahend and add to minuend
– i.e. a - b = a + (-b)
• No subtracter in a computer • So we only need addition and complement circuits
2 ai =
i
∑
n−2 i=0
2 ai +
m−2 i = n −1
∑
∑
2i ai = 0,
ai = 0,
i ∈ [ n − 1, m − 2 ]
Proof （2） ）
若A是负数，a n-1=1扩展前后的数必须相等，有：
A = − 2 n −1 a n −1 + − 2
n −1
∑
i
n−2 i=0
2 i a i = − 2 m −1 a m −1 +
2 i (a i + a i ) + 1
= − 2 n −1 +
∑
n−2 i= 0
2i + 1 = 0
Addition & Subtraction
•
Example for Subtraction
Comment on Addition and Subtraction
• Normal binary addition • Monitor sign bit for overflow
Example from Fig.8.7
Flowchart for Unsigned Binary Multiplication
Multiplying Negative Numbers
• Straightforward multiplication does not work!
• • • • • 1001 x 0011 1001 1001 11011 (-7) (3)
∑
2i
m−2 i = n −1
∑
2i ai =
m−2 i = n −1
∑
2i,
a i = 1, i ∈ [ n − 1, m − 2 ]
Negation(整数取负 整数取负) 整数取负
• Sign-magnitude: invert the sign bit • Complement: 取反+1
– E.g. – – – – – – – 18= 00010010 11101101 + 1 11101110 -18=11101110 00010001 + 1 00010010
1001 A=A-M 1001 shift right
1001 shift right 1001 A=A+M 1001 shift right 1001 shift right
Example of Booth’s Algorithm (3) ’
Division
• More complex than multiplication • Based on long division
(27) (-5)
• Solution 1
– Convert to positive if required – Multiply as above – If signs were different, negate answer
• Solution 2
– Booth’s algorithm
Booth’s Algorithm ’
• 一个n位序列，可表示-2n-1这个负数，但不能表 示2n-1这个正数
proof
•
A = − 2 n −1 a n −1 +
∑
n−2 i= 0
2 iai
B = −2 A + B = −2
n −1
n −1
a
n −1
+
n −1
∑
n−2 i=0
2iai + 1
( a n −1 + a
)+
∑
n−2 i= 0
• 16 bit 2s complement
+32767 = 011111111 11111111 = 215 - 1 -32768 = 100000000 00000000 = -215
Conversion Between Different Bit Lengths
• • • • • • • Positive number pack with leading zeros +18 = 00010010 +18 = 00000000 00010010 Negative numbers pack with leading ones -18 = 11101110 -18 = 11111111 11101110 补码整数的扩展规则：左填充符号位 左填充符号位
Multiplication--Pencil-and-paper
• 1011 Multiplicand (11 dec) • x 1101 Multiplier (13 dec) • 1011 Partial products • 0000 Note: if multiplier bit is 1 copy • 1011 multiplicand (place value) • 1011 otherwise zero • 10001111 Product (143 dec) • Note: need double length result
Negation Special Case 1
• • • • • • 0= 00000000 Bitwise not 11111111 Add 1 to +1 Result 1 00000000 Overflow is ignored, so: 0=0√
Negation Special Case 2
William Stallings Computer Organization and Architecture
Chapter 8 Computer Arithmetic
Arithmetic & Logic Unit
• Does the calculations • Everything else in the computer is there to service this unit
Multiplication--computer
• More efficient • Addition on partial product rather than waiting until the end
– No need for storage all the partial products,fewer registers are needed – Save some time
• • • • -128 = 10000000 bitwise not 01111111 Add 1 to +1 Result 10000000 (overflow)
Range of Numbers
• 8 bit 2’s complement
+127 = 01111111 = 27 -1 -128 = 10000000（补码） = -27
Proof （1） ）
• 对于数A的二进制序列： an-1an-2….a1a0
A = − 2 n −1 a n −1 +
n−2 i= 0
∑
2 iai
• 若A是正数，a n-1=0, 有：
A =
∑
n−2 i= 0
2 iai =
i
m−2
∑
i= 0
2i ai 2 iai
∑
m−2 i = n −1
n−2 i=0
A =
∑
n −1 i= 0
2 ia
i
Sign-Magnitude Representation
• • • • • • Left most bit is sign bit 0 means positive 1 means negative +18 = 00010010 -18 = 10010010 Problems
n −1
a n −1 +
∑
n−2 i=0
2 iai
• 正数的补码是原码，负数的补码是对原码的求 求 反+1
Geometric Depiction of Twos Complement Integers
Benefits
• One representation of zero • Arithmetic works easily
Example of Booth’s Algorithm (1) ’
Example of Booth’s Algorithm (2) ’
• A Q Q-1
0 0 1 1 1 0 0
M
1001 initial values
0000 0011 0111 0011 0011 1001 0001 1010 1101 1110 1100 1100 0110 1011
• For each 1 on the multiplier,an addition and a shift operation are required,but for each 0, only a shift is required
Block Diagram of Multiplier
Specification for fig8.6a
ALU Inputs and Outputs
Integer Representation
• Only have 0 & 1 to represent everything • Positive numbers stored in binary
– e.g. 41=00101001
• No minus sign • No period(.) • n-bit binary digits an-1an-2….a1a0 denotes an unsigned integer A