MEMORY存储芯片MT45W8MW16BGX-708WT中文规格书

Figure 91: Self Refresh Entry/Exit Timing with CAL Mode
&.BW
&.BF
&RPPDQG $''5
Z R &6BQ &6BQ
&.(
'RQ¶W &DUH
Notes: 1.t CAL = 3n CK, t CPDED = 4n CK, t CKSRE/t CKSRE_PAR = 8n CK, t CKSRX = 8n CK, t XS_FAST =
t REFC4 (MIN) + 10ns.
2.CS_n = HIGH, ACT_n = "Don't Care," RAS_n/A16 = "Don't Care," CAS_n/A15 = "Don't
Care," WE_n/A14 = "Don't Care."
3.Only MRS (limited to those described in the SELF REFRESH Operations section), ZQCS, or ZQCL commands are allowed.
4.The figure only displays t XS_FAST timing, but t CAL must also be added to any t XS and t XSDLL associated commands during CAL mode.
Self Refresh Abort
The exit timing from self refresh exit to the first valid command not requiring a locked DLL is t XS. The value of t XS is (t RFC1 + 10ns). This delay allows any refreshes started by the device time to complete. t RFC continues to grow with higher density devices, so t XS will grow as well. An MRS bit enables the self refresh abort mode. If the bit is disabled,the controller uses t XS timings (location MR4, bit 9). If the bit is enabled, the device aborts any ongoing refresh and does not increment the refresh counter. The controller can issue a valid command not requiring a locked DLL after a delay of t XS_ABORT.
Upon exit from self refresh, the device requires a minimum of one extra REFRESH com-mand before it is put back into self refresh mode. This requirement remains the same irrespective of the setting of the MRS bit for self refresh abort.
8Gb: x4, x8, x16 DDR4 SDRAM SELF REFRESH Operation
5.The ODT pin must be driven LOW during MBIST PPR to satisfy DODTLoff from time Tb0 until Tc2. The DRAM may or may not provide RTT_PARK termination
during MBIST-PPR regardless of whether RTT_PARK is enabled in MR5.
Figure 81: MBIST -PPR Sequence
7 7 7D 7D 7E 7E 7E Table 47: MPR Page3 Configuration for MBIST -PPR
Notes: 1.MPR bits are cleared either by a power-up sequence or re-initialization by RESET_n sig-
nal
8Gb: x4, x8, x16 DDR4 SDRAM MBIST -PPR
pability (MR2[6] = 0 and MR2 [7] = 1) or enable the optional auto self refresh mode
(MR2 [6] = 1 and MR2 [7] = 1).
Electrical Characteristics – AC and DC Operating Conditions Supply Operating Conditions
Table 79: Recommended Supply Operating Conditions
Notes: 1.Under all conditions V DDQ must be less than or equal to V DD .
2.V DDQ tracks with V DD . AC parameters are measured with V DD and V DDQ tied together.
3.V DD slew rate between 300mV and 80% of V DD,min shall be between 0.004 V/ms and 600V/ms, 20 MHz band-limited measurement.
4.V DD ramp time from 300mV to V DD,min shall be no longer than 200ms.
5. A stable valid V DD level is a set DC level (0 Hz to 250 KHz) and must be no less than
V DD,min and no greater than V DD,max . If the set DC level is altered anytime after initializa-tion, the DLL reset and calibrations must be performed again after the new set DC level
is final. AC noise of ±60mV (greater than 250 KHz) is allowed on V DD provided the noise
doesn't alter V DD to less than V DD,min or greater than V
DD,max .
6. A stable valid V DDQ level is a set DC level (0 Hz to 250 KHz) and must be no less than
V DDQ,min and no greater than V DDQ,max . If the set DC level is altered anytime after initial-ization, the DLL reset and calibrations must be performed again after the new set DC
level is final. AC noise of ±60mV (greater than 250 KHz) is allowed on V DDQ provided the noise doesn't alter V DDQ to less than V DDQ,min or greater than V DDQ,max .
7. A stable valid V PP level is a set DC level (0 Hz to 250 KHz) and must be no less than
V PP ,min and no greater than V PP ,max . If the set DC level is altered anytime after initializa-
tion, the DLL reset and calibrations must be performed again after the new set DC level
is final. AC noise of ±120mV (greater than 250 KHz) is allowed on V PP provided the noise doesn't alter V PP to less than V PP ,min or greater than V PP ,max .
Table 80: V DD Slew Rate
Notes: 1.Measurement made between 300mV and 80% V DD (minimum level).
2.The DC bandwidth is limited to 20 MHz.
3.Maximum time to ramp V DD from 300 mV to V DD minimum.8Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Operating Conditions。