用verilog编写的8位扩展超前进位加法器代码

= Gi + Pi * Gi-1 + Pi * Pi-1 * Gi-2 + ... + Pi * Pi-1 * ... * P1 * G0
+ Pi * Pi-1 * ... * P1 * P0 * C0
Gij = Gi + Pi * Gi-1 + Pi * Pi-1 * Gi-2 + ... + Pi * Pi-1 * ... * Pj+1 * Gj
Pij = Pi * Pi-1 * ... * Pj+1 * Pj;
Gi,i = Gi;
Pi,i = Pi;
***************************************************************************** */
module adder_8bits( s, co, a, b, ci );
assign c[ 5 ] = g04_04 | p04_04 & c[ 4 ];
assign c[ 6 ] = g05_04 | p05_04 & c[ 4 ];
assign c[ 7 ] = g06_06 | p06_06 & c[ 6 ];
assign c[ 8 ] = g07_00 | p07_00 & c[ 0 ];
8位扩展超前进位加法器
/* *****************************************************************************
Ci+1 = Ai * Bi + Bi * Ci + Ci * Ai
= Ai * Bi + ( Ai + Bi ) * Ci
Gi = Ai * Bi
Pi = Ai + Bi
Ci+1 = Gi + Pi * Ci
= Gi + Pi * ( Gi-1 + Pi-1 * Ci-1 )
= Gi + Pi * ( Gi-1 + Pi-1 * ( Gi-2 + Pi-2 * Ci-2 ) )
.
.
.
= Gi + Pi * ( Gi-1 + Pi-1 * ( Gi-2 + Pi-2 * ( ... ( G0 + P0 * C0 ) ... ) ) )
assign p07_06 = p[ 7 ] & p[ 6 ];
assign g07_04 = g07_06 | p07_06 & g05_04;
assign p07_04 = p07_06 & p05ቤተ መጻሕፍቲ ባይዱ04;
assign g07_00 = g07_04 | p07_04 & g03_00;
assign p07_00 = p07_04 & p03_00;
output [ 7 : 0 ] s;
output co;
input [ 7 : 0 ] a;
input [ 7 : 0 ] b;
input ci;
wire [ 7 : 0 ] g;
wire [ 7 : 0 ] p;
wire [ 8 : 0 ] c;
assign g = a & b;
assign p = a | b;
assign co = c[ 8 ];
assign s = a ^ b ^ c[ 7 : 0 ];
endmodule
module test;
reg clk;
reg [ 7 : 0 ] a;
reg [ 7 : 0 ] b;
reg ci;
wire [ 7 : 0 ] s;
initial begin
clk = 0;
/* *****************************************************************************
Ci+1 = Ai * Bi + Bi * Ci + Ci * Ai
ci = 1;
a = 8'b0000_0000;
b = 8'b0000_0000;
#10000 $stop;
end
always #5 clk <= ~clk;
always @( posedge clk ) begin
a <= a + 8'b0000_0001;
end
always @( negedge clk ) begin
assign g03_00 = g03_02 | p03_02 & g01_00;
assign p03_00 = p03_02 & p01_00;
assign g05_04 = g[ 5 ] | p[ 5 ] & g[ 4 ];
assign p05_04 = p[ 5 ] & p[ 4 ];
assign g07_06 = g[ 7 ] | p[ 7 ] & g[ 6 ];
assign p06_06 = p[ 6 ];
assign g01_00 = g[ 1 ] | p[ 1 ] & g[ 0 ];
assign p01_00 = p[ 1 ] & p[ 0 ];
assign g03_02 = g[ 3 ] | p[ 3 ] & g[ 2 ];
assign p03_02 = p[ 3 ] & p[ 2 ];
b <= b + 8'b0000_0001;
end
adder_8bits u( .s( s ), .co( co ), .a( a ), .b( b ), .ci( ci ) );
endmodule
32 bits adder上一篇下一篇
发布者：syinspire | 发表时间：2007-01-25 21:37 | 标签：32 bits adder
assign g00_00 = g[ 0 ];
assign p00_00 = p[ 0 ];
assign g02_02 = g[ 2 ];
assign p02_02 = p[ 2 ];
assign g04_04 = g[ 4 ];
assign p04_04 = p[ 4 ];
assign g06_06 = g[ 6 ];
assign c[ 0 ] = ci;
assign c[ 1 ] = g00_00 | p00_00 & c[ 0 ];
assign c[ 2 ] = g01_00 | p01_00 & c[ 0 ];
assign c[ 3 ] = g02_02 | p02_02 & c[ 2 ];
assign c[ 4 ] = g03_00 | p03_00 & c[ 0 ];