2015__SiC双脉冲测试IEEE
SiC基反向开关晶体管RSD关键工艺概述
SiC基反向开关晶体管RSD关键工艺概述梁琳;吴文杰;刘程;潘铭【摘要】本文首次概述了采用宽禁带半导体材料4H-SiC制备脉冲功率开关反向开关晶体管(RSD)所涉及到的关键工艺.包括选择性刻蚀、选择性掺杂、欧姆电极制备以及台面终端造型等在内的多步主要工艺均与Si基RSD完全不同,采用氟基气体感应耦合等离子体(ICP)刻蚀得到了合适的刻蚀速率、表面粗糙度及形貌,采用多次氮离子注入及高温退火完成选择性掺杂,采用Ni/Ti/Al多层金属配合适当退火温度完成欧姆电极制备,采用机械切割斜角完成台面终端造型,最终得到了合理的器件正反向阻断特性.【期刊名称】《电工电能新技术》【年(卷),期】2016(035)004【总页数】5页(P56-60)【关键词】SiC RSD;脉冲功率开关;工艺;ICP刻蚀;离子注入;台面终端造型【作者】梁琳;吴文杰;刘程;潘铭【作者单位】华中科技大学光学与电子信息学院,湖北武汉430074;华中科技大学光学与电子信息学院,湖北武汉430074;华中科技大学光学与电子信息学院,湖北武汉430074;华中科技大学光学与电子信息学院,湖北武汉430074【正文语种】中文【中图分类】TN335随着半导体开关性能的不断提高,近年来脉冲功率开关半导体化的趋势日益明显[1]。
常见的功率器件包括功率MOSFET、IGBT、IGCT、SITh等均可应用于脉冲功率领域[2],而基于反向可控等离子层开通的反向开关晶体管 (Reversely Switched Dynistor,RSD)更是直接针对高功率脉冲工况提出,具有兼顾高电压、大电流和高di/dt耐量的理想特性[3-5]。
我们曾经采用3吋Si基RSD堆体在12kV放电电压下成功通过173kA峰值电流[6],采用降低单只器件阻断电压、引入缓冲层以及两步法开通等多种方式从结构及应用层面改善器件特性[7]。
而要在器件的阻断特性和开关特性间取得更好的折中,应考虑采用新型材料。
双脉冲测试的测试原理
双脉冲测试的测试原理
双脉冲测试是一种用于测量电路响应的测试方法。
它基于两个短脉冲的信号,其中第一个脉冲用于激发电路,第二个脉冲用于检测电路的响应。
在双脉冲测试中,第一个脉冲通常称为激励脉冲,它被发送到被测试的电路中。
这个脉冲可以是正弦波、方波或任何其他类型的波形。
激励脉冲的持续时间通常很短,一般在几纳秒到几微秒之间。
在电路受到激励脉冲后,它将开始响应。
这个响应通常是一个信号或波形,可以通过第二个脉冲进行测量。
第二个脉冲通常称为检测脉冲,它在电路响应后发送。
通过测量检测脉冲和激励脉冲之间的时间差,可以计算出电路的响应时间。
这种测试可以用于测量电路中的信号延迟、传输速度、反射和干扰等。
需要注意的是,双脉冲测试需要高精度的测试设备和校准程序,以确保测试结果的准确性。
同时,测试过程也需要避免干扰和误差,以确保测试结果的可靠性。
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sic mosfet双脉冲测试原理
双脉冲测试是广泛应用于MOSFET和IGBT等功率开关元件特性评估的一种测试方法。
在“通过双脉冲测试评估MOSFET的反向恢复特性”中,双脉冲测试原理如下:
首先给SiC MOSFET(S2)栅极发送一个宽驱动脉冲,S2开通,此时电感L电流开始线性上升,该过程用来建立测试用电感电流。
在实际测量时可以根据具体侧测试电流指标调节脉冲的宽度。
然后,上管两端并接一个电感,就可以测试出下管的特性以及上管的反向二极管特性。
最后,在第一个脉冲信号来临之前,电感电流为0,SiC MOSFET阻断并承受直流母线电压。
直到t1时刻,器件开始导通,电感电流按照式规律变化,即随时间按线性规律增加。
式中VDS(on)—SiC MOSFET导通压降;t2时刻,开关管开始关断并换流至二极管D1,流经开关管的电流变为0,负载电感的电流经过二极管D1续流。
由于续流阶段电流回路存在一定的电阻,电流将会有一定程度的减小,但此阶段极短,而且寄生电阻量很小,因此电流减小量可以忽略,近似认为t2和t3时刻电流相等。
t3时刻,第二个脉冲信号使开关管开通,续流二极管开始关断,电感电流换流至开关管并继续按照线性规律增加。
t4时刻,开关管再次关断,电流从开关管换流至续流二极管D1,双脉冲测试结束。
SiC MOSFET SPICE模型的建立与仿真分析
SiC MOSFET SPICE模型的建立与仿真分析叶雪荣;张开新;翟国富;丁新【摘要】SiC MOSFET与Si MOSFET相比,具有耐高压、耐高温、频率快等诸多优点,得到了越来越广泛的应用。
SPICE模型作为含SiC MOSFET电路仿真分析的基础,对其进行研究十分必要。
以SPICE 1模型为例,介绍了基于LTspice的SiC MOSFET建模流程,通过MOS、体二极管、PCB寄生参数等建模过程,完成了SiC MOSFET SPICE 1模型的建立,并通过仿真分析验证了所建立模型的正确性。
【期刊名称】《电器与能效管理技术》【年(卷),期】2019(000)003【总页数】6页(P25-29)【关键词】SiC MOSFET;SPICE 1模型;仿真;LTspice【作者】叶雪荣;张开新;翟国富;丁新【作者单位】[1]哈尔滨工业大学电器与电子可靠性研究所,黑龙江哈尔滨150001;[1]哈尔滨工业大学电器与电子可靠性研究所,黑龙江哈尔滨150001;[1]哈尔滨工业大学电器与电子可靠性研究所,黑龙江哈尔滨150001;[2]航天安通电子科技有限公司,天津300384;【正文语种】中文【中图分类】TM460 引言作为电力电子变换装置系统的核心组件、电力电子变换技术的基础,半导体技术的发展一直是推动电力电子技术发展的关键[1]。
随着SiC材料的发展,其在高压[2-3]、高温[4-5]、大功率[6]、高频[7-8]等应用场合下具有明显的优势,越来越受到研究者的青睐。
国内外学者对于SiC MOSFET建模的方法做了大量研究。
国外学者对于模型的研究主要分为物理建模和等效电路建模,如文献[9]基于SiC器件的物理特性、物理结构提出一种模型,但其不适用于工程中的应用和分析。
部分文献通过改进传统的Si MOSFET模型进行建模,文献[10]提出了一种变温度参数建模方法,非常适用于高压SiC MOSFET。
此方法对SiC MOSFET的建模具有一定的指导意义,已得到业界普遍的认可。
面向6G的高速太赫兹无线通信系统与关键技术验证
doi:10.3969/j.issn.1003-3114.2024.01.004引用格式:董博宇,冯叶青,李国强,等.面向6G的高速太赫兹无线通信系统与关键技术验证[J].无线电通信技术,2024,50(1):34-40.[DONGBoyu,FENGYeqing,LIGuoqiang,etal.HighSpeedTerahertzWirelessCommunicationSystemandKeyTech nologyVerificationfor6G[J].RadioCommunicationsTechnology,2024,50(1):34-40.]面向6G的高速太赫兹无线通信系统与关键技术验证董博宇1,冯叶青2,李国强1,贾俊连1,张俊文1 ,付杰尉2,迟 楠1,朱伏生2(1.复旦大学电磁波信息科学教育部重点实验室,上海200433;2.广东省新一代通信与网络创新研究院,广东广州510663)摘 要:太赫兹通信以其可提供更高速、更大容量和更安全的数据传输的独特优势,在未来6G中成为重要的关键技术之一。
基于固态电子的太赫兹通信系统存在带宽受限、频谱响应不平坦等问题,需要先进的信号形式结合灵活高效的处理方法来提升系统性能。
搭建了基于固态电子的G波段太赫兹无线通信系统,通过采用比特-功率加载的离散多音(BitandPowerLoading DiscreteMultitone,BPL DM)调制技术,实现了对系统频谱资源的有效利用;通过对通信速率的灵活调整、自适应削波和基于三阶多项式的后均衡技术,解决了峰值功率约束带来的挑战,提升了整体传输性能,实现了在195GHz中心频率下,单通道130Gbit/s的通信线路速率。
基于以上技术,为进一步提升系统容量,搭建了4×4的多输入多输出(Multiple InputMultiple Output,MIMO)太赫兹通信系统,总线路速率超过399Gbit/s。
抑制SiC MOSFET瞬态电压尖峰的改进驱动电路设计
创新前沿科技创新与应用Technology Innovation and Application2021年14期抑制SiC MOSFET 瞬态电压尖峰的改进驱动电路设计王文月1,牛萍娟2(1.天津工业大学电气工程与自动化学院,天津300000;2.天津工业大学电子与信息工程学院,天津300000)近些年,随着电力电子技术的发展,航空、电动汽车、新能源发电及石油钻井等领域对电力电子变换器提出更高的要求,即实现高压、高频、高功率密度[1]。
因此以SiC MOSFET 为代表的宽禁带半导体器件因其高开关速度、高开关频率及高热导率等[2-5],受到人们广泛关注。
然而随着SiC MOSFET 开关频率及速度提高,电力电子变换器受电路中寄生参数影响加剧,关断瞬态电压尖峰更为严重。
瞬态电压的尖峰不仅危及开关管的安全,也会降低电力电子变换器的功率密度,加剧电力电子变换器电磁干扰[6-8]。
目前现有抑制电压尖峰方法大多牺牲了开关速度,从而影响SiC MOSFET 开关损耗及变换器效率等。
因此,本文在分析电压尖峰产生原理基础上,在注入栅极电流抑制电压尖峰前提下,提出了一种在栅源极增加有源箝位电路的改进驱动方法,改进后的驱动电路具有抑制尖峰效果好、开关损耗较小、控制方法简单特点。
本文首先分析瞬态电压尖峰产生原理,其次分析了改进驱动电路工作原理,最后在双脉冲测试平台验证了该改进驱动电路的实用性。
1SiC MOSFET 瞬态电压尖峰产生原理为了分析SiC MOSFET 瞬态电压尖峰产生原理,采用如图1所示测试电路,图中:V dc 直流母线电压,R 驱动电阻,C 支撑电容,L 负载电感,SiC MOSFET 及SiC 二极管D 1,考虑SiC MOSFET 关键寄生参数为:栅极驱动电阻R 1,栅极引脚封装电感L g ,源极引脚封装电感L s ,漏极引脚封装电感L d 。
为了方便分析,L g 、L s 与L d 分别为SiCMOSFET 各引脚封装电感与相连接引线电感之和。
SiC MOSFET 双脉冲测试装置
SiC MOSFET 双脉冲测试装置2011 年 2 月SiC MOSFET 双脉冲测试装置Bob Callanan ,Cree IncW R -A N 09,R E V -C M O S F E T双脉冲测试装置 - 2011 年 2 月本文描述了一种双脉冲测试装置,它适合用于确定碳化硅 (SiC) MOSFET 的特征。
该装置是一个课本大小的双脉冲测试器,它将所有关键元件都布置在单块印刷电路板上,以提供可重复的测量。
测试装置的照片如图 1 所示。
测试器的原理图如图 2 所示。
该测试装置包含用于 MOSFET 的测试座 (J6)、栅极驱动器 (U1)、电容组 (C1-C9)、续流二极管 (D1),以及一个紧密集成的双级电流互感器 (T1)。
可以通过 BNC 接头 (J7 & J10) 监测 VDS 和 VGS 。
这些接头的目的不是为了使用同轴电缆,而是使用同轴电缆来探测转接器,以免需要探头接地线夹。
这样,就避免了接地线夹电线的寄生电感妨碍电压测量的情况。
漏极电流用一个双级电流互感器来测量,该互感器包含一个小的 1:10 铁氧体第一级互感器,以及一个 Pearson Electronics 2878 型电流传感器用于第二级。
得到的比例因子是 1V=100A 。
使用九个聚丙烯薄膜电容器 (C1-C9),为测试器提供低电感电压源。
VCC 、GND 和 –VEE 是栅极驱动器的输入电压。
VCC 设置栅极脉冲高电压的值,VEE 设置栅极脉冲低电压的值。
VCC 和 –VEE 之间的最大电压为 30V 。
驱动脉冲应用于脉冲发生器输入 BNC 接头。
建议使用 +10 到 +12V 的脉冲来导通栅极脉冲。
此输入端接到 50 Ω 电阻,以匹配 50 Ω 同轴电缆。
端接电阻器 (R3 和 R4) 具有最大 0.5 W 的总额定功率,因此必须适当地限制输入脉冲占空系数 (~10%),以避免它们烧掉。
电感器跨“低负载” (LOAD LOW) 和“高负载” (LOAD HIGH) 端子连接。
SiC-MOSFET开关模块RC缓冲吸收电路的参数优化设计
总第470期2021年第2期Control and Information Technology61SiC-MOSFET开关模块RC缓冲吸收电路的参数优化设计施洪亮,罗德伟,王佳佳,谭渺,杨奎,周帅,饶沛南(株洲中车时代电气股份有限公司,湖南株洲412001)摘要:针对SiC-MOSFET开关模块开关速度快、开关电压尖峰高、缓冲吸收电路参数难以确定的问题,文章提出一种RC缓冲吸收电路参数快速优化设计方法。
该方法基于包含寄生参数的电路分析模型并利用双脉冲电路,通过不同的缓冲吸收电路参数曲线来确定电路参数的优化区间并选取最优的缓冲吸收电路参数。
仿真和实验结果表明,采用该方法能够针对SiC-MOSFET开关模块关断尖峰电压和缓冲吸收电路总损耗快速设计出满足要求的电路参数,使关断尖峰电压和缓冲吸收电路损耗处于系统优化的最佳区间。
关键词:SiC;RC缓冲吸收;双脉冲;寄生参数;电压尖峰;优化设计中图分类号:TN35文献标识码:A文章编号:2096-5427(2021)02-0061-06doi:10.13889/j.issn.2096-5427.2021.02.010Optimized Parameter Design of RC Snubber Circuit forSiC-MOSFET ModuleSHI Hongliang,LUO Dewei,WANG Jiajia,TAN Miao,YANG Kui,ZHOU Shuai,RAO Peinan(Zhuzhou CRRC Times Electric Co.,Ltd.,Zhuzhou,Hunan412001,China)Abstract:This paper proposes a fast optimization design method for RC snubber circuit parameters in order to solve the high switching voltage spikes of SiC while high switching and difficulties in snubber circuit parameters.This method is based on the circuit analysis model of double-pulse circuit including parasitic parameters.Different snubber parameter curves are used to determine the optimal interval of circuit parameters and select the best snubber parameters.The simulation and experimental results show that the method can quickly optimize the design of the circuit parameters that meet the requirements for the turn-off voltage spike of SiC switching devices and the total loss of the snubber circuit,and the spike voltage and the loss of the snubber circuits are in the optimal range for system optimization.Keywords:SiC;RC snubber;double pulse;parasitic parameters;spike voltage;optimal design0引言SiOMOSFET开关模块(简称“SiC模块”)由于其高开关速度、高耐压、低损耗的特点特别适合于高频、大功率的应用场合。
双脉冲测试下的半导体开关特性研究
一、引言1.1研究背景和动机随着电力电子技术的不断发展和应用的不断扩展,半导体器件作为电力电子系统的核心组成部分之一,其性能和稳定性对系统的整体性能具有至关重要的影响。
而半导体开关作为电力电子系统中的关键部件之一,其特性对整个系统的效率、稳定性以及工作寿命都具有重要意义。
因此,对半导体开关的特性进行准确、全面的评估和研究显得尤为重要。
目前,传统的单脉冲测试方法虽然能够对半导体开关的部分特性进行评估,但其无法完全展现出开关在实际工作中的全部行为。
特别是在高频、高压、高温等极端工作条件下,单脉冲测试方法的局限性更加显著。
因此,需要一种更加全面、准确的测试方法来研究半导体开关的特性,从而为其在实际应用中提供更加可靠的支持。
在这样的背景下,双脉冲测试作为一种新型的测试方法备受研究人员的关注。
相较于传统的单脉冲测试,双脉冲测试能够提供更加丰富的信息,能够更好地模拟开关在实际工作中的工作环境,从而更准确地评估其性能。
因此,对双脉冲测试方法进行深入研究,并探索其在半导体开关特性研究中的应用,具有十分重要的意义。
1.2目的和意义首先,我们将分析双脉冲测试方法的原理和特点,以便更好地理解其在半导体开关特性研究中的应用。
相较于传统的单脉冲测试,双脉冲测试在实验条件和信号模拟方面有所不同,因此有必要深入探讨其差异以及优劣势。
其次,我们将设计合适的双脉冲测试实验方案,并采集相关数据进行分析。
这包括选择合适的实验装置和参数设置,确保测试结果的准确性和可重复性。
通过实验数据的采集和分析,我们将能够更全面地了解半导体开关在双脉冲测试条件下的行为。
然后,我们将比较双脉冲测试和单脉冲测试在评估半导体开关特性上的优劣。
这涉及到测试的准确性、测试时间、成本等多个方面的比较。
通过对两种方法的对比分析,我们可以更好地评估它们的适用性和局限性。
最后,本研究旨在揭示半导体开关在双脉冲测试条件下的工作机制和特性,为其在电力电子系统中的应用提供理论支持。
基于级联常通型SiC_JFET的快速中压直流固态断路器设计及实验验证
第52卷第5期电力系统保护与控制Vol.52 No.5 2024年3月1日Power System Protection and Control Mar. 1, 2024 DOI: 10.19783/ki.pspc.231277基于级联常通型SiC JFET的快速中压直流固态断路器设计及实验验证何 东1,徐星冬1,兰 征1,王 伟2(1.湖南工业大学电气与信息工程学院,湖南 株洲 412007;2.湖南大学电气与信息工程学院,湖南 长沙 410082)摘要:固态断路器(solid state circuit breaker, SSCB)是直流配电网中实现快速、无弧隔离直流故障的关键保护装置。
首先提出了一种基于级联常通型碳化硅(silicon carbide, SiC)结型场效应晶体管(junction field effect transistor, JFET)的新型中压直流SSCB拓扑,直流故障发生时利用金属氧化物压敏电阻(metal oxide varistor, MOV)向SSCB主开关级联常通型SiC JFET器件的栅源极提供驱动电压,可快速实现直流故障保护。
其次详细分析了SSCB关断和开通过程的运行特性,并提出了SSCB驱动电路关键参数设计方法。
最后研制了基于3个级联常通型SiC JFET器件的1.5 kV/63 A中压SSCB样机,通过短路故障、故障恢复实验验证了设计方法的有效性。
结果表明该SSCB关断250 A短路电流的响应时间约为20 μs,故障恢复导通响应时间约为12 μs,为中压直流SSCB的拓扑优化设计和级联常通型SiC JFET器件的动静态电压均衡性能提升提供了支撑。
关键词:直流配电网;固态断路器;碳化硅结型场效应晶体管;金属氧化物压敏电阻;短路故障Design and experimental verification of an ultrafast medium-voltage DC solid-statecircuit breaker using cascaded normally-on SiC JFETsHE Dong1, XU Xingdong1, LAN Zheng1, WANG Wei2(1. College of Electrical and Information Engineering, Hunan University of Technology, Zhuzhou 412007, China;2. College of Electrical and Information Engineering, Hunan University, Changsha 410082, China)Abstract: The solid-state circuit breaker (SSCB) is a crucial component in the protection of DC distribution networks in that they facilitate reliable, arc-free, and fast isolation of DC faults. First, a novel medium-voltage DC SSCB topology based on cascaded silicon carbide (SiC) junction field effect transistors (JFETs) is proposed. When a DC fault occurs, metal oxide varistors (MOVs) are used to provide driving voltage to the gate-source terminals of cascaded normally-on SiC JFETs of the SSCB main switch. These can achieve fast DC fault protection. Additionally, the operational characteristics of the SSCB turn-off and turn-on processes are analyzed in detail, and the design method of key parameters of the SSCB drive circuit is proposed.Finally, a 1.5 kV/63 A medium-voltage SSCB prototype based on three cascaded normally-on SiC JFETs is developed, and the effectiveness of the design scheme is verified through short-circuit fault and fault recovery experiments. The results indicate that the response time for the SSCB to turn off the 250A short-circuit current is about 20 μs. Fault recovery conduction response time is about 12 μs. This provides a foundation for the topology optimization design of medium-voltage DC SSCB and the improvement of dynamic and static voltage balance performance of cascaded normally-on SiC JFETs.This work is supported by the Natural Science Foundation of Hunan Province (No. 2021JJ40172).Key words: DC distribution network; solid-state circuit breaker; SiC JFET; MOV; short-circuit fault0 引言相比传统交流配电网,直流配电网传输效率高、基金项目:湖南省自然科学基金项目资助(2021JJ40172) 线路损耗小,且易于分布式能源的集成,在数据中心、地铁牵引系统、船舶配用电系统等领域具有良好的应用前景[1-4]。
动水环境中有限宽窄缝湍射流的水力特性研究
利
0.70
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报
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0.38
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XUEBAO
Z/B=2.72Rv
(3)
图5 不同环境横、射流雷诺数下的射流轨迹
图6 典型流速比情况下的射流轨迹线
2 . 4 射 流 对 称 面 上 逆 流 区 特 性 与 流 速 比 及 形 状 因 子 的 关 系 在前面对射流近区的流动分析中, 可以看到射流背流面存在着逆流向流动,该逆流区的存在会造成污染物浓度较高的水体在此集聚,不利于 污染物的稀释扩散。为此通过对不同长度窄缝的比较(图9),发现影响逆流区最大流向长度Xbmax/B的因素包 括流速比Rv和喷口的形状因子AR(为喷口长度与宽度的比值),其中形状因子AR的影响更为显著。由此,进 一步拟合得到逆流区最大流向长度Xbmax/B与流速比Rv的喷口的形状因子AR的关系式:
参考文献:
[1] Yasuhiro Kamotani,Issaac Creber.Experiment on a turbulent jet in a cross flow[J].AIAA.Journal,1972,10:425-1429. [2] Kelso R M,Lim T T.An experiment study of round jets in crossflow[J].J Fluid Mech.1996,306:111-144. [3] Crabb D,Durao DFG,Whitelaw JH.A round jet normal to a crossflow[J].ASME,J.Fluids Eng.,1981,103:142-153. [4] Qi Meilan,Fu Renshou,Chen putations for plane turbulent impinging jet in cross flow[J].J of Hydrodynamics,1999,(4):23-37. [5] Demurent A O.Characteristics of three-dimensional turbulent jets in crossflow[J].Int.J Engng Sci.,1993,31:899-913. [6] 槐文信,李炜,彭文启.横流中单圆孔紊动射流计算与特性研究[J].水利学报,1998,(4):7-14. [7] 姜国强,李炜,张晓元.横流中湍射流流场的试验和数值模拟方法[A].中国环境水力学[C].北京:中国水利水电出版 社.2002.133-140.
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Evaluation of Switching Performance of SiC Devices in PWM Inverter-Fed Induction Motor DrivesZheyu Zhang,Student Member,IEEE,Fred Wang,Fellow,IEEE,Leon M.Tolbert,Fellow,IEEE, Benjamin J.Blalock,Senior Member,IEEE,and Daniel J.Costinett,Member,IEEEAbstract—Double pulse test(DPT)is a widely accepted method to evaluate the switching characteristics of semiconductor switches, including SiC devices.However,the observed switching perfor-mance of SiC devices in a PWM inverter for induction motor drives is almost always worse than the DPT characterization,with slower switching speed,more switching losses,and more serious parasitic ringing.This paper systematically investigates the factors that limit the SiC switching performance from both the motor side and in-verter side,including the load characteristics of induction motor and power cable,two more phase legs for the three-phase PWM inverter in comparison with the DPT,and the parasitic capacitive coupling effect between power devices and heat sink.Based on a three-phase PWM inverter with1200V SiC MOSFETs,test re-sults show that the induction motor,especially with a relatively long power cable,will significantly impact the switching performance, leading to a switching time increase by a factor of2,switching loss increase up to30%in comparison with that yielded from DPT, and serious parasitic ringing with1.5μs duration,which is more than50times of the corresponding switching time.In addition,the interactions among the three phase legs cannot be ignored unless the decoupling capacitors are mounted close to each phase leg to support the dc bus voltage during switching transients.Also,the coupling capacitance due to the heat sink equivalently increases the junction capacitance of power devices;however,its influence on the switching behavior in the motor drives is small considering the relatively large capacitance of the motor load.Index Terms—Motor drives,SiC devices,switching performance.I.I NTRODUCTIONA DJUSTABLE speed drive systems are undergoing sig-nificant changes with the application of wide-bandgap semiconductor devices,such as silicon carbide(SiC),due to their increased junction operating temperature,low specific on-resistance,and high switching speed capability.Among these benefits,the fast switching plays a key role in reducing switch-ing losses,shortening dead time for a phase leg,and increasing switching frequency capability.As a result,a SiC motor driveManuscript received August7,2014;accepted November3,2014.Date of publication December4,2014;date of current version May22,2015.This work was supported in part by the II-VI Foundation,by the Engineering Re-search Center Shared Facilities supported by the Engineering Research Center Program of the National Science Foundation and DOE under NSF Award EEC-1041877,and by the CURENT Industry Partnership Program.Recommended for publication by Associate Editor A.Mertens.The authors are with the Department of Electrical Engineering and Computer Science,University of Tennessee,Knoxville,TN37996 USA(e-mail:zzhang31@;fred.wang@;tolbert@; bblalock@;daniel.costinett@).Color versions of one or more of thefigures in this paper are available online at .Digital Object Identifier10.1109/TPEL.2014.2375827inverter can provide lower loss,higher efficiency,and smaller size in comparison with their silicon(Si)counterparts[1]–[8]. To fully utilize the potential advantages of SiC devices,care-ful attention must be given to their high switching speed per-formance.Nowadays,the widely accepted method to assess the switching performance of power devices is the double pulse test (DPT)[9]–[11].However,due to the intrinsic characteristics of SiC devices,such as small junction capacitance,small specific on-resistance,and high di/dt and dv/dt during fast switching transients,their switching behavior becomes more susceptible to parasitics and noise of the application circuit,compared with slower Si devices.Thus,the simple and layout optimized dou-ble pulse tester with an optimally designed load inductor may not sufficiently represent a more complex configuration of ac-tual converters and loads.The DPT-based design will lead to an overestimation of the switching performance,and ultimately an inadequate design of the power converter.Previously reported works observed that in a SiC-based cur-rent source rectifier,the turn-off energy was increased by a factor of5,with three times longer current fall time compared with the test result of DPT under the same operating conditions [12].Similarly,in a SiC-based voltage source inverter,due to the increased overshoot current and slower turn-off time,the total switching energies were increased by a factor of1.5to1.8[13]. Also,in adjustable speed drive applications,the test results indi-cate that the efficiency of the Si PWM inverter will decrease due to the use of long power cables[14].However,there has been few works investigating the mechanisms causing the aforemen-tioned difference in switching performance between the double pulse tester and power converters,especially for SiC devices. This paper systematically evaluates the switching perfor-mance of a SiC-based PWM inverter for induction motor drives (IMD).As shown in Fig.1,there are three primary differ-ences between the configuration of a three-phase PWM in-verter and a double pulse tester:different inductive loads,two more phase legs for inverter,and cooling systems(e.g.,heat sink).First,this paper compares the high-frequency impedances of an induction motor plus power cable and the optimally designed inductor employed in a double pulse tester.The resulting switching behavior differences are analyzed.Sec-ond,the impact of the other two phase legs on the switch-ing performance of the phase leg under test is described for the three-phase PWM inverter.Third,the parasitic capacitive coupling effect between power devices and heat sink,and its influence on the switching performance,is discussed for motor drives.Andfinally,for experimental verification,the switching performance of1200V SiC MOSFETs is evaluated0885-8993©2014IEEE.Personal use is permitted,but republication/redistribution requires IEEE permission.See /publications standards/publications/rights/index.html for more information.Fig.1.Configuration comparison between the double pulse tester and three-phase PWM inverter-fed IMD:(a)DPT circuit;and (b)three-phase PWM inverter-fedIMD.Fig.2.Typical switching current/voltage waveforms.under pulse test and continuous operating condition in a three-phase PWM inverter connected to an induction motor.II.I MPACT OF I NDUCTIVE L OADS ON S WITCHING P ERFORMANCEAs can be observed in Fig.1(a),the load inductor of the DPT circuit is paralleled with the upper switch,assuming the lower switch is selected as the device under test (DUT).During the switching transient,the upper switch stays OFF,and can be modeled as a conducting diode when the switching current is commutating (i.e.,current rise subinterval t cr during turn-on transient and current fall subinterval t cf during turn-off transient in Fig.2)or an output capacitance,while the switching voltage is changing (i.e.,voltage fall subinterval t v f during turn-on tran-sient and voltage rise subinterval t v r during turn-off transient in Fig.2).Thus,the DPT circuit can be redrawn as Fig.3,where Z L represents the inductive load impedance.If Z L is much greater than the equivalent impedance of the upper switch during the switching transient,then the impact of inductive load on the switching performance can be neglected;otherwise,Z L must be taken into consideration.For the specific analysis of the comparisons between DPT load inductor and induction motor load,four 115-μH inductors in series are employed to form a DPT load inductor,which is a typical way of designingDPTFig.3.Simplified DPT circuit.load inductor with small parasitic capacitance;a 7.5-kW induc-tion motor and 2-m power cable are selected to represent of the motor load,since it is a proper load in terms of power rat-ing for the SiC devices under evaluation (CREE CMF20120D 1200-V/24-A SiC MOSFETs).In addition,for the higher power rating induction motor with longer power cable in many practi-cal applications,the associated impedance Z L at high frequency becomes lower [15].Thus,the motor load selected in our study case indicates a conservative impact of induction motor on the switching performance.Then,the generality of the following analysis is not lost.A.Impact of Induction Motor on Switching Performance As illustrated in Fig.3,during the switching current com-mutation subinterval,the impedance of the upper switch is ex-tremely small since it can be considered as a voltage source.During the switching voltage change subinterval,the impedance of the upper switch depends on the output capacitance of the device.Normally,the equivalent impedance of the upper switch is also small in the switching-related frequency range that is determined by the switching speed [9].Typically,the frequency range is several megahertz to tens of megahertz for SiC devices considering switching intervals of tens of nanoseconds.ZHANG et al.:EV ALUATION OF SWITCHING PERFORMANCE OF SIC DEVICES IN PWM INVERTER-FED INDUCTION MOTOR DRIVES5703Fig.4.Impedance and circuit model of inductive loads:(a)Impedance of inductive loads versus C o ss of SiC device;and(b)circuit model of inductiveloads.Fig.5.Impact of parasitics of induction motor on switching current:(a)Turn-on transient;and(b)turn-off transient.In the typical DPT,the load inductor during a switching tran-sient can be approximated as a current source.Ideally,due to the infinite impedance of the current source during this dy-namic process,the load inductor has no impact on theswitching Fig.6.Impedance of induction motor with2-m cable versus induction motor. behavior of the DUT.Practically,the load inductor of the DPT is optimally designed so that its parasitics,such as equivalent parallel capacitance,are very small[10],making the load in-ductor impedance much larger than the upper switch equivalent impedance at frequencies of interest with respect to the switch-ing transition.Therefore,the load inductor has little effect on the switching performance in the DPT.However,in adjustable speed drive systems,the parasitics of the induction motor cause its high-frequency impedance to be significantly decreased,as shown in Fig.4(a).Measured using the Agilent4294A impedance analyzer,the impedance of the DPT load inductor is greater than the induction motor equivalent impedance above200kHz,although the DPT load inductance is smaller than the induction motor inductance.In addition,the measured induction motor impedance in our exam-ple system is even smaller than the equivalent impedance of the SiC device used in this case(CREE CMF20120D SiC MOS-FET)below11.5MHz.Note the device equivalent impedance is mainly determined by its output capacitance and the CREE de-vice has an output capacitance of120pF[16].On the contrary,5704IEEE TRANSACTIONS ON POWER ELECTRONICS,VOL.30,NO.10,OCTOBER2015above700kHz,the DPT load impedance is greater than the de-vice’s impedance due to its output capacitance.Consequently, the induction motor will play a significant role in the switch-ing behavior of the DUT due to the small motor impedance at high frequencies.Also,it is important to note that SiC has smaller output capacitance than its Si counterpart,resulting in higher equivalent impedance and making the SiC switch-ing behavior more susceptible to the parasitics of the induction motor.Based on the measured impedance,circuit models of the DPT load inductor and motor load are built,as shown in Fig.4(b) following the methods in[15],[17]–[19].Each parameter in the circuit model has physical meaning and significance.L d refers to the stator winding leakage inductance;R e represents the high-frequency iron loss of the stator winding;L t,C t,and R t are introduced to capture the second resonance in the mo-tor impedance characteristics,according to[17],that may be caused by the skin effect and turn-to-turn capacitance of the stator windings.As can be observed in Fig.4(a),thefitted curves of the inductive load impedance based on the circuit models can represent the critical characteristics of the motor and DPT impedances.During the switching transient,the large inductance L d can be modeled as a current source,as shown in Fig5.It is the series resonant network formed by L t,C t, and R t that affects the switching pared with the DPT load inductor with extremely small parasitic capaci-tance C t(1.2%C oss of SiC MOSFET under evaluation)and large damping resistance R t(625Ω),the parasitic capacitance C t of the induction motor is six times that of C oss of the SiC MOSFETs,and its corresponding damping resistance R t(10Ω)is relatively small.Therefore,in the time domain,consid-ering the high dv/dt drain-source voltage of the upper switch V ds H across the RLC series resonant network,the induction motor with large C t and small R t causes more serious para-sitic ringing with longer duration.This parasitic ringing causes additional resonant current toflow in the switching commuta-tion loop.Also,the switching performance of the lower switch is affected.Unlike the typical high frequency parasitic ringing (typically tens of megahertz)due to the resonance between the power loop inductance and C oss of power devices,the ringing caused by parasitics of the induction motor has relatively low frequency with5.4MHz in our case study[see Fig.4(a)].Also, this lower frequency ringing will be observed in the drain current of the lower switch during the turn-on transient and drain current of the upper switch during the turn-off transient,as illustrated in Fig.5.B.Impact of Induction Motor With Power Cableon Switching PerformanceInduction motor drive systems fed with a power cable are widely used in many industrial applications.It is,therefore, necessary to evaluate the impact of an induction motor with a power cable on the switching performance.Fig.6dis-plays the impedance comparison between the induction motor and the induction motor with2-m power cable.The impedances of the induction motor and the induction motor plus powercable Fig.7.Equivalent circuit of three-phase PWM inverter considering the parasitics.are identical below100kHz but significant differences occur at high frequency.Especially above10MHz,the impedance of the induction motor with power cable is smaller than that of the induction motor only,and is even comparable to the impedance of the SiC MOSFET’s C oss.Based on the aforementioned anal-ysis in the frequency domain,more serious impact on switching performance can be expected of the induction motor with power cable.Also,since the cable length in practical applications is generally much longer than the2m length used in our case study,more attention must be paid to the power cable’s impact. In the time domain,due to the complicated model of power ca-ble with distributed LC networks,it is difficult to illustrate the precise relationship between the power cable and the switching behavior based on a high-order circuit model.In summary,the capacitive coupling among the conductors of the power cable extends the charging/discharging subinterval during switching transients,leading to lower dv/dt,longer switching time,and larger switching losses.III.I MPACT OF P HASE L EGS AND H EAT S INKON S WITCHING P ERFORMANCEA.Interaction of Phase Legs on Switching PerformanceAs can be observed in Fig.1,as compared to double pulse tester consisting of only one phase leg,a three-phase PWM inverter has two additional phase legs.Thus,additional device and interconnection parasitics will be involved in the circuit. Assuming the upper switches of phases B and C are in on-state, while their lower switches are in off-state during the switching transients of the phase A devices,Fig.7displays the equivalent circuit of a three-phase PWM inverter considering the parasitics, where the upper switches of phases B and C are represented by their on-state resistance R ds(o n),and the junction capacitance C oss represents the lower switches of phases B and C.Also, L p(i n)is the power loop parasitic inductance within each phase leg,while L p(e x t)is the parasitic inductance distributed in theZHANG et al.:EV ALUATION OF SWITCHING PERFORMANCE OF SIC DEVICES IN PWM INVERTER-FED INDUCTION MOTOR DRIVES5705Fig.8.Connection structures of inductive loads according to different sections of space vectormodulation.Fig.9.Uniform equivalent circuit considering constant dc bus voltage thanks to decouplingcapacitors.Fig.10.Uniform equivalent circuit considering capacitive coupling effect induced by heat sink.dc bus.Z LA ,Z LB ,and Z LC are the impedances of the inductive load of each phase.As can be observed in Fig.7,the equivalent inductive load consists of parasitic inductance,on-state resistance,and three-phase inductive loads.Considering the relatively small para-sitic inductance (i.e.,L p (i n )/L p (e x t ))and the small R ds (on)of SiC devices in comparison with the impedance of inductive loads (Z LB /Z LC ),the impact of parasitics induced by the upper switches of phases B and C on the inductive loads can be neg-ligible.In addition,the potentials at nodes B and C will almost stay constant during the switching transient of the phase-A DUT due to the existence of ceramic capacitors with small equiva-lent series inductance utilized as decoupling capacitors mounted close to each phase-leg in practical applications.Therefore,for the lower switches of phases B and C,the voltages across C oss have little variation so that the switching performance of the DUT is hardly affected by the lower switches of phases B andC.Fig.11.SiC-based three-phase PWM inverter.In addition to the parasitics induced by phases B and C,the ON/OFF states of switches in the other phase leg alter the con-nection structure of inductive loads with respect to the phase leg under test.Therefore,different from a fixed inductive load po-sition within the DPT,the tested device in a three-phase PWM inverter during the commutation interval will see different com-binations of the inductive loads.According to the ON/OFF states of the phases B and C switches,based on the space vector modu-lation scheme,there are three connection structures of inductive loads with respect to phase A during a switching transient,as shown in Fig.8.Fortunately,as previously mentioned,the dc bus voltage during the switching transient stays nearly constant thanks to the decoupling capacitors close to each phase leg.Hence,according to circuit theory,the dc bus voltage source is shorted during the dynamic process analysis.Assuming the impedances of inductive loads for all phases are identical and de-noted by Z L ,three different circuits in Fig.8can be simplified as a uniform equivalent circuit,as shown in Fig.9.Consequently,different connection structures due to the switching states of phases B and C have little effect on the switching performance of phase A devices in practical applications.B.Impact of Heat Sink on Switching Performance in Motor DrivesIn a three-phase PWM inverter,SiC devices are attached to a heat sink for thermal ually,a thin layer of insulating material is used to separate the SiC devices from the electrically conductive heat sink.Thus,a parasitic capacitance is5706IEEE TRANSACTIONS ON POWER ELECTRONICS,VOL.30,NO.10,OCTOBER2015Fig.12.Different inductive loads:(a)DPT load inductor;and(b)7.5-kW induction motor with2-m power cable.formed between the drain base plate of the SiC devices and the common heat sink plate[13].In the end,this capacitance C H S is paralleled with devices,which equivalently increases their effective C oss.However,in an IMD for our study,in addition to the coupling capacitance between devices and heat sink,the parasitics of the induction motor is paralleled with devices as well,as shown in pared with the motor parasitic capacitance C t[764pF in Fig.4(b)],the coupling capacitance (39.75pF based on our test setup)is only5.2%of C t.Therefore, the capacitive coupling effect is insignificant when evaluating the switching performance of SiC MOSFETs in an IMD with relatively large capacitive parasitics.IV.E XPERIMENTAL V ERIFICATIONA.Hardware SetupTo evaluate the influence of the aforementioned impact fac-tors in Sections II and III,a three-phase PWM inverter test circuit was designed to satisfy the following requirements: 1)sufficientflexibility such that the three-phase PWM inverter can be evolved from a layout optimized double pulse tester;2)during this design evolution,the layout associated with the DUT must remain consistent;and3)a common heat sink is used for all power devices.Fig.11displays a three-phase PWM in-verter with1200-V CMF20120D SiC MOSFETs,including one uniform mother board,six gate drive daughter boards integrated with devices,and one common heat sink.Hence,a DPT con-figuration can be achieved by means of merely connecting the gate drive boards of phase A with the mother board.In addition, a three-phase PWM inverter can be assembled with all six gate drive boards of three phase-legs mounted to the mother board. Also,using the lower switch of phase A as the DUT,it can be observed that the layouts of both the power and gate loop for the DUT under either DPT configuration or inverter circuit are nearly the same.Fig.12displays two types of inductive loads:DPT load in-ductor and a7.5kW induction motor with a2-m power cable for evaluation of the difference in switching performance for double pulse tester and motor drive conditions.Note that the DPT load inductor consists of four small inductors in series is to minimize parasitics.For the fast transient measurement,the following equipment is used to detect the switching waveforms:adigital Fig.13.Test circuits for evaluation of switching performance with different inductive loads.oscilloscope(Tektronix DPO401)with frequency bandwidth of 1GHz and maximum sampling rate of5GS/s,two THDP0200 high voltage differential probes with frequency bandwidth of 200MHz for drain-source voltage measurement of the upper and lower switches in a phase leg,and two TCP0030A current probes with frequency bandwidth of120MHz for drain current measurement of the upper and lower switches in a phase leg.B.Methodology for Experimental VerificationA four-step verification procedure has been devised,that starts with the double pulse tester and ends with the three-phase PWM inverter-fed IMD.Each step will now be described.1)Evaluation of the impact of different inductive loads onthe switching performance.Here the gate drive boards of phase A are connected with the mother board to form a DPT circuit,and the switching performance of the phaseA lower switch is tested with the optimally designed loadinductor,7.5kW induction motor,and7.5kW induction motor plus2-m power cable.As shown in Fig.13,the switching performance differences in this step are only attributed to the inductive loads.For simplicity,PL-DPT, PL-IM,and PL-IM-PC refer to the test circuits with DPT load inductor,induction motor,and induction motor plus power cable,respectively.2)Evaluation of the interaction of phase legs on switchingperformance.The gate drive boards of phases B and C are added to the mother board to establish a three-phaseZHANG et al.:EV ALUATION OF SWITCHING PERFORMANCE OF SIC DEVICES IN PWM INVERTER-FED INDUCTION MOTOR DRIVES5707Fig.14.Test circuits for evaluation of the impact of phase legs and heat sink on the switching performance:(a)3Φ-IM-1;(b)3Φ-IM-2;(c)3Φ-IM-3;and (d)3Φ-IM-HS-1.inverter,and the switching performance of the DUT is tested by turning ON the upper switches of phases B and C,as shown in Fig.14(a).Hence,compared with the switching behavior of the DUT with the induction motor in step1(i.e.,PL-IM),the impact of parasitics induced by phases B and C can be identified.Then,ac-cording to the modulation scheme,the switches of phasesB andC are controlled in different ON/OFF states dur-ing the switching transient of the DUT,as shown in Fig.14(b)and(c),to evaluate the impact of different inductive load connection structures on switching perfor-mance.For simplicity,3Φ-IM-1,3Φ-IM-2,and3Φ-IM-3 indicate the test circuits as shown in Fig.14(a),(b),and(c), respectively.3)Evaluation of the impact of the heat sink on switchingperformance.A common heat sink is attached with all the power devices in the three-phase inverter,and the switching behavior of the DUT is tested by controlling the upper switches of phases B and C to be on,as shown in Fig.14(d).Thus,in comparison with the switching per-formance of the DUT with the same ON/OFF states of the switches of phases B and C in step2(i.e.,3Φ-IM-1),the capacitive coupling effect induced by the heat sink can be identified.For simplicity,3Φ-IM-HS-1represents the test circuits in Fig.14(d).4)Evaluation of the impact of the induction motor rotationon the switching performance.The switching behaviors in the previous three steps are evaluated based on pulse test,which means that the motor is not rotating,although certain pulse currentsflow through the stator windings.In step4,the switching performance of the DUT is tested when the induction motor is rotating.Based on the same hardware setup as in step3,the difference of the switching performance under the motor running test and pulse test can be evaluated.Also note that the junction temperature variation of the DUT under the continuous operating con-dition will become another factor that impacts the switch-ing behavior.In this test,the low switching frequency of 5kHz and small ac RMS current of11A are selected to minimize active power loss.Also,the heat sink with forced air cooling is utilized for thermal management.Thus,the junction temperature rise of the DUT under no load operating condition for1to2min is insignificant.C.Experimental ResultsFig.15shows the comparison waveforms with three different inductive loads under the operating condition of600V/10A with 5-Ωgate resistance.As can be observed from the overall switch-ing waveforms during both turn-on and turn-off transients,there is a5.4MHz frequency ringing in the switching current with the5708IEEE TRANSACTIONS ON POWER ELECTRONICS,VOL.30,NO.10,OCTOBER2015Fig.15.Impact of different inductive loads on switching performance: (a)Turn-on transient;and(b)turn-off transient.induction motor,which corresponds to the resonance frequency created by the parasitics of the induction motor(see Fig.4). In addition,as predicted,during a turn-on transient,this low frequency ringing current is found from the drain current of the lower switch;while during a turn-off transient,itflows through the upper one.Also note that the ringing duration is up to1.5μs, which is much longer than the tens of nanoseconds’switching time,as shown in the zoomed-in switching waveforms.Further-more,as compared to the switching behavior with the DPT load inductor,the parasitics of the induction motor cause the turn-on and turn-off switching time to increase from26to29ns and32 to38ns,respectively.The total energy loss slightly increases as well.After inserting a2-m power cable between the inverter and motor,the switching performance becomes even worse:Switch-ing time increases up to42%during turn-on,and doubles during turn-off;an additional32%of energy loss is dissipated during the switching transient.More test results with different load currents and gate resis-tances are shown in Fig.16.In order to clearly demonstrate the impact of different inductive loads on the switching perfor-mance,the switching time t sw and energy loss E sw with induc-tion motor and motor plus power cable are normalized based on results with DPT load inductor,which are listed in Tables I and II.These results show that under different loadcurrents parison of t sw and E sw among different inductive loads under different I L and R g:(a)t sw dependence on I L;(b)t sw dependence on R g;(c)E sw dependence on I L;and(d)E sw dependence on R g.TABLE It sw AND E sw VERSUS I L U NDER DPT W ITH V D C OF600V AND R G OF5ΩI L(A)5101520t O N(ns)24262933t O F F(ns)51322928E s w(μJ)135200286398。