1.8–2.6 GHz CMOS VCO
基于O.18μm CMOS工艺的宽带LCVCO设计
基于O.18μm CMOS 工艺的宽带LCVCO 设计
通常衡量VCO 的指标有:自振频率、振荡范围、输出幅度,相噪.功耗等。
一般采用优值FOM(Figure of Merit)来评价VCO 的优劣:
其中:f0 是自振频率,△f 为频偏.L(△f)是频偏△f,处的相噪。
P 为直流
功耗
2 宽带LCVCO 设计实现本文目标是设计一个覆盖1.1 GHz~2.1 GHz 频段的CMOS LCVCO 电路。
覆盖范围包括如表l 所示的各标准协议频段。
使LCVCO 获得大调谐范围的方法之一是增大容抗管的Cmax/Cmin,但这会增
大VCO 的压控增益KCCO。
,致使相噪恶化。
为了解决这个矛盾,通常采用开关电容阵列(DC-CA)把频带分为若干子频带,通过开关电容的接人与断开来实
现子频带之间的切换,子频带内则由容抗管的调谐来实现覆盖,其结构图如图3。
tips:感谢大家的阅读,本文由我司收集整编。
仅供参阅!。
VCO仿真的方法
CMOS环形压控振荡器的设计摘要压控振荡器(VCO)是一个输出振荡频率由电压控制的电子振荡器。
当调制信号发生变化时,其会影响VCO的频率和相位的变化,及实现调频和调相。
VCO和数字脉冲相似,他们均可以进行频移键控调制、相移键控调制和脉冲宽度调制。
对于高频VCO来说,其主要是通过变容二极管连接到谐振电路来控制其输出频率;多出现在LC振荡器中。
而在低频情况下是通过另一种方法来控制(如电压控制电流源从而来改变电容的充放电时间)。
多用于CMOS振荡器,这也是本次研究所采用的方法。
VCO是现代无线通信射频系统中的一个关键部件,它主要用于提供本地振荡信号、频率合成。
同时被广泛应用于通信电路中,例如锁相环、频率综合器,以及时钟产生和环形振荡器。
随着深亚微米CMOS工艺的不断发展,CMOS工艺被广泛应用于射频集成电路(RFIC)的设计中。
核心部件的射频低功耗低噪声的VCO成为整个PLL电路的研究热点。
环形压控振荡器(VCO)在基于CMOS工艺的射频电路中,以其低功耗、面积小、易于集成等优点扮演着重要角色。
本课题的研究内容主要是设计一种基于CMOS工艺的低抖动的环形压控振荡器。
通过改变其器件的参数,从而实现如下技术指标:频率变化范围为1000—1200MHz;压控增益为180MHz/V。
计算出相关的系统参数和指标,并完成各个子模块的时域和频域分析。
关键词:环形压控振荡器延迟单元频率调谐相位噪声抖动Design of CMOS Voltage-Controlled OscillatorABSTRACTA voltage-controlled oscillator or VCO is an electronic oscillator designed to be controlled in oscillation frequency by a voltage input. The frequency of oscillation is varied by the applied DC voltage, while modulating signals may also be fed into the VCO to cause frequency modulation (FM) or phase modulation (PM); a VCO with digital pulse output may similarly have its repetition rate (FSK, PSK) or pulse width modulated (PWM).For high-frequency VCOs the voltage-controlled element is commonly a varicap diode connected as part of an LC tank circuit. It always appears in the LC oscillator. For low-frequency VCOs, other methods of varying the frequency (such as altering the charging rate of a capacitor by means of a voltage controlled current source) are used. And this is usually used in the CMOS oscillator. This is also the method of this study.VCO is a key component of modern wireless communication in RF system, it is mainly used to provide the local signal and the frequency synthesizer. And it usually is used in communication circuits, such as phase-locked loop frequency synthesizers, and clock generation and ring oscillator. With the continuous development of deep sub-micron CMOS technology, CMOS technology has been widely used in radio frequency integrated circuit (RFIC) design. A core component of the RF low-power low-noise VCO of the PLL circuit is hot. Ring voltage-controlled oscillator (VCO) play an important role in the RF circuit of the CMOS process, with its low power consumption, small size, ease of integration advantages.The content of this subject is to design a low-jitter ring voltage controlled oscillator based on CMOS technology. This oscillator, in order to achieve the following technical indicators frequency range of 1000-1200MHz, voltage-controlled gain of 180MHz / V by changing the parameters of the device. Calculate the system parameters and indicators, and the completion of each sub-module time-domain and frequency domain analysis.Key Words: VCO Delay Cell Frequency-Tuning Phase Noise Jitter目录第一章绪论 (1)1.1课题意义 (1)1.2课题的国内外发展状况 (1)1.3课题的研究内容 (2)1.3.1研究方法 (2)1.3.2研究步骤 (2)1.3.3工具简介 (2)第二章VCO的原理 (4)2.1VCO的振荡条件 (4)2.2VCO延迟单元电路的介绍 (7)2.3 VCO频率调谐 (8)2.3.1频率调谐的原理 (9)2.3.2频率调谐的方法 (10)2.4VCO的主要性能指标 (14)2.4.1VCO的噪声种类 (14)2.4.2VCO的主要参数 (15)第三章CMOS环形VCO电路结构及原理 (17)3.1传统单端反相器VCO的结构 (17)3.2电流饥饿型VCO的结构 (18)3.3低抖动VCO的结构 (19)3.3.1电路的结构原理 (19)3.3.2电路的特点 (20)第四章低抖动CMOS环形VCO电路特性的仿真 (22)4.1电压频率特性的描述及仿真 (22)4.1.1输出频率的影响因素 (22)4.1.2输出频率及压控增益的仿真结果及分析 (27)4.2相位噪声的仿真结果及分析 (32)4.3版图的设计 (34)结论 (36)参考文献 (37)致谢 (38)天津理工大学2012届本科毕业设计说明书第一章绪论1.1课题意义压控振荡器是高性能数字系统的关键模块。
AD9520-0_cn
图1.
应用
低抖动、低相位噪声时钟分配 SONET、10Ge、10GFC、同步以太网、 OTU2/3/4的时钟产生 和转换 前向纠错(G.710) 为高速ADC、DAC、DDS、DDC、DUC、MxFE提供时钟 高性能无线收发器 自动测试设备(ATE)和高性能仪器仪表 宽带基础设施
ADI中文版数据手册是英文版数据手册的译文,敬请谅解翻译中可能存在的语言组织或翻译错误,ADI不对翻译中存在的差异或由此产生的错误负责。如需确认任何词语的准确性,请参考ADI提供 的最新英文版数据手册。
07213-001
SPI/I2C CONTROL PORT AND DIGITAL LOGIC
EEPROM
功能框图
CP LF
REFIN
SWITCHOVER AND MONITOR
OPTIONAL
REF1
STATUS MONITOR
PLL
VCO
REFIN
REF2
CLK
DIVIDER AND MUXES
ZERO DELAY
LVPECL/ CMOS DIV/Φ
OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11
12路LVPECL/24路CMOS输出时钟 发生器,集成2.8 GHz VCO
AD9520-0
特性
低相位噪声锁相环(PLL) 片内VCO调谐范围:2.53 GHz至2.95 GHz 可选外部3.3 V/5 V VCO/VCXO至2.4 GHz 1路差分或2路单端参考输入 支持最高250 MHz的CMOS、LVDS或LVPECL参考 参考输入接受16.62 MHz至33.3 MHz晶振 可选参考时钟倍频器 参考监控功能 自动/手动参考保持和参考切换模式,恢复式切换 参考间无 毛刺切换 从保持模式自动恢复 可选数字或模拟锁定检测 可选零延迟工作 12路1.6 GHz LVPECL输出分为4组 每组3路输出,共享一个带相位延迟的1至32分频器 加性输出抖动低至225 fs rms 分组输出的通道间偏斜:<16 ps 可以将每路LVPECL输出配置为2路CMOS输出(fOUT ≤ 250 MHz) 上电时所有输出自动同步 提供手动输出同步 SPI和I²C兼容型串行控制端口 64引脚LFCSP封装 非易失性EEPROM存储配置设置
两种高频CMOS压控振荡器的设计与研究
两种高频CMOS压控振荡器的设计与研究锁相环在通讯技术中具有重要的地位,在调制、解调、时钟恢复、频率合成中都扮演着不可替代的角色。
可控振荡器是锁相环的核心部分。
最近,鉴于对集成电路低功耗和高集成度的追求,越来越多的研究人员投人到基于CMOS工艺的压控振荡器的设计。
环形压控振荡器因为具有宽的调谐范围和小的芯片面积,在电路的精心设计下也可以具有不错的相位噪声性能,从而在数字通信系统中得到广泛的应用。
而随着CMOS工艺特征尺寸的不断减小,根据CMOS工艺按比例缩小理论,电源电压也要同比例降低。
与采用1.8 V电源电压的0.18 μm CMOS工艺相比,传统全差分延时单元结构的输出信号的摆幅被限制在非常小的区域内,不但降低了输出信号的信噪比(SNR),而且必须经过放大等一系列处理后才能送给下一级电路。
文中分析了影响压控振荡器性能的重要参数,同时设计实现了两种多谐压控振荡器,给出了相应的实验结果。
1 VCO的工作原理与性能指标VCO是一个电压/频率转换电路,在环路中作为被控振荡器,它的输出频率应随控制电压线性地变化。
一个理想的VCO其输出频率和输入频率的关系ωout=ω0+KVCOVcont (1)式中,ω0是控制电压Vcont为零时的振荡器的固定频率,KVCO为VCO的增益或灵敏度(单位为rad/s·V-1)。
由式(1)可以推导出VCO的传输函数由式(2)可以得出,当VCO被放在锁相环中时,其输出经分频器后接到鉴相器的输入,对鉴相器输出起作用的不是其频率,而是相位。
所以在锁相环中VCO通常被看作输入为控制电压,输出为相位的系统。
所以VCO在锁相环系统中就像一个理想的积分器,其传输函数可以表示为在实际应用中,VCO的线性范围有限,超出这个范围之后,环路的参数就会变化较大,不利于环路设计。
通常,评价VCO的好坏主要有以下特征:(1)低抖动或低相位噪声:由于电路结构、电源噪声、地噪声等因素的影响,VCO的输出信号并不是理想的方波或正弦波,其输出信号存在一定的抖动,转换成频域后可看出信号中心频率附近也会有较大的能量分布,即相位噪声。
基于电流折叠技术的CMOS全差分VCO设计
基于电流折叠技术的CMOS全差分VCO设计作者:康香英徐卫林来源:《现代电子技术》2009年第10期摘要:针对目前通信系统应用上对压控振荡器的片上集成、宽调谐、调幅、启动特性和功耗等提出的综合性要求,分析和设计了一种压控调频调幅振荡器,其延迟单元采用全差分结构,以消除共模噪声和增加延迟控制的灵活性;并利用交叉耦合的差分负阻和电流折叠的正反馈技术进行频率调谐,使之在宽频范围内具有常数振荡幅度。
采用0.5 μm CMOS工艺进行Spice仿真,结果表明振荡器具有34~197 MHz的宽调谐范围,并能保持常数振荡幅度,功耗仅10 mW,启动时间仅52 ns。
系统还能在0.5~2.0 V范围内进行良好的线性调幅。
关键词:电流折叠;负阻交叉耦合晶体管对;自动振幅控制;全差分压控振荡器中图分类号:TN402文献标识码:B文章编号:1004-373X(2009)10-011-02Design of CMOS Full Differential VCO Based on Current Fold TechniqueKANG Xiangying1,XU Weilin2(1.Xianggang Yixing Refractory Co.Ltd.,Xiangtan,411102,China;2.Institute of Microelectronics and Information Technology,WuhanUniversity,Wuhan,430072,China)Abstract:On-chip VCO with comprehensive target,such as wide tuning,amplitude adjusting,good start up time and lower power,is required in current communication system.A frequency and amplitude adjusting VCO is designed and analyzed.Full differential configuration is used to avoid common mode noise and achieve controlling flexibility of delay cells.Negative resistance differential complementary cross-coupled pair and regenerative feedback technique with current fold are applied to adjust frequency with constant amplitude in large range.Under 0.5 μm CMOS process,Simulation results in SPICE indicate that the VCO proposed behaves in wide linear tuning between 34~197 MHz with constant amplitude,10 mW power dissipation and 52 ns start up time.It also has good linear amplitude adjusting between 0.5~2.0 V.Keywords:current fold;negative resistance complementary cross-coupled pair;automatic amplitude control;fully differential VCO射频振荡器是仪器仪表、自动控制和通信系统等领域广泛使用的基本模块,是构成时钟恢复、频率合成等系统的核心电路[1,2]。
微波毫米波单片集成电路综述论文
微波毫米波单片集成电路综述论文摘要微波集成电路(Microwave Integrated Circuit缩写为MIC)是工作在微波波段和毫米波波段即30GHz~300GHz频率范围,由微波无源元件、有源器件、传输线和互连线集成在一个基片上,具有某种功能的电路。
微波集成电路起始于20世纪50年代。
微波电路技术由同轴线、波导元件及其组成的系统转向平面型电路的一个重要原因,是微波固态器件的发展。
60~70年代采用氧化铝基片和厚膜薄膜工艺;80年代开始有单片集成电路。
微波集成电路大致可以分为两种电路:混合微波集成电路和单片微波集成电路。
混合微波集成电路是用厚膜技术或薄膜技术将各种微波功能电路制作在适合传输微波信号的介质(如高氧化铝瓷、蓝宝石、石英等)上,再将分立有源元件安装在相应位置上组成微波集成电路。
这种电路的特点是根据微波整机的要求和微波波段的划分进行设计和制造,所用集成电路多是专用的。
常用的混合微波集成电路有微带混频器、微波低噪声放大器、功率放大器、倍频器、相控阵单元等各种宽带微波电路。
单片微波集成电路(Monolithic Microwave Integrated Circuit缩写为MMIC)则是将微波功能电路用半导体工艺制作在砷化镓或其他半导体芯片上的集成电路。
这种电路的设计主要围绕微波信号的产生、放大、控制和信息处理等功能进行,大部分电路都是根据不同整机的要求和微波频段的特点设计的,专用性很强。
在这类器件中,作为反馈和直流偏置元件的各个电阻器都采用具有高频特性的薄膜电阻,并且与各有源器件一起封装在一个芯片上,这使得各零件之间几乎无连线,从而使电路的感抗降至最低,且分布电容也极小,因而可用在工作频率和频宽都很高的MMIC 放大器中。
目前,MMIC的工作频率已可做到40GHz,频宽也已达到15GHz,因而可广泛应用于通信和GPS, 等各类设备的射频、中频和本振电路中。
本文主要从单片微波集成电路工艺、基于Si的单片微波集成电路的电路结构的发展、基于Si的单片微波集成电路的制造工艺的发展以及微波毫米波单片集成电路的发展趋势这几方面进行综述分析。
一种宽带低功耗的VCO设计
设计应用技术Telecom Power Technology g tanknk p11.92R ≈ (5)起振的判决条件公式为 mn mptank 2g g g γ+≥ (6)式中:g mn 为NMOS 的跨导值;g mp 为PMOS 的跨导值;γ为保证起振正常的起振因子,通常取3。
因此,在设计中NMOS 和PMOS 管的跨导都取g mn =g mp = 5.76 mS 。
3 测试分析与讨论文章基于SMIC 40 nm 对LC-VCO 进行设计,通过版图绘制以及后仿真的优化测试可知。
本文设计的VCO 版图如图3所示,大小约为0.089 mm 2,整体功耗为1.155 mW 。
图3 VCO 版图控制电压U ctrl 在200~900 mV 时,中心频率下的调谐曲线如图4所示。
由图4可知,传统的可变电容电路所得到的调谐增益K vco 变化较大,对于控制电压的利用率不高,而优化后的调谐曲线较为线性,避免了VCO 调谐线性度较差后产生的锁相环不稳定现象,使其在整个频带中波动较小,与设计的目标相一致。
TT 工艺角(表示NMOS 和PMOS 都是Typical 型)下,25 ℃时,后仿真的64条调谐曲线如图5所示。
相邻2条曲线有一定的交叠,避免了输出的频谱出现断点,同时让工作频率覆盖在4.08~5.62 GHz ,保证了中心频率在4.85 GHz 附近,使整个频率的调谐范围占比为31.75%。
控制电压/mV优化后的调谐曲线初始的调谐曲线200.04.714.724.734.744.754.764.774.78频率/G H z4.794.804.81250.0300.0350.0400.0450.0500.0550.0600.0650.0700.0750.0800.0850.0900.0图4 调谐曲线的比较控制电压/mV5.62 GHz4.08 GHz频率/G H z200.04.04.14.24.34.44.54.64.74.84.95.05.15.25.35.45.55.65.7300.0400.0500.0600.0700.0800.0900.0图5 64条频率调谐曲线VCO 的相位噪声PVT 测试结果如图6所示,在1 MHz 频率偏移处,在TT 工艺角下,25℃常温时,该相位噪声为-116.46 dBc/Hz ,较前仿所测得的相位噪声有所下降,主要原因是后仿带来的寄生电容的不确定性。
电荷泵锁相环的压控振荡器设计
集成CMOS锁相环在电子、通信系统中得到了广泛应用。随着工艺特征尺寸降低,系统频率提高,抖动或者相位噪声成为制约锁相环应用的主要因素之一。
本论文研究标准CMOS工艺下电荷泵锁相环的噪声特性。首先,介绍了锁相环的基本工作原理,利用锁相环系统数学模型设计了环路参数,在此基础上,重点分析了锁相环的抖动与相位噪声特性,基于CSMC0.5μm CMOS工艺设计了一款用作频率合成器的差分结构的电荷泵锁相环。仿真结果表明:输出频率为900MHz时系统相位噪声为-110.4dBc/Hz@1MHz,RMS抖动为1.62ps,功耗为19.6mW。
合肥工业大学
硕士学位论文
电荷泵锁相环的压控振荡器设计
姓名:罗芳杰
申请学位级别:硕士
专业:电工理论与新技术
指导教师:高明伦;尹勇生
20090301
电荷泵锁相环的压控振荡器设计
在电路设计方面,本论文分析了标准CMOS工艺下低抖动、低相位噪声电荷泵锁相环晶体管级电路的实现方法。通过分析环形振荡器的延迟单元结构和相位噪声特性,设计了与标准CMOS工艺兼容的低相位噪声环形压控振荡器,该环形压控振荡器噪声性能接近LC压控振荡器水平。通过分析电荷泵的非理想因素,设计了低电流失配电荷泵,该电荷泵具有良好的电流匹配性能。最后,设计了差分电荷泵锁相环电路,差分结构有效的抑制了共模噪声的影响。
8.期刊论文陈志明.尹勇生.邓红辉.梁上泉.CHEN Zhi-ming.YIN Yong-sheng.DENG Hong-hui.LIANG Shang-quan
一种高性能4阶电荷泵锁相环的设计-合肥工业大学学报(自然科学版)2008,31(8)
文章设计了一款完全集成的高性能4阶电荷泵锁相环.根据系统性能要求,该锁相环的环路滤波器选用3阶无源低通滤波,其他模块在典型结构的基础上采取了改进措施以获得高性能.首先,利用MATLAB进行系统建模,获得锁定时间和环路参数;然后给出了关键电路的结构以及前、后仿真的结果.在
带自适应体偏置的宽带LC VCO自动幅度控制策略
带自适应体偏置的宽带LC VCO自动幅度控制策略周功孩;曾亦可;张科峰;赵阳【摘要】为了优化宽带LC型压控振荡器(LC VCOs)相位噪声性能,提出一种自动幅度控制策略.该策略结合了自适应体偏置和数字校准.当VCO开始工作时,自适应体偏置技术使VCO在不同的工艺角、电压和温度(PVT)情况下快速起振.当谐振频率变化时,在自适应体偏置和数字校准的作用下,VCO的谐振幅度被控制在最优值附近,达到优化相位噪声的目的.在TSMC 0.18 μm CMOS工艺中,覆盖频率范围为1.6~3.2 GHz的宽带LC VCO用来验证该幅度控制策略的可行性.基于SpectreRF的仿真结果表明LC VCO的幅度变化率降低90%,且在3.2 GHz谐振频率,10 kHz频率偏移处的相位噪声改善8.2 dB.%In order to optimize the phase noise of the wideband LC voltage controlled oscillators (LC VCOS), a strategy of automatic amplitude control is proposed. The strategy combines adaptive body-bias technique with digital calibration. When VCO works, the adaptive body-biased technique ensures the VCO oscillating as soon as possible regardless of PVT variations. When oscillation frequency is changed, by using of the adaptive body-biased technique and the digital calibration, amplitude of wideband VCO could be adjusted to the level of optimal value for phase noise optimization. A wideband LC VCO with oscillation frequency ranging from 1. 6 GHz to 3. 2 GHz is used to verify the feasibility of the proposed strategy, which is implemented in TSMC 0.18 祄 CMOS technology. SpectreRF based simulation results show amplitude derivation is reduced by ! Besides, phase noise at 3. 2 GHz carrier and 10 kHz frequency offset is 8. 2 dB better.【期刊名称】《现代电子技术》【年(卷),期】2012(035)020【总页数】4页(P169-172)【关键词】宽带LC VCO;自适应体偏置;数字幅度校准;相位噪声【作者】周功孩;曾亦可;张科峰;赵阳【作者单位】华中科技大学,湖北武汉430074;华中科技大学,湖北武汉430074;华中科技大学,湖北武汉430074;华中科技大学,湖北武汉430074【正文语种】中文【中图分类】TN919-34频率合成器作为无线通信系统中的核心模块,其相位噪声(Phase Noise)与调谐范围(Tuning Range)是衡量收发器性能的重要参数,它的优劣直接影响了收发机的灵敏度和传输信号的可靠性,而频率合成器的相位噪声性能主要取决于VCO,因此设计宽调谐范围、低相位噪声的VCO一直是研究热点[1-3]。
基于噪声滤波技术的24GHz+VCO设计
the VCO tuning range is 2.38GHz-2.52GHz, and the phase noise is -124.8dBc/Hz at 1MHz offset. It draws 2.5mA for VCO core and 13mA for output impedance matching from 1.8-V supply. The Shut-Down mode is integrated in this design and it only needs 8nA current. Key words: Noise Filtering Technology; VCO; AMOS
包括工艺偏差、温度变化等,均能正常工作,设计中有效跨导值取为(2)中需求值的 2 倍。
gNm gPm 2 gm min
2 RT
2rs (0 L)2
(3)
在该设计中,输出阻抗匹配通过片内集成的 Bias-T 结构实现,其输出源跟随器的 NMOS
管通过交流耦合连接于振荡节点中,且加入VDD 2 的直流偏置以保证其直流工作点满足较
Abstract- A 2.4-GHz LC VCO for Bluetooth/ZigBee application is presented in this paper. The VCO exploits the symmetrical noise filtering technology to reduce the impact of the tail-current source to the phase noise performance and accumulation MOS (AMOS) varactors which have a big Cmax / Cmin ratio to get a flat VCO tuning gain within the whole tuning range. The 50 output impedance matching is done with a Bias-T circuit on
CMOSVCO设计综述
CMOS VCO设计综述摘要:本文从相位噪声理论的发展和主流低噪声设计技术两个方面,阐述了CMOS VCO 的发展现状和未来的趋势。
在理论方面,从线性时不变模型到线性时变模型的发展成功的解释了低频噪声和高频谐波噪声转变为相位噪声的物理机理,为CMOS VCO的低噪声设计提供了理论依据和指导。
而随着理论的发展,新的优化技术也不断出现,例如高Q值电感设计技术,互补型结构,对称性设计,尾电流管滤波技术,Harmonic Tuning技术,Back to Back V aractor,AAC技术等等。
本文详细阐述了这些技术的优势和局限性,指出了未来的发展方向。
一.前沿无线通信的广泛应用和半导体工业的迅速发展使得全集成发射接收机(Transeiver)的设计成为一个重要的研究领域[1-7]。
在Transceiver中,压控振荡器是一个非常关键的模块,其位置如图1所示:图1. 接收机原理图由图1可以看出:VCO和鉴相器/电荷泵(PFD/CP),分频器(Divider)以及晶振(Xtal)一起构成了频率综合器,为混频器提供本振信号,实现对输入RF信号的频率搬移,如图2(a)所示:图2 (a)理想本振信号下频率搬移示意图;(b)带相位噪声本振信号下的频率搬移示意图图2(a)给出的是本振为理想信号情况下的频率搬移示意图,此时本振在频谱上表现为一个脉冲。
但是由于器件噪声等非理想因素,真实的本振信号在频率上表现为一个窄带信号(Skirts),如图2(b)所示。
这样,当所要信号附近有一个强干扰信号时,干扰信号就可能通过本振信号的边带搬移到中频处,从而干扰所要信号的正常接受。
表现在接受机性能上,就是会降低选择型(selectivity)和敏感度(Sensitivity)[8]。
设计人员习惯用相位噪声(Phase Noise)来表征本振信号边带的大小(第二节会详述),因此降低本振信号的相位噪声成为提高接受机性能的关键。
频率综合器的各个模块包括VCO,Xtal,PFD/CP以及Divider都会引入噪声源影响本振信号的相位噪声,但是由于噪声引入位置的不同,对于Xtal,PFD/CP,Divider 处的噪声PLL表现出低通特性而对于VCO的噪声PLL表现出高通特性[16]。
vco压控振荡器
All rights reserved. HSPICE, SYNOPSYS.In this document, you will see the circuit construction of a “voltagecontrolled oscillator” and how different key parameters are simulated with HSPICE RF.VCOVoltage controlled oscillator (VCO) is widely used in wireless communication systems, such as frequency synthesizer. A high performance VCO should be carefully considered from a lot of aspects. HSPICERF provides powerful tools, which take care of every characteristics of VCO and make complicated design easy to implement.Below is the circuit schematic that we will discuss in this document:Figure 1. VCO schematicIn this part, a vco is designed to oscillate at 1.6v.1.Oscillator Simulation – Steady-State Signal SimulationIn this figure, M4~M7 are parallel connected PMOS, which are used as varactors for frequency tuning purpose; M1~M3 offers negative conductance to fulfill the oscillating pre-condition; R0 and R1 is used to represent the parasitic resistance of L0 and L1; m_mult is a parameter, which is defined as the parallel connected PMOSsnumber. By tuning the m_mult value, we can get a frequency value that more close to 1.6GHz.In order to achieve a proper m_mult, we can use sn sweep function. Here, Synospsys SIMIF is used to setup new analysis and generate netlist. The setting is shown below.This setting will insert a command as.sn tone=1.6g nharms=10 trinit=100n oscnode=out1 SWEEP m_mult LIN 10 500 560into netlist.Several ways can be used to stimulate an oscillator∙Using IC on an inductor∙Using a PWL source to inject a pulse or ramp VDD.∙Using UIC option in the analysis command.Here, we use the first method.Add a probe command in an include file (inc1.spi) as.probe snfd param=Hertz[1]The sn result will beSo, we can set m_mult=518 as the number that we will use later.2.PhasenoiseAs other analog circuits, oscillators are susceptible to noise. In noisy environment, output signal will change in amplitude and period. Phasenoise is used to evaluate oscillator‟s random deviation of the frequency. HSPICERF has the special .phasenoise command to support non-autonomous circuit simulation.Phasenoise can only be used with .sn or .hb.Below is SIMIF setting to perform phasenoise analysis:It will insert.phasenoise v(out1) DEC 10 1K 10e6 into the netlist.And the simulation result isSo, the phasenoise is -96.25dBc@60KHz.3.JitterPhasenoise can also be explained as JITTER. So jitter calculation is based on the phasenoise analysis. If the keyword JITTER is added following a phasenoise print/probe, for example .probe/print PHASENOISE phnoise jitter. Then jitter value will be dumped to a *.snjt#/*.printsnjt0.Another way to evaluate jitter value is jitter measurement. Z-2007.03 hspicerf release supports RMS jitter, phase jitter, tracking jitter, period jitter, long-term jitter and cycle-to-cycle jitter.The following sentences will be inserted into inc.sp file to produce jitter.*****************measurement command**************.measure phasenoise rms_jitter RMSJITTER phnoise from = 1K to = 1MEG.measure phasenoise per_jitter PERJITTER phnoise from = 1K to = 1MEG.measure phasenoise lt_jitter LTJITTER phnoise from = 1K to = 1MEG.measure phasenoise ctc_jitter CTCJITTER phnoise from = 1K to = 1MEG********************** end *********************Jitter result is stored in *.msnnoi#.DATA1 SOURCE='HSPICERF' VERSION='Z-2007.03'.TITLE '* Generated by: Simulation Interface Version Z-2006.06-SP2-ENG2'ctc_jitter lt_jitter per_jitter rms_jitter temper alter#3.674322e-17 5.745042e-12 1.617088e-154.062358e-1225.000000 14.VCO gain (tuning characteristic)Use SWEEP option in SN command will produce the oscillating frequency VS control voltage.Set the control voltage as a parameter first, named v_ctrl. Then sweep this parameter. Below is the SIMIF setting:This setting will produce a command -- .sn tone=1.6g nharms=10 trinit=100n oscnode=out1 SWEEP v_ctrl LIN 6 0.2 0.7Another sentence is necessary in order to achieve an intuitionistic result..probe snfd param=Hertz[1]The result is stored in *.snf#.K0 = 41.8 MEG/V5.Summary6.Reference[1] Behzad Razavi, “ RF Microelectronics”, Chapter 7.[2] James F. parker and Daniel Ray, “A 1.6-GHz CMOS PLL with On-Chip Loop Filter”.[3] “HSPICE RF user guide Synopsys”,Chapter 9, …Steady-State Shooting Newton Analysis‟, pp. 225, Sep. 2006.[4] Jaijeet Roychowdhury, David Long and Peter Feldmann, “Cyclostationary Noise Analysis of large RF Circuits with Multitone Excitations”, IEEE Journal of Solid-states, vol.33, March 1998.。
3_7GHz宽带CMOSLCVCO的设计
317GHz 宽带CMO S LC VCO 的设计王云峰,叶青,满家汉,吴永俊,陈勇,叶甜春(中国科学院微电子研究所,北京100029)摘要:设计了一款317G H z 宽带C MOS 电感电容压控振荡器。
采用了电容开关的技术以补偿工艺、温度和电源电压的变化,并对片上电感和射频开关进行优化设计以得到最大的Q 值。
电路采用和舰0118μm C MOS 混合信号制造工艺,芯片面积为014mm ×1mm 。
测试结果显示,芯片的工作频率为314~4G H z ,根据输出频谱得到的相位噪声为-100dBc/H z @1MH z ,在118V 工作电压下的功耗为10mW 。
测试结果表明,该VC O 有较大的工作频率范围和较低的相位噪声性能,可以用于锁相环和频率合成器。
关键词:电感电容压控振荡器;宽带;片上电感;射频开关;锁相环中图分类号:T N838 文献标识码:A 文章编号:10032353X (2008)1221126204Design of 317GH z Wideband CMOS LC VCOWang Y unfeng ,Y e Qing ,Man Jiahan ,Wu Y ongjun ,Chen Y ong ,Y e T ianchun(Institute o f Microelectronics o f Chinese Academy o f Sciences ,Beijing 100029,China )Abstract :A 317G H z wideband C MOS LC VC O was designed.Capacitance switching technique was used for com pensating the variance of rocess ,tem perature and the supply.S ome optimization designs were made with the on 2chip inductor and the RF switches to get the maximum Q 2value.The VC O was fabricated in Hejian 0118μm C MOS mixed signal process ,the chip area was 014mm ×1mm.Measurements show that the operating frequency covers 314to 4G H z ,according to the output spectrum ,the phase n oise is -100dBc/H z @1MH z offset while dissipating 10mW from 118V supply.Measure results show the VC O has a large operating range of frequency and low phase noise ,it can be used in P LLs and frequency synthesizers.K ey w ords :LC VC O ;wideband ;on 2chip inductor ;RF switches ;P LL EEACC :1250;1230B0 引言用于射频系统(如无线接收机)的本振电路需要有足够大的调节范围以及良的性能。
VCO Design With On-Chip Calibration System
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 10, OCTOBER 20062157VCO Design With On-Chip Calibration SystemPaavo Väänänen, Niko Mikkola, and Petri HeliöAbstract—This paper presents a low-supply voltage integrated CMOS voltage-controlled oscillator (VCO) with an on-chip digital VCO calibration control system. The VCO utilizes various state-ofthe-art design methods to achieve low phase noise. The calibration system includes a novel high-speed digital divide by two circuit and a counter running on 1-GHz input to enable on-chip frequency measurement. An arithmetic unit and algorithms to perform the calibration are implemented using on-chip logic. Two different types of calibration methods have been implemented and measured in order to compare the proposed VCO gain optimization method with more conventional type of VCO calibration. The measurements show that the VCO design has phase noise from 120.5 dBc/Hz to 118.7 dBc/Hz @ 400-kHz offset, measured over the frequency range from 1.67 to 1.93 GHz. The proposed VCO gain optimization method is capable of reducing the VCO peak-to-peak variation of the presented VCO design from 54.4% to 29.8% in DCS1800 and PCS1900 GSM transmission bands when compared to the conventional type of calibration method. Index Terms—Circuit tuning, CMOS mixed mode circuits, low voltage, phase noise, voltage-controlled oscillator (VCO), VCO calibration, VCO gain.I. INTRODUCTIONDESIGNING an integrated voltage-controlled oscillator (VCO) for communication systems is becoming more and more challenging as the number of the frequency bands that need to be supported by the phase-locked loop (PLL) increases. At the same time, low cost and low supply voltage CMOS processes are used not only for digital but also for RF integrated circuit (IC) designs. Lowering the supply voltage sets a need for coarse automatic frequency calibration, since as said in [1], it is otherwise impossible to cover multiple system bands with and charge pump sufficiently low average VCO gain output voltage range limited by the low supply voltage. The VCO gain needs to be set sufficiently low in order to prevent noise and interference coupling through the control voltage interface. oscillator core used in the preVaractor tuned negativesented design is a common architecture solution for low-phase noise VCO designs. A dependable way to implement coarse frequency calibration control for this type of VCO is to connect a digitally tunable capacitor array in parallel with the varactor [2]. In addition various state-of-the-art design methods are used to achieve low VCO phase noise.Several approaches have been published for building a measurement system and calibration algorithm that selects the right calibration word for digitally tunable capacitor array so that the frequency of the VCO settles as close as possible to the predefined target frequency value before PLL locking [1], [3], [4]. However, channel-to-channel VCO gain variation can still be large after this type of calibration. This work shows that and consequently PLL loop bandwidth variation can be reduced by using slightly more complicated VCO calibration word selection. The proposed on-chip calibration system of the VCO is targeted firstly to select suitable calibration word to produce the right frequency and secondly to select it in such a way that the variation is minimized. The target specification for the VCO design is 35 MHz/V. The system building blocks also include a new digital divide by two architecture capable of operating with the highest required input signal frequency and an asynchronous counter operating at output frequency of the divider. The digital to analog converter used in the design is not presented in details since it is a basic voltage scaling resistor string based design. Calibration and optimization algorithms are implemented using on-chip logic only. The system architecture and building blocks are described with further details in Section II. On-chip hardware solution was set as target in order to keep the software interface to the master system controller simple and to minimize the needed data exchange over the control interface. Calibration is based on fast on-chip frequency measurements and then performing a series of basic arithmetic operations to estimate the right tuning word. Only configuration and control are needed, otherwise inputs, like target frequency and the algorithms are running independently on-chip. Two different algorithms, called the basic frequency calibration and the optimization, will be presented with system simulation results in Section III. The VCO with the calibration system has been implemented using a 1.2-V 0.13- m bulk CMOS process. The experimental results are presented in Section IV. II. SYSTEM ARCHITECTURE AND BLOCK DESIGNS A. System Architecture The proposed on-chip VCO calibration system architecture is shown in Fig. 1. During calibration the voltage control input of the VCO is connected to the calibration digital-to-analog converter (DAC) output, the digital input of which comes from the calibration logic. In normal operation mode, when the VCO is part of the PLL, the control voltage is driven by the PLL loop filter. The digital calibration word of the VCO is controlled by the calibration logic in both modes. The VCO output signal is connected to the divide by two circuits to perform the frequency measurements needed for calibration. The differential quadrature output of the divider is fedManuscript received October 20, 2005; revised April 2, 2006. This paper was recommended by Associate Editor J. Silva-Martinez. P. Väänänen is with Nokia, Tampere FIN-33100, Finland, and also with the Institute of Communications Engineering, Tampere University of Technology, Nokia, Tampere FIN-33100, Finland (e-mail: paavo.vaananen@). N. Mikkola and P. Heliö are with the Nokia, Nokia, Tampere FIN-33100, Finland. Digital Object Identifier 10.1109/TCSI.2006.8838441057-7122/$20.00 © 2006 IEEE2158IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 10, OCTOBER 2006Fig. 1. Proposed VCO calibration system architecture.to a block that consists of four asynchronous counters, which work as a frequency measurement device. The counters are enabled by a strobe signal coming from the calibration logic. The and so the counter values at the end of strobe length is each measurement are proportional to the VCO frequency with and the pre-division ratio. The a resolution defined by calibration logic produces the strobe by division from the reference signal RefCLk that is assumed to be a low jitter clock signal, for example the PLL reference frequency source. The system is configured and controlled through a serial data interface which is a part of the calibration logic block. The measurement sequences and the VCO calibration routines are launched and controlled by the on-chip state machines. The essential sub-block designs are presented in detail in the following sections. B. VCO Design The VCO topology used in the design is presented in Fig. 2. It consists of a cross-coupled pMOS pair with a pMOS curat the tail. To cover the frequency range of rent source DCS1800 and PCS1900 TX bands with adequate margin for the process variation, a switched capacitor array is connected in parallel with the pn-junction varactors. The 5-bit capacitor array is used to increase the overlapping between the voltage to frequency transfer curves of the VCO. This enables the use of smaller range of tuning voltage and so it further decreases the . To variation of tuning voltage sensitivity of the VCO increase the accuracy of the switched capacitor array, a structure that has 32 switchable unit capacitors with identical dimensions has been used. The binary coded control is converted to a thermometer code control to set only one unit capacitor active or inactive when the calibration word is changed to decrease or increase the frequency. The capacitors in the array are formed by using a multi-finger capacitor structure. The benefit of the multi-finger structure is that extra processing steps are not needed. An alternative solution without extra processing steps is to form the capacitor array by using MOS varactors [1], [5]. that has Q-value of 10 @ 2 With the differential inductor GHz and 10-mA bias current for the pMOS cross-coupled pair, the VCO output swing is about 1.2 - (single ended). A differential nMOS push–pull type amplifier feeds the signal out of the chip. produces lowThe flicker noise in the tail current source frequency random amplitude modulation (AM), which modu, converting AM into lates the capacitance of the varactorsFig. 2. VCO.frequency modulation (FM) [6], which results in close-in phase noise. Recently, it was recognized [7]–[9] that the noise from the tail current source is the main contributor to the phase noise shaped phase noise close to in a VCO, especially in the the oscillation frequency. In this study, several design methodologies have been used to decrease the bias noise contribution to the overall VCO phase noise. First, pMOS instead of nMOS tail current source is employed to lower the flicker noise in the tail current since the flicker noise in pMOS devices is lower than in nMOS devices due to the buried channel behavior [10]. Second, to lower the flicker noise further, the tail current is scaled up while keeping constant. A long-channel FET at the current source lowers the flicker noise which upconverts into close-in phase noise around the oscillation frequency [11]. Third, the varactor AM–FM conversion is decreased by keeping the tuning sensitivity of the varactor relatively low. The required tuning range is covered mostly with the switched capacitor array instead because fixed capacitors do not convert AM into FM, only varactors do so [12]. Fourth, pn-diode varactors are used instead of MOS varactors. MOS varactors have steep C(V) characteristic and with such a steep characteristic, the resulting oscillation frequency strongly depends on the oscillation amplitude. If not properly taken into account, this effect can limit the tuning range of the oscillator and increase the level phase noise [6]. With these four bias noise reducof the tion methods, the bias noise contribution to the phase noise is minimized and the cross-coupled pair M1 is the main source of the phase noise. In the cross-coupled pair, again the pMOS transistors (see Fig. 2) are used to lower the flicker noise. The differential pair FETs employ also non-minimum channel lengths to suppress the flicker noise further. The selected pMOS VCO topology provides an excellent noise isolation from the power supply to the sensitive resonance tank. This is extremely important when an on-chip regulator without an external capacitor is used. Substrate coupling has been minimized by using separate substrate ground bonding wires for VCO and other blocks. Further, floating n-doped guard rings have been used to increase impedance between different grounds. All-pMOS VCO topology provides also aVÄÄNÄNEN et al.: VCO DESIGN WITH ON-CHIP CALIBRATION SYSTEM2159slightly better Q of the tank compared to a VCO with a nMOS cross-coupled pair. In nMOS VCO, the parasitic diode of the varactor cathode loads the resonance tank, where as in pMOS VCO the parasitic diode is connected to a virtual ground and has no effect on Q [12]. The AM–FM conversion of the MOS varactors strongly depends on the control voltage [13]. In this study, pn-diode varactors instead of MOS varactors are used in the resonance tank and now the measured phase noise is independent of the control voltage. C. Divider Design The IQ-divider is implemented by using standard digital logic cells and all the signals have rail-to-rail swings. By using full voltage swings in divider internal nodes, transistor turn-on time can be shortened and thus the conversion gain for both amplitude noise (AM) and phase noise (PM) can be cut down [14], [15]. Rail-to-rail flip-flop (FF) based dividers are often called as dynamic dividers. The major drawback is that due to the large signal swings they consume more power than source-coupled logic (SCL) dividers [14], [16], [17]. However, dynamic dividers are often preferred, because they can be realized with a simple structure and obtain lower noise floor than SCL dividers [14]. The third method to implement high-speed dividers, reduced transistor count CMOS dividers, have also been studied in many publications [18]–[20]. It is possible to obtain high-speed operation, with moderate power dissipation and low supply voltage by reducing the transistor count. Drawbacks are that the output swing may not be anymore rail-to-rail, the output duty cycle may be far away from 50%, and circuit may also become very narrow banded when compared to dynamic dividers. Thus, the optimum solution could be a circuit which is utilizing both approaches, a dynamic divider with minimum number of devices in the signal path in order to minimize the power dissipation. The proposed circuit, shown in Fig. 3, is quite close to the digital dynamic divider topology shown in [14]. It has similar shift register structure, but does not contain the inversion cell on signal path. In simulations, removing the inverter from the signal path improves the maximum operation speed by 36%. On the other hand, the circuit is very close to reduced transistor count divider presented in [18]. The difference is that, in the proposed topology, the signal path is built using standard logic tri-state inverters instead of clocked nMOS pairs. This approach provides better drive capability than [18], when an output is driven towards logical zero, and hence improves the matching between rise and fall times of the pulse edges. Basically the proposed divider acts like a digital shift register. One pair of the clocked tri-state inverters (e.g., topmost IT cells) form one data FF, and the second pair (e.g., bottom IT cells) form another FF. Tri-state inverters (IT) are used . The output to drive the output nodes signal state is changed when the input clock is enabling the tri-state inverter. At the high-impedance state, the states are stored into the parasitic capacitance of the nodes . The parasitic capacitances consist mainly of the next stage gate capacitance and the signal routing capacitances. Contrary to the traditional dynamic dividers [14], [16], where a single inverter in the loop is used to achieveFig. 3. IQ-divider core.the positive feedback, here the inversion is obtained by using a symmetrical unbalance circuitry. The unbalance circuit is realized by using a simple nMOS latch like in [18]. The latch ensures that all the output nodes have and keep the different phases in all conditions. The latches present an equal load , and capacitance for each of the nodes hence accurate phase balance and 50% duty cycle can be obtained easily. Consequently, the proposed divider topology provides a simple, easily scalable circuit structure, with all the performance advantages of a dynamic divider and CMOS logic compatible output interface. D. 1-GHz Frequency Counter Design Dividing the VCO output frequency by two before the measurement reduces the counter based frequency measurement resolution. Measurement resolution is limited by (1) where represents the frequency resolution is the frequency division ratio, and is the used measurement time. But since the presented divider has a differential quadrature output, each of the divider output signal cycles can be detected on four different instants and so the limit (1) is divided by factor of four and becomes (2) Therefore, using the quadrature divider and the counters for each divider output branch provides a better measurement accuracy versus used measurement time than using just one of the divider output branches as the measured signal. In practise, the resolution enhancement predicted by (2) is not achieved since both the quadrature and the differential imbalance of the divider cause systematic error. The schematic of one counter branch is shown in Fig. 4. An asynchronous CountStrobe from the calibration logic is synby using a simple synchrochronized to the input clock nizer (sync) block. Output of the synchronizer block drives the first divide-by-two stage. One divide-by-two stage is consisting and an output connected of an FF having a data input is driving the with an inverter. The output of the first FF2160IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 10, OCTOBER 2006Fig. 4. Binary counter.Fig. 5. Calibration logic block diagram.next asynchronous divide-by-two stage. Because the output frequency of the first divide-by-two stage is only half of the input clock frequency, second divide-by-two stage needs to operate only at half the frequency. By cascading multiple divide-by-two stages, asynchronous divide-by- chain is obtained. A digital , , , and IQ-counter function with the outputs is obtained by using four similar divider chains for the , , , and . inputs E. Tuning Logic Architecture The tuning logic consists of the top-level building blocks shown in Fig. 5. The tuner controller and register interface takes care of system interfacing to the external control through the serial interface. It also acts as a calibration system sequencer enabling the frequency measurements as well as calculations performed by arithmetic unit according to the configuration and control commands coming from the system main controller unit. The reference counter is a programmable synchronous counter that produces the count strobe and counts the delays needed for the DAC and the VCO settling before a measurement. The arithmetic unit is capable of performing signed multiplication, adding, and shifting and so it enables the calculation procedures to be executed during calibration. The block called arithmetic unit control and registers contains registers to store the asynchronous counter measurement results and the calculation results, as well as the sequencing instructions for the arithmetic unit for the calculation procedures to solve the VCO calibration word. In other words, it contains in hardware the two presented VCO calibration algorithms, the basic frequency optimization, and the data memory for tuning and the them.Fig. 6. Basic frequency tuning algorithm flow.III. CALIBRATION ALGORITHMS A. Basic Frequency Calibration The proposed basic frequency calibration algorithm can be used for fast coarse calibration of VCO frequency before locking the PLL loop, like the methods presented in [1], [3], [4]. optimization to find It has been used also as a part of the the first calibration word guess for the optimization algorithm. The flow diagram of the algorithm is shown in Figs. 6 and 7. The calibration procedure is started with three frequency measurements made on one pre-defined DAC word and three , , and . The correpredefined calibration words sponding VCO frequency for each measurement point with can be estimated using the counter values , , , and and the following equation:(3) where the pre-division value and the measurement time are known parameters. After the three measurements have been performed the rest of the tuning process is pure calculation. The idea is to model dependence using a the VCO frequency calibration word simple second-order polynomial approximation (4)VÄÄNÄNEN et al.: VCO DESIGN WITH ON-CHIP CALIBRATION SYSTEM2161Fig. 8. Simulated VCO frequency versus voltage characteristics on DCS1800 when basic calibration is used.Fig. 9. Simulated frequency versus voltage characteristics on DCS1800 when basic calibration is used.KFig. 7. TheKoptimization algorithm flow.To get the coefficients , and we need to solve(5)beOnce the coefficients are solved we can define error and the VCO fretween the predefined frequency target quency estimate given by (4) for any calibration word as (6) The calculated absolute error is compared to the absolute error stored during previous iteration rounds or to the set initial value. If is found to be smaller than the stored error value, its stored and used as comparison reference for the next round. The found tuning word is stored as the new candidate for the final VCO calibration word.In the next phase, a new iteration step and value of is defined for the next iteration round. If all the required words have been scanned, the algorithm converges and the value that is stored is set as the VCO calibration word. The basic frequency calibration algorithm simply minimizes the error given by (6) and so the VCO control voltage difference after PLL locking from the predefined tuning voltage used in the characterization measurements. Figs. 8 and 9 present a simulations of the basic tuning algorithm for DCS1800 GSM TX channels. The tuning voltage is set by DAC to 600 mV, which is in the middle of the supply range and therefore optimum when considering a charge pump design with same supply voltages. The polynomial coefficients have been defined once, and the VCO calibration words have been solved using the same coefficients for the rest of the channels. The VCO frequency versus the control voltage with the VCO calibration word selected by the tuner logic is shown in Fig. 8. In other words, each of the tuning characteristic lines presents different calibration word selected by the algorithm when sweeping the frequency channels. It can be seen that the calibration word is selected in such a manner that it tends to minimize the VCO tuning voltage deviation. However, because of the limited accuracy of calculation and for the fact that in practice the VCO frequency versus the calibration word characteristic does not precisely follow the polynomial model2162IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 10, OCTOBER 2006the mid voltage does not accurately settle in to the predefined DAC value. as a function of the target frequency for DCS1800 varies from 26.5 band is shown in Fig. 9. It shows that to 37.8 MHz/V and thus the maximum error compared to target value of 35 MHz/V is from 24.0% to 8.0%. The same simulation and analysis made for PCS1900 band gives variation from 34.4 to 47.2 MHz/V, i.e., from 1.6% to 34.7%, when compared to the target. The overall peak-to-peak VCO gain variation with the presented VCO design is 54% over the two target bands. The proposed calibration algorithm can be divided into two parts; measurements and coefficient calculation being the first part and finding the right calibration word by using the coefficients the second. In the system simulation of the presented implementation with 40-MHz clock beat and 100-kHz measurement resolution, the first part takes 36.1 s and the second part takes 8.98 s. The measurement and coefficient calculation part does not have to be performed every time that the channel is changed and the coefficients are valid until environment, e.g., temperature, changes too much. The coefficients can be updated from time to time to cope with temperature changes or a temperature dependent term may be introduced in (6). B. OptimizationUsing the slope approximation of (7), we can define the estimate for VCO gain as a function of voltage (8) where is the calculated VCO gain estimate on middle tuning voltage used in characterization measurements. In the next phase, an estimate for the control voltage that produces the , the estimate for wanted frequency is solved. Since VCO gain change as function of voltage, is now known we can on tuning define the frequency for any voltage estimate word as (9) The frequency for voltage (9) and (8). can be approximated using(10) Simple iteration loop can be utilized to find the voltage that minimizes the difference between the frequency estimate given . After the voltage estimate is by (10) and the predefined error for calibration word can obtained, the be evaluated using (8) as (11) Once this all is done for , the algorithm changes the calibration word for the next round of error calculation by 1 . If the error is positive it means according to sign of that the calibration word value should be decreased to increase the varactor tuning voltage and digitally tunable capacitor array capacitance for lowering the VCO gain in target channel. If the error sign is negative, the calibration word should be increased. The estimates given by (7) and (10) are used again to define error for the new calibration word candidate. After that the voltage is checked against the predefined limits to insure that the result is sensible. If the check is passed, the errors are compared and if changing the tuning word produces smaller error, a new candidate for the optimized calibration word is stored. This procedure is repeated as long as the check of the found voltage estimate is passed or absolute value of the eserror starts to increase. Thereby the algorithm timated selects the tuning word that according to the presented approxiclosest to the predefined on the mations has . target frequency The simulated frequency versus voltage characteristics of VCO tuned on DCS1800 GSM TX channels is shown in target was set to 35 MHz/V. The optimization Fig. 10. algorithm selects the calibration words so that the VCO tuning voltage for the target channel settles to value that produces the value according smallest error compared to the target to (11). Compared to the basic frequency calibration, this requires using wider VCO tuning voltage range. The need of wider voltage range can be seen when comparing the frequencyoptimization is to decrease the The target of the channel-to-channel VCO gain variation over the frequency band of interest that is caused by non-linear varactor. The method is very similar to the basic frequency tuning but in this behavior as a function of the VCO case modelling of the control voltage is required, which obviously requires more measurements. The flow diagram of the algorithm is shown in Fig. 7. The optimization starts with nine measurements performed with three different predefined VCO tuning voltages and VCO calibration words. Frequencies for each measurement point are defined using (3). To model the VCO, (5) is solved for the set of measurements performed with predefined DAC words. This will , and . Those are the lowest, set the control voltage to , the middle, and the highest measurement tuning voltage, respectively. After that, the polynomial model of (4) can be used to , , calculate the VCO frequency estimates and for any calibration word with the three respec, and . tive voltages , The presented basic frequency calibration algorithm is performed using the coefficients obtained from the measurements is with the middle DAC word. The found calibration word optimization. Estimates used as a starting point for the , , and are calculated and the optimization is carried on by making coarse approximadependence on voltage is linear. The slope tion that the for can be estimated as(7)VÄÄNÄNEN et al.: VCO DESIGN WITH ON-CHIP CALIBRATION SYSTEM2163Fig. 12. Micrograph of the VCO and the calibration system.Fig. 10. Simulated VCO frequency versus voltage characteristics on DCS1800 optimization is used. whenKTABLE I SUMMARY OF VCO MEASUREMENT RESULTSFig. 11. Simulated DCS1800 whenKKfrequency versus voltage characteristics on optimization is used.versus voltage characteristics in Fig. 8 and the ones in Fig. 10. For example, both algorithms select the very same calibration word for the lowest frequency channel, but the channel to make the first change of the calibration word is different. The optimization changes the calibration word in lower frequency channel than the basic frequency tuning, in such a way that the required tuning voltage is lowered to increase the VCO gain in the target frequency. variation can be seen in Fig. 11. The The effect on and it variation is more centralized around the target ranges from 30.4 to 40.0 MHz/V giving percentage variation of 13.1% to 14.4%. Similar simulation and analysis for PCS1900 GSM TX band produced variation from 32.1 to 42.2 MHz/V, i.e., 8.3% to 20.6%. According the simulations, it is clear that the presented optimization does not provide an optimization result due to errors rising from the ideal polynomial approximation of frequency versus calibration word characteristics and the poor linear approximation of as function of voltage. However peak to peak percentaged is cut down from 54.0% to 33.7%. This variation of reduces the PLL closed loop response variation significantly if we assume that the variations of the other loop components donot change. In order to get full benefit from the VCO gain optimization for a PLL design, chargepump needs to be designed in such a manner that its output voltage range covers the required VCO tuning voltage range. Better accuracy could be reached by using a more accurate approximation for the VCO gain dependence on voltage but this would increase the calculation complexity as well as the calibration time. The linear model was selected to guarantee suitable silicon area requirement since pure on-chip hardware solution for VCO calibration was set as a target. When analyzing the calibration time of the proposed optimization algorithm, we can divide it again in two parts as we did with the presented basic frequency calibration. Measurements and coefficient calculation takes naturally more time since they are performed for the three different tuning voltage values. With same clock and measurement timing setup that has been presented for the basic frequency tuning, the first part takes optimization 115.8 s and basic calibration together with 56.8 s according to the system simulations. IV. EXPERIMENTAL RESULTS The VCO with the calibration system was implemented in 0.13- m bulk CMOS process and all the blocks operate on 1.2-V supply. The chip micrograph is presented in Fig. 12. A. VCO Core Measurements A summary of the VCO performance is given in Table I. The measured center frequency of the VCO, as shown in Fig. 13, is 1.8 GHz. The VCO has a continuous tuning range of 2.5%。
低压CMOS压控振荡器设计
低压CMOS压控振荡器设计作者:徐仁伯来源:《硅谷》2008年第12期[摘要]通过对LC压控振荡器原理的分析,设计了一种新型CMOS集成压控振荡器。
该电路通过利用振荡器的输出产生高电压来控制开关电容阵列的开启来实现输出频率在不同频段中转换,从而提高输出频率范围和降低相位噪声。
电路采用TSMC18rf工艺,用Cadence的Spectre工具进行仿真。
结果表明:在0.6V的电源电压下,频率覆盖了2.07GHz 到2.78GHz,可调控范围约为29%,总功耗约为1.8mW,1MHz频偏处相位噪声约为-120dB/Hz,满足了设计要求。
[关键词]压控振荡器低压宽频带电容阵列中图分类号:O46文献标识码:A 文章编号:1671-7597(2008)0620030-02压控振荡器(VCO)是现代无线电通信系统的重要组成部分。
在当今集成电路向尺寸更小、频率更高、功耗更少、价格更低发展的趋势下,应用标准工艺设计生产高性能的压控振荡器已是射频集成电路中的一个重要课题[1][2]。
环形振荡器易于集成,可调频率范围大,但相位噪声不如性能不如LC振荡器。
LC压控振荡器要求高品质因素的无源器件,需要片上电感和变容管器件才能集成[3]。
本文通过一个电压提升电路,利用电路的输出产生一个相对高的电压,用以控制开关调谐电容阵列的开启,实现输出频率在不同频段中转换。
尽管电源电压接近MOS管阈值电压,但仍实现了高频、低压、宽调谐范围的性能。
一、电路设计(一)宽频带频率调节电路对于低压VCO电路,仅仅利用调节可变电容的大小而改变输出频率,频率的可调范围受到可变电容变容范围和控制电压VCON变压范围的限制,而且随着频率变化范围的增大,压控增益Kv也将增大,输出特性曲线就会出现弯曲,相位噪声性能将会变差。
宽频带低LC压控振荡器设计的关键是解决如何在扩展调节范围的同时而不降低电路的噪声性能和增加压控增益Kv。
为了解决这一难题,本文通过在输出并联一个开关调谐电容阵列,将一个宽带调谐范围分段为多个窄带范围来进行调节[5]。
2.6GHz高速CMOS环形振荡器设计
2.6GHz高速CMOS环形振荡器设计肖乃稼;何晓雄;崔华锐【摘要】文章提出了一种偶数级环形振荡器的设计方案,中心频率为2.3 GHz,利用起振电路使其能够快速起振,当环形振荡器的控制电压为1.2~2.0V时,其线性调谐范围为1.9~2.6 GHz;电路设计采用TSMC 0.18μm 1P6M混合信号生产工艺;利用Cadence Spectre RF进行仿真.结果显示,在中心频率为2.3 GHz、偏移载波频率为10 MHz的情况下,环形振荡器的相位噪声为-112.9 dBc/Hz.该电路可用于高速锁相环的设计中.【期刊名称】《合肥工业大学学报(自然科学版)》【年(卷),期】2018(041)008【总页数】6页(P1059-1064)【关键词】压控振荡器;环形振荡器;相位噪声;偶数级;起振【作者】肖乃稼;何晓雄;崔华锐【作者单位】合肥工业大学电子科学与应用物理学院,安徽合肥 230009;合肥工业大学电子科学与应用物理学院,安徽合肥 230009;中国电子科技集团第二十四研究所,重庆 400000【正文语种】中文【中图分类】TN753.5随着集成电路设计和生产工艺的快速发展,集成电路已经进入系统级芯片(systemon chip,SoC)阶段。
锁相环(phase-locked loop)作为片上系统中的时钟源,广泛应用于各类SoC芯片中,其性能决定了整个系统性能的好坏。
而压控振荡器(voltage-controlled oscillator,VCO)是锁相环电路中工作频率最高的单元,也是最核心的单元,人们对如何获得高频、低相位噪声、快速启动时间、较小版图面积的压控振荡器进行了广泛的研究。
在集成电路中压控振荡器主要分为环形振荡器和LC振荡器2类。
LC振荡器需要在片上集成电感,因此会占用很大的芯片面积;而环形振荡器结构相对简单,易于用互补金属氧化物半导体(complementary metal-oxide-semiconductor,CMOS)工艺实现,有着较小的版图面积,因而得到了广泛的应用。
差分LCVCO的设计方法
差分LC VCO的设计方法第28卷第4期2005年12月电子器件ChineseJournalofElectronDevicesV o1.28No.4Dec.2005DesignMethodinOptimizationDifferentialLCVCOMANJia—han,ZHAoKUn (InstituteofMicroelectronicofChineseAcademyofSciences,Beijing100029,China) Abstract:AnanalysisoftWOfamousoscillatorphase—noisemodulesderivestherelationsbetweenphase—noiseandcircuitparameters.Andhence,adesignstrategytooptimizethephasenoiseofVCO, suchasdesigninghighQinductor,adjustingtailcurrentandsizingthedimensionsofnMOSandpMO S,ispre—sented.Attheendofthispaper.a2.4GHzfullyintegratedVCOdesignismentioned.Thesimul ationre—sultdescribesthatthephasenoiseoftheVCOis一120.4dBc/*********************************methodiSvalid.Keywords:integratedLCVCO;noise;phasenoise;phase—lockedloopEEACC:2220;1220差分LCVCO的设计方法满家汉,赵坤(中国科学院微电子研究所,北京100029)摘要:通过分析振荡器的两种典型相位噪声模型,给出了振荡器相位噪声与电路参数的关系.在此基础上,提出了优化VCO相位噪声的设计方法:设计高Q值电感;调整尾电流的大小;调整nMOS管和pMOS管的尺寸.文章最后给出了一个2.4GHz全集成VCO的设计,仿真结果表明在2.4GHz时VCO的相位噪声为一120.4dBc/Hz@600kHz,证明该方法对于VCO的设计具有较好的指导作用.关键词:集成LC压控振荡器;噪声;相位噪声;锁相环中图分类号:TN75文献标识码:A文章编号:1005—9490(2005)04—0809—04近年来,无线通讯技术的迅速发展和无线通讯市场的不断扩大使得射频IC的设计成为微电子领域中的热点.作为射频IC的关键组成部分,压控振荡器(VCO)的设计自然成为了研究的热点,尤其是如何利用CMOS工艺设计实现高性能的集成VCO.相关的研究工作一直在不断进行,近十年来出现了大量的相关文章.其内容包括:片上电感的设计[引,片上可变电容的设计.],设计集成VCOc和振荡器噪声模型分析It-9]等.上述文章大多关注具体的设计问题,对于设计方法的研究则略显不足.本文通过分析振荡器的噪声模型和振荡器内部的非线性因素,结合仿真结果,给出差分集成LCVCO的一种设计方法.1LC振荡器噪声模型的分析振荡器的噪声模型对于振荡器的设计有很大的指导作用.到目前为止,对于振荡器的噪声机理已经进行了大量的研究.在这些噪声模型中,Leeson模型[7],Razavi模型[8和Hajimiri模型[9]是三个比较着名的噪声模型.由于Razavi模型是针对无电感振荡器提出的,因此本文主要讨论Leeson模型和Ha一收稿日期:2005—03—14作者简介:满家汉(1976一),男,河北省深县人,硕士研究生,研究方向为频率综合器的设计,man—****************;赵坤(1977一),男(汉族),河南省安阳人.博士研究生,研究方向为频率综合器的设计和建模.810电子器件第28卷jimiri模型.1.1Leeson模型Leeson模型是一个非常着名的相位噪声模型.考虑图1所示的LC振荡器的等效电路,其中是iX/Af回路中电阻的等效噪声源.,lfl无噪声负tgI'tl卞;中—Ra图lLC振荡嚣的等效电路当电路处于稳定的振荡状态时,整个谐振回路的阻抗为:z[j((U.+A~o)]一一jR'tOo(1)根据振荡器相位噪声的定义,可以得到相位噪声的表达式:cu一1一()由于等式(2)并不能反映1/尸噪声,因此需要修正,得到等式(3)El0]:L(A~o一(+百2FkT).[+(~00㈣其中:a是由闪烁噪声水平决定的一个常数,是过噪声因子.由于没有给出如何减小a和F的具体方法,因此Leeson模型对于设计振荡器的指导作用相对有限.?1.2Hajimiri模型Leeson模型所存在的不足主要源于建模时所假设的条件:即振荡器是LTI系统,这个假设跟实际情况不相符.Hajimiri模型则是建立在时变系统的基础上,因此从最终的结果来看,Hajimiri模型可以更好地反映振荡器相位噪声与电路的关系.Hajimiri模型认为系统是时变的,振荡器的相位噪声来源于噪声的注入.考虑图2所示的LC谐振回路,其中(f)是噪声源.噪声源会随机地在谐振回路中注入噪声,从而改变振荡器的幅度和相位.根据噪声注入时间的不同,噪声对于幅度和相位的作用也不同.如图2(a)所示,当噪声在振幅达到最大值时注入,只改变信号的振幅;如图2(b)所示,当噪声在信号过零点时注入,则只改变信号的相位.对于振荡器来说,在噪声注入时,幅度响应和相位响应存在着很大的不同.由于稳定的振荡器存在着一种限幅机制[9],因此噪声引起的幅度的变化会不断衰减;而噪声所引起的相位变化则保持不变.振荡器对于上述两种情况的响应如图3所示.其中h(£,r)和h(£,r)和分别是相位和幅度的冲击响应函数.图2噪声注入对于输出信号的影响圉3振荡器的相位响应和幅度响应由于限幅机制的存在,在实际分析噪声时不再考虑注入电流对幅度的影响,只考虑电流对相位的影响.Hajimiri模型的另一个假设是系统为线性.表面上看,这与振荡器是一个非线性系统相矛盾的现象.实际上,Hajimiri模型真正关心的是注入电流与相位变化之间是否存在线性关系,而并非关心整个系统是否为线性系统.根据文献Eg]的仿真结果,可以验证注入电流与相位变化之间为线性关系.因此前面给出的线性假设是可以被保证的.根据前面的分析可知,振荡器相位的冲击响应是在时刻r发生的阶跃,其表达式如下:矗.(£,r)一—F(o—J0r)"(£一r)(4)q一其中:r(z)被称为冲击敏感性函数(ISF).它是一个无量纲,且与频率和幅度无关的周期函数,其周期为2n.q是谐振回路中电容上最大的电荷变化量.根据上面分析,可以得到相位变化的表达式:r∞1r∞6t)一lh(£,r)(r)dr一二lr((Uor)i(r)drJ一∞qrilttIJ一∞(5)利用傅立叶展开将ISF函数展开,可表示为:r(r)一Co+∑CnCOS((Uor+)(6)—n=—l由等式(5)和(6)可以看出,噪声经过不同的系数C的加权并求和,最后可以得到噪声对于振荡器输出的相位影响.振荡器的输出可以表示为A?COS[cU£+(£)],由此可以得到振荡器的相位噪声表达第4期满家汉,赵坤:差分LCVCO的设计方法8ll式:CMOS工乙.患?㈩振荡器的1/尸噪声是由低频的闪烁噪声引起的,用闪烁噪声替代等式(7)中的噪声源,可以得到1/尸区域的相位噪声表达式:熹?一差??c~l/j8图5差分LCVCO的电路原理图图4表示噪声转化为输出信号的相位变化及相3.I片上电感的设计位噪声的过程..:2LCVCO设计的基本原则根据图1所示的振荡器等效电路和前面的定义,可以得到如下关系:Vk—Ibia,/gnk(9)g:C,an]~Vk—Ck坚≈I—bias—QL(10)根据文献[12]的分析,当满足振荡条件时,大部分噪声来自于MOS管,可以近似得到下式::/△/≈_砉-?4kTY(gd.+gpd.)(11)g~,uC.()将等式(11)(12)代人等式(7),近似得到关系:.【一VmJ(13)根据上面分析可以得到以下结论:①增大尾电流(即增大幅度),可以显着的改善相位噪声.②增大QL值,可以改善相位噪声.③减小MOS管的宽,可以改善1/尸噪声.MOS器件的闪烁噪声的表达式如下n]:=g.cWCo~WL(14):==——g-吣∞l4'其中:K是一个与工艺有关的常量由上式可以看出,减小MOS管的宽可以使闪烁噪声下降,从而使1/尸噪声下降.3LCVCo的设计流程由于采用互补结构的差分LCVCO具有较好的相噪特性,因此本文选取图5所示的结构作为分析的对象.差分LCVCO的设计采用0.25m1P5M电感的大小会影响其它电路参数的取值,因此必须先确定电感的数值.片上电感的数值完全由物理尺寸决定.调整片上电感的尺寸(包括内径,圈数, 线宽,线间距和厚度)使其达到所需的电感值.在调整这些物理尺寸时,需要注意以下两种效应:①电流的趋肤效应;②涡漩电流效应.根据趋肤效应,高频电流只从一定厚度的表层金属流过.等式(15)给出了频率与所需金属厚度的关系(式中:是金属的电导率):一√(15)金属过厚,并不能有效的提高电感的Q值.根据涡漩电流效应,片上电感需要做成中空的,以减少损耗.在实际设计时,可以利用电感设计工具A—SITIC[2计算不同电感的电感值和Q值.由于电感的Q值在很大程度上影响了VCO的相位噪声特性,因此需要仔细设计,使其在VCO的中心频率处达到最大Q值.3.2可变电容的设计在当前CMOS工艺条件下,主要利用PN结和变容MOS管实现可变电容.PN结可变电容的调节范围较小,而变容MOS管的调节范围较大.在具体设计中,根据可变电容的变化范围来确定变容器件的实现方法.根据中心频率,电感值和频率调节范围,利用下面的不等式确定可变电容的变化范围.1Ck.≤—(16)btankcumx1Ck.≥—(17)ntankcu商"3.3尾电流的设计根据前面的分析,增大尾电流可以增加输出信号的摆幅,减小振荡器的相位噪声.但实际上由于受到电源的限制,输出幅度不可能一直保持线性增大. 根据文献[12],振荡器的幅度变化范围存在两个区域:电流受限区域和电压受限区域.当输出摆幅较小时,输出摆幅与尾电流呈线性关系;当输出摆幅足够大时,输出幅度的增长受到电源电压和MOS管的812电子器件第28卷影响而被限制.当电源电压为2.5V时,通过仿真得到输出幅度和相位噪声随尾电流的变化关系,分别如图6和图7所示.之馨班邕掣-Iu.1曲.】设銎-I蔓'I.1-l图6输出幅度与尾电流的关系图7相住噪声和尾电流的关系由图6和图7可以看出,当处于电流受限区域时,相位噪声随着尾电流的增加而迅速改善;当处于电压受限区域时,尾电流的增加对于相位噪声的改善不明显.这主要有两个原因:①进入电压受限区域后,信号增大的幅度有限;②过大的尾电流导致噪声的增加.另外,过大的输出幅度会使提供尾电流的MOS管进入线性区,这时电流源会失去对电源噪声的隔离作用,从而使VCO的噪声特性进一步恶化.综合考虑相位噪声,功耗和电源噪声这些因素,在设计VCO时尾电流并非越大越好.根据图6和图7的仿真结果,在本设计中,当尾电流值为3mA~4 ITIA时,VCO达到最佳性能.3.4MOS管的设计图5所示的差分LCVCO的振荡条件是:g一gk(18)考虑振荡器的启振条件,必须满足下面的不等式:g≥ag础(19)其中系数a一般取2到3.为了确保电路可以正常工作,g必须足够大.但是根据前面的分析,当g增大时,噪声也会随之变大.在设计时必须对MOS管尺寸的选择进行权衡.4LCVCO的设计本文的设计目标是实现一个2.4OHz的集成LCVCO.设计采用0.25mCMOS工艺,电源电压为2.5V.根据上面的分析,权衡功耗和相位噪声指标,选择尾电流为4mA.图8为最终的版图.提取版图寄生参数进行后仿真,得到以下(表1)的结果:裹12.4GHzVCO后仿真结果相位噪声一120.4dBe/Hz@600kHz振荡频率2.4GHz功耗i0.5mW5小结本文通过分析振荡器的噪声模型,给出了振荡图8VCO版图器相位噪声与电路参数之间的关系.在此基础上提出了一种有效的设计方法,简化了VCO的设计.最后利用文章中提出的方法,设计出一个具有较高性能的2.4GHz集成LCVCO.参考文献:[1]CraninckxJandSteyaertM.A1.8-GHzlow--phase—noise CMOSVCOusingoptimizedhollowspiralinductors[J].IEEE JSolid—StateCircuits.Mayl997.32t736-744.[2]Niknejad.Analysis,Simulation,andApplicationsofPassive DevicesonConductiveSubstractes[,D].PhDthesis.Universi—tyofCaliforniaatBerkeley,2000.[3]MagetJ,TieboutM,KrausR,MOSV aractorsWithn?andp-TypeGatesandTheirInfluenceonanLC—VCOinDigital CMOS[J].IEEEJSolid—StateCircuits,July2000,38:l139一ll47.[4]AndreaniPtMattissonStOntheUseofMOSV aractorsin RFVCO's[J].IEEEJ.Solid—StateCircuits,June2000,35: 905—9l0.[5]HungCandKennethKO,Apackaged1.卜GHzCMOSVCO withphasenoiseof126dBe/Hzata600-kHzoffset[J]. IEEEJ.Solid—StateCircuits.Jan.2000,35:i00—103.[6]BernyAD,NiknejadAMandMeyerRG,AWideband Low—Phase—NoiseCMOSVCO[c].In:IEEECustomInte—gratedCircuitsconference.pp.555—558,2003.[7]LeesonDB,Asimplemodeloffeedbackoscillatornoises spectrum[,J].Pro=.IEEE,Feb.1966,54:329—330.[8]RazaviB,AstudyofphasenoiseinCMOSoscillators[J]. IEEEJSolid—StateCircuits,Mar.1996,31:331—343.[9]HajimiriAandLeeTH,Ageneraltheoryofphasenoisein electricaloscillators[,J].IEEEJ.Solid——StateCircuits.Feb. 1998,33:l79一l94.[io3DaiL,HarjaniR,DesignofHigh—performanceCMOSV olt—age—controlledOscillatorsI'M].KluwerAcademicPublish—ers,2003.[u]RazaviB,DesignofAnalogCMOSIntegratedCircuit[M]. McGraw—HillCo..2001.D2]HamD,HajimiriA.ConceptsandMethodsinOptimization ofIntegratedLCVCOs[J].IEEEJ.Solid—StateCircuits,June2001,36:896—908.。
高性能超低功耗的4.224GHz正交LC VCO
高性能超低功耗的4.224GHz正交LC VCO郑剑钦;李巍;李宁;任俊彦【期刊名称】《固体电子学研究与进展》【年(卷),期】2009(29)2【摘要】采用Jazz 0.18 μmRF CMOS工艺设计并实现应用于MB-OFDM超宽带频率综合器的4.224GHz电感电容正交压控振荡器。
通过解析的方法给出了电感电容正交压控振荡器的模型,并推导出简洁的公式解释了相位噪声性能与耦合因子的关系。
测试结果显示,核心电路在1.5V电源电压下,消耗6mA电流,频率调谐范围为3.566-4.712GHz;在主频频偏1MHz处的相位噪声为-119.99dBc/Hz,对应的相位噪声的FoM(Figure-of-Merit)为183dB;I、Q两路信号等效的相位误差为2.13°。
【总页数】6页(P220-225)【关键词】压控振荡器;正交压控振荡器;相位噪声;相位误差【作者】郑剑钦;李巍;李宁;任俊彦【作者单位】复旦大学专用集成电路与系统国家重点实验室;复旦大学微纳科技创新平台【正文语种】中文【中图分类】TN752【相关文献】1.高性能计算功耗创新低德州仪器推出TMS320C66x多核DSP新品为HPC开发人员提供超低功耗、超高性能解决方案 [J], 徐俊毅2.NEC研发低功耗、超小型LC-VCO [J], 孙再吉;3.低功耗宽带CMOS LC-VCO设计 [J], 肖时茂;马成炎;叶甜春4.一种带有升压电路的0.5V 3GHz低功耗LC VCO设计 [J], 周海峰;韩雁;董树荣;韩晓霞;王春晖5.1.3~2.2GHz低噪声低功耗CMOS LC VCO的设计 [J], 陈华;郭桂良;张玉琳;姜宇;韩荆宇;阎跃鹏因版权原因,仅展示原文概要,查看原文内容请购买。
一种应用于全球导航卫星系统接收机的低功耗宽带压控振荡器
一种应用于全球导航卫星系统接收机的低功耗宽带压控振荡器尹喜珍;肖时茂;马成炎;叶甜春【摘要】This paper presents a new low power small area wide-band Voltage Controlled Oscillator (VCO) for Global Navigation Satellite System (GNSS) receiver. The VCO is separated in two discrete working regions from the characteristic of all-band GNSS signals. The power and phase noise can be optimized individually, the complexity of VCO is reduced and the area is saved. A technique of tuning curve linearization is used; The conventional VCO problem of having narrow effective tuning range of control voltage ( Vctrl) is solved. A linear tuning curve in whole variation of Vctrl is kept, the Amplitude Modulation to Frequency Modulation (AM-FM) conversion is decreased, and the phase noise is allayed. The measured results show that the tuning range of frequency is 49.5%, the gain of VCO (Kvco) is constant when Vctrl varies from 0.1 to 0.9 V. Measured phase noise is lower than -120 dBc at 1 MHz offset, the entire VCO consumes 2 mA current, occupies 0.24 mm2 area. The proposed VCO is implemented in 0.13 p.m 1P6M process, and it is successfully applied to all-band GNSS receiver.%该文设计了一种应用于全球导航卫星系统(GNSS)射频接收芯片的新型低功耗小面积宽频率调节范围的压控振荡器(VCO).根据全波段GNSS信号的特点,将VCO分成两个离散的频率工作区域,可分别对这两个区域进行功耗、相位噪声的优化,减小了VCO结构的复杂度,并节省了芯片面积.利用调谐曲线线性化技术,克服了传统的VCO控制电压有效调节范围窄的问题,使VCO在整个控制电压范围内调节曲线线性,减小了幅度调制转频率调制(AM-FM),降低了相位噪声.测试结果显示,该VCO频率调节范围为49.5%,控制电压在0.1~0.9 V内,VCO增益(KVCO)恒定,当频率偏移为1 MHz时相位噪声小于-120 dBc/Hz,消耗电流2 mA,占用芯片面积为0.24mm2.提出的VCO在0.13 μm 1P6M工艺上实现,已成功应用于全波段GNSS接收机中.【期刊名称】《电子与信息学报》【年(卷),期】2012(034)004【总页数】5页(P1002-1006)【关键词】全球导航卫星系统(GNSS);压控振荡器(VCO);离散工作区域;调谐曲线线性化;滤波【作者】尹喜珍;肖时茂;马成炎;叶甜春【作者单位】中国科学院微电子研究所,北京100029;中国科学院微电子研究所,北京100029;中国科学院微电子研究所,北京100029;杭州中科微电子有限公司,杭州310053;中国科学院微电子研究所,北京100029【正文语种】中文【中图分类】TN752;TN965.51 引言近年来,无线通信系统发展迅猛,手持移动设备作为主流应用,要求一块芯片中集成各种常用通信标准来减小体积,降低成本和功耗。
基于漏栅极反馈技术的低相位噪声VCO设计
基于漏栅极反馈技术的低相位噪声VCO设计管媛辉;吴德胜【摘要】提出了一种新颖的嵌有阻抗变换模块(ITB),而不具有尾电流源的压控振荡器(VCO).ITB的引入抑制了由有源器件引起的噪声退化问题,交叉耦合晶体管基本上工作于饱和状态,抑制了LC谐振回路品质因子的降低.而且,该结构相对于传统的VCO而言,具有更容易满足的起振条件,并且保持了低电压工作下的低噪声性能.基于0.18μm CMOS工艺对该VCO进行设计并流片实现,测试结果表明,所提出的VCO振荡频率为4.82 GHz~6.1 GHz,调谐范围为23.5%,相位噪声为-122.5 dBc/Hz@1 MHz~115.6 dBc/Hz@1 MHz,电路在1 V电压供电下,消耗了1.5 mW的功耗.【期刊名称】《电子器件》【年(卷),期】2019(042)004【总页数】4页(P920-923)【关键词】压控振荡器;低相位噪声;反馈技术;交叉耦合;LC谐振回路;品质因子【作者】管媛辉;吴德胜【作者单位】长春工业大学信息传播工程学院,长春130012;长春工业大学信息传播工程学院,长春130012【正文语种】中文【中图分类】TN432通信工业领域的快速发展,促进了射频集成电路逐步向着高性能、低成本的方向迈进。
压控振荡器VCO作为无线传输系统中的主要模块,得到了业界越来越广泛的关注[1]。
由于差分交叉耦合VCO具有简单易起振的特点,已经成为目前应用最广泛的VCO结构,该结构中,开关晶体管对、尾电流源晶体管以及LC谐振回路的损耗对电路的噪声贡献最大。
滤波技术可以降低电路的噪声,此项技术利用LC滤波器来抑制源极二次谐波分量上的噪声,但是却是以芯片面积的加大为代价的。
电流复用技术也可以改善电路的噪声[2-3],但是该技术中的交叉耦合晶体管对一直处于饱和状态,因而电路的输出摆幅限制于晶体管阈值电压之内,抑制了电路达到的最优相位噪声。
C类VCO将交叉耦合晶体管对的栅极和漏极的直流偏置进行了去耦处理,防止其进入线性区[4],然而,该结构的起振条件并不容易满足。
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Journal of Semiconductors
February 2010
A 1h switched capacitor array and switched inductor array
Wang Xiaosong(王小松) , Huang Shuilong(黄水龙), Chen Pufeng(陈普锋), and Zhang Haiying(张海英)
in the lower and higher bands are defined as follows: 1 !L min D p Lmax ŒCv C .2n !L max D s 1 Ä Cv C .2n ˇv 1 Lmax Cv C .2n ˇL 1 Lmax ˇL Ä Cv C .2n ˇv Ca 1/ C Cp ˇa 1/Ca C Cp
(Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China)
Abstract: The design of a 1.76–2.56 GHz CMOS voltage-controlled oscillator (VCO) with switched capacitor array and switched inductor array is presented. Fabricated in 0.18 m 1P6M CMOS technology, the VCO achieves a 37% frequency tuning range. The measured phase noise varies between –118.5 dBc/Hz and –122.8 dBc/Hz at 1 MHz offset across the tuning range. Power consumption is about 14.4 mW with a 1.8 V supply. Based on a reconfigurable LC tank with switched capacitor array and switched inductor array, the tuning range is analyzed and derived in terms of design parameters, yielding useful equations to guide the circuit design. Key words: tuning range; phase noise; MOS; VCO; switched capacitor array; switched inductor array DOI: 10.1088/1674-4926/31/2/025001 EEACC: 1230B
Fig. 4. Schematic of the wideband VCO.
1/Ca C Cp Ca 1/ C Cp ˇa
;
(5)
;
(6)
Lmax
!H min D s
;
(7)
!H max D s
:
(8) Now, the tuning range (TR) as a function of ˇa , ˇv , ˇp , n, K1 and K2 can be derived by taking the ratio of Eq. (8) to Eq. (5): p !H max TR D K2 !L min Ä Â Ã ˇv ˇa 1 1 n K1 C .2 1/ 1 C ˇa ˇv 1 ˇp Ä Â Ã Â Ã; ˇv ˇa 1 1 1 1 1 K1 C C .2n 1/ C ˇa ˇv 1 ˇv ˇp ˇa ˇp .14/ 2 where ˇp can be rewritten as ˇp = 1 / Cp Lmax !Lmin . Based on Eq. (14), the TR of this work is improved greatly, compared to Ref. [6] which employed a switched capacitor array only, under the same conditions.
pacitor array and a 1 bit switched inductor array, as shown in Fig. 1. ˇv , ˇa and ˇp were defined in Ref. [6], and ˇL is added for the subsequent analysis and derivation. ˇv D ˇa D Cv Cv; min ; (1)
2. Tuning range analysis and derivation
The analysis and derivation are based on a reconfigurable LC tank consisting of an n bit binary-weighted switched ca Corresponding author. Email: wangxiaosong@ Received 16 June 2009, revised manuscript received 29 October 2009 Fig. 1. Reconfigurable LC tank.
c 2010 Chinese Institute of Electronics
025001-1
J. Semicond. 2010, 31(2)
Wang Xiaosong et al.
Fig. 3. TR versus ˇa for different n values. Fig. 2. Theoretical tuning characteristic.
1. Introduction
As the essential block in radio frequency (RF) circuits, the performance of CMOS VCO in terms of tuning range, phase noise and power consumption determines many basic performances of RF transceivers. Recently, with the ever-increasing demand for wireless applications, wide tuning range and low phase noise have been required in CMOS VCOs to support wideband or multi-band transceivers which meet many communication standards. Though multiple VCOs can be used to generate multiple frequency bandsŒ1 , using a single VCO to satisfy the requirements of wideband or multi-band applications is more desirable to save chip size and costŒ2; 3 . For RF transceiver applications, LC VCOs are the superior choice for their better phase noise performance than ring VCOsŒ4 , but their tuning range is relatively narrow. In order to extend the LC VCOs’ tuning range, many researchers have presented a variety of techniques. Compared to the wideband VCO using only varactorsŒ5 , by utilizing a switched capacitor array or/and switched inductor array, the targeted wide frequency range can be received and split into several sub-bands, which can decrease the VCO tuning gain and lower the phase noise. A switched capacitor arrayŒ6 occupies a small area, but is more suitable for the switching of small frequency span. A switched inductor arrayŒ7 is usually used to switch frequency with a larger frequency shift, but its inductors occupy a much larger chip area. Based on the above analysis, a reconfigurable LC tank comprising a switched capacitor array and switched inductor array is employed for the wide tuning range VCO of this work, as a compromise proposal. This paper also analyzes and derives the tuning range parameter, yielding useful equations to guide the design of the wide tuning range VCO, and describes the VCO design.