MT744A-UR中文资料

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MT9090中文资料

MT9090A 特点之一是模块化设计，在现场可以很容易地更换模块，用户可以更换不同的 OTDR 模块，或完成其他光网络测试如 CWDM 通道分析仪模块的光通道分析或光 / 电 10/100/1000MB 以太网测试。模块之间的操作非常相似，因此用户可马上熟悉操作。
Mainframe
µOTDR Module
外彩色显示屏 2) 执行任务用的专用功能键
66) Menu 键容易进入设置和大容量存储
7 可视激光二极管 ( 选项 )
3 Start 键是真正一键测试
88) OTDR 接口
4
4 箭头键用于缩放，光标移动和
( 集成功率计选项 ) 99) 双 USB 接口用于快速容易的数据
5
菜单导航
传送
78
2 Product Brochure l MU909014x/15x
一台真正创新型 OTDR!
介绍第一台没有牺牲性能的手持光时域反射仪 – 来自安立的新型 µOTDR 模块™ ! 其性能与尺寸大 4 倍、价格贵 2 倍的传统 OTDR 匹敌， Network Master MT9090A µOTDR 成为新一代测试仪表。其特点：5 cm 的分辨率用于事件的精确定位，小于 1 米（3 英尺）的盲区和 37dB 的动态范围 – 能测试超过 150 km (90 以上英里 ) 光纤。MT9090A µOTDR 是第一台真正手掌尺寸的手持 OTDR，将便携性提高到新的水平。.
±2 dB
±1 m ±3 × 测量距离 × 10–5 ± 标记分辨率 ( 不包括 IOR 不确定度 )
内存 : 20 MB (<1,000 条曲线 )
外部 (USB 存储器 ): 1 GB (<30,000 条曲线 )

万高产品速选表

A(63-250A) 内置式 AC220V 50Hz/60Hz
b b b b v b b b
0, 5, 15, 30 0, 5, 15, 30 b -
备注：■ 为标准配置，□ 为选配 “*”为仅在选配电流监测模块后具有此功能。
B (63-630A) 装置式 AC220V 50Hz/60Hz
b b b b b b b b b v b b b
WATSN 100-630A PC级型号定义与说明
Ք཮‫(ࡽޙ‬PCप)
WATSN 施耐德万高
N系列自动转换开关
B-
160/ 160 ·
控制器壳架电流额定电流
A B* D
4 极数
3 4
PC
R
X
电器级别工作方式附加功能
PC
R
X
S
F
I
I
控制器类型：A-末端型；B-基本型；D-智能型壳架电流等级：100, 160, 250, 400, 630 额定电流等级：100, 160, 250, 400, 630 极数：3-3极；4-4极电器级别：PC级工作方式：R-自投自复；S-自投不自复；I-互为备用附加功能：X-消防联动；F-反馈信号功能；I-电流监测模块（仅D型控制器可选） *可提供装置式和面板式两种安装方式，如需面板式安装请在订货时备注说明
b v
通讯
电流监测模块
A型
b b b b b b b
b b
b 0-63秒 b 0-63秒 b b -
-
备注：■ 为标准配置，□ 为选配
B型
b b b b b b b b b b b
b b b
b 0-255秒 b 0-255秒 b b b -

MU404 4寸五单元全频专业扬声器产品说明书

感谢您购买产品！请仔细阅读本手册，它将帮助你妥善设置并运行您的系统，使其发挥卓越的性能。

并保留这些说明以供日后参照。

警告：为了降低火灾与电击的风险，请不要将产品暴露在雨中或潮湿环境中。

警告：为了降低电击的风险，非专业人士请勿擅自拆卸该系统。

仅供专业人士操作。

等边三角形中的闪电标记，用以警示用户该部件为非绝缘体，系统内部存在着电压危险，电压。

可能足以引起触电。

可能足以引起触电如系统标有带惊叹号的等边三角形，则是为提示用户严格遵守本用户指南中的操作与维护规定。

注意：请勿对系统或附件作擅自的改装。

未经授权擅自改装将造成安全隐患。

警告：燃不得将明火源(如点的蜡烛)放在器材上面。

1. 请先阅读本说明。

2. 保留这些说明以供日后参照。

3. 注意所有警告信息。

4. 遵守各项操作指示。

5. 不要在雨水中或潮湿环境中使用本产品。

6. 不要将产品靠近热源安装，例如暖气管、加热器、火炉或其它能产生热量的装置（包括功放机）。

7. 不要破坏极性或接地插头的安全性设置。

如果提供的插头不能插入插座，则应当请专业人员更换插座。

8. 保护好电源线和信号线，不要在上面踩踏或拧在一起（尤其是插头插座及穿出机体以外的部分）。

9. 使用厂商规定及符合当地安全标准的附件。

10.雷电或长时间不使用时请断电以防止损坏产品。

12. 不要让物体或液体落入产品内——它们可能引起火灾或触电。

13. 请注意产品外罩上的相关安全标志。

. 仅与厂商指定或与电器一同售出的推车、架子、三脚架、支架或桌子一起使用。

推动小车/电器时，应谨防翻倒。

11注意事项产品的安装调试须由专业人士操作。

在使用非本厂规定的吊装件时，要保证结构的强度并符合当地的安全规范。

警告：1扬声器及扬声器系统的产品有限保修期为自正式购买日起的3年。

由于用户不合理的应用而导致音圈烧毁或纸盆损坏等故障，不包含于产品保修项目。

产品吊附件(包括音箱装配五金件和吊挂配件)的有限保修期为自正式购买日起的1年。

KT973A中文资料

DISCRETE SEMICONDUCTOR Transistors70 • Bipolar Transistors (continued)PartPin to PinCompatibilityPolarity РC max, W V CB max, V V CE max,V V EBmax,VI Cmax, m Аh FEV CE sat,VI CBO, μАF T, МHzNf, dB Package (Pads)KT6136A 2N3906 PNP 0.625 40 40 5 200 100…3000.40.05 250 TO-92KT6137A 2N3904 NPN 0.625 60 40 6 200 100…3000.30.05 300 TO-92 BC182BC182ABC182BNPN 0.5 60 50 6 100 120…450120…220200…4500.60.015 150 10 TO-92 BC183BC183ABC183BBC183CNPN 0.5 45 30 6 100 110…800110…220200…450420…8000.60.015 150 10 TO-92 КТ607А-4КТ607Б-42N4073 NPN 1.5 40 30 40 35 30 35 4 150 0.1 1000 700 TO-92 BC639 NPN 0.625 100 80 5 1500 ≥25 0.50.1 100 TO-92 BC640 PNP 0.625 100 80 5 1500 ≥250.50.1 100 TO-92 КТ646А КТ646БКТ646В2SC495 2CS496 NPN 1.0 60 40 40 60 40 40 4 1000 40…200 >150 150…3400.850.250.2510 10 0.05 250 TO-126 KT660A KT660Б BC337 BC338 NPN 0.5 50 30 45 30 5 800 110...220200 (450)0.5 1.0 200 TO-92КТ805АМ КТ805БМ КТ805ВМ КТ805ИМ KSD362 KSD773 NPN 30 300 45 30 5 5000 V KER >15>15>15 >252.53.0 1.0 TO-92 KT814AKT814БKT814BKT814ГBD136 BD138 BD140 PNP 10 40 50 70 100 5 1500 40…27540…27540…27530…2750.650 40 TO-126 KT815AKT815БKT815BKT815ГBD135 BD137 BD139 NPN 10 40 50 70 100 5 1500 40…27540…27540…27530…2750.650 40 TO-126 KT816AKT816БKT816BKT816ГBD234 BD236 BD238 PNP 25 40 45 60 100 5 3000 25…2750.6100 3.0 TO-126 KT817AKT817БKT817BKT817ГBD233 BD235 BD237 NPN 25 40 45 60 100 5 3000 25...2750.6100 3.0 TO-126 КТ8126А1 КТ8126Б1 MJE13007 MJE13006 NPN 80 700 600 400 300 9 8000 8...60 1.01000 4.0 TO-220 КТ8164А КТ8164Б MJE13005 MJE13004 NPN 75 700 600 400 300 9 4000 8...40 1.01000 TO-220 КТ8170А1 КТ8170Б1 MJE13003 MJE13002 NPN 40 700 600 400 300 9 9 1500 8 (40)1.01000 4.0 TO-126 КТ8176АКТ8176БКТ8176ВTIP31A TIP31B TIP31C NPN 40 60 80 100 60 80 100 5 3000 >25 1.2 3.0 TO-220DISCRETE SEMICONDUCTORTransistors71• Bipolar Transistors (continued)Part Pin to PinCompatibility Polarity РC max, W V CB max,V V CE max,V V EB max,V I Cmax,m А h FE V CE sat, VI CBO, μАF T, МHz Nf, dB Package (Pads) КТ8177АКТ8177БКТ8177ВTIP32A TIP32B TIP32C PNP 40 60 80 100 60 80 100 5 3000 >25 1.2 3.0 TO-220 КТ8212А КТ8212БКТ8212ВTIP41С TIP41B TIP41A NPN 65 60 80 100 60 80 100 5 6000 15…75 1.5 I CES =400 3.0 TO-220КТ8213А КТ8213БКТ8213ВTIP42C TIP42B TIP42A PNP 65 60 80 100 60 80 100 5 6000 15…75 1.5 I CES =400 3.0 TO-220MJE2955 PNP 75 70 60 5 1000020…100 1.1 1000 TO-220 MJE3055 NPN 75 70 60 5 1000020…100 1.1 1000 TO-220 КТ738А КТ739А TIP3055 TIP2955 NPN PNP 90 70 60 5 1500020…100 1.1 1000 TO-218 КТ732А КТ733А MJE4343 MJE4353 NPN PNP 125 160 160 7 160008…15 2.0 750 1.0 TO-218 КТ8224А КТ8224Б* BU2508A BU2508DNPN 100 1500700 7.5 8000 4…7 1.0 I ebo=1.0 100..187 TO-218КТ8225ABU941ZP NPN 155 350 5 15000>300 1.8 Veb=5.0V Iebo=20 TO-218 КТ8228А КТ8228Б* BU2525A BU2525DNPN 125 1500800 7.5 12000 5.0…9.5 5.0 I ebo=1.0 80…150 TO-218КТ8229А TIP35F NPN 125 180 180 5 2500015…75 1.8 I ceo = 1.0 3.0 TO-218 КТ8230А TIP36F PNP 125 180 180 5 2500015…75 1.8 1.0 3.0 TO-218 КТ8261А BUD44D2 NPN 25 700 400 9 2000 >10 0.65 0.1 TO-126 BUL44D2 NPN 40 700 400 9 5000 >10 0.65 0.1 TO-220 КТ8247А BUL45D2 NPN 75 700 400 12 5000 >22 0.5 100 TO-220КТ8248А BU2506F NPN 90 Vcek 1500700 7.5 5000 3.8…9.0 3.0 Icek, mA1.0TO-218 KT538A MJE13001 NPN 0.7 600 400 9 0.5 5…90 0.5 1000 4 TO-92 КТ8248А1 BU2506F NPN 90 Ucek 1500 700 7.5 5000 3.8…9.0 3.0 Icek,мА1.0 TO-218KT8290A BUH100 NPN 100 700 400 9 10000 >10 1.0 0.1 ТО-220 КТ8255А BU407 NPN 60 330 160 6 7000 >15 1.0 1.0 ТО-220 KT8270A MJE13001 NPN 0.7 600 400 9 0.5 5…90 0.5 1000 4 TO-126KT8296AKT8296БKT8296ВKT8296ГKSD882R KSD882O KSD882Y KSD882G NPN 10 40 30 5 3000 60…120100…200160…320200…4000.5 100 TO-126 KT8297AKT8297БKT8297ВKT8297ГKSB772R KSB772O KSB772Y KSB772G PNP 10 40 30 5 3000 60…120100…200160…320200…4000.5 100 TO-126KT872A KT872Б KT872B KT872Г* with clampingdiodeBU508А BU508 BU508DNPN1001500150012001500700 700 600 70061000>61.0 5.0 1.0 1.04.0TO-218KT928A 2N2218 NPN 0.5 60 60 5 0.8 20…100 1.0 5.0 250 TO-126KT928Б 2N2219 NPN 0.5 60 60 5 0.8 50…200 1.0 5.0 250 TO-126 KT928B 2N2219ANPN 0.5 75 75 5 0.8 100…300 1.0 1.0 250TO-126 KT940AKT940БKT940BBF459 BF458 NPN 10 300 250 160 3002501605 100 >25 1.0 0.05 TO-126 КТ969А BF469 NPN 6 300 250 5 100 50…250 1.0 0.05 60TO-126DISCRETE SEMICONDUCTOR Transistors72 • Power Bipolar Darlington TransistorsPart Pin to PinCompatibilityPolarityРC max, W V CB max, V V CE max, V V EB max, V I Cmax, m А h FE V CE sat, VICBO,μА F T, МHzPacka-ge KT8115AKT8115БKT8115BTIP127 TIP126 TIP125 PNP 65 100 80 60 100 80 60 5 5000 >1000 2.0 200 4 TO-220KT8116AKT8116БKT8116BTIP122 TIP121 TIP120 NPN 65 100 80 60 100 80 60 5 5000 >1000 2.0 200 4 TO-220КТ8214АКТ8214БКТ8214ВTIP110 TIP111 TIP112 NPN 50 60 80 100 60 80 100 5 2000 >500 2.5 1000 TO-220КТ8215АКТ8215БКТ8215ВTIP115 TIP116 TIP117 PNP 50 60 80 100 60 80 100 5 2000 >500 2.5 1000 TO-220KT8156A КТ8156Б BU807 NPN 60 330 150 2006 8000 >100 1.5 1000 TO-220KT8158AKT8158БKT8158BBDV65A BDV65B BDV65C NPN 125 60 80 100 60 80 100 5 12000>1000 2.0 400 TO-218KT8159AKT8159БKT8159ВBDV64A BDV64B BDV64C PNP 125 60 80 100 60 80 100 5 12000>1000 2.0 400 TO-218КТ8225А BU941ZP NPN 155 350 350 5 15000>300 2.7 100 TO-218КТ8251А BDV65F NPN 125 180 180 5 10000>100 2.0 0.4 TO-218KT972AKT972БKT972BKT972ГBD875 NPN 8.0 60 45 60 60 60 45 60 60 5 2000 >750 >750 750…5000 750…5000 1.5 1.5 1.5 0.95 200 TO-126KT973AKT973БKT973BBD876 PNP 8.0 60 45 60 60 45 60 5 2000 >750 >750 750…5000 1.5 1.5 1.5 200 TO-126• Unijunction TransistorsPart Pin to Pin Compatibility P max,W Vb, b2 max, V Ie pulse, A Ie rev, μA Veb sat,V ηPackage KT132A KT132Б 2N2646 2N2647 0.3 35 2.0 12.0 0.2 3.5 0.56…0.75 0.68…0.82 Case 22A-01KT133A KT133Б 2N4870 2N4871 0.3 35 1.5 1.0 2.5 0.56…0.75 0.70…0.85TO-92• Logic Level N-Channel MOSFETsPart Pin to Pin Compatibility Vds max, V Rds (on) Ohm Id max, A Vgs max, VP max, W Vgs (th),VPackageКП723Г IRLZ44 60 0.028 50 ±10 150 1.0…2.0 TO-220 КП727В IRLZ34 60 0.05 30 ±10 88 1.0…2.0 TO-220 КП744Г IRL520 100 0.27 9.2 ±10 60 1.0…2.0 TO-220 КП745Г IRL530 100 0.22 15 ±10 88 1.0…2.0 TO-220 КП746Г IRL540 100 0.077 28 ±10 150 1.0…2.0 TO-220 КП737Г IRL630 200 0.4 18 ±10 50 1.0…2.0 TO-220 КП750Г IRL640 200 0.18 18 ±1050 1.0…2.0 TO-220КП775А КП775БКП775В2SK2498А-В 60 55 60 0.009 0.009 0.011 50 ±20150 1.0…2.01.0…2.0 1.0…2.0TO-220DISCRETE SEMICONDUCTORTransistors73• Low Power MOSFETsPartPin to Pin Compatibility P max, W Vgs max, V Vds max,V Vgs(off), V Rds(on), Ohm Id max, A g fs,A/VPackageКП501А КП501Б КП501ВZVN2120 0.5 ±202402002001.0…3.0 1.0…3.0 10 10 15 10 >0.1 TO-92 КП502А BSS124 1.0 ±10 400 1.5…2.5 28 0.12 0.1 TO-92 КП503А BSS129 1.0 ±10400 1.5…2.5 28 0.12 0.1 TO-92КП504А КП504БКП504ВКП504ГКП504ДКП504ЕBSS88 1.0 1.0 0.7 0.7 0.7 0.7 ±102502502001802002000.6…1.2 8 8 8 10 8 8 0.32 0.14 TO-92 КП505А КП505БКП505ВКП505ГBSS295 1.0 1.0 1.0 0.7 ±1050506080.8…2.0 0.8…2.0 0.8…2.0 0.4…0.8 0.3 0.3 0.3 1.2 1.4 0.5 0.5 0.5 TO-92 КП507A BSS315 1.0 ±20 -50 -0.8…-2.00.8 -1.1 TO-92 КП508A BSS92 1.0 ±20-240 -0.8…-2.020 -0.15 TO-92КП509А9 КП509Б9КП509В9BSS131 0.36 0.50 0.36 ±142402402000.8…-2.0 0.6…-1.2 0.8…-2.0 16 8 16 0.1 0.25 0.1 0.06 0.14 0.06 SOT-23 КП510A9 IRML2402 0.54 ±12 20 0.7…-1.6 0.25 1.2 1.3 SOT-23 КП511A КП511Б TN0535 TN0540 0.75 ±20 350 400 0.8…-2.0 22 0.14 0.125 TO-92 КП523А КП523Б BSS297 1.0 1.0 ±20 ±14 200 200 0.8…2.0 0.8…2.0 2.0 4.0 0.48 0.34 0.5 0.5TO-92 КП214А9 2N7002LT1 0.2 ±40 60 1.0…2.5 7.5 0.115 0.08 SOT-23• Power N-Channel MOSFETsPartPin to Pin Compatibility Vds max, V Rds (on), Ohm Id max, AVgs max,V P max, W Vgs (th),VPackageКП723АКП723БКП723ВIRFZ44 IRFZ45 IRFZ40 60 60 50 0.028 0.035 0.028 50 50 50 ±20 150 2.0…4.0 TO-220 КП726А КП726Б BUZ90A BUZ90 600 2.0 1.6 4.0 4.5 ±20 75 2.0…4.0 TO-220 КП727А КП727Б BUZ71 IRFZ34 50 60 0.1 0.05 14 30±20 75 2.0…4.0 TO-220 КП728Г1,Г2 КП728С1,С2КП728Е1,Е2BUZ80A 700650 600 5.0 4.0 3.0 3.0 ±20 75 2.0…4.0 TO-220 КП739АКП739БКП739ВIRFZ14 IRFZ10 IRFZ15 60 50 60 0.2 0.2 0.3 10 10 8.3 ±20 43 2.0…4.0 TO-220 КП740АКП740БКП740ВIRFZ24 IRFZ20 IRFZ25 60 50 60 0.1 0.1 0.12 17 17 14 ±20 60 2.0…4.0 TO-220 КП741А КП741Б IRFZ48 IRFZ46 60 50 0.018 0.024 50 ±20 190 1502.0…4.0 TO-220 КП742А КП742Б STH75N06 STH80N05 60 50 0.014 0.012 75 80±20200 2.0…4.0 TO-218DISCRETE SEMICONDUCTOR Transistors74 • Power N-Channel MOSFETs (continued)PartPin to Pin Compatibility Vds max, V Rds (on), Ohm Id max, A Vgs max, VP max, W Vgs (th),VPackageКП743А КП743БКП743ВIRF510 IRF511 IRF512 100 80 100 0.54 0.54 0.74 5.6 5.6 4.9 ± 20 43 2.0…4.0 TO-220TO-126 КП743А1 100 0.54 5.5 ±2040 2.0…4.0 TO-126 КП744А КП744БКП744ВIRF520 IRF521 IRF522 100 80 100 0.27 0.27 0.36 9.2 9.2 8.0 ±20 60 2.0…4.0 TO-220 КП745А КП745БКП745ВIRF530 IRF531 IRF532 100 80 100 0.16 0.16 0.23 14.0 14.0 12.0 ±20 88 2.0…4.0 TO-220 КП746А КП746БКП746ВIRF540 IRF541 IRF542 100 80 100 0.077 0.077 0.1 28.0 28.0 25.0 ±20 150 2.0…4.0 TO-220 КП747А IRFP150 100 0.055 41.0 ±20230 2.0…4.0 TO-218 КП748А КП748БКП748ВIRF610 IRF611 IRF612 200 150 200 1.5 1.5 2.4 3.3 3.3 2.6 ±20 36 2.0…4.0 TO-220 КП749А КП749БКП749ВIRF620 IRF621 IRF622 200 150 200 0.8 0.8 1.2 5.2 5.2 4.0 ±20 50 2.0…4.0 TO-220 КП737А КП737БКП737ВIRF630 IRF634 IRF635 200 250 200 0.4 0.45 0.68 9.0 8.1 6.5 ±20 74 2.0…4.0 TO-220 КП750А КП750БКП750ВIRF640 IRF641 IRF642 200 150 200 0.18 0.18 0.22 18.0 18.0 16.0 ±20 125 2.0…4.0 TO-220 КП731А КП731БКП731ВIRF710 IRF711 IRF712 400 350 400 3.6 3.6 5.0 2.0 2.0 1.7 ±20 36 2.0…4.0 TO-220 КП751А КП751БКП751ВIRF720 IRF721 IRF722 400 350 400 1.8 1.8 2.5 3.3 3.3 2.8 ±20 50 2.0…4.0 TO-220 КП752А КП752Б КП752В Pilot ProductionIRF730 IRF731IRF732400 350 400 1.0 1.0 1.5 5.5 5.5 4.5 ±20 74 2.0…4.0 TO-220КП753АКП753Б КП753ВPilot ProductionIRF830 IRF831 IRF832 500 450 500 1.5 1.5 2.0 4.5 4.5 4.0 ±20 74 2.0…4.0 TO-220КП771А STP40N10100 0.04 40 ±20150 2.0…4.0 TO-220 КП776А КП776Б КП776В КП776Г Pilot ProductionIRF740 IRF741 IRF742 IRF744400 350 400 4500.55 0.55 0.8 0.6310.0 10.0 8.3 8.8±20 125 2.0…4.0 TO-220DISCRETE SEMICONDUCTORTransistors75• Power N-Channel MOSFETs (continued)Part Pin to Pin Compatibility Vds max, VRds (on),Ohm Id max, A Vgs max,V P max, W Vgs (th),VPackageКП777А КП777Б КП777ВPilot ProductionIRF840IRF841IRF842 500 450 500 0.85 0.85 1.1 8.0 8.0 7.0±20 125 2.0…4.0 TO-220КП778А IRFP250 200 0.085 30.0 ±20190 2.0…4.0 TO-220КП779А Pilot ProductionIRFP450 500 0.4 14.0 ±20190 2.0…4.0 TO-220 КП780АКП780Б КП780В IRF820 IRF821IRF822500 450 500 3.0 3.0 4.0 2.5 2.5 2.2 ±20 50 2.0…4.0 TO-220 КП781АPilot ProductionIRFP350 400 0.3 16.0 ±20 190 2.0…4.0 TO-220 КП783АPilot Production IRF3205 55 0.008 70.0 ±20200 2.0…4.0 TO-220 КП786А Pilot ProductionBUZ80A 800 3.0 4.0 ±20100 2.0…4.0 TO-220 КП787А Pilot Production BUZ91A 600 0.9 8.0 ±20150 2.0…4.0 TO-220 КП789А Pilot ProductionBUZ111S 320 0.008 80.0 ±20250 2.1…4.0 TO-220• Power P-Channel MOSFETsPart Pin to Pin Compatibility Vds max, V Rds (on), Ohm Id max, A Vgs max, V P max, W Vgs (th),VPackageКП784A IRF9Z34 -60 0.14 -18.0 ±20 88 -2.0…-4.0 TO-220 КП785A IRF9540 -100 0.20 -19.0 ±20 150 -2.0…-4.0 TO-220 КП796АUnderDevelopmentIRF9634 -250 1.0 -4.3 ±20 74 -2.0…-4.0 TO-220。

矽普特产品简介

产品型号 XPT4933 XPT4955 XPT4956 XPT4978 XPT5943 XPT5963
XPT5983 XPT9971 XPT8871 XPT9812
XPT9612
XPT9412 XPT9410 XPT9833
XPT9633 XPT9433 XPT9403 XPT6011
XPT6012
道（双声道）提供4W 平均功率
产品型号 XPT6013 XPT6871 XPT6875 XPT4809
XPT9863
XPT8863
XPT2008
XPT2069
XPT2068 C
XPT4098 XPT4871
F XPT4890 XPT4990 XPT0030 XPT4066 XPT4088 XPT4068 XPT6872
4 SOP18/SS OP24/SOP
16
SOP16/QF N16/DIP16 MSOP8/SO P8/ESOP8/
DFN8 MSOP8/SO
P8/DFN
WCSP9
MSOP8/ES OP8/SOP8/
DFN
WCSP
备注单端模式，5V，THD+N≤0.5％，75mW （32Ω）。XPT4963的 SD 是高电平工作，
封装
ETSSOP20
SOP8
ESOP8
MSOP8/SO P8
SOP16/DIP 16/ETSSO P16/ETSS OP20 SOP16/ET SSOP20/DI P16
SOP8/ ESOP8
SOP16/DIP 16/ESOP16
SOP16/ES OP16/DIP1
6
QFN16/SO P16/DIP16
完全兼容 LM4861/8002 ，XPT4871H

MT35中文资料

Ordering InformationMT352/CG/GP1N 64 Pin LQFP TraysMT352/CG/GP1Q 64 Pin LQFP Tape & Reel MT352/CG/GP2Q 64 Pin LQFP*Tape & Reel MT352/CG/GP2N 64 Pin LQFP*Trays* Pb Free Matte Tin0o C to +70o CMT352COFDM DemodulatorData SheetFigure 1 - Block DiagramRF inADCAGCSecondary Tuner controlImpulse SuppressionIF to Baseband conversion &InterpolatorFFTSymbol,Carrier &Timing RecoveryPilot &Channel Processor Control engineSymbol & Bit De-interleaver & DemapperFECMPEGTS2-wire busPrimary 2-wire busMT352Data SheetUnique algorithms that actively filter out impulse noise, without affecting normal performance, have been implemented. This reduces the interference effect from vehicles and electrical appliances, which is known to have significant detrimental effect on the quality of digital TV reception.Programming is simplified utilizing a high level command driven interface. A sophisticated engine controls all acquisition and tracking operations as well as controlling the tuner via a 2-wire bus. Any frequency range can be automatically scanned for digital TV channels. This mechanism ensures minimal interaction, maximum flexibility,fastest acquisition and the fastest auto scan capability of any chip in the market.Blind acquisition mode enables automatic detection of all OFDM signal parameters, including mode, guard and spectral inversion. The frequency capture range is sufficient to compensate for the combined offset introduced by the tuner and broadcaster.The device is packaged in a 64 pin LQFP and consumes less than 220mW of power.Figure 2 - Package OutlineMT352 CG YYWW *W ∆•Pin 1 CornerMT352Data Sheet Pin DescriptionPin Description TablePin No Name Description I/O Type V mA MPEG pins47MOSTRT MPEG packet start OCMOS Tristate 3·3148MOVAL MPEG data valid O3·31 49-53, 56-58MDO(0:7)MPEG data bus O3·31 61MOCLK MPEG clock out O3·31 62BKERR Block error O3·31 63MICLK MPEG clock in I CMOS 3·311STATUS Status output O3·31 6IRQ Interrupt output O Open drain56 Control pins4CLK1Serial clock I CMOS55DATA1Serial data I/O Open drain 56 23XTI Low phase noiseoscillatorICMOS24XTO O10SLEEP Device power down I3·3 12, 15-18SADD(4:0)Serial address set I3·344SMTEST Scan mode enable I3·335CLK2/GPP0Serial clock tuner I/OOpen drain 5636DATA2/GPP1Serial data tuner I/O56 42AGC1Primary AGC O56 41AGC2/GPP2Secondary AGC I/O56 43GPP(3)General purpose I/O I/O56 9RESET Device reset I CMOS527OSCMODE Crystal oscillator mode I CMOS3·326PLLTEST PLL analogue test OAnalog inputs30VIN positive input I31VIN negative input ISupply pinsMT352Data Sheet21PLLVDD PLL supplyS 1·822PLLGND S 07, 19, 37, 39, 59, 64CVDD Core logic power S 1·82, 13, 45, 54, VDD I/O ring power S 3·31, 3, 8, 14, 20, 25, 38, 40, 46, 55, 60GND Core and I/O ground S 028AVDD ADC analog supplyS 1·829, 32AGND S 033DVDD ADC digital supply S 1·834DGNDSPin Description Table (continued)Pin NoName Description I/O TypeV mATable of ContentsFeatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81.1 Analogue-to-Digital Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91.2 Automatic Gain Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91.3 IF to Baseband Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91.4 Adjacent Channel Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101.5 Interpolation and Clock Synchronisation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101.6 Carrier Frequency Synchronisation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101.7 Symbol Timing Synchronisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101.8 Fast Fourier Transform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101.9 Common Phase Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101.10 Channel Equalisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101.11 Impulse Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101.12 Transmission Parameter Signalling (TPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111.13 De-Mapper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111.14 Symbol and Bit De-Interleaving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111.15 Viterbi Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111.16 MPEG Frame Aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111.17 De-interleaver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111.18 Reed-Solomon Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111.19 De-scrambler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121.20 MPEG Transport Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122.0 Software control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123.0 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123.1 2-Wire Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133.2 Host. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133.2.1 Tuner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133.2.2 Examples of 2-Wire Bus Messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143.2.3 Primary 2-Wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143.3 MPEG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153.3.1 Data Output Header Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153.3.2 MPEG data output signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163.3.3 MPEG Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163.3.3.1 MOCLKINV = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173.3.3.2 MOCLKINV = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194.1 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204.4 Crystal Specification and External Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215.0 Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Figure 1 - Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Figure 3 - OFDM Demodulator Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4 - FEC Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 5 - Primary Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6 - Primary 2-Wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7 - DVB Transport Packet Header Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8 - MPEG Output Data Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 9 - MPEG Timing - MOCLKINV = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 10 - MPEG Timing - MOCLKINV = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 11 - Crystal Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 12 - Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Table 1 - Programmable Address Details for 2-Wire Bus in TNIM Evaluation Application. . . . . . . . . . . . . . . . . . . 13 Table 2 - Timing of 2-Wire Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 3 - MOCLKINV = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4 - MDOSWAP = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5 - MDOSWAP = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181.0 Functional DescriptionA functional block diagram of the MT352 OFDM demodulator is shown in Figure 3. This accepts an IF analogue signal and delivers a stream of demodulated soft decision data to the on-chip Viterbi decoder. Clock, timing and frequency synchronization operations are all digital and there are no analogue control loops except the AGC. The frequency capture range is large enough for all practical applications. This demodulator has novel algorithms to combat impulse noise as well as co-channel and adjacent channel interference. If the modulation is hierarchical, the OFDM outputs both high and low priority data streams. Only one of these streams is FEC-decoded, but the FEC can be switched from one stream to another with minimal interruption to the transport stream.Figure 3 - OFDM Demodulator DiagramThe FEC module shown in Figure 4 consists of a concatenated convolutional (Viterbi) and Reed-Solomon decoder separated by a depth-12 convolutional de-interleaver. The Viterbi decoder operates on 5-bit soft decisions to provide the best performance over a wide range of channel conditions. The trace-back depth of 128 ensures minimum loss of performance due to inevitable survivor truncation, especially at high code rates. Both the Viterbi and Reed-Solomon decoders are equipped with bit-error monitors. The former provides the bit error rate (BER) at the OFDM output. The latter is the more useful measure as it gives the Viterbi output BER. The error collecting intervals of these are programmable over a very wide range.Figure 4 - FEC Block DiagramThe FSM controller shown in Figure 3 above controls both the demodulator and the FEC. It also drives the 2-wire bus to the tuner. The controller facilitates the automated search of all parameters or any sub-set of parameters of the received signal. It can also be used to scan any defined frequency range searching for OFDM channels. Thismechanism provides the fast channel scan and acquisition performance, whilst requiring minimal software overhead in the host driver.The algorithms and architectures used in the MT352 have been heavily optimized to minimize hardware and chip area. This is proven by its 220mW (typical) power consumption, which is the lowest of any OFDM device in the market today.1.1 Analogue-to-Digital ConverterThe MT352 has a high performance 10-bit analogue-to-digital converter (ADC) which can sample a 6, 7 or 8MHz bandwidth OFDM signal, with its spectrum centred at:• 4.57MHz near-zero IF•36.17MHz IF•43.75MHz IFThe ADC can be clocked using:•Crystal oscillator with a 20.48MHz crystal• 4 MHz or 27MHz clock inputAn on-chip programmable phase locked loop (PLL) is used to generate the ADC sampling clock. The crystal frequency of 20.48MHz is used for 36.17MHz IF sampling and 19.6267MHz is used for 43.75MHz IF sampling. Note that this 19.6267MHz sampling clock can be generated from the 20.48MHz crystal by appropriately programming the PLL. Hence the same 20.48MHz crystal can support 6, 7 and 8MHz OFDM as well as 36.17 and 43.75MHz IF.1.2 Automatic Gain ControlAn AGC module compares the absolute value of the digitized signal with a programmable reference. The error signal is filtered and is used to control the gain of the amplifier. A sigma-delta modulated output is provided, which has to be RC low-pass filtered to obtain the voltage to control the amplifier. Upper and lower limits can be set to the AGC control voltage using registers.The programmable AGC reference has been optimized. A large value for the reference leads to excessive ADC clipping and a small value results in excessive quantization noise. Hence the optimum value has been determined assuming the input signal amplitude to be Gaussian distributed. The latter is justified by applying the central limit theorem in statistics to the OFDM signal, which consists of a large number of randomly modulated carriers. This reference or target value may have to be lowered slightly for some applications. Slope control bits have been provided for the AGCs and these have to be set correctly depending on the Gain-versus-Voltage slope of the gain control amplifiers.The bandwidth of the AGC is set to a large value for quick acquisition then reduced to a small value for tracking. The AGC is free running during OFDM channel changes and locks to the new channel while the tuner lock is being established. This is one of the features of MT352 used to minimize acquisition time. A robust AGC lock mechanism is provided and the other parts of the MT352 begin to acquire only after the AGC has locked. Two AGC control outputs are available, one to drive an RF amplifier and the other to control an IF amplifier. The parameters for both loops are programmable. In the default mode, only the IF AGC loop is activated.1.3 IF to Baseband ConversionSampling a 36.17MHz IF signal at 20.48MHz results in a spectrally inverted OFDM signal centred at 4.79MHz. Sampling a 43.75MHz IF signal at 19.6267MHz gives a non-inverted signal at 4.5MHz. The first step of the demodulation process is to convert this signal to a complex (in-phase and quadrature) signal in baseband. A correction for spectral inversion is implemented during this conversion process. Note also that the MT352 has control mechanisms to search automatically for an unknown spectral inversion status.1.4 Adjacent Channel FilteringAdjacent channels, in particular the Nicam digital sound signal associated with analogue channels, are filtered prior to the FFT.1.5 Interpolation and Clock SynchronisationMT352 uses digital timing recovery and this eliminates the need for an external VCXO. The ADC samples the signal at a fixed rate, for example, 20.48MHz. Conversion of the 20.48MHz signal to the OFDM sample rate is achieved using the time-varying interpolator. The OFDM sample rate is 64/7MHz for 8 MHz and this is scaled by factors 6/8 and 7/8 for 6 and 7MHz channel bandwidths. The nominal ratio of the ADC to OFDM sample rate is programmed in a MT352 register (defaults are for 20.48MHz sampling and 8MHz OFDM). The clock recovery phase locked loop in the MT352 compensates for inaccuracies in this ratio due to uncertainties of the frequency of the sampling clock.1.6 Carrier Frequency SynchronisationThere can be frequency offsets in the signal at the input to OFDM, partly due to tuner step size and partly due to broadcast frequency shifts, typically 1/6MHz. These are tracked out digitally, without the need for an analogue frequency control (AFC) loop.The default frequency capture range has been set to ±285kHz in the 2K mode and ±142kHz in the 8K mode. However, these values can be doubled, if necessary, by programming an on-chip register. It is recommended that this larger capture range be used for channel scan in order to find channels with broadcast frequency shifts, without having to adjust the tuner.After the OFDM module has locked, the frequency offset can be read from an on-chip register.1.7 Symbol Timing SynchronisationThis module computes the optimum sample position to trigger the FFT in order to eliminate or minimize inter-symbol interference in the presence of multi-path distortion. Furthermore, this trigger point is continuously updated to dynamically adapt to time-variations in the transmission channel.1.8 Fast Fourier TransformThe FFT module uses the trigger information from the timing synchronization module to set the start point for an FFT. It then uses either a 2K or 8K FFT to transform the data from the time domain to the frequency domain. An extremely hardware-efficient and highly accurate algorithm has been used for this purpose.1.9 Common Phase Error CorrectionThis module subtracts the common phase offset from all the carriers of the OFDM signal to minimize the effect of the tuner phase noise on system performance.1.10 Channel EqualisationThis consists of two parts. The first part involves estimating the channel frequency response from pilot information. Efficient algorithms have been used to track time-varying channels with a minimum of hardware. The second part involves applying a correction to the data carriers based on the estimated frequency response of the channel. This module also generates dynamic channel state information (CSI) for every carrier in every symbol.1.11 Impulse FilteringMT352 contains several mechanisms to reduce the impact of impulse noise on system performance.1.12 Transmission Parameter Signalling (TPS)An OFDM frame consists of 68 symbols and a superframe is made up of four such frames. There is a set of TPS carriers in every symbol and all these carry one bit of TPS. These bits, when combined, include information about the transmission mode, guard ratio, constellation, hierarchy and code rate, as defined in ETS 300 744. In addition, the first eight bits of the cell identifier are contained in even frames and the second eight bits of the cell identifier are in odd frames. The TPS module extracts all the TPS data, and presents these to the host processor in a structured manner.1.13 De-MapperThis module generates soft decisions for demodulated bits using the channel-equalized in-phase and quadrature components of the data carriers as well as per-carrier channel state information (CSI). The de-mapping algorithm depends on the constellation (QPSK, 16QAM or 64QAM) and the hierarchy α = 0, 1, 2 or 3). Soft decisions for both low- and high-priority data streams are generated.1.14 Symbol and Bit De-InterleavingThe OFDM transmitter interleaves the bits within each carrier and also the carriers within each symbol. The de-interleaver modules consist largely of memory to invert these interleaving functions and present the soft decisions to the FEC in the original order.1.15 Viterbi DecoderThe Viterbi decoder accepts the 5-bit soft decision data from the OFDM demodulator and outputs a decoded bit-stream. The decoder does the de-puncturing of the input data for all code rates other than 1/2. It then evaluates the branch metrics and passes these to a 64-state path-metric updating unit, which in turn outputs a 64-bit word to the survivor memory. The Viterbi decoded bits are obtained by tracing back the survivor paths in this memory. A trace-back depth of 128 is used to minimize any loss in performance, especially at high code rates.The decoder re-encodes the decoded bits and compares these with received data (delayed) to compute bit errors at its input, on the assumption that the Viterbi output BER is significantly lower than its input BER.1.16 MPEG Frame AlignerThe Viterbi decoded bit stream is aligned into 204-byte frames. A robust synchronization algorithm is used to ensure correct lock and to prevent loss of lock due to noise impulses.1.17 De-interleaverErrors at the Viterbi output occur in bursts and the function of the de-interleaver is to spread these errors over a number of 204-byte frames to give the Reed-Solomon decoder a better chance of correcting these. The de-interleaver is a memory unit which implements the inverse of the convolutional interleaving function introduced by the transmitter.1.18 Reed-Solomon DecoderEvery 188-byte transport packet is encoded by the transmitter into a 204-byte frame, using a truncated version of a systematic (255,239) Reed-Solomon code. The corresponding (204,188) Reed-Solomon decoder is capable of correcting up to eight byte errors in a 204-byte frame. It may also detect frames with more than eight byte errors. In addition to efficiently performing this decoding function, the Reed-Solomon decoder in MT352 keeps a count of the number of bit errors corrected over a programmable period and the number of uncorrectable blocks. This information can be used to compute the post-Viterbi BER.1.19 De-scramblerThe de-scrambler de-randomizes the Reed-Solomon decoded data by generating the exclusive-OR of this with a pseudo-random bit sequence (PRBS). This outputs 188-byte MPEG transports packets. The TEI bit of the packet header is set to indicate uncorrectable packets.1.20 MPEG Transport InterfaceMPEG data can be output in parallel or serial mode. The output clock frequency is automatically chosen to present the MPEG data as uniformly spaced as possible to the transport processor. This frequency depends on the guard ratio, constellation, hierarchy and code rate. There is also an option for the data to be extracted from the MT352 with a clock provided by the user.2.0 Software controlAcquisition of an OFDM channel and frequency scan for OFDM channels are controlled by an on-chip state machine, which minimizes the software requirement in the host processor. To acquire a channel, the host programs the channel frequency in the MT352. The on-chip state machine then writes the frequency information to the tuner, awaits tuner lock and acquires the OFDM channel to generate the transport stream. The controller can be made to automatically search for every parameter in the OFDM signal, including spectral inversion status. Furthermore, this controller will re-acquire the channel in the event of an interruption to the incoming signal.To scan a frequency range, the host programs the start and end frequencies for the search as well as the step size, which defaults to 8 MHz. The MT352 then automatically scans the frequency range by appropriately programming the tuner and searching for OFDM signals. Once a channel has been located, the host is interrupted to read the channel information from the MT352. Then MT352 continues the search. By default, only the channels which can generate a reliable transport stream are reported, but there is also provision for locating very weak channels. The frequency capture range of MT352 can be maximized to capture channels with frequency offsets without re-programming the tuner, in both 2K and 8K modes.The above approach to channel acquisition and scan has resulted in very fast acquisition and scan times whilst minimizing software overhead in the host processor. Furthermore, all this functionality has very efficiently been mapped into hardware to result in a device consuming less than 220mW of power.3.0 InterfacesFigure 5 - Primary InterfacesThe MT352 interfaces to other parts of a terrestrial receiver system can be partitioned into three groups: the host controller, the tuner and the MPEG decoder. One other pin, the Status output, is multi-functional and can directlydrive a LED to show the status of a range of different internal lock flags. Alternatively, it can drive an audio transducer to give an audio frequency that is dependent upon the error rate of the received signal.This feature can be used for faster installation of a system where the aerial may need to be adjusted, as signal strength is not the best guide for the optimum aerial position for COFDM reception.3.1 2-Wire Bus3.2 HostThe primary 2-wire bus serial interface uses pins:•DATA1 (pin 5) serial data, the most significant bit is sent first.•CLK1 (pin 4) serial clock.The 2-wire bus address is determined by applying VDD or VSS to the SADD[4:0] pins.In the current TNIM evaluation application, the 2-wire bus address is 0001 111 R/ W with the pins connected as follows:ADDR[7] ADDR[6] ADDR[5] ADDR[4] ADDR[3] ADDR[2] ADDR[1]Not programmable SADD[4] SADD[3] SADD[2] SADD[1] SADD[0]VSS VSS VSS VDD VDD VDD VDD Table 1 - Programmable Address Details for 2-Wire Bus in TNIM Evaluation ApplicationWhen the MT352 is powered up, the RESET pin 28 should be held low for at least 50ms after VDD has reached normal operation levels. As the RESET pin goes high, the logic levels on SADD[4:0] are latched as the 2-wire bus address. ADDR[0] is the R/ W bit.The circuit works as a slave transmitter with the lsb set high or as a slave receiver with the lsb set low. In receive mode, the first data byte is written to the RADD virtual register, which forms the register sub-address. The RADD register takes an 8-bit value that determines which of 256 possible register addresses is written to by the following byte. Not all addresses are valid and many are reserved registers that must not be changed from their default values. Multiple byte reads or writes will auto-increment the value in RADD, but care should be taken not to access the reserved registers accidentally.Following a valid chip address, the 2-wire bus STOP command resets the RADD register to 00. If the chip address is not recognized, the MT352 will ignore all activity until a valid chip address is received. The 2-wire bus START command does NOT reset the RADD register to 00. This allows a combined 2-wire bus message, to point to a particular read register with a write command, followed immediately with a read data command. If required, this could next be followed with a write command to continue from the latest address. RADD would not be sent in this case. Finally, a STOP command should be sent to free the bus.When the 2-wire bus is addressed (after a recognized STOP command) with the read bit set, the first byte read out is the contents of register 00.3.2.1 TunerThe MT352 has a General Purpose Port that can be configured to provide a secondary 2-wire bus. Master control mode is selected by a single register control bit.The allocation of the pins is: GPP0 pin 35 = CLK2, GPP1 pin 36 = DATA2.。

MT9041中文资料

3-83®Figure 1 - Functional Block DiagramMode MS FSEL1FSEL2PRIVDD VSS C3C1.5C2C4C8C16F0o FP8-STB FP8-GCIInterface DividerCircuitMCLKo MCLKiIC0IC1Phase Loop DCODetectorFilterSelectFeatures•Provides T1 and E1 clocks, and ST-BUS/GCI framing signals locked to an input reference of either 8 kHz (frame pulse), 1.544 MHz (T1), or 2.048 MHz (E1)•Meets AT & T TR62411 and ETSI ETS 300 011 specifications for a 1.544 MHz (T1), or 2.048 MHz (E1) input reference•Typical unfiltered intrinsic output jitter is 0.013 UI peak-to-peak•Jitter attenuation of 15 dB @ 10 Hz, 34 dB @ 100 Hz and 50 dB @ 5 to 40 kHz •Low power CMOS technologyApplications•Synchronization and timing control for T1 and E1 digital transmission links•ST-BUS clock and frame pulse sources •Primary Trunk Rate ConvertersDescriptionThe MT9041 is a digital phase-locked loop (PLL)designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1.544 MHz,or 8 kHz reference. The T1 and E1 outputs are fully compliant with AT & T TR62411 (ACCUNET ® T1.5)and ETSI ETS 300 011 intrinsic jitter and jitter transfer specifications, respectively, when synchronized to primary reference input clock rates of either 1.544 MHz or 2.048 MHz.The PLL also provides additional high speed output clocks at rates of 3.088 MHz, 4.096 MHz, 8.192MHz, and 16.384 MHz for backplane synchro-nization.Ordering Information MT9041AP 28 Pin PLCC-40°C to +85°CISSUE 1May 1995MT9041Multiple Output Trunk PLLAdvance Information元器件交易网MT9041Advance Information3-84Figure 2 - Pin ConnectionsPin DescriptionPin #Name Description1V SS Negative Power Supply Voltage. Nominally 0 Volts. 2,3IC0Internal Connection 0. Connect to V SS.4PRIPrimary Reference Input (TTL compatible). This input (either 8 kHz, 1.544 MHz, or 2.048 MHz as controlled by the input frequency selection pins) is used as the primary reference source for PLL synchronization.5V DD Positive Supply Voltage. Nominally +5 volts.6MCLKo Master Clock Oscillator Output. This is a CMOS buffered output used for driving a 20 MHz crystal.7MCLKiMaster Clock Oscillator Input. This is a CMOS input for a 20 MHz crystal or crystal oscillator. Signals should be DC coupled to this pin.8FP8-GCI Frame Pulse Output (CMOS compatible). This is an 8 kHz output framing pulse thatindicates the start of the active GCI-BUS frame. The pulse width is based upon the period of the 8.192 MHz synchronization clock.9F0oFrame Pulse Output (CMOS compatible). This is an 8 kHz output framing pulse that indicates the start of the active ST-BUS frame. The pulse width is based upon the period of the 4.096 MHz synchronization clock. This is an active low signal.10FP8-STB Frame Pulse Output (CMOS compatible). This is an 8 kHz output framing pulse thatindicates the start of the active ST-BUS frame. The pulse width is based upon the period of the 8.192 MHz synchronization clock. 11C1.5Clock 1.544 MHz (CMOS compatible). This ouput is a 1.544 MHz (T1) output clock locked to the reference input signal.12C3Clock 3.088 MHz (CMOS compatible). This output is a 3.088 MHz output clock locked to the reference input signal.13C2Clock 2.048 MHz (CMOS compatible). This output is a 2.048 MHz (E1) output clock locked to the reference input signal.14C4Clock 4.096 MHz (CMOS compatible). This output is a 4.096 MHz output clock locked to the reference input signal.15V SS Negative Power Supply Voltage. Nominally 0 Volts.16C8Clock 8.192 MHz (CMOS compatible). This output is an 8.192 MHz output clock locked to the reference input signal.165432789101123192021222425262728V S S I C 0I C 0P R I VDD MCLKo MCLKi FP8-GCIF0o FP8-STBC1.5IC0IC1IC0IC0MS IC0IC0F S E L 2F S E L 1R S T 12131415161718C 2V S S C 8C 16VD DC 4C 3元器件交易网Advance InformationMT90413-8517C16Clock 16.384 MHz (CMOS compatible). This output is a 16.384 MHz output clock locked to the reference input signal.18V DD Positive Supply Voltage. Nominally +5 volts.19IC0Internal Connection 0. Connect to V SS.20IC1Internal Connection 1. Leave open circuit.21, 22IC0Internal Connection 0. Connect to V SS.23MS Mode Select Input (TTL compatible). This input selects the PLL mode of operation (i.e. , NORMAL or FREERUN, see T able 1). 24, 25IC0Internal Connection 0. Connect to V SS.26FSEL2Frequency Select - 2 Input (TTL compatible). This input, in conjunction with FSEL1, selects the frequency of the input reference source (i.e., 8 kHz, 1.544 MHz, or 2.048 MHz; see T able 3).27FSEL1Frequency Select - 1 Input (TTL compatible). This input, in conjunction with FSEL2, selects the frequency of the input reference source (i.e., 8 kHz, 1.544 MHz, or 2.048 MHz; see T able 3).28RSTReset (TTL compatible). This input (active LOW) puts the MT9041 in its reset state. T o guarantee proper operation, the device must be reset after power-up. The time constant for a power-up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the RST pin must be held low for a minimum of 60 nsec to reset the device.Pin Description (continued)Pin #Name Description元器件交易网MT9041Advance Information3-86Functional DescriptionThe MT9041 is a fully digital, phase-locked loop designed to provide timing references to interface circuits for T1 and E1 Primary Rate Digital Transmission links. As shown in Figure 1, the PLL employs a high resolution Digitally Controlled Oscillator (DCO) to generate the T1 and E1 outputs. The interface circuit on the output of the DCO generates 1.544 MHz (C1.5), 3.088 MHz (C3), 2.048MHz (C2), 4.096 MHz (C4), 8.192 MHz (C8), 16.384MHz (C16), and three 8 kHz frame pulses F0o, FP8-STB, and FP8-GCI.Figure 3 - PLL Block DiagramAs shown in Figure 3, the PLL of the MT9041consists of a phase detector (PD), a loop filter, a high resolution DCO, and a digital frequency divider. The digitally controlled oscillator (DCO) is locked in frequency (n x f ref ) to one of three possible reference frequencies, configured using pins FSEL1 and FSEL2. The PLL is capable of providing a full range of E1/T1 clock signals synchronized to the primary PRI input. The loop filter is a first order lowpass structure that provides approximately a 2 Hz bandwidth.Modes of OperationThe MT9041 can operate in one of two modes,NORMAL or FREERUN, as controlled by mode select pin MS (see T able 1).Normal Mode .There are three possible input frequencies for selection as the primary reference clock. These are 8kHz, 1.544 MHz or 2.048 MHz. Frequency selectionMS Description of Operation0NORMAL 1FREERUNTable 1- Operating Modes of the MT9041DividerDCOPhase Loop Filterf reff syncDetectoris controlled by the logic levels of FSEL1 and FSEL2,as shown in Table 2. This variety of input frequencies was chosen to allow the generation of all the necessary T1 and E1 clocks from either a T1, E1 or frame pulse reference source.PLL Measures of PerformanceTo meet the requirements of AT & T TR62411 and ETSI 300 011, the following PLL performance parameters were measured:•locking range and lock time •free-run accuracy •intrinsic jitter•jitter transfer function •output jitter spectrum •wanderLocking Range and Lock TimeThe locking range of the PLL is the range that the input reference frequency can be deviated from its nominal frequency while the output signals maintain synchronization. The relevant value is usually specified in parts-per-million (ppm). For both the T1and E1 outputs, lock was maintained while an 8 kHz input was varied between 7900 Hz to 8100 Hz (corresponding to ±12500 ppm). This is well beyond the required ±100 ppm. The lock range of 12500ppm also applies to 1.544 MHz and 2.048 MHz reference inputs.The lock time is a measure of how long it takes the PLL to reach steady state frequency after a frequency step on the reference input signal. The locking time is measured by applying an 8000 Hz signal to the primary reference and an 8000.8 Hz (+100 ppm) to the secondary reference. The output is monitored with a time interval analyzer during slow periodic rearrangements on the reference inputs.The lock time for both the T1 and E1 outputs is approximately 311 ms, which is well below the required lock time of 1.0 seconds.FSEL 2FSEL 1Input Reference Frequency00Reserved 018kHz 10 1.544 MHz 112.048 MHzTable 2 - Input Frequency Selection of the MT9041元器件交易网Advance InformationMT90413-87Freerun AccuracyThe Freerun accuracy of the PLL is a measure of how accurately the PLL can reproduce the desired output frequency. The freerun accuracy is a function of master clock frequency which must be 20 MHz ±32 ppm in order to meet AT & T TR62411 and ETSI specifications. Jitter PerformanceThe output jitter of a digital trunk PLL is composed of intrinsic jitter, measured using a jitter free reference clock, and frequency dependent jitter, measured by applying known levels of jitter on the references clock. The jitter spectrum indicates the frequency content of the output jitter.Intrinsic JitterIntrinsic jitter is the jitter added to an output signal by the processing device, in this case the enhanced PLL. Tables 3 and 4 show the average measured intrinsic jitter of the T1 and E1 outputs. Each measurement is an average based upon a ±100 ppm deviation (in steps of 20 ppm) on the input reference clock. Jitter on the master clock will increase intrinsic jitter of the device, hence attention to minimization of master clock jitter is required.Jitter Transfer FunctionThe jitter transfer function is a measure of the transfer characteristics of the PLL to frequency specific jitter on the referenced input of the PLL. It is directly linked to the loop bandwidth and the magnitude of the phase error suppression characteristics of the PLL. It is measured by applying jitter of specific magnitude and frequencies to the input of the PLL, then measuring the magnitude of the output jitter (both filtered and unfiltered) on the T1 or E1 output.Care must be taken when measuring the transfer characteristics to ensure that critical jitter alias frequencies are included in the measurement (i.e.,for digital phase locked loops using an 8 kHz input).T ables 5 and 6 provide measured results for the jitter transfer characteristics of the PLL for both a 1.544MHz and 2.048 MHz reference input clock. The transfer characteristics for an 8 kHz reference input will be the same.Figures 4 and 5 show the jitter attenuation performance of the T1 and E1 outputs plotted against AT & T TR62411 and ETSI requirements,respectively.Output Jitter in UIp-pReference InputFLT0 UnfilteredFLT110Hz - 8kHzFLT210Hz - 40kHzFLT38kHz - 40kHz8 kHz .011.004.006.0021.544 MHz .011.001.002.0012.048 MHz.011.001.002.001Table 3 -Typical Intrinsic Jitter for the T1 OutputTypical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing .Output Jitter in UIp-pReference InputFLT0 UnfilteredFLT120Hz - 100kHzFLT2700Hz - 100kHz8 kHz .011.002.0021.544 MHz .011.002.0022.048 MHz.011.002.002Table 4 - Typical Intrinsic Jitter for the E1 OutputTypical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing .元器件交易网MT9041Advance Information3-88Input Jitter Modulation Frequency(Hz)Input Jitter Magnitude (UIp-p)Measured Jitter Output (UIp-p)T1 Reference Input E1 Reference Input Output Jitter Magnitude (UIp-p)Jitter Attenuation(dB)Output Jitter Magnitude (UIp-p)Jitter Attenuation(dB)1020 2.4218.34 2.4118.382020 1.6221.83 1.61821.844020.90026.94.90826.8610020.37534.54.37634.5233010.06044.44.06044.445008.03247.96.03247.9610007.01553.38.01553.3850000.8.00348.52.00348.527900 1.044.00350.83.00350.837950 1.044.00350.83.00350.837980 1.044.00350.83.00350.837999 1.044.00350.83.00350.838001 1.044.00350.83.00350.838020 1.044.00350.83.00350.838050 1.044.00350.83.00350.838100 1.044.00350.83.00350.83100000.4.00342.50.00342.50Table 5 - Typical Jitter Transfer Function for the T1 OutputNotes1) For input jitter from 10 kHz to 100 kHz, the jitter attenuation is of such magnitude that intrinsic jitter dominates the output signal, rendering the jitter transfer function unmeasurable.2) Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing .元器件交易网Advance InformationMT90413-89Input Jitter Modulation Frequency(Hz)Input Jitter Magnitude (UIp-p)Measured Jitter Output (UIp-p)T1 Reference Input E1 Reference Input Output Jitter Magnitude (UIp-p)Jitter Attenuation(dB)Output Jitter Magnitude (UIp-p)Jitter Attenuation(dB)10 1.5.35512.52.35112.6220 1.5.18618.13.18518.1840 1.5.09523.97.09623.88100 1.5.03931.70.03931.70200 1.5.02137.08.02037.50400 1.5.01241.94.01241.941000 1.5.00647.96.00746.627900* 1.044.00254.35.00254.357950* 1.044.00254.35.00254.357980* 1.044.00254.35.00254.357999* 1.044.00254.35.00254.358001* 1.044.00254.35.00254.358020* 1.044.00254.35.00254.358050* 1.044.00254.35.00254.358100* 1.044.00254.35.00254.35100000.35.00438.84.00341.341000000.20.00433.98.00336.48Table 6 - Typical Jitter Transfer Function for the E1 OutputNotes1) For input jitter from 10 kHz to 100 kHz, the jitter attenuation is of such magnitude that intrinsic jitter dominates the output signal, rendering the jitter transfer function unmeasurable.2) Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing .* Output jitter dominated by intrinsic jitter.元器件交易网MT9041Advance Information3-90Figure 4 - Typical Jitter Attenuation for T1 OutputFigure 5 - Typical Jitter Attenuation for E1 Output605040301020110201003001K10K JITTERATTENUATION(dB)b)a)SLOPE -20 dB PER DECADESLOPE -40 dBPER DECADEFrequency (Hz)dB-0.519.5JITTERATTENUATION(dB)104040010K-20 dB/decadeFrequency (Hz)元器件交易网Advance InformationMT90413-91*Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.‡Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.‡Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.Absolute Maximum Ratings*- Voltages are with respect to ground (V SS ) unless otherwise stated.ParameterSymbol Min Max Units 1Supply Voltage V DD -0.37.0V 2Voltage on any pin V I V SS -0.3V DD +0.3V 3Input/Output Diode Current I IK/OK ±150mA 4Output Source or Sink Current I O ±150mA 5DC Supply or Ground Current I DD /I SS ±300mA 6Storage T emperature T ST -55125°C 7Package Power DissipationPLCCP D900mWRecommended Operating Conditions - Voltages are with respect to ground (V SS ) unless otherwise stated.CharacteristicsSym Min Typ ‡Max Units Test Conditions1Supply Voltage V DD 4.5 5.05.5V 2Input HIGH Voltage V IH 2.0V DD V 3Input LOW Voltage V IL V SS 0.8V 4Operating T emperatureT A-402585°CDC Electrical Characteristics - Voltages are with respect to ground (V SS ) unless otherwise stated.V DD =5.0 V±10%; V SS =0V; T A =-40 to 85°C.CharacteristicsSym MinTyp ‡Max Units Test Conditions 1S U P Supply Current I DD 55mAUnder operating condition2I N Input HIGH voltage V IH 2.0V 3Input LOW voltage V IL 0.8V 4O U TOutput current HIGH I OH -4mA V OH =2.4 V 5Output current LOWI OL 4mA V OL =0.4 V6Leakage current on all inputsI IL10µAV IN =V SS元器件交易网MT9041Advance Information3-92AC Electrical Characteristics (see Fig. 6)†-Voltages are with respect to ground (V SS ) unless otherwise stated.CharacteristicsSym MinTyp ‡Max Units Test Conditions18 kHz reference clock period t P8R 125µs 2I N P U T S1.544 MHz reference clock period t P15R 648ns 32.048 MHz reference clock period t P20R 488ns 4Input to output propagation delay with an 8 kHz reference clock t PD8183ns MCLKi =20.000 000MHz 5Input to output propagation delay with a 1.544 MHz reference clock t PD15243ns MCLKi =20.000 000MHz 6Input to output propagation delay with a 2.048 MHz reference clock t PD20183nsMCLKi =20.000 000MHz7Input rise time (except MCLKi)8ns 8Input fall time (except MCLKi)8ns 9Delay between C1.5 and C2t D-20-1518ns 10Frame pulse F0o output pulse widtht W-F0o 244ns 11Frame pulse F0o output rise time t R-F0o 59ns Load = 85pF 12Frame pulse F0o output fall time t F-F0o 59ns Load = 85pF13Frame pulse FP8-STB output pulse widtht W-FP8STB 122ns 14Frame pulse FP8-STB output rise timet R-FP8STB 59ns Load = 85pF 15Frame pulse FP8-STB output fall time t F-FP8STB 59ns Load = 85pF 16O U T P U T SFrame pulse FP8-GCI output pulse widtht W-FP8GCI 122ns 17Frame pulse FP8-GCI output rise timet R-FP8GCI 59ns Load = 85pF 18Frame pulse FP8-GCI output fall timet F-FP8GC I 59ns Load = 85pF 19C1.5 clock period t P-C1.5648ns 20C1.5 clock output rise time t RC1.559ns Load = 85pF 21C1.5 clock output fall time t FC1.559ns Load = 85pF 22C1.5 clock output duty cycle 50%23C3 clock periodt P-C3324ns 24C3 clock output rise time t RC359ns Load = 85pF 25C3 clock output fall time t FC359ns Load = 85pF 26C3 clock output duty cycle 50%27C2 clock periodt P-C2488ns 28C2 clock output rise time t RC259ns Load = 85pF 29C2 clock output fall time t FC259ns Load = 85pF 30C2 clock output duty cycle50%元器件交易网†-Timing is over recommended temperature & power supply voltages.‡-Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.31C4 clock periodt P-C4244ns 32C4 clock output rise time t RC459ns Load = 85pF 33C4 clock output fall time t FC459ns Load = 85pF 34O U T P U T SC4 clock output duty cycle 50%35C8 clock periodt P-C8122ns 36C8 clock output rise time t RC859ns Load = 85pF 37C8 clock output fall time t FC859ns Load = 85pF 38C8 clock output duty cycle 50%39C16 clock periodt P-C1661ns 40C16 clock output rise time t RC1659ns Load = 85pF 41C16 clock output fall time t FC1659ns Load = 85pF 42C16 clock output duty cycle435055%Duty cycle on MCLKi =50%AC Electrical Characteristics (see Fig. 6)†-Voltages are with respect to ground (V SS ) unless otherwise stated.CharacteristicsSym MinTyp ‡MaxUnits Test ConditionsFigure 6 - Timing Information for MT9041C16C8C4C2C3C1.5t P-C8t W-FP8STBt P-C16t P-C4t W-F0ot W-FP8GCIt PD-20FP8-GCIFP8-STBF0oPRI-2.048 MHzPRI-1.544 MHzt PD-15t PD-8PRI- 8 kHzt D-20-15t P-C2t P-C3t P-C1.5†Timing is over recommended temperature & power supply voltages‡Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testingFigure 7 - Master Clock InputAC Electrical Characteristics (see Fig. 7)† - Voltages are with respect to ground (V SS ) unless otherwise stated.CharacteristicsSym MinTyp ‡Max Units Test Conditions1C L O C K Master clock input rise time t rMCLKi 4ns 2Master clock input fall time t fMCLKi 4ns 3Master clock frequency t pMCLKi19.999362020.000640MHz 4Duty Cycle of the master clock405060%MCLKi2.4V 1.5V 0.4Vt rMCLKt fMCLKNotes:。

北京彪骐佳讯

北京彪骐佳讯科技有限公司光纤收发器系列13.1 10/100M自适应光纤收发器产品描述10/100M自适应光纤收发器通过10BASE-T或100BASE-TX到100BASE-FX之间的光电转换，可以将传统的10M以太网或100M快速以太网通过快速以太网光纤链路扩展到110Km的范围。

产品图片产品特点●支持全双工和半双工网络通信，并带有自动协商能力●支持VLAN超长数据包的传输，可以与支持IEEE802.1Q协议的交换机产品匹配使用●支持LINK LOSS链路远程预告警功能●REMOTE PAUSE功能保证数据包传送的完整性●自适应10Mbps、100Mbps和10M/100Mbps环境，便于网络的升级●采用高性能的交换芯片和大容量的片内缓存，具有流量控制、差错检测等●功能，实现真正的无阻塞传输交换性能，保证数据传输的更高的安全性与稳定性●良好的散热性保证长时间的稳定工作●稳定可靠的开关电源，保证产品长时间不间断的工作●内置AC220V、DC-48V和外置5V供电，满足不同用户的需要技术参数产品应用订货信息选项1：光纤接口： SC-单/多模、ST-单/多模、FC-单/多模选项2：结构形式：内置电源、外置电源、收发模块13.2 单纤双向光纤收发器产品描述单纤双向光纤收发器通过单芯光纤的传输实现扩展基于双绞线的以太网目的，完成10BASE-T 或100BASE-TX 到100BASE-FX 之间的光电转换。

产品图片产品特点● 单纤光纤的传输极大的降低网络组建成本● 单模传输环境，可以将网络扩展至120km 的范围● 性能优异的光电器件保证了产品工作的稳定性和安全性 ● 内置AC220V 、DC-48V 和外置5V 供电，满足不同用户的需要技术参数产品应用：选项1：光纤接口：SC-单/多模、ST-单/多模、FC-单/多模选项2：结构形式：内置电源、外置电源、收发模块13.3 光纤收发器机架产品描述光纤收发器机架是一款用于机房内集中供电、集中管理的经济型光纤收发系统。

CHI MEI PA-765B E56070 元件说明书

•Component •元件UL file numberUL档案号Part number型号Remark备注Vendor供应商•FRONT CASE•前身E56070 PA-765B CHI MEI•TOP CASE•上身E56070 PA-765B CHI MEI•BOTTOM CASE•下身E56070 PA-765B CHI MEI•Batterycompartment•电池箱E207780 PC945(GG) QMFZ2 SABIC JAPAN L L C•Transformercover•火牛上盖E50075 LV2250V TEIJIN•TransformerHousing 火牛下盖E50075 LV2250V TEIJIN•Aux foam pad•Aux盖E257267 E50A-60 ZHI JIN•Side plate•侧盖E56070 PA-765B CHI MEI•Battery BayRubber Cover•电池箱盖E257267 E50A-60 ZHI JIN•batterydoors•电池盖E56070 PA-765B CHI MEI•AAA batterycover•3A 电池门E56070 PA-765B CHI MEI•Light guide•导光片E54705 CL PMMA SUMIPEX•Frontcontrolpanel 显示压件E248280 PC+ABS Jacobson•Strainrelief•线卡E107293 6P-4 晋煜•Power cord •电源线E137516 SJTW ZJCZ 利源電業製品廠有限公司LEE YUEN ELECTRICAL MFY LTD. E143681 LY-13B ELBZ7•Lead wire •引线E244721 UL 1007 20AWGL=330mmAVLV2 惠州市远达电业五金制品有限公司HUI ZHOU YUEN DA ELECTRONIC & HARDWARECO.,LTDE329541 UL 1007 18AWGVH3.96-H-2PVH3.96-TL=186mmZPFW2 深圳艾格科技有限公司Shenzhen Aiger Technology Co.,LtdE330646 UL 1007#24 XH-TXH-4P L=140mmAVLV2 深圳市展旺连接器有限公司Shen Zhen Zhan Wang Linker CO.,LTDE330646 UL 1007#24 XH-TXH-2P L=260mmAVLV2E330646 UL 2547#28 PH-TPH-3P L=260mmAVLV2E330646 UL 2547#28 PH-TPH-3P L=220mmAVLV2E330646 UL 1185 22AWG XH-T XH-2P L=150mmAVLV2•Integralfuse •保险丝E340427 SFC0800A(800mA/250V FastActing Glass TubeFuse)JDYX 瑞卓电子(东莞)有限公司Dongguan Reomax Electronics Co., LTD•Fuse Holder •保险丝座E239034 H3（10A/250V）IZLT2 惠州市海牛電子有限公司HUIZHOU HINEW ELECTRIC APPLIANCE CO.,LTD.变压器材料清單/ MATERIAL LISTNO. MATERIAL DESCRIPTION Ul file MANUFACTURERS / SUPPLIERS1. 膠芯/Bobbin 最小0.71mm厚尼龍66 101(r9)一層minimum 0.71mm thick PA66101(r9) one layerUL:E41938 杜邦/E I Dupont De Nemours & Co Inc2 膠套/Shroud 最小0.50mm厚尼龍66 101(r9)一層minimum 0.50mm thick PA66101(r9) one layerUL:E41938 杜邦/E I Dupont De Nemours & Co Inc3 初級線圈PrimaryWinding 聚氨酯漆包線MW75C(130℃) 或Polyurethane Wire,MW75C(130℃)UL:E258125 河源天裕電子塑膠有限公司He Yuan Sky Wealth Electronic And PlasticCo Ltd.4 初級跨線絕緣Pri. windingcrossoverinsulation CT25聚脂膠紙/CT-25 Polyestertape厚度:0.05mm*2 層/Thickness:0.05mm*2 layersUL:E165111 靖江亞華壓敏黏膠有限公司Jingjiang Yahua Pressure Sensitive Glue COLTD5 溫度保險Thermal Fuse Type: A4-F130 Deg.C ( 250V/2A)UL:E140847 雅寶電子有限公司/Aupo Electronics Inc.6 初級引線Primary Leads UL-1672 AWG #22 VW-1 300V105Deg.CUL:E191230UL:E189674UL:E211048UL:E214859恒輝（香港）發展有限公司Ever Bright (Hongkong) development CompanyLimited.深圳东聚Shenzhen Dong Ju Wire & CableCo.,Ltd.琦富瑞Qifurui Electronics co阳泰氟电线电缆YANGTAI WIRE & CABLE CO LTD7 初級引線Primary Leads 聚氨酯漆包線MW75C(130℃) 或Polyurethane Wire,MW75C(130℃)or聚氨酯漆包線MW79C(155℃)Polyurethane Wire,MW79C(155℃)UL:E258125UL:E201757河源天裕電子塑膠有限公司He Yuan Sky Wealth Electronic And PlasticCo Ltd.太平洋電線電纜深圳公司Pacific ElectricWire&Cable(shenzhen)Co.,Ltd.8 次級引線SecondaryLeads UL-1015 AWG #20 VW-1 600V105Deg.CUL:E191230UL:E189674UL:E211048UL:E214859恒輝（香港）發展有限公司Ever Bright(Hongkong) development Company Limited.深圳东聚Shenzhen Dong Ju Wire & CableCo.,Ltd.琦富瑞Qifurui Electronics co阳泰氟电线电缆YANGTAI WIRE & CABLE CO LTD9 次級引線SecondaryLeads CT25聚脂膠紙/CT-25 Polyestertape厚度:0.05mm*3 層/UL:E165111 靖江亞華壓敏黏膠有限公司Jingjiang Yahua Pressure Sensitive Glue COLTD.Thickness:0.05mm*3 layers聚酯膠片型號:MYLAR EL21 0.25mm厚PET film Type:MYLAR EL21 0.25mmThickUL:E93687 杜邦帝人/ Dupont Teijin Films U S L P10 外層絕緣Outinsulation CT25聚脂膠紙/CT-25 Polyestertape厚度:0.05mm*3 層/Thickness:0.05mm*3 layers聚酯膠片型號:MYLAR EL21 0.25mm厚PET film Type:MYLAR EL21 0.25mmThickUL:E165111UL:E93687靖江亞華壓敏黏膠有限公司Jingjiang Yahua Pressure Sensitive Glue COLTD.杜邦帝人/ Dupont Teijin Films U S L P11 鐵芯片LaminationCore EI-57 硅鋼片(H18 黑) 片厚0.50，疊厚35.3+/-0.5mmEI-57 silicon steel sheet(H18black), thickness:0.50mm,depth thickness:35.3+/-0.5mmN/A 東莞東駿電器有限公司Dongguan Dongjun Electrical Appliances Co.,Ltd.12 安裝架/Bracket 冷軋板鍍鋅Cold rolled Steel with Zinc-coatedN/A 東莞駿豐五金製品廠Dongguan JunFeng MetalManufactory13 屏蔽殼/Endbell 冷軋板鍍鋅Cold rolled Steel with Zinc-coatedN/A 東莞駿豐五金製品廠Dongguan JunFeng MetalManufactory14 次級連接器Secondaryconnector Housing: JS-1121-02 & Terminal:JS-1121-THousing: A3963H-2P & Terminal:A3963-TPUL: E113875UL: E326732喬訊電子有限公司Chyao shiunn electronicIndustrial Ltd.長江連接器有限公司ChangJiang Connectors CoLtd15 浸漬/Impregnation Insulating Varnish/絕緣油Type: 8562/C, class FUL:E200154 恒昌化學塗料公司HANG CHEUNG PETROCHEMICALLTD。

1SMA4750A中文资料

Maximum Surge Current IRM(2) (mApk) 1380 1260 1190 1070 970 890 810 730 660 605 550 500 454 414 380 344 305 285 250 225 205 190 170 150 135 125 115 110 95 90 80 70 65 60 55 50 45
Notes : (1) The type number listed have a standard tolerance on the nominal zener voltage of ± 5%. (2) The revese surge current is a non-repetitive, 8.3ms pulse width square wave or equivalent sine-wave superimposed on IZT per JEDEC Method
元器件交易网
ELECTRICAL CHARACTERISTICS
Type Device Marking
728A 729A 730A 731A 732A 733A 734A 735A 736A 737A 738A 739A 740A 741A 742A 743A 744A 745A 746A 747A 748A 749A 750A 751A 752A 753A 754A 755A 756A 757A 758A 759A 760A 761A 762A 763A 764A Voltage VZ @ IZT (V) 3.3 3.6 3.9 4.3 4.7 5.1 5.6 6.2 6.8 7.5 8.2 9.1 10 11 12 13 15 16 18 20 22 24 27 30 33 36 39 43 47 51 56 62 68 75 82 91 100 IZT (mA) 76.0 69.0 64.0 58.0 53.0 49.0 45.0 41.0 37.0 34.0 31.0 28.0 25.0 23.0 21.0 19.0 17.0 15.5 14.0 12.5 11.5 10.5 9.5 8.5 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.7 3.3 3.0 2.8 2.5

FBT型号直接代换速查表![终稿]

FBT型号直接代换速查表!FBT型号直接代换速查表!FBT型号直接代换速查表!FCO-14A042 FTX-14A015 DNF-FL2727FEA185A DG300004021FEA237A BSC25-0202A BSC26-M02C1 BSC24-1402、79A361-1FEA241 KJF-9458A KJF-9320C 730-302-1433BFEA284 FEA86012D LCE CF0724A ZTFJ73345AFEA287B FEA287C、730-302-0564AFEA287C / 730-302-0564A FEA287BFEA374 CT-8355、79A348-3 FEA374F 79A348-1AFEA374F FEA374 CT-8355、79A348-3 79A348-1AFEA382 LCE CF0910FEA383 39L518AZT LCE CF1143 39L499AZTFEA469 FEA826 75A355-4-A 6174Z-1036A 79A355-5 79A355-1 BSC25-6503/C-FBT-1527 6174Z-1045A BSC24-1438FEA469D BSC25-6503/C-FBT-1527 79A355-503 BSC24-1438 6174Z-10 36A 79A355-5 6174Z-1045A、79A355-1FEA531A FEA531CFEA531C FEA531AFEA557 AT2097/16FEA565A 39L2065AZ、2385206700 39L1057AZ、2385205300FEA602B / 79A371-1C-TC FEA603A、79A371-1C-BFEA603A/ 79A371-1C-B FEA602B、79A371-1C-TCFEA634/ 79A355-1 FEA826 79A355-4-A(S) 6174Z-1036A 79A355-5 79A355-1 BSC25-6503/C-FBT-1527 6174Z-1045A BSC24 -1438FEA636 AT2097/07AFEA626/ LZ250A.000P FEA662A、LZ250A.013P LZ250A013J TAD53712、LZ250A.013TFEA662A/ LZ250A.013P FEA662、LZ250A.000P LZ250A 013J TAD53712、LZ250A.013TFEA677 TBC000* 277 BSM31-3905、TBC000 *150AFEA677/TBC000 * 277 BSM31-3905、TBC000 * 150AFEA687 BSC24-1420 730-312-1434FEA689/ 79A569-1 BSC25-6503/CFBT-1527 CT-8204A 6174 Z-1045A BSC24-1438 79A355-4-A(S) 6174Z-1036AFEA689/ 79A569-1D FEA689B、79A569-1-B FEA937、79A371-1C-CFEA689B/ 79A569-1-B FEA689、79A569-1DFEA711A/ 79A769-1-A 79A769-2-A 79A769-2-C 79A769-1-C 79A761-2-B FEA817A 79A769T-1-B FEA945B FEA915 FEA 711C、79A769-1-BFEA711C/ 79A769-1-B 79A769T-1-B FEA945B 79A761-2-B F EA817A FEA915、79A769-1-C FEA711A、79A769-1-A 79A769-2-AFEA755 FKG-15A001 FN1434FEA759 FKH-17A002 FKH-17A001FEA771/ DG3000008800 BSC24-N2333S FEA766A BSC25-6503/C-FBT-1 770DFFEA780 730-302-7681A FEA880 6174Z-1008F、730-302-7681A MF-6398 FEA780BFEA780B / 730-302-7601D FEA780、730-302-7681A FEA880 61714Z-1008F、730-302-7681A MF-6398 FEA780BFEA800A/ 79A955-1-A FEA800B/79A995-1-AHFEA800B/ 79A995-1-AH FEA800A、79A955-1-AFEA817 79A769-1-B、FEA711C 79A769T-1-B、FEA945B FEA711A 79A761-2-BFEA824 FKD-15D002FEA825A FEA827 CT-8459、LFT0007FEA826 79A355-4-A FEA469 6174Z-1036A、79A355-5 79A355-1 BSC25-6503/C-FBT-1527 6174Z-1045A 79A35 5-4-AHFEA827 CT-8459、LFT0007 FEA825AFEA830 FKG-15A001 FKG15A006FEA831 FQB-17A001 LCE CF1648、BH26-00108A FSA0188FEA833 LCE CF1741/730-302-572CFEA836 FEA861A/730-302-X975C FEA861/730-302-X975FEA848A FSN-15B052N/730-302-566DAFEA850 / 2385208600 2385210300 LCE CF1938 FEA850A 2385211800 2385211900FEA850A 2385210300 LCE CF1938 FEA850 2385211800 23852119 00FEA861/ 730-302-X975 FEA836、730-306-X759 FEA861 、730-302-X975CFEA861 / 730-302-X975C FEA836、730-302-X975 FEA861、730-302-X975FEA867A/ TFB-7012 FEA908、TFB-8503 FEA883 LCE CF1380B、TFB-7010 FEA976 FEA978 FEA880 FEA780FEA883 FEA867A、TFB-7012 FEA908、TFB-8503 LCE CF1380B、TFB-7010 FEA976 FEA978FEA886/ 313816874001 FSN-15C004N FEA888 FEA88A、313816878061FEA886A /313816878051 FEA888A、313816878061FEA888 FEA886、313816874001 FSN-15C004N FEA888 FEA888AFEA888A FEA886、313816874001 FSN-15C004N FEA888 FEA886A、313816878051FEA906 FEA907 19.70052.001 19.70056.S01 19.70056.001FEA907 79.70052.001 FEA906 19.70056.S01 19.70056.011FEA908/ TFB-8503 FEA867A、TFB-7012 FEA883 LCE CF1380B、TFB-7010 FEA976 FEA978FEA915 79A769-2-A 79A769-1-A FEA711A 79A769-2-CFEA915/ 79A769-1-C FEA711A、79A769-1-A、9602-04-101A FEA711C、79A769-1-BFEA937 HFT264MFEA937/ 79A371-1C-C FEA689、79A569-1DFEA945B 79A769-1-B FEA711C FEA711A FEA817AFEA946 FWK0062B、730-302-797N MF-6581、730-302-797N FEA946A LCE CF1737FEA946A FEA946 FWK0062B、730-302-797N MF-6581、730-302-797N LCE CF1737FEA953/ TFB-7015 FLO0108、TFB-7021FEA976 FEA867A、TFB-7012 FEA883A FEA908 FEA978 LCE CF1380B、TFB-7010 FEA978 FEA867A、TFB-7012 FEA883A FEA908 FEA976 LCE CF1380B、TFB-7010 FEA73015H MF-3131、5RH0000108 BSM35-3219 FFA81045H BSC25-0218 FFA76017U FFA76028U FFA76028U/FFFA76028U FFA76017U FFA76028U/FFFA76028U/F FFA76028U FFA76017UFFA79014U MF-3323A MF-3323 BSC25-0134FFA81024U LCE CF0883FFA81045 BSC25-0218 FFA81045H FFA73015H BSM35-3219FFA81045H MF-3131、5RH0000108 BSM35-3219 FFA73015HFFA81049H 79A355-503 BSC24-1438 BSC25-6503/C-FBT-1527 79A355 -4-AFFA82012H FFA82022HFFA82022H FFA82025H CFB-4/121、M374392 LCE CF0801 FFA82012H FFA82025H FFA82022H CFB-4/121、M374392 LCE CF0801FFA86012D FEA284、5RH0000060 LCE CF0724A ZTFJ73345AFJ2672 KJF-9215BFKD-14A001 FKD-15A001 FKD-15C003 FN/DNF1528FKD-15A001 FKD-14A001 FKD-15C003 FN/DNF1528FKD-15C003 FKD-14A001 FKD-15A001 FN/DNF1528FKD-15D002 FEA824FKG-15A001 FEA755 FN1434 FKG-15A006(3、4脚对换）FKG-15A006 FEA830 FKG-15A001（3、4脚对换）FKG-15A007 FQM-15A009FKG-15D001 FKG-15D002（将聚焦盒引脚向下右两脚连接）FKH-17A001 FKH-17A002 FEA759FKH-17A002 FEA759 FKH-17A001FLO0108/ TFB-7021 FEA953、TFB-7015FN/DNF1528 FKD-14A001 FKD-15A001 FKD-15C003FN1434 FEA755 FKG-15A001FPH0213 LCE CFT2091SFQA-15A001 BH26-00017AFQB-17A001 FEA831 LCE CF1648、BH26-00108A FSA0298FQB-17B015 FSA0188 FQB-17B002FQM-15A007 FQM-15A007B FQM-15A009/BFQM-15A007B FQM-15A007 FQM-15A009/BFQM-15A009/B FQM-15A007B FQM-15A007FQM-15B003 FSA0210FQM-17A008 BSC25-1448、6174T11006BFQM-17A001 FQM-17A012FQM-17A012 FQM-17A011FQM-17B002 BH26-00109A LCE CF1781 FQM-17B015 FSA0188FQM-17B007 BSM35-3316DQ770 V770 BSM35-3316D/F772 BSM35-3316/ F770D LCE CF1570、2850007210FQM-15B015 FQM-15B002FQM-17B019 FQM-17B021FQM-17B021 FQM-17B019FSA0188 BH26-00109A LCE CF1781 FQM-17B015 FQM-17B002FSA0210 FQM-15B003FSA0298 FQB-17A001 FEA831 LCE CF1648、BH26-00108AFSA-15A002 FSA-15A003FSA-15A003 FSA-15A002FSD-15B002 FSD-15B002AFSD-15B002A FSD-15B002FSN-14A024 BSM31-3305、730-302-850M 6174Z-2003HFSN-14A029S 6174Z-2003F 6174Z-2003HFSN-15A008 6174Z-2003C FSN-15A008S 154-388G CFB-4/085AFSN-15A008S 6174Z-2003C FSN-15A008 CFB-4/085A 154-388GFSN-15A019S 730-302-X570A FEA708AFSN-15B027N TFB-274T FEA848A、730-302-566DBFSN-15C004N FEA886、313816874001 FEA888 FEA888A、3138 168 78061 AT2097-33 AT2097-34 AT2097-21 AT2097-38 FSW-17A001 FSW-17A002FSW-17A002 FSW-17A001FTX-14A015 FCO-14A042 DNF-FL2727FUA-17A010 TRAN-8693、530-302-700SA BSC25-1459 MF-6623 FUA-17A019 6174Z-1008F MF-6398FUA-17A019 FUA-17A010 TRAN-8693、530-302-700SA BSC25-1459 MF-6623 6174Z-1008F MF-6398FUA-17C003 FUA-17C004 FUA-17C006FUA-17C004 FUA-17C003 FUA-17C006FUA-17C006 FUA-17C003 FUA-17C004FWK0030 LCE CF1628、730-302-770VC FWK0030AFWK0030A FWK0030 LCE CF1628、730-302-770VCFWK0062B FEA946 MF-6581、730-302-797N LCE CF1611HFT264M 79A371-1C-C FEA937KD-1731 KD-1732PF-A（5，7脚空）FSA0298KD-1732PF-A KD-1731 FSA0298KFS-60807A KFS-61410 KFS-61101 154-382B LCE CF0710KFS-60854 LCE CF0394KFS-61101 KFS-61410 154-382B LCE CF0710 KFS-60807AKFS-61140A FCO-14A030C DNF-FL2700KFS-61376 LCE CF1280KFS-61410 KFS-61101 154-382B LCE CF0710 KFS-60807AKFS-61432 6174Z-2002E 6174Z-2002JKFS-61478 LCE CF0929KJF-9203D LBCH0110-000KJF-9215B FJ2672KJF-9320C KJF-9458A 154-388F、730-302-1433B FEA241、730-302-1433 KJF-9458A KJF-9320C 154-388F、730-302-1433B FEA241、730-302-1433 KJF-9902B/F KJF-9902B/PKJF-9902B/P KJF-9902B/FLBCH011-000 KJF-9203DLCE CF0394 KFS-60854LCE CF0590A LCE CF0590BLCE CF0590B LCE CF0590ALCE CF0612 /313811877590 LCE CF0612A、313811879410LCE CF0612A /313811879410 ETF39L639AZT、313811877581 ETF35L510AZT、313811878501 AT2094-02LCE CF0612A /313811879410 LCE CF0612/313811877590LCE CF0625 /19.70026.001 BSM54-3207、19.70038.A01 LCE CF0698A、19.70034.001 LCE CF0689、19.70028.001LCE CF0689 /19.70028.001 BSM54-3207、19.70038.A01 LCE CF0698A、19.70034.001 LCE CF0625、19.70026.001LCE CF0698A LCE CF0625 BSM54-3207、19.70038.A01 LCE CF0698 LCE CF0706 Y265161 Y265163LCE CF0710 KFS-61410 KFS-61101 154-382B KFS-60807ALCE CF0724A FEA284、5RH0000060 FFA86012D ZTFJ73345ALCE CF0754B 19.70032.001LCE CF0801 FFA82025H FFA82022H CFB-4/121/M374392LCE CF0821 TFB-251T、5062625120LCE CF0857 LCE CF0857A、313812875530LCE CF0857A LCE CF0857LCE CF0883 FFA81024ULCE CF0910 FEA382、HH00002LCE CF0929 KFS-61478LCE CF0959 HH000001LCE CF0960 39L2024AZ、HH000005 FEA477、HH00005LCE CF0969 LCE CF0969B LCE CF0969C LCE CF1033A LCE CF09 69ALCE CF0969A LCE CF1033A LCE CF0969B LCE CF0969C LCE CF0 969LCE CF0969B LCE CF0969 LCE CF0969C LCE CF0969A LCE CF10 33ALCE CF0969C LCE CF0969 LCE CF0969B LCE CF0969A LCE CF10 33ALCE CF1027 LCE CF1263、2850004510LCE CF1033A LCE CF0969 LCE CF0969B LCE CF0969A LCE CF09 69CLCE CF1043 LCE CF1043ELCE CF1043E LCE CF1043、0480-0000-0040LCE CF1119A /313817875452 AT2097-21 FB-5B/CF1486、313816873121 AT2097-33 AT2097-34 ETF39L2075AZB、313817876342 AT2097-38LCE CF1143 39L518AZT FEA383 39L499AZT、410-F012BLCE CF1263 /2850004510 LCE CF1027LCE CF1280 KFS-61376LCE CF1285 LCE CF1433、47F13-0911A LCE CF1611、47F13-1090B LCE CF1380B / TFB-7010 FEA867A、TFB-7012 FEA908、TFB-8503 FEA883LCE CF1388B LCE CF1388CLCE CF1388C LCE CF1388BLCE CF1433 LCE CF1611 LCE CF1285LCE CF1517 BSC25-0208M TRAN-6516 BSC25-0208MLCE CF1570 FQM-17B007LCE CF1611 LCE CF1433、47F13-0911A LCE CF1285、47F13-0910A LCE CF1628 730-302-770VCLCE CF1628 / 730-302-770VC FWK0030 FWK0030ALCE CF1648 FEA831 FQB-17A001 BH26-00108ALCE CF1737 FEA946A、47F13-1091S MF-6581、730-302-797NLCE CF1741 FEA833、730-302-566DLCE CF1781 HBH26-00109A FQM-17B002 FSA0188LCE CF1821 BSC24-N2375S、730-302-786FD LCE CF1920 730-302-796FDLCE CF1827B BSC24-N2374S、730-302-796PF BSM75-3709N、730-302-796PF LCE CF1921LCE CF1873 CT-8151、331100000107LCE CF1920 LCE CF1821 730-302-786FD 730-302-796FDLCE CF1921 LCE CF1827B BSC24-N2374S BSM75-3709NLCE CF1938 2385210300 FEA850 FEA850A 2385211900LCE CF2091S FPH0213LCE CF2101C/ 79A763A 79A763B504 FAO0220/79A763ALZ250A 013J FEA662、LZ250A.000P FEA662A、LZ250A.013P LZ250A.013T MF-2095 Y265065CMF-3131 BSM35-3219 FFA81045H FFA73015HMF-3323 MF-3323A FFA79014U BSC25-0134MF-3323A FFA79014U BSC25-0134 MF-3323MF-6114 BSC25-0251M、37-SC25M0-2510X TFB-016、5062601600MF-6398 FEA780、730-302-7681A FUA-17A010 FEA880MF-6407 BSM26-0202 BSM75-3707 CT-8670、KTC9970 BSC26-1451 MF-6421 BSC26-1451 BSC26-1460MF-6540 490-170-6540 MF-6540B 490-170-6687MF-6540B 490-170-6687 490-1706540 MF-6540MF-6581/ 730-302-797N FWK0062B、730-302-797N FEA946 FEA946A LCE CF1737MF-6623 FUA17010 TRAN-8693 、530-302-700SAMSU1FVH002 CA-0215TAD53712 /LZ250A.013T FEA662、LZ250A.000P FEA662A、L250A.013P LZ250A 013JTBC000*007 TBC000*033 BSC24-4005TBC000*033 BSC24-4005 TBC000*007TFB-016 BSC25-0251M、37-SC25M0-2510X MF-6114TFB023 TFB025TFB025 TFB023TFB-251T LCE CF0821TFB-274T FSN-15B027NTFB-3501 TFB-3502TFB-3502 TFB-3501TFB-7002A/ FEA766A BSC24-N233S FEA771 BSC25-6503/C-FBT -1770DFTRAN-6515 LCE CF1517TRAN-8693 FUA17010 MF-6623V770 BSM35-3316D/Q770 BSM35-3316D/F772 BSM35-3316/F770D FQM-17B007Y265065C MF-2095Y265161 LCE CF0706 Y265163Y265163 Y265161 LCE CF0706Y265275 Y265387 Y265432BY265382 Y265434 6174Z-1024AY265387 Y265275 Y265432BY265432B Y265387 Y265275Y265434 6174Z-1024A Y265382ZTFJ3385A ZTFJ73369A、80000371ZTFJ73345A FEA284、5RH0000060 FFA86012D LCE CF0724A ZTFJ73369A/ 8000370 ZTFJ3385A。

英飞拓产品型号

英飞拓产品型号英飞拓产品型号渠道产品，价格优惠，不满意可退货 150********2．1 固定摄像机-PALV5101-A50142 ⼀体化摄像机2．3 因定半球摄像机2．4 V1700A系列快球2．5 V1750A系列充氮快球2．6 V1700S系列内置单模光端机的快球2．7 V1900A系列快球2．8⼀体化云台摄像机2．9恒速球形护罩/云台2．10快球零部件1．模拟监控前端产品2．1 固定摄像机V5101-A2014 V5101-A3014 V5101-A5014 V5101-A2019 V5101-A3019 V5102-A2014 V5102⽇夜型因定摄像机V5102-A3014 V5102-A5014V5102-A3019 V5102-A2019V5103宽动态彩⾊固定摄像机V5103-A3014V1025-1H⾼解析度彩⾊摄像机V1025-1HV1026-1⾼解析度⽇夜转换型摄像机V1026-1V1027-1 1/2英⼨宽动态⾼灵敏度低照度彩⾊摄像机V1027-1V1033-1宽动态⽇夜转换型摄像机V1033-12．2⼀体化摄像机PALV1224⼀体化彩⾊摄像机V1224-22A14V1244⼀体化⽇夜转换摄像机V1244-23A14 V1244-26A14 V5411-A2014ST V5411-A2014SU V5411-A2014SV 2．3固定半球摄像机PALV5411-A2014SW V5411-A2014SX V5411-A2014SYV5411-A2014SZ480线⼿动变焦⾃动光圈镜头V5411-A2014 SBV5411-A2014 SDV5411-A2014SE V5411-A2014SC V5411-A2014SF520线固定焦距镜头V5411-A3014ST V5411-A3014SU V5411-A3014SV V5411-A3014SW V5411-A3014SX V5411-A3014SY V5411-A3014SZ520线⼿动变焦⾃动光圈镜头V5411-A3014SB V5411-A3014SD V5411-A3014SE V5411-A3014SCV5512室内⽇夜型因定半球摄像机V5411-A3014SF V5512-A2014SB V5512-A2014SE520线⼿动变焦⾃动光圈镜头V5512-A3014SB V5512-A3014SEV5413室内宽动态彩⾊固定半球摄像机V5512-A3014SB V5413-A3024SB V5413-A3024SE2．3固定半球摄像机PALV5411-A2014ST V5411-A2014SU V5411-A2014SV V5411-A2014SW V5411-A2014SXV5411-A2014SY480线⼿动变焦⾃动光圈镜头V5411-A2014SZ V5411-A2014SB V5411-A2014SD V5411-A2014SE V5411-A2014SC V5411-A2014SF520线固定焦距镜头V5411-A3014ST V5411-A3014SU V5411-A3014SV V5411-A3014SW V5411-A3014SZ V5411-A3014SY V5411-A3014SX520线⼿动变焦⾃动光圈镜头V5411-A3014SB V5411-A3014SD V5411-A3014SE V5411-A3014SCV5512室内⽇夜型因定半球摄像机V5411-A3014SF V5512-A2014SB520线⼿动变焦⾃动光圈镜头V5512-A2014SE V5512-A3014SB V5512-A3014SB V5512-A3014SEV5413室内宽动态彩⾊固定半球摄像机V5413-A3024SBV1700A系列快球PAL室内吸顶装快球V1725A-C1C2C6 V1726A-C1C2C6 V1727A-C1C2C6 V1728A-C1C2C6 V1724A-C1C2C6 V1729A-C1C2C6 V1723A-C1C2C6室内⽀架装快球V1725A-C1C2B6 V1726A-C1C2B6 V1727A-C1C2B6 V1728A-C1C2B6 V1724A-C1C2B6 V1729A-C1C2B6 V1723A-C1C2B6室外吸顶装快球V1745A-C1C2C6 V1746A-C1C2C6 V1747A-C1C2C6 V1748A-C1C2C6 V1744A-C1C2C6 V1749A-C1C2C6 V1743A-C1C2C6室外⽀架装快球V1745A-C1C2B6 V1746A-C1C2B6 V1747A-C1C2B6 V1748A-C1C2B6 V1744A-C1C2B6 V1749A-C1C2B6 V1743A-C1C2B62．5 V1750A 系列充氮快球-PAL室内充氮吊装快球V1757A-C1C3B6 V1758A-C1C3B6 V1759A-C1C3B6 V1753A-C1C3B6 V1791室内内置单模光端机吸顶装快球V1725S-C1C2C6 V1726S-C1C2C6 V1727S-C1C2C6 V1728S-C1C2C6 V1729S-C1C2C6 V1723S-C1C2C6室内内置单模光端机⽀架装快球V1725S-C1C2B6V1726S-C1C2B6V1727S-C1C2B6 V1728S-C1C2B6 V1729S-C1C2B6 V1723S-C1C2B6室外内置单模光端机吸顶装快球V1745S-C1C2C6 V1746S-C1C2C6 V1747S-C1C2C6 V1748S-C1C2C6 V1743S-C1C2C6 V17243S-C1C2C6室外内置单模光端机⽀架装快球V1745S-C1C2B6 V1746S-C1C2B6 V1747S-C1C2B6 V1748S-C1C2B6 V1749S-C1C2B6 V1724S-C1C2B62．7V1900A系列快球PAL室内吸顶装快球V1901A-C1C2C6 V1902A-C1C2C6 V1903A-C1C2C6 V1904A-C1C2C6 V1906A-C1C2C6室内⽀架装快球V1901A-C1C2B6 V1902A-C1C2B6 V1903A-C1C2B6 V1904A-C1C2B6 V1906A-C1C2B6室外吸顶装快球V1911A-C1C2C6 V1912A-C1C2C6 V1913A-C1C2C6 V1914A-C1C2C6 V1916A-C1C2B6 V1917A-C1C2B6室外⽀架装快球V1911A-C1C2B6 V1912A-C1C2B6 V1913A-C1C2B6 V1914A-C1C2B6 V1916A-C1C2B6 V1917A-C1C2B62．8 ⼀体化云台摄像机V1492-18A15 V1492-23A15 V1492-26A15 V1492-35A15 V1492-36A15 V1492-18A16 V1492-23A16 V1492-26A16 V1492-35A16 V1492-36A16 V1492-18A17 V1492-23A17 V1492-26A17 V1492-35A17 V1492-36A17 V1492-18A18 V1492-23A18 V1492-26A18 V1492-35A18V1492-36A18⼀体化云台⽀架（适⽤于V1492、V1493）V1662-W1 V1662-S1 V1662-C1 V1662-DV1493中型⾼速云台V1493-D16V7A15 V1493-DP16V7A15 V1493-A15 V1493-D16V7A16 V1493-DP16V7A16 V1493-A16 V1493-D16V7A17 V1493-DP16V7A17 V1493-A17 V1493-D16V7A18 V1493-DP16V7A18 V1493-A18V1631隔爆云台摄像机V1631-23A19 V1631-25A19防爆护罩V1421-15SHB6-2V1421-15SHB8-2V1421-15A6-2V1421-15A8-2隔爆云台⽀架V1664-W V1664-C V1664-S V1665-W12．9恒速球形护罩/云台V1682 系列室内/室外恒速球形云台V1682-C2B-9HBPV1682-C2B-9HBP2．10 快球零部件V1761 V1761L V1762 V1763 V1764 V1764A V1764B V1765 V1765A V1766适⽤V1750A系列充氮快球V1761S V1762S V1763S球芯V1700N系列⽹络快球球芯(PAL)(坜另配视频缟码卡)V1825N-C16 V1826N-C16 V1827N-C16 V1828N-C16 V1829N-C16 V1825N-C15 V1826N-C15 V1827N-C15V1828N-C16 V1829N-C16V1700A系列快球球芯(PAL)V1825A-C16 V1826A-C16 V1827A-C16 V1828A-C16 V1829A-C16 V1825N-C15 V1826N-C15 V1827N-C15V1828N-C16 V1829N-C16V1750A系列充氮快球球芯(PAL)V1825AP-C16 V1826AP-C16 V1827AP-C16 V1828AP-C16 V1829AP-C16 V1825AP-C15 V1826AP-C15 V1827AP-C15 V1828AP-C15 V1829AP-C15V1700S系列光端机快球球芯（PAL）V1825AF-C16 V1826 AF-C16 V1827 AF-C16 V1828 AF-C16 V1829 AF-C16 V1825AF-C15 V1826 AF-C15 V1827 AF-C15 V1828 AF-C15 V1829 AF-C15V1900A系列快球球芯（PAL）V1901A-C16 V1902A-C16 V1903A-C16 V1904A-C16 V1905A-C16 球罩快球下罩（不带法兰）V1840-C2 V1840-S2 V1840-C3 V1840-S3室内吸顶装配罩下罩（带法兰）V1840-C2C V1840-S2C V1840-C3C V1840-S3C室内⽀架装配罩下罩（带法兰）V1840-C2B V1840-S2B V1840-C3B V1840-S3B室外⽀架装和吸顶装配罩下罩（带法兰和加热器）V1840-C2O V1840-S2O V1840-C3O V1840-S3O V1840P-C3OV1840P-S3O快球上罩（带法兰）V1850-IC V1850-IB V1850-OC V1850-OB V1850P-OB V1852-IC V1852-IB V1852-OC V1852-OB快球电源板V1860A-C6 V1860N-L6 V1860A-C5 V1860N-L5快球电源V3922-24A-26．键盘及辅助设备6．1 键盘V2100 V2109X V2111X V2110 V2115 V2116X7．3 V2020系列中型矩阵切换/控制器V2020AX-16X4 V2020AX-16X8 V2020AX-16X12 -16X16 V2020AX-16X20 V2020AX-16X24 V2020AX-16X28V2020AX-16X32 V2020AX-32X4 V2020AX-32X8 V2020AX-32X12 V2020AX-32X16 V2020AX-32X20 V2020AX-32X24 V2020AX-32X28 V2020AX-32X32 V2020AX-48X4 V2020AX-48X8V2020AX-48X12 V2020AX-48X16 V2020AX-48X20 V2020AX-48X24 V2020AX-48X28 V2020AX-48X32 V2020AX-64X4 V2020AX-64X8 V2020AX-64X12 V2020AX-64X16 V2020AX-64X20 V2020AX-64X24 V2020AX-64X28 V2020AX-64X32 V2020AX-80X4 V2020AX-80X8 V2020AX-80X12 V2020AX-80X16 V2020AX-80X20 V2020AX-80X24V2020AX-80X28 V2020AX-80X32 V2020AX-96X4 V2020AX-96X8 V2020AX-96X12 V2020AX-96X16 V2020AX-96X20 V2020AX-96X24 V2020AX-96X28 V2020AX-96X32V2020AX-112X4 V2020AX-112X8 V2020AX-112X12 V2020AX-112X16 V2020AX-112X20 V2020AX-112X24V2020AX-112X28 V2020AX-112X32 V2020AX-128X4 V2020AX-128X8 V2020AX-128X12 V2020AX-128X16V2020AX-128X20 V2020AX-128X24 V2020AX-128X28 V2020AX-128X32 V2020AX-144X4 V2020AX-144X8V2020AX-144X12 V2020AX-144X16 V2020AX-144X20 V2020AX-144X24 V2020AX-144X28 V2020AX-144X32V2020AX-160X4 V2020AX-160X8 V2020AX-160X12 V2020AX-160X16 V2020AX-160X20 V2020AX-160X24V2020AX-160X28 V2020AX-160X32 V2020AX-176X4 V2020AX-176X8 V2020AX-176X12 V2020AX-176X16V2020AX-176X20 V2020AX-176X24 V2020AX-176X28 V2020AX-176X32 V2020AX-192X4 V2020AX-192X8V2020AX-192X12 V2020AX-192X16 V2020AX-192X20 V2020AX-192X24 V2020AX-192X28 V2020AX-192X32 V2020AX-208X4 V2020AX-208X8 V2020AX-208X12 V2020AX-208X16 V2020AX-208X20 V2020AX-208X24V2020AX-208X28 V2020AX-208X32 V2020AX-224X4 V2020AX-224X8 V2020AX-224X12 V2020AX-224X16V2020AX-224X20 V2020AX-224X24 V2020AX-224X28 V2020AX-224X32 V2020AX-240X4 V2020AX-240X8 V2020AX-240X12 V2020AX-240X16 V2020AX-240X20 V2020AX-240X24 V2020AX-240X28 V2020AX-240X32V2040AX-16X4 V2040AX-16X8 V2040AX-16X12 V2040AX-16X16 V2040AX-16X20 V2040AX-16X24V2040AX-16X28 V2040AX-16X32 V2040AX-32X4 V2040AX-32X8 V2040AX-32X12 V2040AX-32X16V2040AX-32X20 V2040AX-32X24 V2040AX-32X28 V2040AX-32X32 V2040AX-48X4 V2040AX-48X8V2040AX-48X12 V2040AX-48X16 V2040AX-48X20 V2040AX-48X24 V2040AX-48X28 V2040AX-48X32V2040AX-64X4 V2040AX-64X8 V2040AX-64X12 V2040AX-64X16 V2040AX-64X20 V2040AX-64X24 V2040AX-64X28 V2040AX-64X32 V2040AX-80X4 V2040AX-80X8 V2040AX-80X12 V2040AX-80X16 V2040AX-80X20V2040AX-80X24 V2040AX-80X28 V2040AX-80X32V2040AX-96X4 V2040AX-96X8 V2040AX-96X12 V2040AX-96X16 V2040AX-96X20 V2040AX-96X24 V2040AX-96X28 V2040AX-96X32 V2040AX-112X4 V2040AX-112X8 V2040AX-112X12 V2040AX-112X16 V2040AX-112X20 V2040AX-112X24 V2040AX-112X28V2040AX-112X32 V2040AX-128X4 V2040AX-128X8 V2040AX-128X12 V2040AX-128X16V2040AX-128X20 V2040AX-128X24 V2040AX-128X28 V2040AX-128X32 V2040AX-144X4V2040AX-144X8 V2040AX-144X12 V2040AX-144X16 V2040AX-144X20 V2040AX-144X24V2040AX-144X28 V2040AX-144X32 V2040AX-160X4 V2040AX-160X8 V2040AX-160X12V2040AX-160X16 V2040AX-160X20 V2040AX-160X24 V2040AX-160X28 V2040AX-160X32 V2040AX-176X4V2040AX-176X8 V2040AX-176X12 V2040AX-176X16 V2040AX-176X20V2040AX-176X24 V2040AX-176X28 V2040AX-176X32 V2040AX-192X4 V2040AX-192X8V2040AX-192X12 V2040AX-192X16 V2040AX-192X20 V2040AX-192X24 V2040AX-192X28V2040AX-192X32V2040AX-208X4 V2040AX-208X8 V2040AX-208X12 V2040AX-208X16 V2040AX-208X20 V2040AX-208X24V2040AX-208X28 V2040AX-208X32 V2040AX-224X4 V2040AX-224X8 V2040AX-224X12 V2040AX-224X16V2040AX-224X20 V2040AX-224X24 V2040AX-224X28 V2040AX-224X32 V2040AX-240X4 V2040AX-240X8V2040AX-240X12 V2040AX-240X16 V2040AX-240X20 V2040AX-240X24 V2040AX-240X28 V2040AX-240X32V2040AX-256X4V2040AX-256X8 V2040AX-256X12 V2040AX-256X16 V2040AX-256X20 V2040AX-256X24V2040AX-256X28 V2040AX-256X32A2011X-16X5 A2011X-32X5 A2020X-16X4 A2020X-16X8 A2020X-16X12 A2020X-16X16 A2020X-16X20 A2020X-16X24 A2020X-16X28 A2020X-16X32 A2020X-32X4 A2020X-32X8 A2020X-32X12 A2020X-32X16 A2020X-32X20 A2020X-32X24 A2020X-32X28A2020X-32X32 A2020X-48X4 A2020X-48X8 A2020X-48X12 A2020X-48X16 A2020X-48X20A2020X-48X24 A2020X-48X28 A2020X-48X32 A2020X-64X4 A2020X-64X8 A2020X-64X12A2020X-64X16 A2020X-64X20 A2020X-64X24 A2020X-64X28 A2020X-64X32 A2020X-80X4A2020X-80X8 A2020X-80X12 A2020X-80X16 A2020X-80X20 A2020X-80X24 A2020X-80X28A2020X-80X32 A2020X-96X4 A2020X-96X8 A2020X-96X12 A2020X-96X16 A2020X-96X20 A2020X-96X24 A2020X-96X28 A2020X-96X32 A2020X-112X4A2020X-112X8 A2020X-112X12 A2020X-112X16 A2020X-112X20 A2020X-112X24A2020X-112X28 A2020X-112X32 A2020X-128X4 A2020X-128X8 A2020X-128X12 A2020X-128X16 A2020X-128X20 A2020X-128X24 A2020X-128X28 A2020X-128X32A2020X-144X4 A2020X-144X8 A2020X-144X12 A2020X-144X16 A2020X-144X20 A2020X-144X24 A2020X-144X28 A2020X-144X32 A2020X-160X4 A2020X-160X8 A2020X-160X12 A2020X-160X16 A2020X-160X20 A2020X-160X24 A2020X-160X28A2020X-160X32 A2020X-176X4 A2020X-176X8 A2020X-176X12 A2020X-176X16 A2020X-176X20A2020X-176X24 A2020X-176X28 A2020X-176X32 A2020X-192X4 A2020X-192X8 A2020X-192X12 A2020X-192X16 A2020X-192X20 A2020X-192X24 A2020X-192X28 A2020X-192X32 A2020X-208X4 A2020X-208X8。

Urovo-DT50-Mobile-Computer-User-Guide

lUSER GUIDEDT50操作指南DT50 User GuideAndroid 9.0https://.au注释：Note:*本说明是针对DT50通用功能，您的PDA设备可能没有其中某些功能，或者说明书没有介绍您的DT50设备终端某些功能。

* This Guide is for general functions of DT50 only. Your PDA device may not have some functions wherein or the Instruction gives no description to some functions in your DT50 device terminal.*本说明书的插图可能与实际产品不同，请以实物为准。

* There may be differences between the illustrations in this Guide and the actual product. And the actual product shall prevail.©版权所有深圳优博讯科技股份有限公司 2019.© All rights reserved Shenzhen Urovo Technology Co., Ltd. 2019.使用条款Terms of usage声明Statement本手册包含深圳市优博讯科技股份有限公司的专有信息。

他的目的仅仅是为了帮助使用当事人更好的操作、使用及维护本文所描述的设备。

未经优博讯的书面许可，不得复制或向任何一方披露本文专有信息。

This Guide includes proprietary information of Shenzhen Urovo Technology Co., Ltd. Its purpose is to help users better operate, use and maintain the device described herein only. Without written permit of Urovo, the proprietary information in the text shall not be copied or disclosed to any other party.产品改进Product improvement优博讯的产品将会持续改进，所有规格和设计如有变更，恕不另行通知。

捷波悍马HA07-Ultra 主板说明书

第二章硬件安装 2-1 硬件安装步骤 ..............................................................................................7 2-2 检查主板的跳线设置....................................................................................7 2-3 安装 CPU .....................................................................................................7 2-3-1 术语表.....................................................................................7 2-3-2 关于 AMD Athlon64 Socket AM2+ CPU............................8 2-4 安装系统内存................................................................................................9 2-5 安装扩展卡....................................................................................................10 2-5-1 扩展卡的安装过程 ................................................................10 2-5-2 定义扩展卡的 IRQS..............................................................10 2-5-3 主板的中断请求表 ................................................................11 2-5-4 PCI-Express 插槽..................................................................11 2-6 连接器和引脚连接头....................................................................................12 2-6-1 连接器 .................................................................................12 2-6-2 引脚连接头 ..........................................................................15 2-7 启动计算机 ..................................................................................................19

Richtek 技术公司 RT9048A 数据手册说明书

RT9048A®Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.©Ordering InformationNote :Richtek products are :❝ RoHS compliant and compatible with the current require-ments of IPC/JEDEC J-STD-020.❝ Suitable for use in SnPb or Pb-free soldering processes.1.5A, Low Input Voltage, Ultra-Low Dropout Linear Regulator with EnableGeneral DescriptionThe RT9048A is a high performance positive voltage regulator designed for applications requiring ultra-low input voltage and ultra-low dropout voltage at up to 1.5A. The feature of ultra-low dropout voltage is ideal for applications where output voltage is very close to input voltage. The input voltage can be as low as 1.6V and the output voltage is adjustable by an external resistive divider as low as 0.65V. The RT9048A provides an excellent output voltage regulation over variations in line, load and temperature.Over-current and over-temperature protection functions are provided. Additionally, an enable pin is designed to further reduce power consumption while shutdown and the shutdown current is as low as 0.1μA.The RT9048A is available in the WDFN-8L 3x3 package.Features●Input Voltage as Low as 1.6V●*********************************●Over-Current Protection●Over-Temperature Protection●0.1μA Input Current in Shutdown Mode ●Enable Control●RoHS Compliant and Halogen FreeApplications●T elecom/Networking Cards ●Motherboards/Peripheral Cards ●Industrial Applications ●Wireless Infrastructure ●Set-Top Box●Medical Equipment ●Notebook Computers●Battery Powered SystemsSimplified Application CircuitG : Green (Halogen Free and Pb Free)：WDFN-8L 3x3 (W-Type)Marking InformationRJ = : Product CodeYMDNN : Date CodeV OUTRT9048A©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Pin ConfigurationWDFN-8L 3x3GNDADJVOUTRT9048A©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.OperationThe RT9048A is a low input voltage low dropout LDO that supports the input voltage range from 1.6V to 6V and the output current can be up to 1.5A. The RT9048A uses internal charge pump to achieve low input voltage operation and the internal compensation network is well designed to achieve fast transient response with good stability.In steady-state operation, the feedback voltage is regulated to the reference voltage by the internal regulator.When the feedback voltage signal is less than the reference, the on resistance of the power MOSFET is decreased to increase the output current through the power MOSFET , and the feedback voltage will be charge back to reference. If the feedback voltage is less than the reference, the power MOSFET current is decreased to make the output voltage discharge back to reference by the loading current.Reverse Current ProtectionThe reverse current protection is guaranteed by the N-MOSFET with bulk capacitors connected to GND and the internal circuit. The reverse voltage detection circuit shuts the total loop down if the output voltage is higher than input voltage.UVLO ProtectionThe RT9048A provides an input under-voltage lockout protection (UVLO). When the input voltage exceeds the UVLO rising threshold voltage (1.43V typ.), the device resets the internal circuit and prepares for operation. If the input voltage falls below the UVLO falling threshold voltage during normal operation, the device will be shut down. A hysteresis (150mV typ.) between the UVLO rising and falling threshold voltage is designed to avoid noise.Current Limit ProtectionThe RT9048A continuously monitors the output current to protect the pass transistor against abnormal operations.When an overload or short circuit is encountered, the current limit circuitry controls the pass transistor's gate voltage to limit the output within the predefined range.Output Active DischargeWhen the RT9048A is operating at shutdown mode, the device has an internal active pull down circuit that connects the output to GND through a 500Ω resistor for output discharging purpose.Over-Temperature ProtectionThe over-temperature protection function will turn off the MOSFET when the junction temperature exceeds160°C (typ.). Once the junction temperature cools down by approximately 30°C, the regulator will automatically resume operation.Soft-StartThe V OUT soft-start ramp up speed has related with V IN driving ability, with higher V IN input level with faster V OUT ramp up speed and less soft-start time required. Table 1,Table 2, Table 3 and Table 4 show the required soft-start time with different V IN operating range for design reference.Table 1. Output 0.75V Soft-Start time with V INRT9048A©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Table 2. Output 0.9V Soft-Start time with V INTable 3. Output 1.1V Soft-Start time with V INTable 4. Output 1.8V Soft-Start time with V INRT9048A©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Absolute Maximum Ratings (Note 1)●Supply Voltage, VIN ------------------------------------------------------------------------------------------------------ −0.3V to 7V ●Other Pins------------------------------------------------------------------------------------------------------------------- −0.3V to 6V ●Power Dissipation, P D @ T A = 25°CWDFN-8L 3x3--------------------------------------------------------------------------------------------------------------3.22W●Package Thermal Resistance (Note 2)WDFN-8L 3x3, θJA ---------------------------------------------------------------------------------------------------------31°C/W WDFN-8L 3x3, θJC --------------------------------------------------------------------------------------------------------8°C/W ●Lead Temperature (Soldering, 10 sec.)-------------------------------------------------------------------------------260°C ●Junction T emperature -----------------------------------------------------------------------------------------------------150°C●Storage T emperature Range -------------------------------------------------------------------------------------------- −65°C to 150°C ●ESD Susceptibility (Note 3)HBM (Human Body Model)----------------------------------------------------------------------------------------------2kVRecommended Operating Conditions (Note 4)●Supply Voltage, VIN ------------------------------------------------------------------------------------------------------1.6V to 6V●Junction T emperature Range -------------------------------------------------------------------------------------------- −40°C to 125°CElectrical Characteristics(V IN = 1.6V to 6V, I OUT = 10μA to 1.5A, V ADJ = V OUT , T A = 25°C, unless otherwise specified)RT9048A©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Note 1. Stresses beyond those listed under “Absolute Maximum Ratings ” may cause permanent damage to the device.These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability.Note 2. θJA and θJC are measured or simulated at T A = 25°C based on the JEDEC 51-7 standard.Note 3. Devices are ESD sensitive. Handling precaution is recommended.Note 4. The device is not guaranteed to function outside its operating conditions.Note 5. Guaranteed by design.RT9048A©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Typical Application CircuitFigure 1. Adjustable Voltage RegulatorOUTOUT VRT9048A©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Typical Operating CharacteristicsDropout Voltage vs. Output Current5010015020025030000.30.60.91.21.5Output Current (A)D r o p o u t V o l t a g e (m V )Reference Voltage vs. Temperature0.600.610.620.630.640.650.660.670.680.690.70-50-25255075100125Temperature (°C)R e f e r e n c e V o l t a g e (V )Quiescent Current vs. Temperature0.00.20.40.60.81.01.21.41.6-50-25255075100125Temperature (°C)Q u i e s c e n t C u r r e n t (m A)Shutdown Current vs. Temperature0.000.100.200.300.400.500.600.700.800.901.00-50-25255075100125Temperature (°C)S h u t d o w n C u r r e n t (μA )UVLO vs. Temperature0.80.91.01.11.21.31.41.51.61.7-50-25255075100125Temperature (°C)UV L O (V )EN Threshold Voltage vs. Input Voltage0.650.700.750.800.850.900.951.001.051.101.522.533.544.555.56Input Voltage (V)E N T h r e s h o l d V o l ta g e (V )RT9048A©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.PSRR2040608010 100 1K10K100K1MFrequency (Hz)P o w e r -S u p p l y R e j e c t i o n R a t i o (d B )Time (200μs/Div)V EN (5V/Div)I OUT (1A/Div)V OUT(1V/Div)V IN = 2.5V, V OUT = 1.8V, V EN = 5V, I OUT = 1.5ATime (200μs/Div)V EN (5V/Div)I OUT (1A/Div)V OUT(1V/Div)V IN = 2.5V, V OUT = 1.8V, V EN = 5V, I OUT = 1.5ATime (50μs/Div)V IN = 2.5V, V OUT= 1.8V, I OUT = 0.5A to 1.5AI OUT(500mA/Div)V OUT (50mV/Div)Time (4ms/Div)V IN = 2.5V to 3.3V, V OUT = 1.8V, I OUT = 1.5AV OUT (10mV/Div)V IN(50mV/Div)EN Threshold Voltage vs. Temperature0.40.50.60.70.80.91.01.11.2-50-25255075100125Temperature (°C)E N T h r e s h o l d V o lt a g e (V )RT9048A©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Application InformationThe RT9048A is a low voltage, low dropout linear regulator.The input voltage supporting range is from 1.6V to 6V and the adjustable output voltage is from 0.65V to (V IN −V DROP ).Output Voltage SettingThe RT9048A output voltage is adjustable from 0.65V to V IN − V DROP via the external resistive voltage divider. The voltage divider resistors can have values of up to 800k Ωbecause of the very high impedance and low bias current of the sense comparator. The output voltage is set according to the following equation :OUT ADJ R1V = V 1+R2⎛⎫⨯ ⎪⎝⎭where V ADJ is the reference voltage with a typical value of 0.65V.Chip Enable OperationThe RT9048A goes into sleep mode when the EN pin is in a logic low or left open condition. In this condition, the pass transistor, error amplifier, and band gap are all turned off, reducing the supply current to only 0.1μA (typ.). The EN pin can be directly tied to VIN to enable the device and work normally.Dropout VoltageThe dropout voltage refers to the voltage difference between the VIN and VOUT pins while operating at specific output current. The dropout voltage V DROP also can be expressed as the voltage drop on the pass-FET at specific output current (I RATED ) while the pass-FET is fully operating at ohmic region and the pass-FET can be characterized as an resistance R DS(ON). Thus, the dropout voltage can be defined as (V DROP = V IN − V OUT = R DS(ON)) x I RATED ). For normal operation, the suggested LDO operating range is (V IN > V OUT + V DROP ) for good transient response. Vice versa, while operating at the ohmic region will degrade the performance severely.C IN and C OUT SelectionThe RT9048A is designed specifically to work with low ESR ceramic output capacitor for space saving and performance consideration. Using a ceramic capacitor with capacitance range from 10μF to 47μF on the output ensures stability.Input capacitance is selected to minimize transient input droop during load current steps. For general application,the requirement of input capacitor with a 10μF is recommended to minimize input impedance and provide the desired effect and do not affect stability.Thermal ConsiderationsThermal protection limits power dissipation in the RT9048A. When the operation junction temperature exceeds 160°C, the OTP circuit starts the thermal shutdown function and turns the pass element off. The pass element turns on again after the junction temperature cools by 30°C.The RT9048A output voltage will be closed to zero when output short circuit occurs as shown in Figure 2. It can reduce the IC temperature and provides maximum safety to end users when output short circuit occurs.Figure 2. Short Circuit Protection when Output ShortCircuit OccursV OUT Short to GNDV OUTI OUTDS9048A-00 December 2020©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula :P D(MAX) = (T J(MAX) − T A ) / θJAwhere T J(MAX) is the maximum junction temperature, T A is the ambient temperature, and θJA is the junction to ambient thermal resistance.For recommended operating condition specifications, the maximum junction temperature is 125°C. The junction to ambient thermal resistance, θJA , is layout dependent. For WDFN-8L 3x3 package, the thermal resistance, θJA , is 31°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at T A = 25°C can be calculated by the following formula :P D(MAX) = (125°C − 25°C) / (31°C/W) = 3.22W for WDFN-8L 3x3 packageThe maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA . The derating curve in Figure 3 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation.Layout ConsiderationsFor best performance of the RT9048A, the PCB layout suggestions below are highly recommend. All circuit components placed on the same side and as near to the respective LDO pin as possible. Place the ground return path connection to the input and output capacitor. Connect the ground plane with a wide copper surface for good thermal dissipation. Using vias and long power traces for the input and output capacitors connections is discouraged and has negative effects on performance. Figure 4 shows a layout example that reduce conduction trace loops,helping to minimize inductive parasitics and load transient effects while improving the circuit stability.Figure 3. Derating Curve of Maximum Power Dissipation0.00.51.01.52.02.53.03.54.0255075100125Ambient Temperature (°C)M a x i m u m P o w e r D i s s i p a t i o n (W )©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Figure 4. PCB Layout GuideDS9048A-00 December 2020©Copyright 2020 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.W-Type 8L DFN 3x3 PackageFootprint InformationRichtek Technology Corporation14F, No. 8, Tai Yuen 1st Street, Chupei CityHsinchu, Taiwan, R.O.C.Tel: (8863)5526789Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.。

YMF744B资料

YMF744BDS-1S PreliminaryOVERVIEWYMF744B (DS-1S) is a high performance audio controller for the PCI Bus. DS-1S consists of two separated functional blocks. One is the PCI Audio block and the other is the Legacy Audio block. PCI Audio block allows Software Driver to handle maximum of 73 concurrent audio streams with the Bus Master DMA engine. The PCI Audio Engine converts the sampling rate of each audio stream and the streams are mixed without utilizing the CPU or causing system latency. By using the Software Driver from YAMAHA, PCI Audio provides 64-voice XG wavetable synthesizer with Reverb and variation. It also supports DirectSound hardware accelerator, Downloadable Sound (DLS) and DirectMusic accelerator.Legacy Audio block supports FM Synthesizer, Sound Blaster Pro, MPU401 UART mode and Joystick function in order to provide hardware compatibility for numerous PC games on real DOS without any software driver. To achieve legacy DMAC compatibility on the PCI, DS-1S supports both PC/PCI and Distributed DMA protocols. DS-1S also supports Serialized IRQ for legacy IRQ compatibility.DS-1S supports the connection to AC’97 which provides high quality DAC, ADC and analog mixing, and it can connect two AC’97s. In addition, it supports consumer IEC958, Audio Digital Interface (SPDIF), to connect external audio equipment by digital.FEATURES• PCI 2.2 Compliant• PC’98/PC’99 specification Compliant• PCI Bus Power Management rev. 1.0 Compliant (Support D0, D2 and D3 state)• Supports clock run• PCI Bus Master for PCI AudioTrue Full Duplex Playback and Capture with different Sampling RateMaximum 64-voice XG capital Wavetable Synthesizer including GM compatibilityDirectSound Hardware AccelerationDirectMusic Hardware AccelerationDownloadable Sound (DLS) level-1• Legacy Audio compatibilityFM SynthesizerHardware Sound Blaster Pro compatibilityMPU401 UART mode MIDI interfaceJoystick• Supports Serialized IRQ • Supports PC/PCI and Distributed DMA for legacy DMAC (8237) emulation• Supports I2S serial input for Zoomed Video Port • Supports Consumer IEC958 Output (SPDIF OUT)• Supports Consumer IEC958 Input (SPDIF IN)• Supports AC’97 Interface (AC-Link) Revision 2.1• AC’97 Digital Docking• Supports 4-Channel Speaker• Hardware Volume Control• EEPROM Interface• Single Crystal operation (24.576MHz)• 3.3V Power supply (5V tolerant)• 128-pin LQFP YMF744B-V : 0.5mm pin pitchYMF744B-R : 0.4mm pin pitchLOGOSPIN CONFIGURATIONYMF744B-V (0.5mm pin pitch)128 Pin LQFP Top ViewA D 7A D 6A D 5P V D D 0A D 4A D 3A D 2A D 1P V S S 0A D 0S E R I R Q #P C G N T #P C R E Q #C L K R U N #C V D D 0R O M D I R O M C S V S S 0FRAME#2345678910111213141516171819202122232425262728293031323334353637381021011009998979695949392919089888786858483828180797877767574737271706968676665CBE2#AD16AD17AD18AD20AD21AD22PVSS4AD23IDSEL CBE3#AD24AD25PVDD2PVSS3IRDY#TRDY#DEVSEL#PVDD1STOP#PERR#SERR#PAR CBE1#PVSS2AD15AD14AD13AD12AD11AD10AD9AD8AD19AD26SPDIFIN TEST#VSS3VDD1CSDO CBCLK CSDI0CSYNC VDD2CMCLK IRQ5GPIO2GPIO1GPIO0RESERVE8RESERVE9RESERVE10VSS1XI24XO24LOOPF SPDIFOUT ZVBCLK ZVLRCK ZVSDI PVSS1CBE0#IRQ9IRQ10IRQ11IRQ7CVDD1LVDD DOCKEN#CSDI2RESERVE3RESERVE2VSS2VDD0CRST#R E S E R V E 0R E S E R V E 13R E S E R V E 14R E S E R V E 15R E S E R V E 16R E S E R V E 12R E S E R V E 1111031041051061071081091101111121131141151161171181191201211221231241251261271286463626160595857565554535251504948474645444342414039A D 27A D 28P V S S 5A D 29A D 30A D 31R E Q #G N T #G P 3G P 4G P 5G P 6G P 7R E S E R V E 1C V D D 2I N T A #G P 1G P 2R S T #P V D D 3R O M D O /V O L D W #R O M S K /V O L U P #R X DT X D G P 0P V S S 6P C I C L KYMF744B-R (0.4mm pin pitch)128 Pin LQFP Top View64636261605958575655545352515049484746454443424140393833343536379695949392919089888786858483828180797877767574737271706968676665ZVLRCK VDD1CMCLK CSDO IRQ10IRQ9IRQ7IRQ5GPIO2GPIO1GPIO0RESERVE3CSDI2DOCKEN#VSS1ZVBCLK LOOPF LVDD CVDD1SPDIFIN SPDIFOUT ZVSDI IRQ11XO24XI24RESERVE2VSS2VDD0CRST#CSYNC CSDI0CBCLK DEVSEL#234567891011121314151617181920212223242526272829303132IRDY#FRAME#PVSS3CBE2#AD17AD18AD19AD20AD21AD22PVSS4AD23IDSEL CBE3#TRDY#PVDD1STOP#SERR#PAR CBE1#PVSS2AD15AD14AD13AD12AD11AD10AD9AD16AD24PERR#R S T #103104105106107108109110111112113114115116117118119120121122123124125126127128102100999897101A D 25P V D D 2A D 26A D 27A D 28P V S S 5A D 29A D 30G P 6G P 7R E S E R V E 1C V D D 2I N T A #R E S E R V E 0P V D D 3P V S S 6G P 4G P 5R E Q #P C I C L K G P 1G P 2G P 3G N T #A D 31G P 0R X D T E S T #V S S 3T X D V D D 2V S S 0R E S E R V E 11R E S E R V E 12R E S E R V E 13R E S E R V E 10R E S E R V E 9A D 4A D 3A D 2A D 1P V S S 0A D 0S E R I R Q #P C G N T #P C R E Q #C L K R U N #C V D D 0R O M D I R O M D O /V O L D W #R O M S K /V O L U P #R O M C S R E S E R V E 16R E S E R V E 15R E S E R V E 14R E S E R V E 8P V D D 0A D 8P V S S 1C B E 0#A D 7A D 6A D 51PIN DESCRIPTION1. PCI Bus Interface (54-pin)Name I/O Type Size FunctionPCICLK I P PCI ClockRST#I P ResetAD[31:0]IO Ptr Address / DataC/BE[3:0]#IO Ptr Command / Byte EnablePAR IO Ptr ParityFRAME#IO Pstr FrameIRDY#IO Pstr Initiator ReadyTRDY#IO Pstr Target ReadySTOP#IO Pstr StopIDSEL I P ID SelectDEVSEL#IO Pstr Device SelectREQ#O Ptr PCI RequestGNT#I P PCI GrantPCREQ#O Ptr PC/PCI RequestPCGNT#I P PC/PCI GrantPERR#IO Pstr Parity ErrorSERR#O Pod System ErrorINTA#O Pod Interrupt signal output for PCI busSERIRQ#IO Ptr Serialized IRQCLKRUN#IO Ptr Clock Run2. AC’97 Interface (8-pin)Name I/O Type Size FunctionCRST#O T6mA Reset signal for AC’97CMCLK O C6mA Master Clock for AC’97 (24.576MHz)CBCLK I T-AC-link: Bit Clock for AC’97 audio dataCSDO O T6mA AC-link: AC’97 Serial audio output dataCSYNC O T6mA AC-link: AC’97 Synchronized signalCSDI0I T-AC-link: AC’97 Serial audio input data (Primary) CSDI2I Tup-AC-link: AC’97 Serial audio input data (Secondary) DOCKEN#I Tup-Docking Enable3. External Audio Interface (5-pin)Name I/O Type Size Function SPDIFOUT O T2mA Digital Audio Interface output SPDIFIN I Tup-Digital Audio Interface input ZVBCLK I Tup-Zoomed Video Port Bit Clock ZVLRCK I Tup-Zoomed Video Port L/R Clock ZVSDI I Tup-Zoomed Video Port Serial Data4. Legacy Device Interface (15-pin)Name I/O Type Size FunctionIRQ5O Ttr12mA Interrupt5 of Legacy AudioIt is directly connected to the interrupt signal of System I/O chip.IRQ7O Ttr12mA Interrupt7 of Legacy AudioIRQ9O Ttr12mA Interrupt9 of Legacy AudioIRQ10O Ttr12mA Interrupt10 of Legacy Audio IRQ11O Ttr12mA Interrupt11 of Legacy Audio.GP[3:0]I A-Game PortGP[7:4]I Tup-Game PortRXD I Tup-MIDI Data ReceiveTXD O T2mA MIDI Data Transfer5. Miscellaneous (11-pin)Name I/O Type Size Function ROMCS O T2mA Chip select for external EEPROMROMSK / VOLUP#IO Tup2mA Serial clock for external EEPROM or Hardware Volume (Up)ROMDO / VOLDW#IO Tup2mA Serial data output for external EEPROM or Hardware Volume (Down)ROMDI I Tup-Serial data input for external EEPROM XI24I C-24.576 MHz CrystalXO24O C-24.576 MHz CrystalLOOPF I A-Capacitor for PLLGPIO[2:0]IO Tup2mA General purpose Input / OutputGPIO2 can use for a reset pin of Secondary AC’97.TEST#I Tup-LSI Test pin (Do not connect externally.)6. Power Supply (22-pin)Name I/O Type Size FunctionPVDD[3:0]--- 3.3V Power supply for PCI Bus Interface PVSS[6:0]---Ground for PCI Bus InterfaceCVDD[2:0]--- 3.3V Power supply for Core logicVDD[2:0]--- 3.3V Power supplyVSS[3:0]---GroundLVDD--- 3.3V Power supply for PLL Filter7. Reserve Pin (13-pin)Name I/O Type Size FunctionRESERVE0O Pod-Reserve pins (Do not connect externally.) RESERVE[3:2]I Tup-RESERVE[16:8,1]---TYPET : TTL A : Analog Ptr : Tri-State PCITtr : Tri-State TTL C : CMOS Pstr : Sustained Tri-Sate PCI Tup : Pull up (Max. 300kohm) TTL P : PCI Pod : Open Drain PCIBLOCK DIAGRAMPCI Side Band PC/PCI S-IRQAudio Function Config RegisterPCI InterfaceLegacy AudioFM Synthesizer SB Pro D-DMA EngineMPU401JoystickPCI Bus Master DMA ControllerPCI Native Audio XG Synthesizer DirectSound Acc.Wave In/OutZV Port SRC Sampling ConverterSPDIF OutputAC-Link Interface Revision2.1SPDIF InputS e l e c t o rGPIO EEPROM I/FFUNCTION OVERVIEW1. PCI INTERFACEDS-1S supports the PCI bus interface and complies to PCI revision 2.2.1-1. PCI Bus CommandDS-1S supports the following PCI Bus commands.1-1-1. Target Device ModeC/BE[3:0]#Command0000Interrupt Acknowledge(not support)0001Special Cycle(not support)0010I/O Read0011I/O Write0100reserved0101reserved0110Memory Read0111Memory Write1000reserved1001reserved1010Configuration Read1011Configuration Write1100Memory Read Multiple (not support)1101Dual Address Cycle(not support)1110Memory Read Line(not support)1111Memory Write and Invalidate(not support)DS-1S does not assert DEVSEL# when accessed with commands that are indicated as (not supported) or reserved.1-1-2. Master Device ModeC/BE[3:0]#Command0110Memory Read0111Memory WriteWhen DS-1S becomes a Master Device, it generates only memory write and read cycle commands.1-2. PCI Configuration RegisterIn addition to the Configuration Register defined by PCI Revision 2.2, DS-1S provides proprietary PCI Configuration Registers in order to control legacy audio function, such as FM Synthesizer, Sound Blaster Pro, MPU401 and Joystick. These additional registers are configured by BIOS or the configuration software from YAMAHA Corporation.The following shows the overview of the PCI Configuration Register.Offset b[31..24]b[23..16]b[15..8]b[7..0]00-03h Device ID Vendor ID04-07h Status Command08-0Bh Base Class Code Sub Class Code Programming IF Revision ID0C-0Fh Reserved Header Type Latency Timer Reserved10-13h PCI Audio Memory Base Address14-17h Legacy Audio I/O Base Address (Dummy for SB, FM, MPU, D-DMA)18-1Bh Legacy Audio I/O Base Address (Dummy for Joystick)1C-2Bh Reserved2C-2Fh Subsystem ID Subsystem Vendor ID30-33h Reserved34-37h Reserved Cap Pointer38-3Bh Reserved3C-3Fh Maximum Latency Minimum Grant Interrupt Pin Interrupt Line40-43h Extended Legacy Audio Control Legacy Audio Control44-47h Subsystem ID Write Subsystem Vendor ID Write48-4Bh DS-1S Power Control 1DS-1S Control4C-4Fh DS-1S Power Control 2D-DMA Slave Configuration50-53h Power Management Capabilities Next Item Pointer Capability ID54-57h Reserved Power Management Control / Status58-5Bh DS-1S Secondary AC’97 Power Control ACPI Mode5C-5Fh Reserved60-63h Sound Blaster Base Address FM Synthesizer Base Address64-67h Joystick Base Address MPU401 Base Address68-FFh ReservedReserved registers are hardwired to “0”. All data written to these registers are discarded. The values read from these registers are all zero.DS-1S can be accessed by using any bus width, 8-bit, 16-bit or 32-bit.00-01h: Vendor IDRead OnlyDefault: 1073hAccess Bus Width: 8, 16, 32-bitb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0Vendor IDb[15:0]........Vendor IDThis register contains the YAMAHA Vendor ID registered in Revision 2.2. This register is hardwired to 1073h.02-03h: Device IDRead OnlyDefault: 0010hAccess Bus Width: 8, 16, 32-bitb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0Device IDb[15:0]........Device IDThis register contains the Device ID of DS-1S. This register is hardwired to 0010h.04-05h: CommandRead / WriteDefault: 0000hAccess Bus Width: 8, 16, 32-bitb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0 -------SER-PER---BME MS IOSb0................IOS: I/O SpaceThis bit is a dummy one that is capable of writing. This bit indicates for BIOS or OS that DS-1S includes I/O devices.b1................MS: Memory SpaceThis bit enables DS-1S to response to Memory Space Access.“0”: DS-1S ignores Memory Space Access.(default)“1”: DS-1S responds to Memory Space Access.b2................BME: Bus Master EnableThis bit enables DS-1S to act as a master device on the PCI bus.“0”: Do not set DS-1S to be the master device.(default)“1”: Set DS-1S to be the master device.b6................PER: Parity Error ResponseThis bit enables DS-1S responses to Parity Error.“0”: DS-1S ignores all parity errors.“1”: DS-1S performs error operation when DS-1S detects a parity error.b8................SER: SERR# EnableThis bit enables DS-1S to drive SERR#.“0”: Do not drive SERR#.(default)“1”: Drives SERR# when DS-1S detects an Address Parity Error on normal target cycle or a Data Parity Error on special cycle.06-07h: StatusRead / Write ClearDefault: 0210hAccess Bus Width: 8, 16, 32-bitb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0 DPE SSE RMA RTA STA DEVT DPD---CAP----b4................CAP: Capability(Read Only)This bit indicates that DS-1S supports the capability register. This bit is read only. When 58-59h : ACPI Mode register, ACPI bit is “0”, the bit is “1”. When ACPI bit is “1”, the bit is “0”.b8................DPD: Data Parity Error DetectedThis bit indicates that DS-1S detects a Data Parity Error during a PCI master cycle.b[10:9]........DEVT: DEVSEL TimingThis bit indicates that the decoding speed of DS-1S is Medium.b11..............STA: Signaled Target AbortThis bit indicates that DS-1S terminates a transaction with Target Abort during a target cycle.b12..............RTA: Received Target AbortThis bit indicates that a transaction is terminated with Target Abort while DS-1S is in the master memory cycle.b13..............RMA: Received Master AbortThis bit indicates that a transaction is terminated with Master Abort while DS-1S is in the master memory cycle.b14..............SSE: Signaled System ErrorThis bit indicates that DS-1S asserts SERR#.b15..............DPE: Detected Parity ErrorThis bit indicates that DS-1S detects Address Parity Error or Data Parity Error during a transaction.08h: Revision IDRead OnlyDefault: 02hAccess Bus Width: 8, 16, 32-bitb7b6b5b4b3b2b1b0Revision IDb[7:0]..........Revision IDThis register contains the revision number of DS-1S. This register is hardwired to 02h.09h: Programming InterfaceRead OnlyDefault: 00hAccess Bus Width: 8, 16, 32-bitb7b6b5b4b3b2b1b0Programming Interfaceb[7:0]..........Programming InterfaceThis register indicates the programming interface of DS-1S. This register is hardwired to 00h.0Ah: Sub-class CodeRead OnlyDefault: 01hAccess Bus Width: 8, 16, 32-bitb7b6b5b4b3b2b1b0Sub-class Codeb[7:0]..........Sub-class CodeThis register indicates the sub-class of DS-1S. This register is hardwired to 01h. DS-1S belongs to the Audio Sub-class.0Bh: Base Class CodeRead OnlyDefault: 04hAccess Bus Width: 8, 16, 32-bitb7b6b5b4b3b2b1b0Base Class Codeb[7:0]..........Base Class CodeThis register indicates the base class of DS-1S. This register is hardwired to 04h. DS-1S belongs to the Multimedia Base Class.0Dh: Latency TimerRead / WriteDefault: 00hAccess Bus Width: 8, 16, 32-bitb7b6b5b4b3b2b1b0Latency Timerb[7:0]tency TimerWhen DS-1S becomes a Bus Master device, this register indicates the initial value of the Master Latency Timer.0Eh: Header TypeRead OnlyDefault: 00hAccess Bus Width: 8, 16, 32-bitb7b6b5b4b3b2b1b0Header Typeb[7:0]..........Header TypeThis register indicates the device type of DS-1S. This is hardwired to 00h.10-13h: PCI Audio Memory Base AddressRead / WriteDefault: 00000000hAccess Bus Width: 8, 16, 32-bitb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0 MBA---------------b31b30b29b28b27b26b25b24b23b22b21b20b19b18b17b16MBA (higher)b[31:15]......MBA: Memory Base AddressThis register indicates the physical Memory Base address of the PCI Audio registers in DS-1S. The base address can be located anywhere in the 32-bit address space. Data in the DS-1S register is not prefetchable.Size of the register to be mapped into the memory space is 32,768 bytes.14-17h: Legacy Audio I/O Base Address (Dummy for SB, FM, MPU, D-DMA) Read / WriteDefault: 00000001hAccess Bus Width: 8, 16, 32-bitb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0IOBASE0-----I/O b31b30b29b28b27b26b25b24b23b22b21b20b19b18b17b16 ----------------b0................IO(Read Only)This bit indicates that the base address is assigned to I/O. This bit is hardwired to “1”.b[15:6]........IOBASE0This register is used so that the OS may secure I/O resources for Sound Blaster Pro, FM Synthesizer, MPU401 and D-DMA controller. Because this register is a dummy one, each for the I/O addresses of the above blocks is assigned with the I/O addresses set to 4C-4Dh and 60-65h respectively by the software driver.18-1Bh: Legacy Audio I/O Base Address (Dummy for Joystick)Read / WriteDefault: 00000001hAccess Bus Width: 8, 16, 32-bitb15B14b13b12b11b10b9b8b7b6b5b4b3b2b1b0IOBASE1-I/O b31B30b29b28b27b26b25b24b23b22b21b20b19b18b17b16 ----------------b0................IO(Read Only)This bit indicates that the base address is assigned to I/O. This bit is hardwired to “1”.b[15:2]........IOBASE1This register is used so that the OS may secure I/O resource for the joystick port. Because this register isa dummy one, the joystick I/O address is assigned with the I/O address set to 66-67h by the softwaredriver.2C-2Dh: Subsystem Vendor IDRead OnlyDefault: 1073hAccess Bus Width: 8, 16, 32-bitb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0Subsystem Vendor IDb[15:0]........Subsystem Vendor IDThis register contains the Subsystem Vendor ID. In general, this ID is used to distinguish adapters or systems made by different IHVs using the same chip by the same vendor. This register is read only. To write the IHV’s Vendor ID, use 44-45h (Subsystem Vendor ID Write Register). IHVs must change this ID to their Vendor ID in the BIOS POST routine.In case of the system such as Sound Card which BIOS can not control, this ID can be changed by connecting EEPROM externally. Then, Subsystem Vendor ID Write Register is invalid.In case EEPROM is not externally, the default value is the YAMAHA's Vendor ID, 1073h.2E-2Fh: Subsystem IDRead OnlyDefault: 0010hAccess Bus Width: 8, 16, 32-bitb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0Subsystem IDb[15:0]........Subsystem IDThis register contains the Subsystem ID. In general, this ID is used to distinguish adapters or systems made by different IHVs using the same chip by the same vendor. This register is read only. To write the IHV's Device ID, use 46-47h (Subsystem ID Write Register). IHVs must change this ID to their ID in the BIOS POST routine.In case of the system such as Sound Card which BIOS can not control, this ID can be changed by connecting EEPROM externally. Then, Subsystem ID Write Register is invalid.In case EEPROM is not externally, the default value is the YAMAHA's Device ID, 0010h.34h: Capability Register PointerRead OnlyDefault: 50hAccess Bus Width: 8, 16, 32-bitb7b6b5b4b3b2b1b0Capability Register Pointerb[7:0]..........Capability Register PointerThis register indicates the offset address of the Capabilities register in the PCI Configuration register when 58-59h: ACPI Mode register, ACPI bit is “0”. DS-1S provides PCI Bus Power Management registers as the capabilities. The Power Management registers are mapped to 50h - 57h in the PCI Configuration register, and this register indicates “50h”.When ACPI bit is “1”, this register indicates “00h”.3Ch: Interrupt LineRead / WriteDefault: 00hAccess Bus Width: 8, 16, 32-bitb7b6b5b4b3b2b1b0Interrupt Lineb[7:0]..........Interrupt LineThis register indicates the interrupt channel that INTA# is assigned to.3Dh: Interrupt PinRead OnlyDefault: 01hAccess Bus Width: 8, 16, 32-bitb7b6b5b4b3b2b1b0Interrupt Pinb[7:0]..........Interrupt PinDS-1S supports INTA# only. This register is hardwired to 01h.3Eh: Minimum GrantRead OnlyDefault: 05hAccess Bus Width: 8, 16, 32-bitb7b6b5b4b3b2b1b0Minimum Grantb[7:0]..........Minimum GrantThis register indicates the length of the burst period required by DS-1S.This register is hardwired to 05h.3Fh: Maximum LatencyRead OnlyDefault: 19hAccess Bus Width: 8, 16, 32-bitb7b6b5b4b3b2b1b0Maximum Latencyb[7:0]..........Maximum LatencyThis register indicates how often DS-1S generates the Bus Master Request.This register is hardwired to 19h.40-41h: Legacy Audio ControlRead / WriteDefault: 907FhAccess Bus Width: 8, 16, 32-bitb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0 LAD SIEN MPUIRQ SBIRQ SDMA I/O MIEN MEN GPEN FMEN SBENb0................SBEN: Sound Blaster EnableThis bit enables the mapping of the Sound Blaster Pro block in the I/O space specified by the SBIO bits, when LAD is set to “0”. The FM Synthesizer registers can be accessed via SB I/O space, while the SB block is enabled, even if FMEN is set to “0”.“0”: Disable the mapping of the SB block to the I/O space“1”: Enable the mapping of the SB block to the I/O space(default)b1................FMEN: FM Synthesizer EnableThis bit enables the mapping of the FM Synthesizer block in the I/O space specified by the FMIO bits, when LAD is set to “0”. FM Synthesizer registers can be accessed via SB I/O space, while the SB block is enabled, even if FMEN is set to “0”.“0”: Disable the mapping of the FM Synthesizer block to the FMIO space“1”: Enable the mapping of the FM Synthesizer block to the FMIO space(default)After setting FMEN to “1”, about 100 msec is necessary before accessing these I/O space.b2................GPEN: Gameport EnableThis bit enables the mapping of the Joystick block in the I/O space specified by the JSIO bits, when LAD is set to “0”.“0”: Disable the mapping of the Joystick block“1”: Enable the mapping of the Joystick block(default)b3................MEN: MPU401 EnableThis bit enables the mapping of the MPU401 block in the I/O space specified by the MPUIO bits, when LAD is set to “0”.“0”: Disable the mapping of the MPU401 block“1”: Enable the mapping of the MPU401 block(default)b4................MIEN: MPU401 IRQ EnableThis bit enables the interrupt service of MPU401, when LAD is set to “0” and MEN is set to “1”.MPU401 generates an interrupt signal when it receives any kind of MIDI data from the RXD pin.“0”: The MPU401 block can not use the interrupt service.“1”: The MPU401 block can use interrupt signals determined by the MPUIRQ bits.(default)b5................I/O: I/O Address Aliasing ControlThis bit selects the number of bits to decode for the I/O address of each block.“0”: 16-bit address decode“1”: 10-bit address decode(default)b[7:6]..........SDMA: Sound Blaster DMA-8 Channel SelectThese bits select the DMA channel for the Sound Blaster Pro block.“0”:DMA ch0“1”:DMA ch1(default)“2”:reserved“3”: DMA ch3b[10:8]........SBIRQ: Sound Blaster IRQ Channel SelectThese bits select the interrupt channel for the Sound Blaster Pro block.“0”:IRQ5(default)“1”:IRQ7“2”:IRQ9“3”:IRQ10“4”:IRQ11“5” - “7”:reserved.b[13:11]......MPUIRQ: MPU401 IRQ Channel SelectWhen MIEN is set to “1”, these bits select the interrupt channel for the MPU401 block.“0”:IRQ5“1”:IRQ7“2”:IRQ9(default)“3”:IRQ10“4”:IRQ11“5” - “7”:reservedSame interrupt channels can be assigned to SBIRQ and MPUIRQ.b14..............SIEN: Serialized IRQ enableDS-1S supports 3 types of interrupt protocols: PCI interrupt (INTA#), Legacy interrupt (IRQs) and Serialized IRQ. The interrupt protocol is selected with IMOD and SIEN as follows.The interrupt channels for IRQs and Serialized IRQ are determined by SBIRQ and MPUIRQ,. Only one protocol can be used at once.SIEN IMOD Interrupt protocol00Legacy interrupt (IRQs) (default)01PCI interrupt (INTA#)1 *Serialized IRQD: Legacy Audio DisableThis bit disables the Legacy Audio block.“0”: Enables the Legacy Audio block“1”: Disables the Legacy Audio block(default)When this bit is set to “1”, DS-1S does not respond to the I/O Target transaction for legacy I/O address on the PCI bus.42-43h: Extended Legacy Audio ControlRead / WriteDefault: 0000hAccess Bus Width: 8, 16, 32-bitb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0 IMOD SBVER SMOD--MAIM--------b8................MAIM: MPU401 Acknowledge Interrupt MaskThis bit determine whether interrupt is asserted when the acknowledge, which is occurred by changing MPU401 mode form default to UART, is returned.“0”: Interrupt is asserted when the acknowledge is returned.(default)“1”: Interrupt is masked when the acknowledge is returned.b[12:11]......SMOD: SB DMA modeThese bits determine the protocol to achieve the DMAC(8237) function on the PCI bus.“0”:PC/PCI(default)“1”:reserved“2”:Distributed DMA“3”reservedb[14:13]......SBVER: SB Version SelectThese bits set the version of the SB Pro DSP. The value set in these bits is returned by sending the E1h DSP command.“0”:ver 3.01(default)“1”:ver 2.01“2”:ver 1.05“3”:reservedb15..............IMOD: Legacy IRQ modeThe legacy interrupt protocol is selected with IMOD and SIEN. Refer to the explanation of SIEN bit.44-45h: Subsystem Vendor ID Write RegisterRead / WriteDefault: 1073hAccess Bus Width: 16-bitb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0Subsystem Vendor ID Writeb[15:0]........Subsystem Vendor ID Write RegisterThis register sets the Subsystem Vendor ID that is read from 2C-2Dh (Subsystem Vendor ID register).The default value is the YAMAHA Vendor ID, 1073h.IHVs must change this ID to their Vendor ID in the BIOS POST routine.In case EEPROM connects externally, this register is invalid, and do not reflect to Subsystem Vendor ID.46-47h: Subsystem ID Write RegisterRead / WriteDefault: 0010hAccess Bus Width: 16-bitb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0Subsystem ID Writeb[15:0]........Subsystem ID Write RegisterThis register sets the Subsystem ID that is read from 2E-2Fh (Subsystem ID register).The default value is the DS-1S Device ID, 0010h. IHVs must change this ID to their ID in the BIOS POST routine.In case EEPROM connects externally, this register is invalid, and do not reflect to Subsystem ID.48-49h: DS-1S ControlRead / WriteDefault: 0001hAccess Bus Width: 8, 16, 32-bitb15b14b13b12b11b10b9b8b7b6b5b4b3b2B1b0 ------------ACLS WRST-CRSTb0................CRST: AC’97 Software Reset Signal ControlThis bit controls the CRST# signal.“0”: Inactive (CRST#=High)“1”: Active (CRST#=Low)(default)b2................WRST: AC’97 Warm ResetThis bit places the AC’97 in warm reset condition when the BIT_CLK signal on the AC’97 remains in inactive state. If this bit is set to “1”, it will automatically return to “0” after 1.3µs time duration. This bit is valid only while the ACLS bit is set to “0”. Except in this case, even if this bit is attempted to be set to “1”, no warm reset will be generated (write operation of “1” remains disabled).“0”: Normal (default)“1”: AC’97 Warm Resetb3................ACLS: AC-Link Status(Read Only)This bit indicates whether or not the AC-link is active. This bit is “1” when the AC-link remains in active state (the BIT_CLK signal is active). This bit is “0” during the following conditions: - When the CRST# pin is active (CRST#=Low)- When either the PR4 bit or PR5 bit of 4A-4Bh: DS-1S Power Control 1 register is set to “1”“0”: AC’97 Inactive (default)“1”: AC’97 Active。

国家和地区缩写

国家和地区缩写国际标准化组织的ISO 3166-1国际标准是ISO 3166的第一部分，有ISO标准国家代码。

1974年首次出版。

ISO 3166-1为国家和地区建立国际认可的代码，代码分为3种，即二位字母代码、三位字母代码、三位数字代码。

分配的代码必须在联合国《国家名称用语公报》（Terminology Bulletin - Country Names）或联合国统计局统计用国家地区代码[1]之中，列入条件为下列三者任其一：联合国会员国、联合国任何特别机构会员、参加《国际法院规约》目前有249个国家和地区被列入“ISO 3166-1”代码表中。

除了这些正式代码外，还有保留代码与私用代码。

译名参考[编辑]中华人民共和国国家标准GB/T 2659-2000《世界各国和地区名称代码》与ISO 3166-1:1997等效采用。

[2]上表中国大陆习用的国家地区名称一般依据此标准，并参考中华人民共和国外交部的用词。

[3] [4] 《中华民国国家标准》CNS 12842《国家名称代码表示法》对应ISO 3166-1:1993，最新修订公布日期版本是民国95年（2006年）4月19日。

[5] [6]，上表台湾习用的国家地区名称一般依据此标准，也参考中华民国外交部的用词。

[7]香港习用的国家地区名称一般依据香港邮政邮政指南附录：海外邮政—运送目的地的服务资料的名称。

ISO 3166-1保留代码[编辑]保留代码不是正式代码，但因特殊原因而保留给有些国家和地区。

保留的原因有过渡保留、限期不定保留、例外保留。

保留代码有二位字母代码和三位字母代码，但没有数字代码。

过渡保留代码[编辑]ISO 3166-1正式代码停用时，就成为过渡保留代码，至少保留5年。

ISO 3166-3收录过时的ISO 3166-1二位字母代码。

以下是过渡保留二位字母代码：BU - 缅甸（英文和法文名称已改变，所以代码改成MM，但中文名称不变。

）NT - 中立区，1983年在沙特阿拉伯和伊拉克之间分割。

英飞特专利

英飞特专利：1、适用于多路并联ＬＥＤ的直流母线电压跟随型控制电路申请号/专利号：201010117067本发明公开了一种适用于多路并联ＬＥＤ的直流母线电压跟随型控制电路，包括一个直流输出电压源，直流输出电压控制电路和负载；所述的直流输出电压源输出端接多路由恒流控制电路和ＬＥＤ灯串联而成的负载，其特征在于所述的直流输出电压控制电路检测出多路负载中ＬＥＤ灯串的电压最高的一路，并将检测出的电压信号转换为恒定的电流信号，该电流信号与ＬＥＤ压降的电压信号成特定的比例特性，然后通过电阻分压后产生输出直流电压的基准信号Ｖｏｒ，传递到电压环的正向输入端作为基准信号，与电压环的另一个输入端即输出电压采样信号Ｖｏｓ比较，并输出控制信号给直流输出电压源，使其调整输出电压Ｖｏ。

本发明结构简单，适用于各种恒流控制电路。

申请日：2010年01月27日公开日：2010年06月23日授权公告日：申请人/专利权人：英飞特电子（杭州）有限公司申请人地址：浙江省杭州市滨江区东信大道66号东方通信城B座309发明设计人：吴新科;葛良安;姚晓莉;任丽君专利代理机构：浙江杭州金通专利事务所有限公司代理人：沈孝敬专利类型：发明专利分类号：H05B37/022、适用于倍压整流的同步整流驱动电路申请号/专利号：200920125072本实用新型公开了一种适用于倍压整流的同步整流驱动电路，包括高频变压器Ｔ１、电流互感器ＣＴ１、输出电容Ｃ１、输出电容Ｃ２、同步整流管ＳＲ１、同步整流管ＳＲ２和两个分别用于驱动同步整流管ＳＲ１和同步整流管ＳＲ２的驱动单元，其特征在于所述的每个驱动单元包括一个整形与复位电路和一个驱动自供电电路。

与现有技术相比，本实用新型的有益效果是：１．只需要一个电流互感器，实现两路ＳＲ的驱动，简化了电路，降低了成本。

２．可以实现驱动电路的自供电和ＳＲ的浮驱动，驱动简单，无须能量回馈电路。

３．适用于较高电压输出并采用低压同步整流器件，降低导通损耗，提高效率。

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