ICX069AK中文资料

Description

The ICX069AK is an interline CCD solid-state image sensor suitable for PAL color video cameras. High resolution is achieved through the use of Ye, Cy, Mg,and G complementary color mosaic filters. At the same time, high sensitivity and low dark current are achieved through the adoption of HAD (Hole-Accumulation Diode) sensors.

This chip features a field period readout system and an electronic shutter with variable charge-storage time.The package is a 10mm-square 14-pin DIP (Plastic).

Features

•High resolution, high sensitivity and low dark current •Horizontal register: 3.6 to 5.0V drive •No voltage adjustment

(Reset gate and substrate bias are not adjusted.)•Low smear

•Excellent antiblooming characteristics •Continuous variable-speed shutter

•Ye, Cy, Mg, and G complementary color mosaic filters on chip Device Structure •Image size:

Diagonal 4.5mm (Type 1/4)

•Number of effective pixels:752 (H) ×582 (V) approx. 440K pixels •Total number of pixels:

795 (H) ×596 (V) approx. 470K pixels

•Interline CCD image sensor •Chip size: 4.47mm (H) ×3.80mm (V)•Unit cell size: 4.85µm (H) ×4.65µm (V)

•Optical black:

Horizontal (H) direction:Front 3 pixels, rear 40 pixels Vertical (V) direction:Front 12 pixels, rear 2 pixels •Number of dummy bits:Horizontal 22

Vertical 1 (even fields only)•Substrate material:

Silicon

ICX069AK

Diagonal 4.5mm (Type 1/4) CCD Image Sensor for PAL Color Video Cameras

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

14 pin DIP (Plastic)

3

Optical black position

(Top View)

Substrate clock φSUB – GND Supply voltage

Clock input voltage

Voltage difference between vertical clock input pins Voltage difference between horizontal clock input pins H φ1, H φ2 – V φ4H φ1, H φ2 – GND H φ1, H φ2 – φSUB V L – φSUB

V φ1, V φ3, V DD , V OUT – V L RG – GND

V φ2, V φ4, H φ1, H φ2, GND – V L Storage temperature Operating temperature

Block Diagram and Pin Configuration (Top View)

Note) : Photo sensor

V O U T

G N D

V φ1

V φ2

V φ3

V φ4V D D

G N φS U B

V L

R G

H φ1

H φ2

N C

Pin No.1234567

V φ4V φ3V φ2V φ1NC GND V OUT

Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock

GND Signal output

891011121314

V DD GND φSUB V L RG H φ1H φ2

Supply voltage

GND

Substrate clock

Protective transistor bias Reset gate clock

Horizontal register transfer clock Horizontal register transfer clock

Symbol Description

Pin No.Description

Pin Description Absolute Maximum Ratings

–0.3 to +40–0.3 to +18–30 to +9–15 to +16

to +10to +15to +16–16 to +16–10 to +15–55 to +10–65 to +0.3–0.3 to +27.5–0.3 to +20.5–0.3 to +17.5–30 to +80–10 to +60

V V V V V V V V V V V V V V °C °C

∗1V DD , V OUT – GND V DD , V OUT – φSUB V φ1, V φ2, V φ3, V φ4 – GND V φ1, V φ2, V φ3, V φ4 – φSUB

Item

Ratings Unit Remarks

∗1+24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.

Symbol