3706 datasheet
LTC3706EGN#PBF;LTC3706EGN#TRPBF;LTC3706IGN#PBF;LTC3706IGN#TRPBF;中文规格书,Datasheet资料
13706fdTYPICAL APPLICATIONDESCRIPTIONForward Controller with PolyPhase CapabilityThe L TC ®3706 is a PolyPhase capable secondary-side controller for synchronous forward converters. When used in conjunction with the L TC3705 gate driver and primary-side controller , the part creates a complete isolated power supply that combines the power of PolyPhase operation with the speed of secondary-side control.The L TC3706 has been designed to simplify the design of highly efficient, secondary-side forward converters. Working in concert with the L TC3705, the L TC3706 forms a robust, self-starting converter that eliminates the need for the separate bias regulator that is commonly used in secondary-side control applications. In addition, a pro-prietary scheme is used to multiplex gate drive signals and DC bias power across the isolation barrier through a single, tiny pulse transformer .The L TC3706 provides remote sensing, accurate power good and overvoltage monitoring circuits to support preci-sion, high current applications. A linear regulator controller with thermal protection is also provided to simplify the generation of secondary-side bias voltage.The L TC3706 is available in a 24-lead SSOP package.36V-72V to 3.3V/20A Isolated Forward ConverterFEATURESAPPLICATIONSnIsolated 48V Telecommunication Systems n Internet Servers and Routersn Distributed Power Step-Down Converters nAutomotive and Heavy EquipmentnSecondary-Side Control for Fast T ransient Response n Self-Starting Architecture Eliminates Need for Separate Bias Regulatorn Proprietary Gate Drive Encoding Scheme Reduces System Complexityn PolyPhase ® Operation Reduces C INRequirements n Current Mode Control Ensures Current Sharing n PLL Fixed Frequency: 100kHz to 500kHz n ±1% Output Voltage Accuracy n T rue Remote Sense Differential Amplifier n Power Good Output Voltage Monitor n High Voltage Linear Regulator Controller n Wide Supply Range: 5V to 30Vn Available in a Narrow 24-Lead SSOP PackageV IN –V IN +3OUT –OUT +L , L T , L TC, L TM, PolyPhase, Burst Mode, Linear Technology and the Linear logo are registered trademarks and No R SENSE and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 6144194, other patents pending./23706fdPIN CONFIGURATIONABSOLUTE MAXIMUM RATINGSV CC ........................................................... –0.3V to 10V V IN ........................................................... –0.3V to 33V SW ............................................................... –5V to 50V NDRV ......................................................... –0.3V to 13V ITH, RUN/SS, V SOUT , V S +, V S –, REGSD ....... –0.3V to 7VAll Other Pins ............................................ –0.3V to 10VOperating Temperature Range (Note 2) LTC3706E GN .......................................–40°C to 85°C LTC3706IGN ........................................–40°C to 85°C Junction Temperature (Note 3) ............................ 125°C Storage Temperature Range ..................–65°C to 150°C Lead Temperature (Soldering, 10 sec) ...................300°C(Note 1)ORDER INFORMATIONLEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE L TC3706EGN#PBF L TC3706EGN#TRPBF L TC3706EGN 24-Lead Plastic SSOP –40°C to 85°C L TC3706IGN#PBF L TC3706IGN#TRPBF L TC3706IGN 24-Lead Plastic SSOP –40°C to 85°C LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE L TC3706EGN L TC3706EGN#TR L TC3706EGN 24-Lead Plastic SSOP –40°C to 85°C L TC3706IGNL TC3706IGN#TRL TC3706IGN24-Lead Plastic SSOP–40°C to 85°CConsult L TC Marketing for parts specified with wider operating temperature ranges.For more information on lead free part marking, go to: http://www.linear .com/leadfree/For more information on tape and reel specifications, go to: http://www.linear .com/tapeandreel//ELECTRICAL CHARACTERISTICSThel indicates specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. V CC = 7V, V IN = 15V, GND = PGND = 0V, unless otherwise noted.SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Main Control LoopV FB Regulated Feedback Voltage(Note 4) ITH = 1.2V l0.5940.6000.606V I FB Feedback Input Current(Note 4)2100nA ∆V FB(LINREG)Feedback Voltage Line Regulation V IN = 6V to 30V, ITH = 1.2V0.001%/V ∆V FB(LOADREG)Feedback Voltage Load Regulation Measured in Servo Loop,ITH = 0.5V to 2Vl–0.01–0.1%V ISMAX Maximum Current Sense Threshold R SENSE Mode, 0V < V IS– < 5VV IS– = V CC, 0V < V IS+ < 2V (CT Mode)681.15781.28881.4mVVV ISOC Over-Current Shutdown Threshold R SENSE Mode, 0V < V IS– < 5VV IS– = V CC, 0V < V IS+ < 2V (CT Mode)871.451001.651131.85mVVg m T ransconductance Amplifier g m 2.40 2.75 3.10mS I RUN/SS(C)Soft-Start Charge Current V RUN/SS = 2V–4–5–6µA I RUN/SS(D)Soft-Start Discharge Current3µA V RUN/SS RUN/SS Pin On Threshold V RUN/SS Rising l0.40.450.5V t ON,MIN Minimum On-Time200ns FG, SG R UP FG, SG Driver Pull-Up On Resistance FG, SG Low 1.5 2.7ΩFG, SG R DOWN FG, SG Driver Pull-Down On Resistance FG, SG High 1.5 2.7ΩPT+, PT– R UP PT+, PT– Driver Pull-Up Resistance PT+, PT– Low 1.5 2.7ΩPT+, PT– R DOWN PT+, PT– Driver Pull-Down Resistance PT+, PT– High 1.5 2.7Ω∆V FB(OV)Output Overvoltage Threshold V FB Rising151719% V CC SupplyV CCOP Operating Voltage Range510V V CCREG Regulated Output Voltage 6.67.07.4VI CC Supply CurrentOperatingShutdown f OSC = 200kHz (Note 5)V RUN/SS = GND4.2240mAµAV UVLO UV Lockout V CC Rising l 4.52 4.60 4.70V V HYS UV Hysteresis0.4V V IN SupplyV INOP Operating Voltage Range530VI IN Supply CurrentNormal ModeShutdown f OSC = 200kHzV RUN/SS = GND900460µAµAV INUVLO UV Lockout V IN Rising l 3.90 4.30 4.51V V INHYS0.2V V REGSD REGSD Shutdown Threshold V REGSD Rising4Vg m,REGSD REGSD T ransconductance5µS /33706fd43706fdELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: The L TC3706E is guaranteed to meet the performance specifica-tions over the 0°C to 85°C operating temperature range. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. The L TC3706I is guaranteed and tested over the full –40°C to 85°C operating temperature range.Note 3: Junction temperature T J (in °C) is calculated from the ambient tem-perature T A and the average power dissipation P D (in Watts) by the formula: T J = T A + θJA • P DRefer to the Applications Information section for details.Note 4: The L TC3706 is tested in a feedback loop that servos V FB to a voltage near the internal 0.6V reference voltage to obtain the specified ITH voltage (V ITH = 1.2V).Note 5: Operating supply current is measured in test mode. Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. See the Typical Performance Characteristics section.SYMBOL PARAMETERCONDITIONSMINTYP MAXUNITSOscillator and Phase-Locked LoopI FS FS/SYNC Pin Sourcing Current 20µA f LOW Oscillator Low Frequency Set Point V FS/SYNC = GND 165200235kHz f HIGH Oscillator High Frequency Set Point V FS/SYNC = VCC247300353kHz ∆f (R FS )Oscillator Resistor Set Accuracy 75kΩ < R FS/SYNC < 175kΩ–2220%f PLL(MAX)Maximum PLL Sync Frequency 500kHz f PLL(MIN)Minimum PLL Sync Frequency75kHzPGOOD Output V FBH /0.6Power Good Upper Threshold V FB Rising 115117119%V FBL1/0.6Power Good Lower Threshold V FB Rising 91.59394.5%V FBL2/0.6Power Good Lower Threshold V FB Falling89.59192.5%Differential Amplifier (V SENSE AMP)ADA GainV S – = GND, 1V ≤ V S + ≤ 5V0.9901 1.010V/V CMRR DA Common Mode Rejection Ratio 75dB R IN Input Resistance 80kΩf BW–3dB Bandwidth3MHzThe l indicates specifications which apply over the full operatingtemperature range, otherwise specifications are at T A = 25°C. V CC = 7V, V IN = 15V, GND = PGND = 0V, unless otherwise noted./53706fdTYPICAL PERFORMANCE CHARACTERISTICSMaximum Current Sense RUN/SS ON Threshold Oscillator Frequency T A = 25°C, unless otherwise noted.Maximum Current Sense IS Pins Source Current V CC Supply Current V CC Regulator Output Voltage Maximum Current Sense /63706fdGate Driver On-Resistance TYPICAL PERFORMANCE CHARACTERISTICST A = 25°C, unless otherwise noted.Undervoltage Lockout REGSD Shutdown Threshold /PIN FUNCTIONSSG (Pin 1): Gate Drive for the “Synchronous” MOSFET. FG (Pin 2): Gate Drive for the “Forward” MOSFET. PGOOD (Pin 3): Open-Drain Power Good Output. The FBpin is monitored to ensure that the output is in regulation. When the output is not in regulation, the PGOOD pin is pulled low.MODE (Pin 4): Tie to either GND or V CC to set the maxi-mum duty cycle at either 50% or 75% respectively. Tie to ground through either a 200k or 100k resistor (50% or 75% maximum duty cycle) to disable pulse encoding. In this mode, normal PWM signals will be generated at the PT+ pin, while a clock signal is generated at the PT– pin. PHASE (Pin 5): Control Input to the Phase Selector. This pin determines the phasing of the controller CLK relative to the synchronizing signal at the FS/SYNC pin.FB (Pin 6): The Inverting Input of the Main Loop Error Amplifier.ITH (Pin 7): The Output of the Main Loop Error Amplifier. Place compensation components between the ITH pin and GND.RUN/SS (Pin 8): Combination Run Control and Soft-Start Inputs. A capacitor to ground sets the ramp time of the output voltage. Holding this pin below 0.4V causes the IC to shut down all internal circuitry.V SOUT, V S+, V S– (Pins 9, 10, 11): V SOUT is the output of a precision, unity-gain differential amplifier. Tie V S+ and V S– to the output of the main DC/DC converter to achieve true remote differential sensing. This allows DCR error effects to be minimized.GND (Pin 12): Signal Ground.FS/SYNC (Pin 13): Combination Frequency Set and SYNC pin. Tie to GND or V CC to run at 200kHz and 300kHz respectively. Place a single resistor to ground at this pin to set the frequency between 100kHz and 500kHz. To synchronize, drive this pin with a clock signal to achieve PLL synchronization from 75kHz to 500kHz. Sources 20µA of current.SLP (Pin 14): Slope Compensation Input. Place a single resistor to ground to set the desired amount of slope compensation.I S– (Pin 15): Negative Input to the Current Sense Circuit. When using current sense transformers, this pin may be tied to V CC for single-ended sensing with a 1.28V maximum current trip level.I S+ (Pin 16): Positive Input to the Current Sense Circuit. Connect to the positive end of a current sense resistor or to the output of a current sense transformer. REGSD (Pin 17):T his p in i s u sed t o p revent o verheating o f t he external linear regulator pass device that generates the V CC supply voltage from the V IN voltage. A current proportional to the voltage across the external pass device flows out of this pin. The IC shuts down the linear regulator when the voltage on this pin exceeds 4V. Place a resistor (or a resistor and capacitor in parallel) between this pin and GND to limit the temperature rise of the external pass device. NDRV (Pin 18): Drive Output for the External Pass Device of the V CC Linear Regulator. Connect to the base (NPN) or gate (NMOS) of an external N-type device.V IN (Pin 19): Connect to a higher voltage bias supply, typically the output of a peak detected bias winding. When not used, tie together with the V CC and NDRV pins.SW (Pin 20): Connect to the drain of the “synchronous” MOSFET. This input is used for adaptive shoot-through prevention and leading edge blanking.PT–, PT+ (Pins 21, 22): Pulse T ransformer Driver Outputs. For most applications, these connect to a pulse trans-former (with a series DC blocking capacitor). The PWM information is multiplexed together with DC power and sent through a single pulse transformer to the primary side. This information may be decoded by the L TC3705 gate driver and primary-side controller.PGND (Pin 23): Gate Driver Ground Pin.V CC (Pin 24): Main V CC Input for all Driver and Control Circuitry./73706fdBLOCK DIAGRAM83706fd/OPERATIONMain Control LoopThe L TC3706 is designed to work in a constant frequency, current mode 2-transistor forward converter. During normal operation, the primary-side MOSFETs (both top and bottom) are “clocked” on together with the forward MOSFET on the secondary side. This applies the reflected input voltage across the inductor on the secondary side. When the current in the inductor has ramped up to the peak value as commanded by the voltage on the ITH pin, the current sense comparator is tripped, turning off the primary-side and forward MOSFE Ts. To avoid turning on the synchronous MOSFET prematurely and causing shoot-through, the voltage on the SW pin is monitored. This voltage will usually fall below 0V soon after the primary-side MOSFETs have turned completely off. When this condition is detected, the synchronous MOSFET is quickly turned on, causing the inductor current to ramp back downwards. The error amplifier senses the output voltage, and adjusts the ITH voltage to obtain the peak current needed to maintain the desired main-loop output voltage. The L TC3706 always operates in a continuous current, synchronous switching mode. This ensures a rapid transient response as well as a stable bias supply voltage at light loads. A maximum duty cycle (either 50% or 75%) is internally set via clock dividers to prevent saturation of the main transformer. In the event of an overvoltage on the output, the synchronous MOSFET is quickly turned on to help protect critical loads from damage.Gate Drive EncodingSince the L TC3706 controller resides on the secondary side of an isolation barrier, communication to the primary-side power MOSFETs is generally done through a transformer. Moreover, it is often necessary to generate a low voltage bias supply for the primary-side gate drive circuitry. In order to reduce the number of isolated windings present in the system, the L TC3706 uses a proprietary scheme to encode the PWM gate drive information and multiplex it together with bias power for the primary-side drive and control, using a single pulse transformer. Note that, unlike optoisolators and other modulation techniques, this multiplexing scheme does not introduce a significant time delay into the system.For most forward converter applications, the PT+ and PT– outputs will contain a pulse-encoded PWM signal. These outputs are driven in a complementary fashion with an essentially constant 50% duty cycle. This results in a stable volt-second balance as well as an efficient transfer of bias power across the pulse transformer. As shown in Figure 1, the beginning of the positive half-cycle coincides with the turn-on of the primary-side MOSFETs. Likewise, the beginning of the negative half-cycle coincides with the maximum duty cycle (forced turn-off of primary switches). At the appropriate time during the positive half-cycle, the end of the on-time (PWM going LOW) is signaled by briefly applying a zero volt differential across the pulse transformer. Figure 1 illustrates the operation of this multiplexing scheme.The L TC3705 primary-side controller and gate driver will decode this PWM information as well as extract the power needed for primary-side gate drive.Figure 1. Gate Drive Encoding Scheme (V MODE = GND)DUTY CYCLE = 15%V PT1+ – V PT1DUTY CYCLE = 0%/93706fd103706fdOPERATIONvalues using the SLP pin as shown in Table 1. Note that the amount of slope compensation doubles when the duty cycle exceeds 50%.Table 1SLP PIN SLOPE (D < 0.5)SLOPE (D > 0.5)GND 0.05 • I SMAX • f OSC0.1 • I SMAX • f OSCV CCNone None 400kΩ to GND 0.1 • I SMAX • f OSC 0.2 • I SMAX • f OSC 200kΩ to GND 0.15 • I SMAX • f OSC 0.3 • I SMAX • f OSC 100kΩ to GND 0.25 • I SMAX • f OSC 0.5 • I SMAX • f OSC 50kΩ to GND0.5 • I SMAX • f OSC1.0 • I SMAX • f OSCIn Table 1 above, I SMAX is the maximum current limit, and f OSC is the switching frequency.Current Sensing and Current LimitFor current sensing, the L TC3706 supports either a current sense resistor or a current sense transformer . The current sense resistor may either be placed in series with the inductor (either high side or ground lead sensing), or in the source of the “forward” switch. If a current sense transformer is used, the I S – input should be tied to V CC and the I S + pin to the output of the current sense transformer . This causes the gain of the internal current sense amplifier to be reduced by a factor of 16×, so that the maximum current sense voltage (current limit) is increased from 78mV to 1.28V . An internal, adaptive leading edge blanking circuit ensures clean operation for “switch” current sensing applications.Current limit is achieved in the L TC3706 by limiting the maximum voltage excursion of the error signal (ITH volt-age). Note that if slope compensation is used, the precise value at which current limit occurs will be a function of duty cycle (See the Typical Performance Characteristics section). If a short circuit is applied, an independent overcurrent comparator may be tripped. In this case, the L TC3706 will enter a “hiccup” mode using the soft-start circuitry.Self-Starting ArchitectureWhen the LTC3706 is used in conjunction with the LTC3705 primary-side controller and gate driver , a complete self-starting isolated supply is formed. When input voltage is first applied in such an application, the L TC3705 will begin switching in an “open-loop” fashion, causing the main output to slowly ramp upwards. This is the primary-side soft-start mode. On the secondary side, the L TC3706 derives its operating bias voltage from a peak-charged capacitor . This peak-charged voltage will rise more rapidly than the main output of the converter , so that the L TC3706 will become operational well before the output voltage has reached its final value.When the L TC3706 has adequate operating voltage, it will begin the procedure of assuming control from the primary side. To do this, it first measures the voltage on the power supply’s main output and then automatically advances its own soft-start voltage to correspond to the main output voltage. This ensures that the output voltage increases monotonically as the soft-start control is transferred from primary to secondary. The L TC3706 then begins sending PWM signals to the L TC3705 on the primary side through a pulse transformer . When the L TC3705 has detected a stable signal from the secondary controller , it transfers control of the primary switches over to the L TC3706, beginning the secondary-side soft-start mode. The L TC3706 continues in this mode until the output voltage has ramped up to its final value. If for any reason, the L TC3706 either stops sending (or initially fails to send) PWM information to the L TC3705, the L TC3705 will detect a FAUL T and initiate a soft-start retry. (See the L TC3705 data sheet.) Slope CompensationSlope compensation is added at the input of the PWM comparator to improve stability and noise margin of the peak current control loop. The amount of slope compen-sation can be selected from one of five preprogrammed/分销商库存信息:LINEAR-TECHNOLOGYLTC3706EGN#PBF LTC3706EGN#TRPBF LTC3706IGN#PBF LTC3706IGN#TRPBF。
9906;中文规格书,Datasheet资料
Nominal data
Type Phase Nominal voltage Frequency Speed Power input Min. ambient temperature Max. ambient temperature Air flow Sound power level Sound pressure level VAC Hz min-1 W °C °C m3/h B dB(A) 9906 1~ 115 60 2850 12.0 -40 70 135 5.4 42
/
9906
AC axial compact fan
Technical features
General description AC voltage fan with internal rotor shaded-pole motor. Protected from overload by impedance protection. Fan housing made of metal, impeller made of mineral-reinforced PA plastic. Air exhaust over bars. Direction of rotation counter-clockwise seen on rotor. Electrical connection to 2 flat plugs 2.8 x 0.5 mm. Fan housing with grounding lug for M4 tapping screw. Mass 320 g. Please note our new ACmaxx series. With identical fastening dimensions and voltages, this series achieves higher energy efficiency. 0.325 kg 119 x 119 x 25 mm Mineral-reinforced PA plastic Metal Air exhaust over bars Left, looking at rotor Ball bearings 52500 h 25000 h 2 flat plugs 2.8 x 0.5 mm Protected from overload using impedance protection VDE, CSA, UL, CE
和谐XPS安全自动化产品数据表说明书
Product data sheetSpecificationsTime delayed output, Harmony XPS,for Estop, guard, OSSD, 24 V AC/DC, springXPSBAT12A1ACMainRange of ProductHarmony Safety Automation Product or Component Type Safety module Safety module name XPSBATSafety module application For emergency stop and protective guard applications For OSSD monitoringFunction of moduleEmergency stop button with 2 NC contacts Guard monitoring with 1 or 2 limit switches Light curtain monitoring RFID switchMonitoring of electro-sensitive protection equipment (ESPE)Safety levelCan reach PL e/category 4 for normally open relay contact ISO 13849-1Can reach SILCL 3 for normally open relay contact IEC 62061Can reach SIL 3 for normally open relay contact IEC 61508Can reach PL c/category 1 for normally closed relay contact ISO 13849-1Can reach SILCL 1 for normally closed relay contact IEC 62061Can reach SIL 1 for normally closed relay contact IEC 61508Safety reliability dataMTTFd > 30 years ISO 13849-1Dcavg >= 99 % ISO 13849-1PFHd = 0.98E-09 for SS0 ISO 13849-1PFHd = 0.96E-09 for SS1 ISO 13849-1HFT = 1 IEC 62061PFHd = 0.98E-09 for SS0 IEC 62061PFHd = 0.96E-09 for SS1 IEC 62061SFF > 99% IEC 62061HFT = 1 IEC 61508-1PFHd = 0.98E-09 for SS0 IEC 61508-1PFHd = 0.96E-09 for SS1 IEC 61508-1SFF > 99% IEC 61508-1Type = B IEC 61508-1Electrical circuit type NC pair OSSD pairConnections - terminalsRemovable spring terminal block, 0.2...2.5 mm² solid or flexibleRemovable spring terminal block, 0.25...2.5 mm² flexible with ferrule single conductor Removable spring terminal block, 0.2...1.5 mm² solid or flexible twin conductorRemovable spring terminal block, 2 x 0.25...1 mm² flexible with ferrule without cable end, with bezel Removable spring terminal block, 2 x 0.5...1.5 mm² flexible with ferrule with cable end, with bezel [Us] Rated Supply Voltage24 V AC - 15...10 %24 V DC - 20...20 %ComplementarySynchronisation time between inputs 0.5 s 2 sType of startAutomatic/manual/monitored Power consumption in W2 W 24 V DCD i s c l a i m e r : T h i s d o c u m e n t a t i o n i s n o t i n t e n d e d a s a s u b s t i t u t e f o r a n d i s n o t t o b e u s e d f o r d e t e r m i n i n g s u i t a b i l i t y o r r e l i a b i l i t y o f t h e s e p r o d u c t s f o r s p e c i f i c u s e r a p p l i c a t i o n sPower consumption in VA5 VA 24 V AC 50/60 HzInput protection type Internal, electronicSafety outputs 2 NO1 NOSafety inputs2Maximum wire resistance500 OhmTime delay range0...900 sInput compatibility Normally closed circuit ISO 14119Mechanical contact ISO 14119OSSD pair IEC 61496-1-2Normally closed circuit ISO 138503-wire proximity sensors PNP[Ie] rated operational current5 A AC-13 A AC-155 A DC-13 A DC-13Control outputs 3 pulsed outputInput/Output type Semiconductor output Z1, 20 mA[Ith] conventional free air12 Athermal currentAssociated fuse rating6 A gG NO relay output circuit IEC 60947-1 Minimum output current20 mA relay outputMinimum output voltage24 V relay outputMaximum response time on20 msinput open[Ui] rated insulation voltage250 V 2)EN/IEC 60947-1[Uimp] rated impulse withstand4 kV II EN/IEC 60947-1voltageLocal signalling LED green power power ONLED red error errorLED yellow state 1 safety output instantaneousLED yellow state 2 safety output delayedLED yellow start 1 startLED yellow start 2 startLED yellow S12 safety input S12LED yellow S22 safety input S22Mounting Support35 mm symmetrical DIN railDepth 4.72 in (120 mm)Height 3.94 in (100 mm)Width 1.77 in (45 mm)Net Weight0.77 lb(US) (0.350 kg)EnvironmentStandards IEC 60947-5-1IEC 61508-1 functional safety standardIEC 61508-2 functional safety standardIEC 61508-3 functional safety standardIEC 61508-4 functional safety standardIEC 61508-5 functional safety standardIEC 61508-6 functional safety standardIEC 61508-7 functional safety standardISO 13849-1 functional safety standardIEC 62061 functional safety standardProduct certifications TÜVcULusIP degree of protection IP20 terminals)EN/IEC 60529IP40 housing)EN/IEC 60529IP54 mounting area)EN/IEC 60529 Ambient air temperature for-13…131 °F (-25…55 °C)operationAmbient Air Temperature for-13…185 °F (-25…85 °C)StorageRelative Humidity5…95 % non-condensingOrdering and shipping detailsCategory22477-SAFETY MODULES (PREVENTA)Discount Schedule SAF2GTIN3606482034037Nbr. of units in pkg.1Package weight(Lbs)10.65 oz (302 g)Returnability NoPacking UnitsUnit Type of Package 1PCEPackage 1 Height 2.52 in (6.4 cm)Package 1 width 5.24 in (13.3 cm)Package 1 Length 6.02 in (15.3 cm)Unit Type of Package 2S03Number of Units in Package 216Package 2 Weight11.92 lb(US) (5.409 kg)Package 2 Height11.81 in (30 cm)Package 2 width11.81 in (30 cm)Package 2 Length15.75 in (40 cm)Package 3 Height11.81 in (30 cm)Offer SustainabilitySustainable offer status Green Premium productCalifornia proposition 65WARNING: This product can expose you to chemicals including: Lead and lead compounds, which isknown to the State of California to cause cancer and birth defects or other reproductive harm. For moreinformation go to REACh Regulation REACh DeclarationEU RoHS Directive Pro-active compliance (Product out of EU RoHS legal scope)EU RoHS DeclarationMercury free YesRoHS exemption information YesChina RoHS Regulation China RoHS declarationEnvironmental Disclosure Product Environmental ProfileCircularity Profile End of Life InformationWEEE The product must be disposed on European Union markets following specific waste collection andnever end up in rubbish bins.Dimensions Drawings DimensionsFront and Side Views(A) : Product drawing(B) : Spring terminal(C) : Side view(1) : Removable terminal blocks, top(2) : Removable terminal blocks, bottom(3) : LED indicators(4) : Delay factor selector(5) : Delay base selector(6) : Sealable transparent coverMounting to DIN railScrew-mountingConnections and SchemaWiring Diagram(1) : A1-A2 (Power supply)(2) : S11–S21 (Control outputs (DC+) of safety-related inputs), S12-S22 (Input channels (CH+) of safety-related inputs)(3) : Y1 (Control output of Start/Restart input), Y2 (Input channel for automatic/manual start), Y3 (Input channel for monitored start with falling edge)13-14-23-24 : Terminals of the safety-related outputs (instantaneous)37-38 : Terminals of the safety-related outputs (delayed)Z1 : Solid state output, not safety-related。
2N3906中文资料(nte)中文数据手册「EasyDatasheet - 矽搜」
VCE = 1V, I C = 1mA
40 − − 80 − −
2N3905 2N3906
VCE = 1V, I C = 10mA
50 − 150 100 − 300
2N3905 2N3906
VCE = 1V, I C = 50mA
30 − − 60 − −
2N3905 2N3906
VCE = 1V, I C = 100mA
芯片中文手册,看全文,戳
2N3905 & 2N3906 硅PNP晶体管
一般用途
TO92类型封装
绝对最大额定值：
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器件总功耗（T
C = +255C), PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W
减免上述255℃. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12MW / 5C
减免上述255℃. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0MW / 5C
器件总功耗（T
GS-2406T PLUS GS-3405T PLUS Series 热转式 热感式 SUR
GS-2406T PLUS / GS-3405T PLUS / Series热转式/热感式SURPASS PLUS条码印表机使用手册Ver.1.1.3Agency Compliance and ApprovalsEN 55032, Class AEN 55024This is a class A product. In a domestic environment this product may cause radiointerference in which case the user may be required to take adequate measures.FCC part 15B, Class AThis equipment has been tested and found to comply with the limits for a Class Adigital device, pursuant to Part 15 of the FCC Rules. These limits are designed toprovide reasonable protection against harmful interference when the equipment isoperated in a commercial environment. This equipment generates, uses, and canradiate radio frequency energy and, if not installed and used in accordance with themanufacturer’s instruction manual, may cause harmful interference with radiocommunications. Operation of this equipment in a residential area is likely to causeharmful interference, in which case you will be required to correct the interference atyour own expense.FCC 符合声明此设施符合第15 部份的规则。
LT3704 中文数据手册 datasheet
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3706M-E1S中文资料
————————————————————————————————————————————初级控制全隔离电池充电IC AP3706Jul. 2008 Rev. 1.3 BCD 半导体制造有限公司概述AP3706 是高性能的 ，专为 储电池充电和适配器应用设计的AC/DC 电源控制器. 该设备采用脉冲频率调制（PFM ）方法建立非连续导通模式（DCM ）反激式电源.AP3706 提供恒压恒流控制(CV/CC)而不需要光电耦合器和二次线路控制。
在保持稳定的同时，它取消（原来必要的）环路补偿电路。
AP3706 实现了卓越的控制能力和高效能转换, 空载功耗在265V AC 输入时低于200mW 。
AP3706 提供SOIC-8 和 DIP-8 封装规格。
主要特点· 初级端控制矩形恒流和恒压输出 · 取消光耦合器和次级CV/CC 控制线路 · 取消环路补偿电路· DCM 工作在反激式拓扑结构· 任意频率调制降低系统电磁干扰（EMI ） · 波谷导通大功率 NPN 晶体管 · 内置软启动 · 开放电路保护 · 超电压保护 · 短路保护应用· 适配器/为手机、无绳电话、PDA\MP3和其他便携仪器充电 · 待机和备用电源应用图 1. AP3706 封装图管脚编排图 2. AP3706管脚编排（顶视）————————————————————————————————————————————初级控制全隔离电池充电IC AP3706图 3. AP3706实用结构图Jul. 2008 Rev. 1.3 BCD 半导体制造有限公司————————————————————————————————————————————初级控制全隔离电池充电IC AP3706编号信息BCD半导体无铅产品, 指定后缀为"E1", 遵从RoHS规定.商品后缀"G1"为环保封装。
潘森高能电池产品安全数据表说明书
This product is used in a hermetically sealed state. So, it is not an object of the SDS system. This document is provided to customers as reference information for the safe handling of the product. The information and recommendations set forth are made in good faith and are believed to be accurate at the date of preparation. Panasonic Corporation makes no warranty expressed or implied.PRODUCT SAFETY DATA SHEET1 Chemical product and company identificationName of Product : Lithium Iron Disulfide battery FR6 (FR14505), FR03 (FR10G445)Name of Company : Panasonic Energy Co., Ltd.Address : 1-1Matsushita-cho, Moriguchi-city, Osaka, 570-8511, JapanEmergency Contact : +81-80-9932-3190 (JST Working hours)+81-6-6991-1141 (Holiday)2Hazards identificationGHS Classification : No applicableToxicity : Vapor generated from burning batteries, may irritate eyes, skin and throat.Hazard : Electrolyte and lithium metal are inflammable.Risk of explosion by fire if batteries are disposed in fire or heated above 100degrees C.Stacking or jumbling batteries may cause external short circuits, heatgeneration, fire or explosion.3Composition/information of ingredientsComponent Material CAS RN Content •i%•jPositive electrode Iron disulfide 1317-37-9 24 - 35 Carbon black 133-86-4 0 - 4 Graphite 7782-42-5 0 - 4Negative electrode* Lithium or Lithium alloy 7439-93-2 6.7 •iFR6) 6.6 •iFR03•jElectrolyte 1,2-dimethoxyethane 110-71-4 2 - 4 1,3-dioxolane 646-06-0 5 - 9 Lithium iodide - 0.3 - 3(Remarks) * Each size contains less than 1 gram of lithium per cell.4First aid measures (in case of electrolyte leakage from the battery)Eye contact : Flush the eyes with plenty of clean water for at least 15 minutesimmediately, without rubbing. Get immediate medical treatment.If appropriate procedures are not taken, this may cause eye injury.Skin contact : Wash the affected area under tepid running water using a mildsoap. If appropriates procedures are not taken, this may cause soreson the skin. Get medical attention if irritation develops or persists.Inhalation: Remove to fresh air immediately. Get medical treatmentimmediately.5 Firefighting measuresFire extinguishing agent : Alcohol-resistant foam and dry sand are effective.Extinguishing method : Be sure on the windward to extinguish the fire, since vapor maymake eyes, nose and throat irritate, Wear the respiratory protectionequipment in some cases.6Accidental release measures (in case of electrolyte leakage from the battery)Take up with absorbent cloth, treat cloth as inflammable.Move the battery away from the fire.7 Handling and storageHandling : žWhen packing the batteries, do not allow battery terminals tocontact each other, or contact with other metals. Be sure to packbatteries by providing partitions in the packaging box, or in aseparate plastic bag so that the single batteries are not mixedtogether.žUse strong material for packaging boxes so that they will not bedamaged by vibration, impact, dropping and stacking duringtheir transportation.žDo not short-circuit, recharge, deform, throw into fire ordisassemble.žDo not mix different type of batteries.žDo not solder directly onto batteries.žInsert the battery correctly in electrical equipment.Storage : •E Do not let water penetrate into packaging boxes during theirstorage and transportation.•E Do not store the battery in places of the high temperature orunder direct sunlight.žPlease also avoid the places of high humidity. Be sure not toexpose the battery to condensation, rain or frozen condition8.Exposure controls and personal protectionAcceptable concentration : Not specified about Lithium Battery.Facilities : Nothing in particularProtective Equipment (in case of electrolyte leakage from the battery)Respiratory Protection : For most condition no respiratory protection.Hand Protection : Safety gloves.Eye Protection : Safety goggle9.Physical and chemical propertiesAppearance : Cylindrical shapeNominal Voltage : 1.5 V10. Stability and reactivitySince batteries utilize a chemical reaction they are actually considered a chemical product.As such, battery performance will deteriorate over time even if stored for a long period of time without being used. In addition, the various usage conditions such as discharge, ambient temperature, etc. are not maintained within the specified ranges the life expectancy of the battery may be shortened or the device in which the battery is used may be damaged by electrolyte leakage.11.Toxicological informationSwallowing can lead to chemical bums, perforation of soft tissue, and death. Severe bums can occur within 2 hours of ingestion. Seek medical attention immediately.12.Ecological informationIn case of the worn out battery was disposed in land, the battery case may be corroded, and leak electrolyte. However, there is no environmental impact information.Mercury (Hg), Cadmium (Cd) and Lead (Pb) are not used in cell.13.Disposal considerationsWhen the battery is worn out, dispose of it under the ordinance of each local government.14.Transport informationHandlingDuring the transportation of a large amount of batteries by ship, trailer or railway, do not leave them in the places of high temperatures and do not allow them to be exposed to condensation.During the transportation do not allow packages to be dropped or damaged.Proper shipping name : Lithium metal batteriesUN Number, UN Class : UN3090, Class9 (for the Air transport by PI968 Section IA or IB): Exemption (for the Marine transport SP188 and the Air transportby Section II of PI 969 or 970)Even though the cells are classified as lithium metal batteries(UN3090 or UN3091), they are not subject to some requirements ofDangerous Goods Regulations because they meet the following:1. for cells, the lithium content is not more than 1 g ;2. each cell is of the type proven to meet the requirements of each test inthe UN Manual of T ests and Criteria, PartúL, sub-section 38.3.3. each cell is manufactured in ISO9001 certified factory.4. the test summary is available from;https:///ww/downloads/battery-test-summary Please refer to the following reference information about concrete ways of transportation. Actual content of packaging label and shipping documents varies by shipping companies. Make sure to confirm in advance with your shipping company.Information of referenceReference Packing Instruction(PI)/Special provision(SP)NoteAir transport IATA DGR PI 968 SectionúJ A Cells, Cargo Aircraft only; Net quantity perpackage Max. 35kgPI 968 SectionúJ B Cells, Cargo Aircraft only; net quantity perpackage Max. 2.5kgPI 969 SectionúK Cells packed with equipmentPI 970 SectionúK Cells contained in equipment Marine transport IMDG Code SP 18815.Regulatory information•E IATA Dangerous Goods Regulations Edition 64 (IATA DGR)•E IMO International Maritime Dangerous Goods Code 2020 and 2022 Edition (IMDG Code)•E UN Recommendations on the Transportation of Dangerous Goods, Model Regulations•E UN Recommendations on the Transportation of Dangerous Goods, Manual of Tests and Criteria •E EU Battery Directive•i2006/66/EC, 2013/56/EU)•E Regulation (EC) No. 1907/2006 on the Registration, Evaluation, Authorization and Restriction of Chemicals (REACH)•E State of California Regulations - Best management practices for Perchlorate Materials•E Act on Preventing Environmental Pollution of Mercury (Japan)16.Other informationThis PSDS is provided to customers as reference information in order to handle batteries safely.It is necessary for the customer to take appropriate measures depending on the actual situation such as the individual handling, based on this information.Prepared by: Engineering DepartmentEnergy Device Business DivisionPanasonic Energy Co., Ltd.。
UC3906 Datasheet
UC2906UC3906 Sealed Lead-Acid Battery ChargerFEATURES•Optimum Control for Maximum Battery Capacity and Life •Internal State Logic Provides Three Charge States •Precision Reference Tracks Battery Requirements OverTemperature•Controls Both Voltage and Current at Charger Output •System Interface Functions •Typical Standby SupplyCurrent of only 1.6mA DESCRIPTIONThe UC2906 series of battery charger controllers contains all of the necessary circuitry to optimally control the charge and hold cycle for sealed lead-acid batter-ies. These integrated circuits monitor and control both the output voltage and cur-rent of the charger through three separate charge states; a high current bulk-charge state, a controlled over-charge, and a precision float-charge, or standby, state.Optimum charging conditions are maintained over an extended temperature range with an internal reference that tracks the nominal temperature charac-teristics of the lead-acid cell. A typical standby supply current requirement of only 1.6mA allows these ICs to predictably monitor ambient temperatures.Separate voltage loop and current limit amplifiers regulate the output voltage and current levels in the charger by controlling the onboard driver. The driver will sup-ply up to 25mA of base drive to an external pass device. Voltage and current sense comparators are used to sense the battery condition and respond with logic inputs to the charge state logic. A charge enable comparator with a trickle bias output can be used to implement a low current turn-on mode of the charger, preventing high current charging during abnormal conditions such as a shorted battery cell.Other features include a supply under-voltage sense circuit with a logic output to indicate when input power is present. In addition the over-charge state of the charger can be externally monitored and terminated using the over-charge indi-cate output and over-charge terminate input.UC2906UC3906 Supply Voltage (+V IN). . . . . . . . . . . . . . . . . . . . . . . . . . . 40VOpen Collector Output Voltages. . . . . . . . . . . . . . . . . . . 40VAmplifier and Comparator Input Voltages. . . -0.3V to +40VOver-Charge Terminate Input Voltage. . . . . . -0.3V to +40VCurrent Sense Amplifier Output Current. . . . . . . . . . 80mAOther Open Collector Output Currents. . . . . . . . . . . . 20mATrickle Bias Voltage Differential with respect to V IN. . . -32VTrickle Bias Output Current. . . . . . . . . . . . . . . . . . . . -40mADriver Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80mAPower Dissipation at T A = 25°C(Note 2). . . . . . . . 1000mWPower Dissipation at T C = 25°C (Note 2). . . . . . . . 2000mWOperating Junction Temperature. . . . . . . . -55°C to +150°CStorage Temperature. . . . . . . . . . . . . . . . . -65°C to +150°CLead Temperature (Soldering, 10 Seconds). . . . . . . 300°CNote 1:Voltages are referenced to ground (Pin 6). Currentsare positive into, negative out of, the specified terminals.Note 2: Consult Packaging section of Databook for thermallimitations and considerations of packages.ABSOLUTE MAXIMUM RATINGS (Note 1)Unless otherwise stated, these specifications apply for T A = -40°C to +70°C for theUC2906 and 0°C to +70°C for the UC3906, +V IN = 10V, T A = T J.ELECTRICAL CHARACTERISTICS:the reference and the thermal resistance, junction-to-ambient.ELECTRICAL CHARACTERISTICS:Unless otherwise stated, these specifications apply for T A = -40°C to +70°C for theUC2906 and 0°C to +70°C for the UC3906, +V IN = 10V, T A = T J.UC2906UC3906Dual Level Float Charger OperationsThe UC2906 is shown configured as a dual level float charger in Figure 1. All high currents are handled by the external PNP pass transistor with the driver supplying base drive to this device. This scheme uses the TRICKLE BIAS output and the charge enable comparator to givethe charger a low current turn on mode. The output cur-rent of the charger is limited to a low-level until the battery reaches a specified voltage, preventing a high current charging if a battery cell is shorted. Figure 2 shows the state diagram of the charger. Upon turn on the UV sense circuitry puts the charger in state 1, the high rate bulk-charge state. In this state, once the enable threshold has been exceeded, the charger will supply a peak current that is determined by the 250mV offset in the C/L ampli-fier and the sensing resistor R S.T o guarantee full re-charge of the battery, the charger’s voltage loop has an elevated regulating level, V OC , during state 1 and state 2. When the battery voltage reaches 95% of V OC , the charger enters the over-charge state,state 2. The charger stays in this state until the OVER-CHARGE TERMINATE pin goes high. In Figure 1, the charger uses the current sense amplifier to generate this signal by sensing when the charge current has tapered to a specified level, I OCT . Alternatively the over-charge could have been controlled by an external source, such as a timer, by using the OVER-CHARGE INDICATE signal at Pin 9. If a load is applied to the battery and begins to dis-charge it, the charger will contribute its full output to the load. If the battery drops 10% below the float level, the charger will reset itself to state 1. When the load is re-moved a full charge cycle will follow. A graphical repre-sentation of a charge, and discharge, cycle of the duallever float charger is shown in Figure 3.UC2906UC3906OPERATION AND APPLICATION INFORMATIONUC2906UC3906 OPERATION AND APPLICATION INFORMATION (continued)Compensated Reference Matches Battery Requirements When the charger is in the float state, the battery will be maintained at a precise float voltage, V F . The accuracy of this float state will maximize the standby life of the battery while the bulk-charge and over-charge states guarantee rapid and full re-charge. All of the voltage thresholds on the UC2906 are derived from the internal reference. This reference has a temperature coefficient that tracks the temperature characteristic of the optimum-charge and hold levels for sealed lead-acid cells. This further guaran-tees that proper charging occurs, even at temperature ex-tremes.Dual Step Current Charger OperationFigures 4, 5 and 6 illustrate the UC2906’s use in a differ-ent charging scheme. The dual step current charger is useful when a large string of series cells must be charged. The holding-charge state maintains a slightly elevated voltage across the batteries with the holding cur-rent, 1H . This will tend to guarantee equal charge distribu-tion between the cells. The bulk-charge state is similar to that of the float charger with the exception that when V 12is reached, no over-charge state occurs since Pin 8 is tied high at all times. The current sense amplifier is used to regulate the holding current. In some applications a series resistor, or external buffering transistor, may be requiredat the current sense output to prevent excessive power dissipation on the UC2906.A PNP Pass Device Reduces Minimum Input to Out-put DifferentialThe configuration of the driver on the UC2906 allows a good bit of flexibility when interfacing to an external pass transistor. The two chargers shown in Figures 1 and 4both use PNP pass devices, although an NPN device driven from the source output of the UC2906 driver can also be used. In situations where the charger must oper-ate with low input to output differentials the PNP pass de-vice should be configured as shown in Figure 4. The PNP can be operated in a saturated mode with only the series diode and sense resistor adding to the minimum differen-tial. The series diode, D1, in many applications, can be eliminated. This diode prevents any discharging of the battery, except through the sensing divider, when the charger is attached to the battery with no input supply voltage. If discharging under this condition must be kept to an absolute minimum, the sense divider can be refer-enced to the POWER INDICATE pin, Pin 7, instead of ground. In this manner the open collector off state of Pin 7 will prevent the divider resistors from discharging thebattery when the input supply is removed.UC2906UC3906OPERATION AND APPLICATION INFORMATION (continued)UC2906UC3906 OPERATION AND APPLICATION INFORMATION (continued)UNITRODE INTEGRA TED CIRCUITS7 CONTINENTAL BLVD. • MERRIMACK, NH 03054TEL. 603-424-2410 • FAX 603-424-3460IMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK.In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.Copyright © 1999, Texas Instruments IncorporatedThis datasheet has been downloaded from:Free DownloadDaily Updated Database100% Free Datasheet Search Site100% Free IC Replacement Search SiteConvenient Electronic DictionaryFast Search SystemAll Datasheets Cannot Be Modified Without PermissionCopyright © Each Manufacturing Company。
UC3706中文资料
UC2706UC3706Dual Output DriverFEATURES•Dual,1.5A Totem Pole Outputs •40nsec Rise and Fall into 1000pF •Parallel or Push-Pull Operation •Single-Ended to Push-Pull Conversion •High-Speed,Power MOSFET Compatible•Low Cross-Conduction Current Spike •Analog,Latched Shutdown •Internal Deadband Inhibit Circuit •Low Quiescent Current •5to 40V Operation•Thermal Shutdown Protection •16-Pin Dual-In-Line Package •20-Pin Surface Mount PackageDESCRIPTIONThe UC1706family of output drivers are made with a high-speed Schottky process to interface between low-level control functions and high-power switching devices -particularly power MOSFET's.These de-vices implement three generalized functions as outlined below.First:They accept a single-ended,low-current digital input of either polar-ity and process it to activate a pair of high-current,totem pole outputs which can source or sink up to 1.5A each.Second:They provide an optional single-ended to push-pull conversion through the use of an internal flip-flop driven by double-pulse-suppression logic.With the flip-flop disabled,the outputs work in parallel for 3.0A capability.Third:Protection functions are also included for pulse-by-pulse current limiting,automatic deadband control,and thermal shutdown.These devices are available in a two-watt plastic “bat-wing”DIP for op-eration over a 0°C to 70°C temperature range and,with reduced power,in a hermetically sealed cerdip for -55°C to +125°C operation.Also avail-able in surface mount Q and Lpackages.BLOCK DIAGRAMINV N.I OUT H L H LH H L LL H L LOUT =INV and N.I.OUT =INV or N.I.TRUTHTABLE10/98ABSOLUTE MAXIMUM RATINGS.......................................N--Pkg ............J--Pkg Supply Voltage,V IN .........................40V..................40V Collector Supply Voltage,V C ..................40V..................40V Output Current (Each Output,Source or Sink)Steady--State..........................±500mA..............±500mA Peak Transient..........................±1.5A................±1.0A Capacitive Discharge Energy..............20m J .................15m J Digital Inputs ..............................5.5V .................5.5V Analog Stop Inputs.........................V IN ..................V IN Power Dissipation at T A =25°C (See Note).......2W ..................1W Power Dissipation at T (Leads/Case)=25°C......5W ...................2(See Note)Operating Temperature Range ......................--55°C to +125°C Storage Temperature Range........................--65°C to +150°C Lead Temperature (Soldering,10Seconds)................300°CNote:All voltages are with respect to the four ground pins which must be connected together.All currents are positive into,negative out of the specified trerminal.ConsultPackaging sections of the Databook for thermal limitations and considerations of package.CONNECTION DIAGRAMSground.ELECTRICAL CHARACTERISTICS:Unless otherwise stated,these specifications apply for T A =–55°C to +125°C forthe UC1706,–25°C to +85°C for the UC2706and 0°C to +70°C for the UC3706;V IN =V C =20V.T A =T J .PARAMETERSTEST CONDITIONSMINTYP MAX UNITS V IN Supply Current V IN =40V810mA V C Supply Current V C =40V,Outputs Low 45mA V C Leakage Current V IN =0,V C =30V,No Load.050.1mA Digital Input Low Level 0.8V Digital Input High Level 2.2V Input Current V I =0–0.6–1.0mA Input LeakageV I =5V.050.1mAELECTRICAL CHARACTERISTICS:Unless otherwise stated,these specifications apply for T A=–55°C to+125°C for the UC1706,–25°C to+85°C for the UC2706and0°C to+70°C for the UC3706;V IN=V C=20V.T A=T J.PARAMETERS TEST CONDITIONS MIN TYP MAX UNITS Output High Sat.,V C-V O I O=-50mA 2.0VOutput Low Sat.,V O I O=50mA0.4VI O=500mA 2.5VInhibit Threshold V REF=0.5V0.40.6VV REF=3.5V 3.3 3.7V Inhibit Input Current V REF=0–10–20m A Analog Threshold V CM=0to15V100130160mV Input Bias Current V CM=0–10–20m A Thermal Shutdown155°CTYPICAL SWITCHING CHARACTERISTICS:V IN=V C=20V,T A=25°C.Delays measured to10%output change.PARAMETERS TEST CONDITIONS OUTPUT C L=UNITS From Inv.Input to Output:open 1.0 2.2nF Rise Time Delay110130140ns 10%to90%Rise204060ns Fall Time Delay8090110ns 90%to10%Fall253050ns From N.I.Input to Output:Rise Time Delay120130140ns 10%to90%Rise204060ns Fall Time Delay100120130ns 90%to10%Fall253050ns V C Cross-Conduction Current Spike Duration Output Rise25nsOutput Fall0ns Inhibit Delay Inhibit Ref.=1V,Inhibit Inv.=0.5to1.5V250ns Analog Shutdown Delay Stop Non-Inv.=0V,Stop Inv.=0to0.5V180nsCIRCUIT DESCRIPTIONOutputsThe totem-pole outputs have been designed to minimize cross-conduction current spikes while maximizing fast, high-current rise and fall times.Current limiting can be done externally either at the outputs or at the common V C pin.The output diodes included have slow recovery and should be shunted with high-speed external diodes when driving high-frequency inductive loads.Flip/FlopGrounding pin7activates the internal flip-flop to alter-nate the two outputs.With pin7open,the two outputs operate simultaneously and can be paralleled for higher current operation.Since the flip-flop is triggered by the digital input,an off-time of at last200nsec must be pro-vided to allow the flip/flop to change states.Note that the circuit logic is configured such that the“OFF”state is de-fined as the outputs low.Digital InputsWith both an inverting and non-inverting input available, either active-high or active-low signals may be accepted. These are true TTL compatible inputs—the threshold is approximately1.2V with no hysteresis;and external pull-up resistors are not required.Inhibit CircuitAlthough it may have other uses,this circuit is included to eliminate the need for deadband control when driving relatively slow bipolar power transistors.A diode from each inhibit input to the opposite power switch collector will keep one output from turning-on until the other has turned-off.The threshold is determined by the voltage on pin15which can be set from0.5to3.5V.When this cir-cuit is not used,ground pin15and leave1and16open.UC3706CIRCUIT DESCRIPTION(cont.)APPLICATIONSLevel Shifting to Ground Referenced PWMsAnalog ShutdownThis circuit is included to get a latched shutdown as close to the outputs as possible,from a time standpoint.With an internal 130mV threshold,this comparator has a common-mode range from ground to (V IN –3V).When not used,both inputs should be grounded.The time re-quired for this circuit to latch is inversely proportional to the amount of overdrive but reaches a minimum of 180nsec.As with the flip-flop,an input off-time of at least 200nsec is required to reset the latch between pulses.Supply VoltageWith an internal 5V regulator,this circuit is optimized foruse with a 7to 40V supply;however,with some slight re-sponse time degradation,it can also be driven from 5V .When V IN is low,the entire circuit is disabled and no cur-rent is drawn from V C .When combined with a UC1840PWM,the Driver Bias switch can be used to supply V IN to the UC1706.V IN switching should be fast as if V C is high,undefined operation of the outputs may occur with VI N less than 5V .Thermal ConsiderationsShould the chip temperature reach approximately 155°C,a parallel,non--inverting input is activated driving both outputs to the low state.UC3706 APPLICATIONS(cont'd)UNITRODE CORPORA TION7CONTINENTAL BLVD.•MERRIMACK,NH03054TEL.(603)424-2410•FAX(603)424-3460IMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK.In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.Copyright © 1999, Texas Instruments Incorporated。
TS-SEN-PD-0007A.0-BF3703 Datasheet
BYD Microelectronics Co., Ltd.VGA CMOS Image SensorBF3703DatasheetRevision HistoryRevised. Date Revision Brief Description Author Proofread AuthorizeYaqian Zhou Lei Hu Wenge 2010-8-12 A/0 Initialrelease Li1. General DescriptionThe BF3703 is a highly integrated VGA camera chip which includes CMOS image sensor (CIS) and image signal processing function (ISP). It is fabricated with the world’s most advanced CMOS image sensor process to realize ultra-low dark noise, high sensitivity and very low power imaging system. The sensor consists of a 653 x 493 effective pixel array which has an optical format of 1/10 inch. It has integrated noise canceling CDS (Correlated Double Sampling) circuits, analog global gain and separated R/G/B gain controller, auto black level compensation and on-chip 10-bit ADC. The on-chip ISP provides a very smooth AE (Auto Exposure) and accurate AWB (Auto White Balance) control. It provides various data formats, such as Bayer RGB, RGB444, RGB555, RGB565, YCBCR 4:2:2. It has a commonly used two-wire serial interface for host to control the operation of the whole sensor.The product is capable of operating at up to 30 frames per second at 24MHZ clock in VGA mode, with complete user control over image quality and data formatting. All required image processing functions, including exposure control, white balance control, color saturation control and so on, are also programmable through the two-wire serial bus.2. Featuresz Standard optical format of 1/10 inch.z30 frame/sec VGA mode @ 24MHz master clock.z Ultra-low dark noise at high temperature.z Various output formats: YCBCR4:2:2, RGB444, RGB555, RGB565, Raw Bayer(652 x 492).z Power supply: 2.7~3.1V for core, 1.7~3.1V for I/O.z Horizontal /Vertical mirror.z50/60Hz flicker cancellation.z Programmable I/O drive capability.z Automatic black level control.z Image processing function: Lens Shading Correction, Gamma Correction, Bad pixel correction, Color Interpolation, False Color Suppression, Purple Fringe Correction, Low Pass Filter, Color Space Conversion, Color Correction, Edge Enhancement, Auto exposure, Auto White Balance, Color Saturation and Contrast, and Data Format Conversion.z12 types of special video effectz On-chip test pattern generation of many types including customer programmablez Package: CSP, Bare Die3. Applicationsz Cellular Phone Camerasz Notebook and desktop PC camerasz PDAsz Toysz Digital still cameras and camcordersz Video telephony and conferencing equipmentsz Security systemsz Industrial and environmental systems4. Technical Specificationsz Active pixel array: 653 x 493z Pixel size: 2.25μm×2.25μmz Sensitivity: 1V/lux.sz Dark current: 3 mV/S at 40℃z Power consumption: 56mW @ 30fps and single 2.8V supply z Standby current: 30uAz S/N Ratio: 35dBz Dynamic range: 58dBz Operating temperature: -20~60℃z Stable Image temperature 0~50℃z Optimal lens chief ray angle: 25º5. Functional OverviewBF3703 has an active image array of 653x493 pixels. The active pixels are read out progressively through column/row driver circuits. In order to reduce fixed pattern noise, CDS circuits are adopted. The ASP block is mainly used to control global gain and color gains to get accurate exposure and white balance under different light condition and color temperature. The analog signal is transferred to digital signal by A/D converter. The digital signals are processed in the ISP Block, including Bayer interpolation, low pass filter, color correction, gamma correction, data format conversion and so on. Users can easily control these functions via two-wire serial interface bus.5.1 Pixel Array7 6 5 4 3 2 1 012349049149248945488487486Dark rowDummy rowFigure 2. Sensor Array RegionThe active pixel array is configured as 653 columns by 493 rows. Dummy pixels and dark rows are added outside the active pixel array.Pixel array is covered by Bayer color filters as can be seen in the figure2. The primary color BG/GR array is arranged in line-alternating fashion. Since each pixel can have only one type of color filter on it, only one color component can be obtained by a pixel. BF3703 can provide the Raw Bayer data or YUV data through an 8-bit output data bus. If no flip in column, column is read out from 0 to 651. If flip in column, column is read out from 652 to 1. If no flip in row, row is read out from 0 to 491. If flip in row, row is read out from 492 to 1. In this way, the output pixel color order is always the same.Pixel array output signal order is always:BGBGBG……GRGRGR…..5.2 Column CDSBF3703 has column/row driver circuits to read out the pixel data progressively. The CDS (Correlated Double Sampling) circuit reduces temporal noise and pixel level FPN (Fixed Pattern Noise). The unique patented column buffer amplifier and ASP (Analog Signal Processing) circuit remove column level FPN caused by various sources of manufacturing process variations.5.3 Timing controllerThe timing controller controls the following functionsz Array control and frame generationz Internal timing signal generation and distributionz Frame rate timingz External timing outputs (VSYNC, HREF and VCLK)5.4 Analog Signal ProcessorThis block performs all analog image functions including Color gain/Global gain control and black level compensation. Each of the R, G, B color pixel signals can be multiplied by different gain factors to balance the color of the image at various light conditions.5.5 A/D converterThe analog signals are converted to digital forms column by column and row by row, through out the whole array. BF3703 provides the 10-bit Raw Bayer data for ISP through an internal 10-bit data bus.5.6 Automatic Black ControlThe automatic black level controller calculates the data of the dark row and controls the lowest black level for output image data.5.7 Image Signal ProcessorThis block performs all image processing functions including Lens Shading Correction, Gamma Correction, Bad pixel correction, Color Interpolation, False Color Suppression, Low Pass Filter, Color Space Conversion, Color Correction, Edge Enhancement, Auto exposure, Auto White Balance, Color Saturation, Contrast, and Data Format Conversion.6. Specifications6.1 Electrical Characteristics6.1.1. Absolute Maximum Ratingsz Supply voltage (VDDIO): 1.7 ~ 3.1 Vz Supply voltage (VDD3A): 2.7 ~ 3.1 Vz Operating temperature: -20~60 ℃z Storage temperature: -30~80 ℃z ESD Rating, Human Body mode: 2000 VCaution:Stresses exceeding the absolute maximum ratings may induce failure.6.1.2. DC ParametersTable 1. DC Operation ConditionsSymbol Parameter Unit Min. Typ.Max. NotesVDDIO I/O power supply V 1.7 2.8 3.1VDD3A Analog power supply V 2.7 2.8 3.1 --I_vddio VDDIO supply current,normal operation modemA -- 10.0-- 1I_vdd3a VDD3A supply current,normal operation modemA -- 10.0-- 2Vih Input voltage logic “1” V 0.7*VDDIO-- -- --Vil Input voltage logic “0” V -- -- 0.2*VDDIO --Voh Output voltage logic “1” V 0.9*VDDIO-- -- -- Vol Output voltage logic “0” V -- --0.1*VDDIO -- Note：1. Because power consumption of I/O depends on the output load and system environment, usershould supply enough current to sensor for stable operation. It is measured when output load is floated.2. Because current of analog circuit depends on the registers’ values, it is measured at specificregister’s value.6.1.3. Clock RequirementTable 2. AC Operation ConditionsSymbol Parameter Unit Min.Typ. Max. NotesMCLK Main clock frequency MHz-- 24 -- 1SCLk two-wire serial interface clock frequency KHz -- 400 -- 2Inormal Current in YUV4:2:2 output mode mA -- 20 -- 3Idown Current in power down mode uA -- 30 -- 4Note:1. XCLK(external clock) may be divided by internal clock division logic to get MCLK for easy integration with high speed video codec system.2. SCLK is driven by host processor. For the detail serial bus timing, refer to two-wire serialinterface section3. VDDIO=2.8V, VDD3A=2.8V(YUV4:2:2 output).4. Hardware power down.6.2 Electro-Optical CharacteristicsClock frequency: 24MHz.Operating voltage: VDDIO=2.8V, VDD3A=2.8V.Operating temperature: 25°CTable 3. Electro-Optical CharacteristicsParameter Unit Min.Typ. Max.NotesSensitivity V/Lux·sec -- 1 1Dark current mV/sec -- 3 6 2-- --35dBS/N ratio dB ---- --Dynamic Range dB --58dBFrame Rate fps -- -- 30 3Notes:1. With color filter, measured at 50 lux green light condition at room temperature.2. Measured at dark condition for exposure time of 1s (40 Celsius).3. With 652×492 window size at MCLK 24MHz.6.3 Input-Output AC CharacteristicsFigure 3. Two-Wire Serial Interface TimingFigure 4. Horizontal Timing Raw Bayer DataFigure 5. Horizontal Timing YUV4:2:2Figure 6. VGA Frame TimingTable 4. AC CharacteristicsSymbol DescriptionsMin.Typ. Max. Unit t P t P =2 x t MCLK-- 83.2 -- ns f MCLK Master Clock Frequency --24--MHzf VCLK Video Clock Frequency for Raw data , f V = f MCLK /2 for YUV/RGB , f V = f MCLK -- 12/24 -- MHzt LINE Line length--784x t P -- nst R, t F two-wire serial interface rise/fall times-- -- 300 ns t LOW Clock Low Period 1.3 -- -- us t HIGH Clock High Period 600 -- -- ns t HD:STA Start condition Hold Time 600 -- -- ns t SU:STA Start condition Setup Time 600 -- -- ns t HD:DAT Data-in Hold Time 0 -- -- ns t SU:DAT Data-in Setup Time 100 -- -- ns t SU:STO Stop condition Setup Time 600 -- -- nst1 XCLK rising to VCLK (RAW DATA)-- 28.8 -- nst2 VCLK rising to HREF (RAW DATA)-- 43.8 -- nst3 XCLK rising to VCLK (YUV) -- 19.2 -- ns t4VCLK rising to HREF (YUV)--21.6--ns6.4 Color Filter Spectral CharacteristicsThe optical spectrum of color filters is shown below.Figure 7. Spectral Characteristics7. Two-wire serial interface& Register7.1 Theory of OperationThe registers of BF3703 are written and read through the two-wire serial interface. BF3703 has two-wire serial interface slave. BF3703 is controlled by the two-wire serial interface clock (SCLK), which is driven by the two-wire serial interface master. Data is transferred into and out of BF3703 through the two-wire serial interface data (SDA) line. The SCL and SDA lines are pulled up to VDD by a 2kΩ off-chip resistor. Either the slave or the master device can pull the lines down. The two-wire serial interface protocol determines which device is allowed to pull the two lines down at any given time.Note: Two-wire serial interface device address of BF3703 is6eh.Start bitThe start bit is defined as a HIGH to LOW transition of the data line while the clock line is HIGH.Stop bitThe stop bit is defined as a LOW to HIGH transition of the data line while the clock line is HIGH.Slave AddressThe 8-bit address of a two-wire serial interface device consists of 7 bits of address and 1 bit of direction.A “0” in the LSB of the address indicates write mode, and “1” indicates read-mode.Data bit transferOne data bit is transferred during each clock pulse. The two-wire serial interface clock pulse is provided by the master. The data must be stable during the HIGH period of the two-wire serial interface clock: it can only change when the two-wire serial interface clock is LOW. Data is transferred 8 bits at a time, followed by an acknowledge bit.Acknowledge bitThe receiver generates the acknowledge clock pulse. The transmitter (which is the master when writing, or the slave when reading) releases the data line, and receiver indicates an acknowledge bit by pulling the data line low during the acknowledge clock pulse.No-acknowledge bitThe no-acknowledge bit is generated when the data line is not pulled down by the receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate a read sequence.SequenceA typical read or write sequence begins by the master sending a start bit. After start bit, the master sends the slave device’s 8-bit address. The last bit of the address determines if the request will be a read or a write, where “0” indicates write and “1” indicates read. The slave device acknowledges its address by sending an acknowledge bit back to the master.If the request was a write, the master then transfers the 8-bit register address to which a write should take place. The slave sends an acknowledge bit to indicate that the register address has been received. The master then transfers the data 8 bits at a time, with the slave sending an acknowledge bit after each 8 bits. The BF3703 uses 8 bit data for its internal registers, thus requiring one 8-bit transfer to write to one register. After 8 bits are transferred, the register address is automatically incremented, so that the next 8 bits are written to the next register address. The master stops writing by sending a start or stop bit.A typical read sequence is executed as follows. First the master sends the write-mode slave address and 8-bit register address just as in the write request. The master then sends a start bit and the read-mode slave address. The master then clocks out the register data 8 bits at a time. The mastersends an acknowledge bit after each 8-bit transfer. The register address is auto-incremented after each 8 bit is transferred. The data transfer is stopped when the master sends a no-acknowledge bit.7.2 Two-wire Serial Interface Functional DescriptionSingle Write Mode OperationMultiple Write Mode (Register address is increased automatically) 1 operationSingle Read Mode OperationMultiple Read Mode (Register address is increased automatically) 1 OperationFrom master to slave From slave to masterS:Start condition. Sr: Repeated Start (Start without preceding stop.)Slave Address: write address =DCh =11011100bread address = DDh = 11011101bR/W: Read/Write selection. High = read, LOW = write.A:Acknowledge bit. NA: No Acknowledge.Data: 8-bit data P: Stop conditionNote1: Continuous writing or reading without any interrupt increases the register address automatically.If the address is increased above valid register address range, further writing does not affect thechip operation in write mode. Data from invalid registers are undefined in read mode.7.3 Register Summary (full list)Table 5. BF3703 all registers AddressName Width Default value Description 00hDBLKHE 6 20h Reserved. 01hBLUE_GAIN 6 19h Blue gain register. 02h RED_GAIN 6 15h Red gain register.03h VHREF 8 00h VREF and HREF control. Bit[7:6]: VREF end low 2 Bits(high 8 Bit at VSTOP[7:0]) Bit[5:4]: VREF start low 2 Bits(high 8 Bit at VSTART[7:0])Bit[3:2]: HREF end 2 LSB(high 8 MSB at register HSTOP )Bit[1:0]: HREF start 2 LSB(high 8 MSB at register HSTART )05hLOFFN1E 6 1eh Coarse negative offset control-even column. 06hLOFFN0 8 e0h Bit[7]: Two wire serial interface switch. Bit[6]: Reserved. Bit[5:0]: Fine negative offset control col. 08h TAREG3 8 00h Reserved.09h COM2 8 10h Common control 2.When 0x20[6]=0,Bit[1:0]: Data & clk & hsync output drive capability.00: 1x, 01: 2x, 10: 3x, 11: 4x.When 0x20[6]=1,Bit[7:6]: Vclk output drive capability.00: 1x, 01: 2x, 10: 3x, 11: 4x.Bit[5]: Spare.Bit[4]: Standby mode.0: Disable standby mode.1: Enable standby mode.Bit[3:2]: Hsyc output drive capability.00: 1x, 01: 2x, 10: 3x, 11: 4x.Bit[1:0]: Data output drive capability.00: 1x, 01: 2x, 10: 3x, 11: 4x.0ah COM5 8 21h Common control 5.Bit[7:4]: Total column number1 for gate subsample.Bit[3:0]: Column select number1 for gate subsample.0bh COM48 00h Common control 4.Bit[7]: 0: Select even row, 1: Select odd row.Bit[6]: 0: Select even column, 1: Select odd column.Bit[5:4]: 0x:Output normal HSYNC/VSYNC.10: HSYNC=0,VSYNC=0.11: HSYNC=1,VSYNC=1.Bit[3:0]: Skip frame counter.0ch COM3 8 00h Common control 3. Bit[7]: PROCRSS RAW selection, 0: Process raw from YCBCR to RGB conversion in data format, 1: Process raw from color interpolation(deniose, gamma, lsc is selectable), Bit[6]:Output data MSB and LSB swap, Bit[5:4]: PROCESS RAW sequence(when 0x0c[7]=0), 00: (LINE0:BGBG/LINE1:GRGR), 01: (LINE0:GBGB/LINE1:RGRG), 10: (LINE0:GRGR/LINE1:BGBG), 11: (LINE0:RGRG/LINE1:GBGB). Bit[3]: 0:no HREF when VSYNC_DAT=0,1:Always has HREF no matter VSYNC_DAT=0 or not,Bit[2]: DATA ahead 1 clk(YUV MCLK, RawData PCLK) or not,Bit[1]: HREF ahead 1 clk(YUV MCLK, RawData PCLK) or not,Bit[0]: HREF ahead 0.5 clk(YUV MCLK, RawData PCLK) or not,0x0c[1:0]:00:HREF and data is synchronous,01:HREF before data 0.5 clk,10:HREF before data 1 clk,11:HREF before data 1.5 clk.0dhDBLKLE 6 20h Reserved. 0ehDBLKHO 6 20h Reserved. 0fhDBLKLO 6 20h Reserved. 10h COM6 8 21h Common control 6. Bit[7:4]: Total row number1 for gate subsample.Bit[3:0]: Row select number1 for gate subsample.11h CLKRC 8 80h Mclk division control. Bit[7]: Double Clock Option. 0:Disable double clock option, Meaning the maximum MCLK can be as high as half input clock. 1:Enable double clock option, Meaning the maximum MCLK can be as high as input clock. Bit[6]: Use external clock directly(F(internal clock)==F(input clock)). Bit[5:4]: Mclk divider factor 00: Divided by 1, 01: Divided by 2,10: Digital power down,11: Divided by4.Bit[3:2]: Pclk control.0: Normal,1: Inverse and dly 1.5ns,2: Inverse and dly 3ns,3: Inverse and dly 5.5ns.Bit[1]: Spare.Bit[0]: Doubler clock selection. 0: Mclk, 1: Mclk/2.12h COM7 8 00h Common control 7. Bit[7]: SCCB Register Reset. 0: No change, 1: Resets all registers to default values. Bit[6]: Reserved. Bit[5]: Row subsample Selection. 0: Enable, 1: Disable. Bit[4]: 1/2 digital subsample Selection(only for YUV422/RGB565/RGB555/RGB444 output). Bit[3]: Reserved.Bit[2]: YUV422/RGB565/RGB555/RGB444 Selection.Bit[1]: Reserved.Bit[0]: Raw RGB Selection.{0x12[2],0x12[0]}00: YUV422,01: Bayer RAW,10: RGB565/RGB555/RGB444(use with 0x3a),11: Process RAW(use with 0x0c[7]).13h COM8 8 07h Common control 8. Bit[7:4]: Reserved. Bit[3]: Select when to use small steps to adjust the integration time. 0: When INT_TIM lower than 10ms, 1: When INT_TIM lower than 20ms.Bit[2]: AGC Enable. 0:OFF , 1: ON.Bit[1]: AWB Enable. 0:OFF , 1: ON.Bit[0]: AEC Enable. 0:OFF , 1: ON.14h LOFFN1O6 1eh Coarse negative offset control-odd col. 15h COM10 8 02h Common control 10. Bit[7]: Reserved. Bit[6]: 0:HREF, 1:HSYNC. Bit[5]: 0:VSYNC_IMAGE, 1:VSYNC_DAT. Bit[4]: VCLK reverseBit[3]: HREF option. 0: Active high, 1: Active low.Bit[2]: ReservedBit[1]: VSYNC option. 0: Active low, 1: Active high.Bit[0]: HSYNC option. 0: Active high, 1: Active low.16h BIAS2 8 09h Reserved.17h HSTART 8 00h Output Format-Horizontal Frame(HREF column)start high 8-Bit(low 2Bits are at VHREF[1:0])18h HSTOP 8 a0h Output Format-Horizontal Frame(HREF column)end high 8-Bit(low 2 Bits are at VHREF[3:2])19h VSTART 800h Output Format-Vertical Frame(row)start high 8-Bit(low 2 Bits are at VHREF[5:4]) 1ah VSTOP8 78h Output Format-Vertical Frame(row)end high 8-Bit(low 2 Bits are at VHREF[7:6]) 1bh PLLCTL 8 80h PLL control. Bit[7]: PLL pdn Enable. 0: Enable, 1: Disable. Bit[6:4]: Spare. Bit[3:2]: Loop divide, default11 (Divided by 3). 00: Divided by 4, 01: Divided by 1, 10: Divided by 2,11: Divided by 3.Bit[1:0]: Output divide, default 11 (Divided by 24).00: Divided by 1,01: Divided by 6,10: Divided by 12,11: Divided by 24.1ch MIDH 8 7fh,RO Reserved.1dh MIDL8 a2h,RO Reserved.1eh MVFP 8 00h Mirror/Vflip Enable. Bit[7:6]:Reserved Bit[5]: Mirror. 0: Normal image, 1: Mirror image.Bit[4]: Vflip enable. 0: Normal image, 1: Vertically flip.Bit[3:0]: Reserved1fh DBLK_TARG 8 20hBlack control target for G.Bit[7:0]: Black control target for G. Bit[6:0]: Reserved.20h TDREG 8 00h Bit[7]: Reserved.Bit[6]: Hsync&clk pad drive capability control.0: Same drive capability, 1: Drive capability adjustment independently.(refer to register COM2)Bit[5:0]: Reserved.21hReserved. 22h DBLK_TARR 8 20hBlack control target for R. Bit[7:0]:Black control target for R. Bit[6:0]: Reserved.23h GLGAINREG 7 33h GreenGain[2:0]:Bit[6:4]: For even column (used as GreenEgain[2:0]).Bit[2:0]: For odd column (used as GreenOgain[2:0]).24h AE_LOCK1 88Ah Y target value 1. 25hAE_LOCK2 8 7Ah Y target value 2. 26h DBLK_TARB 8 20h Black control target for B, Bit[6:0]:Black control target for B.27h STEP 8 04hBit[7:6]: Coarse adjustment range,00: 4, 01: 8, 10: 12, 11: 16. Bit[5:0]: Step.28h DBLK_CNTL 8 00h Reserved.29h BIAS1 8 04h BIAS control 1.Bit[7]: Black control fine adjustment resolution control for even column.Bit[6]: Black control coarse adjustment resolution control for even column.Bit[5]: Black control fine adjustment resolution control for odd column. Bit[4]: Black control coarse adjustment resolution control for odd column.Bit[3]: Spare.Bit[2:0] ADC bias setting.0d: Lower bias, 15d: Higher bias.2ah EXHCH 8 00hDummy Pixel Insert MSB.Bit[7:4]: Dummy Pixel Insert MSB. Bit[3:0]: Reserved.2bh EXHCL 8 00h Dummy Pixel Insert LSB. Bit[7:0]: Dummy Pixel Insert LSB.2dh INT_TIMH 8 06h Integration time MSB.2eh INT_TIML 8 66h Integration time LSB.2fh DREF 8 e2h Reserved.30h HSYST 864h Control the rising edged of HSYNC, HSYNC rising edge low 8 Bits. 31hHSYEN 8 14h Control the falling edged of HSYNC, HSYNC falling edge low 8 Bits. 32h LS_MODE 8 1fhBit[7:5]: Reserved, Bit[4]: Light sensor control. 0: Disable, 1: Enable. Bit[3:0]: Reserved.33h OFFSET_MODE 8 00h Lens shading offset selection:Bit[7]: 0: Use black average value(from Black Control function) as offset 1: Use register OFFSET_REG as offsetBit[6:0]: Reserved.34h OFFSET_REG 838h Lens shading offset. 35h R_COEF8 46h Lens shading gain of R.36h Y0H_G,Y0H_B,X0H_G,X0H_B6 05h Bit[5: Y0H_G. Center row coordinate HSB of G channel. Bit[4]: Y0H_B. Center row coordinate HSB of B channel. Bit[3:2]: X0H_G. Center col coordinate HSB of G channel. Bit[1:0]: X0H_B. Center col coordinate HSB of B channel. 37h Y0L_B8 f6h Reserved. 38h X0L_B8 46h Reserved. 39hOFFSET2 8 80hGamma Offset 2: Bit[7]: 0: Positive , 1: Negative Bit[6:0]: Value. 3ah TSLB 8 00h Data output sequence. If YUV422 is selected. The Sequence is: Bit[1:0]:Output YUV422 Sequence 00: YUYV, 01: YVYU 10: UYVY, 11: VYUY If RGB565/RGB555/RGB444 is selected. The Sequence is: Bit[4:0]:Output RGB565/RGB555/RGB444 Sequence RGB565: 00h: R5G3H,G3LB5， 01h: B5G3H,G3LR5. 02h: B5R3H,R2LG6， 03h: R5B3H,B2LG6. 04h: G3HB5,R5G3L ， 05h: G3LB5,R5G3H. 06h: G3HR5,B5G3L ， 07h: G3LR5,B5G3H. 08h: G6B2H,B3LR5， 09h: G6R2H,R3LB5. RGB555:0Ah: 1'b0R5G2H,G3LB5, 0Bh: G3LB5,1'b0R5G2H.0Ch: R5G3H,G2LB51'b0, 0Dh: G2LB51'b0, R5G3H.0Eh: B5G3H,G2L1'b0,R5, 0Fh: R5G3H,G2L1'b0,B5.10h: B51'b0G2H,G3LR5, 11h: R51'b0G2H,G3LB5.RGB444:12h: 4'b0R4,G4B4, 13h: G4B4,4'b0R4.14h: 4'b0B4,G4R4, 15h: G4R4,4'b0B4.16h: R4G4,B44'b0, 17h: B44'b0,R4G4.18h: B4G4,R44'b0, 19h: R44'b0,B4G4.1Ah: B4G4,R4B4, 1Bh: R4G4,B4R4.1Ch: R4G2H2'b0,G2LB42'b0, 1Dh: B4G2H2'b0,G2LR42'b0.1Eh: B41'b0G3H,G1L2'b0R41'b0, 1Fh: R41'b0G3H,G1L2'b0B41'b0.3bhY_AVER_TH 7 60h Reserved. 3chOFFSET_TH2 7 24h Reserved. 3dh COM11 8 59hCommon control 11. Bit[7:4]: Total row number2 for gate sub. Bit[3:0]: Total column number2 for gate sub.3eh TAREG2 8 03h Bit[7]:Tri-state option for output clock, HSYNC,VSYNC at power-down period.0: Tri-state at this period,1: No Tri-state at this period.Bit[6]: Tri-state option for output data OEN at power-down period.0: Tri-state at this period,1: No Tri-state at this period.Bit[5:0]: Reserved.3fh OFFSET1 8 9ah Gamma Offset 1.Bit[7]: 0: Use black average value(from Black Control function) as offset. 1: Use register OFFSET1[6:0] as offset.Bit[6:0]:OFFSET1 value.40h k0 850h Gamma Correction Slop Coefficient 0. 41h k1 850h Gamma Correction Slop Coefficient 1. 42h k2 858h Gamma Correction Slop Coefficient 2. 43h k3 855h Gamma Correction Slop Coefficient 3. 44h k4 850h Gamma Correction Slop Coefficient 4. 45h k5 849h Gamma Correction Slop Coefficient 5. 46h k68 44h Gamma Correction Slop Coefficient 6.47hk7 8 3eh Gamma Correction Slop Coefficient 7. 48hk8 8 38h Gamma Correction Slop Coefficient 8. 49h k9 8 34h Gamma Correction Slop Coefficient 9. 4ahSUBSAMPLE 7 60h Bit[6:4]:Reserved Bit[3]:Window enable. 1: Window function enable, 0: Normal output(default). Bit[2]: Subsample mode.1: Realize subsample, 0: No subsample.Bit[2:0]: 0xx: NO subsample(normal),100:4/5sub, 101:3/5sub, 110:2/3sub, 111:1/2sub.4bh k10 830h Gamma Correction Slop Coefficient 10. 4ch k11 82dh Gamma Correction Slop Coefficient 11. 4eh k12 828h Gamma Correction Slop Coefficient 12. 4fh k13 823h Gamma Correction Slop Coefficient 13. 50h k14 820h Gamma Correction Slop Coefficient 14. 51h TARGET1 801h Color Correction Coefficient 1. 52h TARGET2 80dh Color Correction Coefficient 2. 53h TARGET3 80eh Color Correction Coefficient 3. 54hTARGET4 8 0ah Color Correction Coefficient 4. 55hBRIGHT 8 00h Brightness control. Bit[7]: 0: Positive, 1: Negative. Bit[6:0] : Value. 56hY_COEF 8 40h Y Coefficient for Contrast. 57hTARGET5 8 42h Color Correction Coefficient 5. 58hTARGET6 8 4ch Color Correction Coefficient 6. 59hTARGET7 8 55h Color Correction Coefficient 7. 5ahTARGET8 8 76h Color Correction Coefficient 8. 5bh TARGET9 8 21h Color Correction Coefficient 9. 5ch TARGET 8 0eh Bit[7]: Color Correction adjustment enable, 1: Disable, 0: Enable. Bit[6:5]: Reserved. Bit[4]: Sign of Color Correction Coefficients 9.Bit[3:0]: Reserved.5dh TARGET_SIGN8 9ch Bit[7]: Sign of Color Correction Coefficients 8.Bit[6]: Sign of Color Correction Coefficients 7.Bit[5]: Sign of Color Correction Coefficients 6.Bit[4]: Sign of Color Correction Coefficients 5.Bit[3]: Sign of Color Correction Coefficients 4. Bit[2]: Sign of Color Correction Coefficients 3.Bit[1]: Sign of Color Correction Coefficients 2.Bit[0]: Sign of Color Correction Coefficients 1. 5fhDARK_AVERE 8 20h,RO DARKROW_AVER FOR EVEN COLUMN 60hGLB_GAIN_TH 8 20h Reserved. 61hMa_Th_Ctr 8 e3h Reserved. 64hDARK_AVER0 8 20h,RO Dark row average value for odd column. 65hG_COEF 8 46h Lens shading gain of G. 66hB_COEF 8 46h Lens shading gain of B. 67hMANU 8 80h Manual U value. 68h MANV 8 80h Manual V value.69h DICOM1 8 00h Dither control 1. Bit[7]: YCBCR RANGE select. 0: YCBCR 0~255, 1: Y 16~235, CBCR 16~240. Bit[6]: Negative image enable 0: Normal image, 1: Negative image Bit[5]: UV output value select. 0: Output normal value, 1: Output fixed value set in MANU and MANV.Bit[4]: U 、V dither when YCBCR mode/R 、B dither when RGB mode:0: Low 2 Bits, 1: Low 3Bits.Bit[3]: Y dither when YCBCR mode/G dither when RGB mode:0: Low 2 Bits, 1: Low 3Bits.Bit[2]:Y dither enable.Bit[1] :U 、V dither enable.Bit[0]: RGB dither enable.6ah GNGAINREG 8 81h Bit[7:3]: Reserved. Bit[2:0]: G channel Gain (Bit2~Bit0 is used as GreenGain[5:3]).6bh COM9 8 02h Common control 9.Bit[7]: 0:Use column_gate_sub for CKGATE, 1: Use HREF for CKGATE,default=0.Bit[6]: Reserved.Bit[5:4]: Average weight select, default value=00. Bit[3]: 0:Nomal, 1:CKGATE ahead 1 MCLK(YUV) or PCLK(rawdata).Bit[2]: 0:NomaL, 1:CKGATE ahead 0.5 MCLK(YUV) or PCLK(rawdata).Bit[1]: 0:No CKGATE when HREF=0, 1: Always has CKGATE.Bit[0]: 0:No gate sub, 1: Gate sub enable.6ch CLKDIV 8 10h Reserved.6fh DICOM28 20h Reserved. 70h IntCtr 8 6fh Interpolation control. Bit[7:4]: Reserved. Bit[3]:Edge enhancement switch. 0: Off, 1: On. Bit[2]: Processed rawdata output format switch. (use with 0x0c[7]=1)0: 648x488, 1:652x492,Bit[1]: ReservedBit[0]: Low pass filter switch.0: Off, 1:On.71hBpcCtr 8 a6h Reserved. 72hDenCtr 8 4fh Reserved. 73hEdgCtr 8 2fh Reserved. 74hDaECtr 8 27h Reserved. 75h DakCtr 8 0eh Reserved.76h EffCtr 8 00h Bit[7]: Special effect output on/off 0: Off, 1: On. Bit[6:4]: Special effect choice 011: Sketch, 100: Cuprum relievo, 101: Blue relievo, 110: Black relievo,111: White relievo, default: Normal relievo.Bit[3]: Sram on/off0: On, 1: Off.Bit[2:0]: Reserved.。
3706a低阻表技术参数
3706a低阻表技术参数
3706A低阻表是一款精密的电阻测量仪器，具有高精度、低阻抗、宽测量范围等特点，适用于各种电阻测量应用场景。
以下是该表的技术参数：
1.测量范围：3706A低阻表的测量范围广泛，可以测量0.1Ω到10MΩ的电阻
值。
2.测量精度：该表的测量精度非常高，可以达到±0.05%的误差范围。
这使得
该表能够满足各种高精度电阻测量需求。
3.分辨率：3706A低阻表的分辨率为0.001Ω，能够精确地测量电阻值。
4.输入阻抗：该表的输入阻抗高达10^12Ω，可以有效地降低电流测量误差，
从而提高电阻测量的准确性。
5.测试电压：3706A低阻表可提供0.1V至10V的测试电压，适用于各种不同
的电阻测量场景。
6.测试电流：该表的最大测试电流为10mA，能够满足大多数电阻测量应用的
需求。
7.显示：3706A低阻表采用大屏幕液晶显示屏，可以清晰地显示电阻值和测试
电压、电流等参数。
8.存储：该表内置存储器，可以保存最近测量过的20组数据，方便用户随时
查看和调用。
9.接口：3706A低阻表配备USB接口，可以方便地将测量数据传输到计算机或
其他设备中进行处理和分析。
10.电源：该表使用内置锂电池供电，可连续工作8小时以上，无需外接电源。
总之，3706A低阻表是一款高精度、低阻抗、宽测量范围的电阻测量仪器，适用于各种电阻测量应用场景。
其卓越的性能和广泛的应用范围使其成为电阻测量的
理想选择。
此外，该表还具有大屏幕液晶显示屏、内置存储器和USB接口等先进技术特点，使得电阻测量更加方便、快捷、准确。
datasheet
datasheetFeatures Array?12-bit Battery-cell Voltage MeasurementSimultaneous Battery Cells Measurement in ParallelCell Temperature MeasurementCharge Balancing Capability–Parallel Balancing of Cells PossibleIntegrated Power Supply for MCUUndervoltage DetectionLess than 10µA Standby CurrentLow Cell Imbalance Current (<10µA)Hot Plug-in CapableInterrupt Timer for Cycling MCU Wake-upsCost-efficient Solution Due to Cost-optimized 30V CMOS TechnologyReliable Communication between Stacked ICs Due to Level Shifters with Current Sources and Checksum Monitoring of DataDaisy-chainable–Each IC Monitors up to 6 Battery Cells–16 ICs (96 Cells) per String–No Limit on Number of StringsPackage QFN48 7mm×7mmApplicationsBattery Measurement, Supply and Monitoring IC for Li-ion and NiMH Battery Systems in Electric (EV) and Hybrid Electrical (HEV) VehiclesBenefitsHighest Safety Level for Li-ion Battery Systems in Combination with ATA6871Cost Reduction Due to Integrated Measurement Circuit and High Voltage Power-supply1.DescriptionThe ATA6870 is a measurement and monitoring circuit designed for Li-ion and NiMH multicell battery stacks in hybrid electrical vehicles.The ATA6870 monitors the battery-cell voltage and the battery-cell temperature with a 12-bit ADC.The circuit also provides charge-balancing capability for each battery-cell.In addition, a linear regulator is integrated to supply a microcontroller or other external components. Reliable communication between stacked ICs is achieved by level-shift-ers with current sources. The ATA6870 can be connected to three, four, five or six battery-cells. Up to 16 circuits (96 cells) can be cascaded in one string. The number ofstrings is not limited.29116B–AUTO–10/09ATA6870[Preliminary]2.Block DiagramFigure 2-1.Block Diagram39116B–AUTO–10/09ATA6870[Preliminary]3.Pin ConfigurationFigure 3-1.Pinning QFN48, 7mm ×7mmTable 3-1.Pin DescriptionPad Number Pad Name Function RemarkExposed PadHeatslug1DISCH5Output to drive external cell-balancing transistor 2MBA T5Battery cell sensing line3DISCH4Output to drive external cell-balancing transistor 4MBA T4Battery cell sensing line5DISCH3Output to drive external cell-balancing transistor 6MBA T3Battery cell sensing line7DISCH2Output to drive external cell-balancing transistor 8MBA T2Battery cell sensing line9DISCH1Output to drive external cell-balancing transistor 10MBA T1Battery cell sensing line11IRQ Interrupt output for MCU/A TA6870 below 12CLK System clock13CS_N Chip select input from MCU/A TA6870 below 14SCK SPI clock input from MCU/A T A6870 below 15MOSI Master Out Slave In input from MCU SPI data input 16MISO Master In Slave Out output for MCU SPI data output 17MFIRSTSelect Master/Slave49116B–AUTO–10/09ATA6870[Preliminary]18DTST T est-mode pin Keep pin open (output)19SCANMODE T est-mode pin Connected to VSSA 20CS_FUSE T est-mode pin Connected to VSSA 21VDDFUSE T est-mode pin Connected to VSSA22DVSS Digital negative supply23DVDD Digital positive supply input (3.3V)Connected to AVDD 24GND Ground 25A TST T est-mode pin Keep pin open (output)26AVDD 3.3V Regulator output 27AVSS Analog negative supply28TEMPVSS Ground for temperature measuring 29TEMP1T emperature measuring input 130TEMP2T emperature measuring input 231TEMPREF Reference voltage for temperature measuring 32BIASRES Internal supply current adjustment 33PWTST T est - mode pinKeep pin open (output)34POW_ENA Power regulator enable/disable 35PD_N_OUT Power down output36VDDHVM Power regulator output to supply e.g. an external microcontroller37VDDHVP Power regulator supply voltage 38PD_N Power down input39MISO_IN Master In Slave Out input from A T A6870 above 40MOSI_OUT Master Out Slave In output for A TA6870 above 41SCK_OUT SPI clock output for input of A T A6870 above 42CS_N_OUT Chip select output for input of A TA6870 above 43CLK_OUT System clock output for input of A TA6870 above 44IRQ_IN Interrupt input from A T A6870 above 45VDDHV Supply voltage 46MBA T7Battery cell sensing line47DISCH6Output to drive external cell-balancing transistor 48MBA T6Battery cell sensing lineTable 3-1.Pin Description (Continued)Pad NumberPad Name Function Remark59116B–AUTO–10/09ATA6870[Preliminary]4.ATA6870 System OverviewThe ATA6870 can be stacked up to 16 times in one string. The communication with MCU is car-ried out on the lowest level through an SPI bus. The data on the SPI bus is transmitted to the 15other ATA6870s using the communication interface implemented inside ATA6870.Figure 4-1.Battery Management Architecture with One Battery String69116B–AUTO–10/09ATA6870[Preliminary]Figure 4-2.Battery Management Architecture with Several Battery Strings79116B–AUTO–10/09ATA6870[Preliminary]5.Absolute Maximum RatingsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Unless otherwise specified all voltages to pin VSSA.Parameters PinSymbol Min.Max.Unit Ambient temperature T A –40+85°C Junction temperature T J –40+125°C Storage temperature T S –55+150°C Battery cell voltage MBA T(i+1), MBA T(i)V MBAT(i+1) - V MBAT(i)–0.3+5.5V V VDDHV - V VMBA T7max V VDDHV - V VMBA T7–5.5+0.3V V MBAT1MBA T1V MBAT1–0.3+0.3V Supply voltage power regulator VDDHVP V VDDHVP –0.3+33.6V Operating supply voltage VDDHV V VDDHV –0.3+30V Supply voltage DVDD (regulator is Off)DVDD V DVDD –0.3+5.5V Supply voltage AVDD (regulator is Off)AVDD V AVDD –0.3+5.5V Test-inputVDDFUSE V VDDFUSE –0.3+5.5V Reference voltage for temperature measuring (regulator is Off)TEMPREF V TEMPREF –0.3VDD+0.3V Supply voltage VDDHVM (regulator is Off)VDDHVM V VDDHVM –0.3+5.5V Digital Ground DVSS V AVSS - V GND –0.3+0.3V Analog Ground AVSS V AVSS - V GND –0.3+0.3V Digital/Analog Ground AVSS, DVSS V AVSS - V DVSS –0.3+0.3V Ground voltage for temperature measuringTEMPVSS V TEMPVSS–0.3+0.3VInput voltage for logic I/O pinsCLK, CS_N,SCK, MOSI,DTST, A TST ,SCANMODE,MFIRST ,POW_ENA,CS_FUSE,PWTST V CLK , V CS_N ,V SCK , V MOSI ,V DTST , V ATST ,V SCANMODE ,V MFIRST ,V POW_ENA ,V CS_FUSE , V PWTST–0.3VDD + 0.3VIRQ, MISOV IRQ , V MISO–0.3+5.5V Input voltage for analog I/O pinsTEMP1, TEMP2, BIASRESV TEMP1, V TEMP2,V BIASRES –0.3VDD + 0.3V Input voltage for digital high voltage input pinsMISO_IN,IRQ_IN V MISO_IN , V IRQ_INVDDHV – 0.3VDDHV + 0.3VVoltage at digital high voltage output pins MOSI_OUT, SCK_OUT , CS_N_OUT, CLK_OUT V MOSI_OUT , V SCK_OUT , V CS_N_OUT , V CLK_OUT VDDHV – 0.3VDDHV + 0.3V Input: PD_N PD_N V PD_N VDDHV – 5.5VDDHV + 0.3V Output: PD_N_OUTPD_N_OUT V PD_N_OUT –5.5+0.3V Voltage at cell balancing outputsDISCH(i)VDISCH(i)V MBA T(i) – 0.3V MBAT(i+1) + 0.3V89116B–AUTO–10/09ATA6870[Preliminary]HBM ESDANSI/ESD-STM5.1JESD22-A114AEC-Q100 (002)ESD±2kVCDM ESD STM 5.3.1500V 1, 12, 13, 24, 25, 36, 37, 48750V Latch-up acc. to AECQ100-004, JESD78ALA TCH-UP±100mA5.Absolute Maximum Ratings (Continued)Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Unless otherwise specified all voltages to pin VSSA.Parameters PinSymbolMin.Max.Unit 6.Thermal ResistanceParametersSymbolValueUnitPackage. QFN48 7×7Max. thermal resistance junction-ambient (1)R thja max 20K/W Max. thermal resistance junction-case R thjC maxTBDK/WNote:1.Package mounted on 4 large PCB (per JESD51-7) under natural convention as defined in JESD51-2.99116B–AUTO–10/09ATA6870[Preliminary]7.Circuit Description and Electrical CharacteristicsUnless otherwise specified all parameters in this section are valid for a supply voltage range of 6.9V7.1Operating ModesThe ATA6870 has two operation modes.1.Power-down Mode (PDmode)2.Normal Mode (NORM Mode)7.1.1Power-down ModeIn Power-down Mode all blocks of the IC are switched off.The circuit can be switched from Power-down to ON Mode or back via the PD_N input. If the pin is connected to VDDHV via an external optocoupler, for example, the circuit is in ON Mode. If several ATA6870 are stacked, the power-down signal must be only provided for the IC on the top level of the stack. The next lower IC receives this information from the PD_N_OUT output of its upper IC. The PD_N_OUT pin must be connected to either the PD_N pin of the next lower ATA6870 or to VSSA.109116B–AUTO–10/09ATA6870[Preliminary]Figure 7-1.Power-down119116B–AUTO–10/09ATA6870[Preliminary]7.1.2Normal Operating Mode (NORM Mode)The ATA6870 turns on when the PD_N signal is switched from low to high. The power supplies AVDD and DVDD as well as VDDHVM (if the input signal POW_ENA =high) are turned on. The configuration registers are set to their default values. In NORM Mode the ATA6870 can acquire analog data (voltage or temperature channels) upon request from the host microcontroller.When the host microcontroller orders an acquisition through the SPI bus, the IC starts digitizing all voltage and one temperature channel in parallel. The on-chip digital signal processor filters, in real time, the channel samples. Whenconversion and filtering are done, the data-ready interrupt to the host processor indicates the data availability. The MCU can now read the ADC result reg-isters. The MCU reads the ATA6870’s status registers to check each IC and to acknowledge the interrupt. When ATA6870 is in NORM Mode, the MCU can be active or in idle mode. In order to wake-up the MCU by an interrupt, the Low Frequency Timer (LFT) can be activated in ATA6870.Interrupt is signaled with a high level on IRQ pin. The LFT is re-programmable on the fly and can be reset through SPI, but is not stoppable.Figure 7-2.ATA6870 in NORM ModeTable 7-1.Electrical CharacteristicsNo.ParametersTest ConditionsPin Symbol Min.Typ.Max.Unit Type*1.1Maximum allowed input current in Power-down Mode (e.g., leakage current of an optocoupler)PD_N I PD_N 50µA A 1.2Input current in ON Mode PD_NI PD_N 2.55mA A 1.3Maximum voltage (pin PD_N left open)I PD_N =0to 50µAPD_NV VDDHV - V PD_N 5VA1.4Propagation delay time from Power-down Mode to NORM Mode min slopeDVDD t VDDON3ms A1.5Propagation delay time from NORM Mode toPower-down ModeDVDDt VDDOFF10ms A*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameterI PD_N 1 mAmsec -------------=129116B–AUTO–10/09ATA6870[Preliminary]7.2Interface to Battery CellsEach input line MBAT(i) and the supply lines VDDHV, AVSS can be protected by additional resistors and a filter capacitor as shown below.Figure 7-3.External Components between ATA6870 and the Battery CellsMBAT (i) are high impedance input (~2M Ω). Thus, external components can be added to protect ATA6870 chip against current spikes and overvoltage at battery cell level.Table 7-2.Electrical CharacteristicsNo.Parameters Test ConditionsPin Symbol Min.Typ.Max.Unit Type*2.1Supply voltage VDDHV V VDDHV 6.930V A 2.2Current consumption IVDDHV (Normal Mode)VDDHVI VDDHV15mAA2.3Current consumption in Power-down mode (PDmode) I VDDHV + I MBA T(i)max (1)V MBAT(i+1) – V MBAT(i) = 3.7VVDDHV 10µA A2.4Imbalance from battery cell to battery cell in Power-down Mode(PDN Mode)V MBAT(i+1) – V MBAT(i) = 3.7V MBA T(i+1)I MBAT(i+1)10µA A*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note:/doc/204d40240722192e4536f65b.html rgest input current of the cell inputs MBA T(i)139116B–AUTO–10/09ATA6870[Preliminary]7.3Reduced Number of Battery Cells ConfigurationIt is possible for ATA6870 to operate with a reduced number of cells: 3, 4, 5, and 6 cell operation are possible. In these cases, the cell-chip inputs corresponding to the missing cells should be connected to the upper cell potential of the module.Figure 7-4.Connection with 4 Cells onlyBattery cell 1 (MBAT1, MBAT2) and battery cell 6 (MBAT6, MBAT7) must always be used for the lowest/highest cell. Table 7-3.Electrical CharacteristicsNo.ParametersTest ConditionsPin SymbolMin.Typ.Max.Unit Type*3.1R_IN MBA T(i)1k ΩD 3.2R_VDDHV VDDHV 50ΩD 3.3R_VSSAVSS50ΩD*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter149116B–AUTO–10/09ATA6870[Preliminary]7.4ATA6870 External MCU SupplyThe ATA6870 provides a 3.3V power-supply for external components such as the microcon-troller unit (MCU). The input pin for this supply is pin VDDHVP, and the output pin is VDDHVM.This regulator is able to supply the MCU directly from the topmost battery cell of a string. The power regulators of all stacked ATA6870 are therefore put in serial configuration to avoid imbal-ance.The regulator can be disabled with the digital input pin POW_ENA.Logic levels: Low = V DVSS , High = V DVDDTable 7-4.Truth TablePin SymbolValue FunctionPOW_ENAV POW_ENALow Voltage regulator disabled HighVoltage regulator enabled159116B–AUTO–10/09ATA6870[Preliminary]Figure 7-5.MCU Supply with the Internal Power Supply169116B–AUTO–10/09ATA6870[Preliminary]Table 7-5.Electrical CharacteristicsNo.Parameters Test ConditionsPin Symbol Min.Typ.Max.Unit Type*4.1Supply voltage VDDHVP V VDDHVP 6.933.3V A 4.2Output voltage VDDHVM V VDDHVM 3.13.3 3.5V A4.3DC output current VDDHVM I VDDHVM 20mA A 4.4Peak output current (1)VDDHVM I VDDHVM50mA A 4.5Capacitor load (2)VDDHVM 3033µF D 4.6Capacitor load (2)VDDHVM 200220nF D 4.7High level input voltage POW_ENA V POW_ENA 0.7 × V DVDDV A 4.8Low level input voltage POW_ENA V POW_ENA 0.3 × V DVDDV A 4.9Hysteresis POW_ENAV POW_ENA 0.05 × V DVDD V C 4.10Input currentV POW_ENA =0V to V DVDDPOW_ENAI POW_ENA–1+1µAA*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes:1.Maximum current the power regulator can provide, time limited by thermal consideration only2.These capacitors are mandatory179116B–AUTO–10/09ATA6870[Preliminary]Figure 7-6.MCU Supply with an External Power Supply189116B–AUTO–10/09ATA6870[Preliminary]7.5Analog Blocks7.5.1Battery Voltage MeasuringFigure 7-7.Block Diagram Battery Voltage MeasurementThe battery voltage measurement block contains ?a 3-input multiplexer ?a voltage reference,?a 12-bitADCthe upper part of digital voltage level shifters7.5.1.1Input MultiplexerThe multiplexer has 3 inputs. Each of the functions are described in the table below:The multiplexer inputs are controlled by SPI.Table 7-6.Inputs of the MultiplexerInputFunctionV(MBA T (i+1), MBA T (i))Input voltage measurement V(VREF (i))Gain error acquisition of ADC V(MBA T (i), MBA T (i))Offset error acquisition of ADC199116B–AUTO–10/09ATA6870[Preliminary]7.5.1.212 Bits Incremental ADCThe purpose of this cell is to convert an analog input into a 12-bit digital word.Figure 7-8.Table 7-7.Electrical CharacteristicsNo.ParametersTest Conditions Pin SymbolMin.Typ.Max.Unit Type*5.1Accuracy of voltage channel (1)Maximum input noise 0.5mVrmsMBA T(i+1), MBA T(i)–10+10mVA5.2Accuracy of voltage channel (1)(2)Maximum input noise0.5mVrmsV MBA T(i+1) – V MBA T(i) = 3.6VMBA T(i+1),MBA T(i)–7+7mV A5.3Input voltage range MBA T(i+1), MBA T(i)V MBA T(i+1), V MBA T(i)5V A 5.4Input resolution (1 LSB)V LSB 1.5mV A 5.5Reference voltage V Ref1.667V D 5.6Offset voltage MBA T(i+1), MBA T(i)V MBA T(i+1), V MBA T(i)410LSB A 5.7Gain voltage MBA T(i+1), MBA T(i)V MBA T(i+1), V MBA T(i)655LSB/VA 5.8System clock CLK f CLK 450500550kHz D 5.9SPI interface clock SCKf SCK 0.5 × f CLKD 5.10Conversion rate (3)t conv = (212 + 1) / f CLKt conv 8.194ms D 5.11Input bandwidthMBA T(i+1), MBA T(i)f BW50HzD*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes:1.The accuracy of the voltage channels is guaranteed with no external resistor in the MBA T(i), MBA T(i+1) lines.2.Reduced temperature range (–20°C to + 65°C)3.Conversion rate without readout times of SPI。
欧美电子产品数据手册说明书
Eaton 167706Eaton Moeller series xEffect - FRCmM-NA RCCB. Residual currentcircuit breaker (RCCB), 40A, 4p, 30mA, type G/A, UL, 110VGeneral specificationsEaton Moeller series xEffect - FRCmM-NA RCCB167706FRCMM-40/4/003-G/A-NA-110401508164247280 mm71 mm70 mm0.32 kg RoHS conformUL 1053ÖVE E 8601 IEC/EN 61008 EN45545-2 IEC 61373Additionally protects against special forms of residual pulsating DC which have not been smoothed.Product Name Catalog NumberModel CodeEAN Product Length/Depth Product Height Product Width Product Weight Compliances Certifications Catalog Notes40 AIs the panel builder's responsibility. The specifications for the switchgear must be observed.7035-35 °CMeets the product standard's requirements.Is the panel builder's responsibility. The specifications for the switchgear must be observed.DIN railQuick attachment with 2 latch positions for DIN-rail IEC/EN 6071540 ADoes not apply, since the entire switchgear needs to be evaluated.0.03 A100 V AC - 210 V AC, 94 V AC - 132 V AC (UL)Meets the product standard's requirements.Short time-delayed8 ms delay at 60 Hz10 ms delay at 50 HzInterlocking device500 A eaton-rcd-application-guide-br019003en-en-us.pdfUL 1053 DIN Rail RCCBEaton's Volume 4—Circuit Protectioneaton-xeffect-industrial-switchgear-range-catalog-ca003002en-en-us.pdf eaton-xeffect-frcmm-na-rccb-catalog-ca003019en-en-us.pdfDA-DC-03_FRCmeaton-circuit-breaker-xeffect-frcmm-na-rccb-dimensions.epsMA180503312DA-CD-f9_ul1053_4pDA-CS-f9_ul1053_4pEaton Specification Sheet - 167706eaton-circuit-breaker-xeffect-frcmm-rccb-wiring-diagram-002.eps eaton-xeffect-frcmm-rccb-wiring-diagram-002.jpgRated operational current for specified heat dissipation (In) 10.11 Short-circuit ratingRAL-numberPermitted storage and transport temperature - min10.4 Clearances and creepage distances10.12 Electromagnetic compatibilityMounting MethodAmperage Rating10.2.5 LiftingRated fault current - maxTest circuit range10.2.3.1 Verification of thermal stability of enclosures Tripping timeFitted with:Rated residual making and breaking capacity Application notesBrochuresCatalogsCertification reports DrawingsInstallation instructions mCAD model Specifications and datasheets Wiring diagramsFrequency rating50 Hz / 60 Hz10.8 Connections for external conductorsIs the panel builder's responsibility.Fault current rating30 mATerminal protectionFinger and hand touch safe, DGUV VS3, EN 50274Special featuresFRCmM-NA-110Residual current circuitbreakersType G/A (ÖVE E 8601)Sensitivity typePulse-current sensitiveAmbient operating temperature - max40 °CHeat dissipation per pole, current-dependent3.275 WClimatic proofing25-55 °C / 90-95% relative humidity according to IEC 60068-2Built-in depth70.5 mmShort-circuit ratingMax. admissible back-up fuse: 63 A gG/gL, 70 A class J fuse (UL)FeaturesResidual current circuit breakerAdditional equipment possibleLifespan, electrical4000 operationsTerminal capacity (cable)M5 (with cross-recessed screw as defined in EN ISO 4757-Z2, PZ2)Connectable conductor cross section (solid-core) - min1.5 mm²Contact position indicator colorRed / green10.9.3 Impulse withstand voltageIs the panel builder's responsibility.Number of polesFour-poleTerminal capacity (solid wire)1.5 mm² - 35 mm²Ambient operating temperature - min-25 °C10.6 Incorporation of switching devices and componentsDoes not apply, since the entire switchgear needs to be evaluated.Rated short-circuit strength5 kA (UL, as per CSA)10 kA with back-up fuse10.5 Protection against electric shockDoes not apply, since the entire switchgear needs to be evaluated.Used withFRCmM-NA-110Type G/A (�VE E 8601)Residual current circuit breakersMounting positionAs requiredEquipment heat dissipation, current-dependent13.1 W10.13 Mechanical functionThe device meets the requirements, provided the information in the instruction leaflet (IL) is observed.10.2.6 Mechanical impactDoes not apply, since the entire switchgear needs to be evaluated.10.9.4 Testing of enclosures made of insulating materialIs the panel builder's responsibility.ApplicationSwitchgear for 110-V systems10.3 Degree of protection of assembliesDoes not apply, since the entire switchgear needs to be evaluated.Voltage rating (IEC/EN 60947-2)110/190 VVoltage typeACTerminal capacity (stranded cable)16 mm² (2x)Leakage current typeAFrame45 mmBuilt-in width (number of units)70 mm (4 SU)Terminals (top and bottom)Lift terminalsAmbient humdity range5 - 95 %Impulse withstand current3 kA (8/20 μs) surge-proofWidth in number of modular spacings410.2.3.2 Verification of resistance of insulating materials to normal heatMeets the product standard's requirements.10.2.3.3 Resist. of insul. mat. to abnormal heat/fire by internal elect. effectsMeets the product standard's requirements.Lifespan, mechanical10000 operationsStatus indicationWhite / blue10.9.2 Power-frequency electric strengthIs the panel builder's responsibility.Connectable conductor cross section (solid-core) - max35 mm²Degree of protectionIP20, IP40 with suitable enclosureIP20Rated short-time withstand current (Icw)10 kAOvervoltage tested - max530 VPollution degree210.7 Internal electrical circuits and connectionsIs the panel builder's responsibility.Connectable conductor cross section (multi-wired) - min 1.5 mm²Rated impulse withstand voltage (Uimp)4 kV10.10 Temperature riseThe panel builder is responsible for the temperature rise calculation. Eaton will provide heat dissipation data for the devices.FunctionsShort-time delayed trippingVoltage rating (UL)208/120 V, 60 HzConnectable conductor cross section (multi-wired) - max 16 mm²TypeCurrent test marks as perinscriptionMaximum operatingtemperature is 75 °C:Starting at 40 °C, the max.permissible continuouscurrent decreases by 2.5%for every 1 °CThe maximum operatingcurrent of back-up fuse mustnot exceed the residualcurrent circuit breaker'srated operational current10.2.2 Corrosion resistanceMeets the product standard's requirements.10.2.4 Resistance to ultra-violet (UV) radiationMeets the product standard's requirements.10.2.7 InscriptionsMeets the product standard's requirements.Eaton Corporation plc Eaton House30 Pembroke Road Dublin 4, Ireland © 2023 Eaton. All Rights Reserved. Eaton is a registered trademark.All other trademarks areproperty of their respectiveowners./socialmedia3 kA60 °C40 A gG/gL0.03 A 22 mA190 V440 VSurge current capacity Permitted storage and transport temperature - max Admissible back-up fuse overload - max Rated fault current - min Pick-up current Rated operational voltage (Ue) - max Rated insulation voltage (Ui)。
SQT-103-01-F-D;SQT-106-01-LM-D;SQT-110-03-F-D;SQT-120-01-F-S;中文规格书,Datasheet资料
SPECIFICATIONS
For complete specifications see ?SQT
Mates with: TMMH, TMM, MTMM, MMT, TW, LTMM, ZLTMM, ESQT, TCMD
Choice of one through six rows
SQT-106-01-LM-D SQT-112-01-F-D SQT-110-01-L-Q
SQT-110-03-F-D SQT-107-01-L-T SQT-125-01-F-D
(2,29) .050 .090
(2,00) .0787
–RA OPTION
(–Q, –5 & –6 not available)
/
分销商库存信息:
SAMTEC SQT-103-01-F-D SQT-120-01-F-S SQT-110-01-LM-Q SQT-116-01-S-D
TMM/ SQT TMMH
HORIZONTAL
(2,00mm) .0787" pitch
1
NO. PINS PER ROW
LEAD STYLE
(6,35mm) .250"
PLATING OPTION
ROW OPTION
Note: Some lengths, styles and options are non-standard, non-returnable.
20°C
5.5A
(2,62mm) .103" to (5,03mm) .198" Insertion Force: (Single contact only)
40°C
5A
60°C
3656;中文规格书,Datasheet资料
/
分销商库存信息:
EBM-PAPST 3656
Mass Dimensions Material of impeller Housing material Direction of air flow Direction of rotation Bearing Lifetime L10 at 40 °C Lifetime L10 at maximum temperature Connection line Motor protection Approval
Web data sheet XI · Page 2 of 4 ebm-papst St. Georgen GmbH & Co. KG · Hermann-Papst-Straße 1 · D-78112 St. Georgen · Phone +49 7724 81-0 · Fax +49 7724 81-1309 · info2@ ·
/
3656
AC axial compact fan
Product drawing
Web data sheet XI · Page 3 of 4 ebm-papst St. Georgen GmbH & Co. KG · Hermann-Papst-Straße 1 · D-78112 St. Georgen · Phone +49 7724 81-0 · Fax +49 7724 81-1309 · info2@ ·
Nominal data
Type Phase Nominal voltage Frequency Speed Power input Min. ambient temperature Max. ambient temperature Air flow Sound power level Sound pressure level VAC Hz min-1 W °C °C m3/h B dB(A) 3656 1~ 230 50 2700 12.0 -40 75 75 4.9 37
LM4766TNOPB,LM4766TFNOPB, 规格书,Datasheet 资料
LM4766LM4766 Overture Audio Power Amplifier Series Dual 40W Audio Power Amplifier with MuteLiterature Number: SNAS031E芯天下--/LM4766Overture ™Audio Power Amplifier Series Dual 40W Audio Power Amplifier with MuteGeneral DescriptionThe LM4766is a stereo audio amplifier capable of delivering typically 40W per channel with the non-isolated "T"package and 30W per channel with the isolated "TF"package of continuous average output power into an 8Ωload with less than 0.1%(THD+N).The performance of the LM4766,utilizing its Self Peak In-stantaneous Temperature (˚Ke)(SPiKe ™)Protection Cir-cuitry,places it in a class above discrete and hybrid amplifi-ers by providing an inherently,dynamically protected Safe Operating Area (SOA).SPiKe Protection means that these parts are safeguarded at the output against overvoltage,undervoltage,overloads,including thermal runaway and in-stantaneous temperature peaks.Each amplifier within the LM4766has an independent smooth transition fade-in/out mute that minimizes output pops.The IC’s extremely low noise floor at 2µV and its extremely low THD+N value of 0.06%at the rated power make the LM4766optimum for high-end stereo TVs or mini-component systems.Key Specificationsj THD+N at 1kHz at 2x 30W continuousaverage output power into 8Ω0.1%(max)j THD+N at 1kHz at continuous averageoutput power of 2x 30W into 8Ω0.009%(typ)Featuresn SPiKe Protectionn Minimal amount of external components necessary n Quiet fade-in/out mute moden Non-Isolated 15-lead TO-220package nWide Supply Range 20V -78VApplicationsn High-end stereo TVs n Component stereo n Compact stereoConnection DiagramPlastic Package10092802Top ViewNon-Isolated TO-220Package Order Number LM4766TSee NS Package Number TA15AIsolated TO-220Package Order Number LM4766TF See NS Package Number TF15BSPiKe ™Protection and Overture ™are trademarks of National Semiconductor Corporation.March 2006LM4766Overture ™Audio Power Amplifier Series Dual 40W Audio Power Amplifier with Mute©2006National Semiconductor Corporation Typical ApplicationNote:Numbers in parentheses represent pinout for amplifier B.*Optional component dependent upon specific design requirements.10092801FIGURE 1.Typical Audio Amplifier Application CircuitL M 4766 2Absolute Maximum Ratings(Notes4, 5)If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Supply Voltage|V CC|+|V EE|(No Input)78V Supply Voltage|V CC|+|V EE|(with Input)74V Common Mode Input Voltage(V CC or V EE)and|V CC|+|V EE|≤60V Differential Input Voltage60V Output Current Internally Limited Power Dissipation(Note6)62.5W ESD Susceptability(Note7)3000VJunction Temperature(Note8)150˚C Thermal ResistanceNon-Isolated T-PackageθJC1˚C/W Isolated TF-PackageθJC2˚C/W Soldering InformationT and TF Packages260˚C Storage Temperature−40˚C to+150˚COperating Ratings(Notes4,5) Temperature RangeT MIN≤T A≤T MAX−20˚C≤T A≤+85˚C Supply Voltage|V CC|+|V EE|(Note1)20V to60VElectrical Characteristics(Notes4,5)The following specifications apply for V CC=+30V,V EE=−30V,I MUTE=−0.5mA with R L=8Ωunless otherwise specified.Lim-its apply for T A=25˚C.Symbol Parameter Conditions LM4766Units(Limits)Typical Limit(Note9)(Note10)|V CC|+Power Supply Voltage GND−V EE≥9V1820V(min) |V EE|(Note11)60V(max) P O Output Power T Package,V CC=±30V,THD+N=0.1%(max),f=1kHz,f=20kHz4030W/ch(min)TF Package,V CC=±26V(Note13),THD+N=0.1%(max),3025W/ch(min) (Notes3,13)(Continuous Average)f=1kHz,f=20kHzTHD+N Total Harmonic DistortionPlus Noise T Package30W/ch,R L=8Ω,20Hz≤f≤20kHz,A V=26dB0.06%TF Package25W/ch,R L=8Ω,20Hz≤f≤20kHz,A V=26dB0.06%X talk Channel Separation f=1kHz,V O=10.9Vrms60dBSR(Note3)Slew Rate V IN=1.2Vrms,t rise=2ns95V/µs(min)I total Total Quiescent Power Both Amplifiers V CM=0V,48100mA(max) (Note2)Supply Current V O=0V,I O=0mAV OS(Note2)Input Offset Voltage V CM=0V,I O=0mA110mV(max)I B Input Bias Current V CM=0V,I O=0mA0.21µA(max)I OS Input Offset Current V CM=0V,I O=0mA0.010.2µA(max)I O Output Current Limit|V CC|=|V EE|=10V,t ON=10ms,43Apk(min)V O=0VV OD Output Dropout Voltage|V CC–V O|,V CC=20V,I O=+100mA 1.54V(max)(Note2)(Note12)|V O–V EE|,V EE=−20V,I O=−100mA 2.54V(max)LM47663Electrical Characteristics (Notes 4,5)(Continued)The following specifications apply for V CC =+30V,V EE =−30V,I MUTE =−0.5mA with R L =8Ωunless otherwise specified.Lim-its apply for T A =25˚C.SymbolParameterConditionsLM4766Units (Limits)Typical Limit (Note 9)(Note 10)PSRR Power Supply Rejection RatioV CC =30V to 10V,V EE =−30V,12585dB (min)(Note 2)V CM =0V,I O =0mAV CC =30V,V EE =−30V to −10V 11085dB (min)V CM =0V,I O =0mACMRR Common Mode Rejection Ratio V CC =50V to 10V,V EE =−10V to −50V,11075dB (min)(Note 2)V CM =20V to −20V,I O =0mAA VOL(Note 2)Open Loop Voltage Gain R L =2k Ω,∆V O =40V 11580dB (min)GBWP Gain Bandwidth Product f O =100kHz,V IN =50mVrms 82MHz (min)e IN Input NoiseIHF–A Weighting Filter 2.08µV (max)(Note 3)R IN =600Ω(Input Referred)SNR Signal-to-Noise RatioP O =1W,A–Weighted,98dB Measured at 1kHz,R S =25ΩP O =25W,A–Weighted 112dBMeasured at 1kHz,R S =25ΩA MMute AttenuationPin 6,11at 2.5V11580dB (min)Note 1:Operation is guaranteed up to 60V,however,distortion may be introduced from SPiKe Protection Circuitry if proper thermal considerations are not taken into account.Refer to the Application Information section for a complete explanation.Note 2:DC Electrical Test;Refer to Test Circuit #1.Note 3:AC Electrical Test;Refer to Test Circuit #2.Note 4:All voltages are measured with respect to the GND pins (5,10),unless otherwise specified.Note 5:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the device is functional,but do not guarantee specific performance limits.Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits.This assumes that the device is within the Operating Ratings.Specifications are not guaranteed for parameters where no limit is given,however,the typical value is a good indication of device performance.Note 6:For operating at case temperatures above 25˚C,the device must be derated based on a 150˚C maximum junction temperature and a thermal resistance of θJC =1˚C/W (junction to case)for the T package.Refer to the section Determining the Correct Heat Sink in the Application Information section.Note 7:Human body model,100pF discharged through a 1.5k Ωresistor.Note 8:The operating junction temperature maximum is 150˚C,however,the instantaneous Safe Operating Area temperature is 250˚C.Note 9:Typicals are measured at 25˚C and represent the parametric norm.Note 10:Limits are guarantees that all parts are tested in production to meet the stated values.Note 11:V EE must have at least −9V at its pin with reference to ground in order for the under-voltage protection circuitry to be disabled.In addition,the voltage differential between V CC and V EE must be greater than 14V.Note 12:The output dropout voltage,V OD ,is the supply voltage minus the clipping voltage.Refer to the Clipping Voltage vs.Supply Voltage graph in the Typical Performance Characteristics section.Note 13:When using the isolated package (TF),the θJC is 2˚C/W verses 1˚C/W for the non-isolated package (T).This increased thermal resistance from junction to case requires a lower supply voltage for decreased power dissipation within the package.Voltages higher than ±26V maybe used but will require a heat sink with less than 1˚C/W thermal resistance to avoid activating thermal shutdown during normal operation.L M 4766 4Test Circuit #1(Note 2)(DC Electrical Test Circuit)10092803Test Circuit #2(Note 3)(AC Electrical Test Circuit)10092804LM47665Bridged Amplifier Application Circuit10092805FIGURE 2.Bridged Amplifier Application CircuitL M 4766 6Single Supply Application CircuitNote:*Optional components dependent upon specific design requirements.Auxiliary Amplifier Application Circuit10092806FIGURE 3.Single Supply Amplifier Application Circuit10092807FIGURE 4.Special Audio Amplifier Application CircuitLM47667Equivalent Schematic(excluding active protection circuitry)LM4766(One Channel Only)10092808L M 4766 8External Components DescriptionComponents Functional Description1R B Prevents currents from entering the amplifier’s non-inverting input which may be passed through to the load upon power down of the system due to the low input impedance of the circuitry when the undervoltagecircuitry is off.This phenomenon occurs when the supply voltages are below1.5V.2R i Inverting input resistance to provide AC gain in conjunction with R f.3R f Feedback resistance to provide AC gain in conjunction with R i.4C i(Note14)Feedback capacitor which ensures unity gain at DC.Also creates a highpass filter with R i at f C=1/(2πR i C i).5C S Provides power supply filtering and bypassing.Refer to the Supply Bypassing application section for proper placement and selection of bypass capacitors.6R V(Note14)Acts as a volume control by setting the input voltage level.7R IN(Note14)Sets the amplifier’s input terminals DC bias point when C IN is present in the circuit.Also works with C IN to create a highpass filter at f C=1/(2πR IN C IN).Refer to Figure4.8C IN(Note14)Input capacitor which blocks the input signal’s DC offsets from being passed onto the amplifier’s inputs.9R SN(Note14)Works with C SN to stabilize the output stage by creating a pole that reduces high frequency instabilities.10C SN(Note14)Works with R SN to stabilize the output stage by creating a pole that reduces high frequency instabilities. The pole is set at f C=1/(2πR SN C SN).Refer to Figure4.11L(Note14)Provides high impedance at high frequencies so that R may decouple a highly capacitive load and reduce the Q of the series resonant circuit.Also provides a low impedance at low frequencies to short out R andpass audio signals to the load.Refer to Figure4.12R(Note14)13R A Provides DC voltage biasing for the transistor Q1in single supply operation.14C A Provides bias filtering for single supply operation.15R INP(Note14)Limits the voltage difference between the amplifier’s inputs for single supply operation.Refer to the Clicks and Pops application section for a more detailed explanation of the function of R INP.16R BI Provides input bias current for single supply operation.Refer to the Clicks and Pops application section fora more detailed explanation of the function of R BI.17R E Establishes a fixed DC current for the transistor Q1in single supply operation.This resistor stabilizes the half-supply point along with C A.18R M Mute resistance set up to allow0.5mA to be drawn from pin6or11to turn the muting function off.→RMis calculated using:R M≤(|V EE|−2.6V)/l where l≥0.5mA.Refer to the Mute Attenuation vs Mute Current curves in the Typical Performance Characteristics section.19C M Mute capacitance set up to create a large time constant for turn-on and turn-off muting.20S1Mute switch that mutes the music going into the amplifier when opened.Note14:Optional components dependent upon specific design requirements.LM47669Typical Performance CharacteristicsTHD+N vs FrequencyTHD+N vs Frequency1009285510092856THD+N vs Output Power THD+N vs Output Power1009285810092857THD+N vs Distribution THD+N vs Distribution1009287210092873L M 4766 10Typical Performance Characteristics(Continued)Channel Separation vsFrequencyClipping Voltage vs Supply Voltage1009281010092868Output Power vs Load Resustance Output Power vs Supply Voltage1009287410092878Power Dissipation vsOutput Power Power Dissipation vsOutput Power1009287610092877LM476611Typical Performance Characteristics(Continued)Max Heatsink Thermal Resistance (˚C/W)at the Specified Ambient Temperature (˚C)10092875Note:The maximum heatsink thermal resistance values,θSA ,in the table above were calculated using a θCS =0.2˚C/W due to thermal compound.Safe AreaSPiKe ProtectionResponse1009285910092860Pulse Power Limit Pulse Power Limit1009286310092864L M 4766 12Typical Performance Characteristics(Continued)Pulse Response Large Signal Response1009286610092887Power Supply Rejection RatioCommon-ModeRejection Ratio 1009288810092889Open Loop Frequency ResponseSupply Current vsCase Temperature1009289010092865LM4766 13Typical Performance Characteristics(Continued)Input Bias Current vs Case TemperatureMute Attenuation vs Mute Current (per Amplifier)1009286710092885Mute Attenuation vs Mute Current (per Amplifier)Output Power/Channel vs Supply Voltagef =1kHz,R L =4Ω,80kHz BW1009288610092891Output Power/Channel vs Supply Voltagef =1kHz,R L =6Ω,80kHz BW Output Power/Channel vs Supply Voltagef =1kHz,R L =8Ω,80kHz BW1009289210092893L M 4766 14Application InformationMUTE MODEThe muting function of the LM4766allows the user to mute the music going into the amplifier by drawing more than 0.5mA out of each mute pin on the device.This is accom-plished as shown in the Typical Application Circuit where the resistor R M is chosen with reference to your negative supply voltage and is used in conjunction with a switch.The switch when opened cuts off the current flow from pin6or11to −V EE,thus placing the LM4766into mute mode.Refer to the Mute Attenuation vs Mute Current curves in the Typical Performance Characteristics section for values of attenu-ation per current out of pins6or11.The resistance R M is calculated by the following equation:R M≤(|−V EE|−2.6V)/I pin6where I pin6=I pin11≥0.5mA.Both pins6and11can be tied together so that only one resistor and capacitor are required for the mute function.The mute resistance must be chosen such that greater than1mA is pulled through the resistor R M so that each amplifier is fully pulled out of mute mode.Taking into account supply line fluctuations,it is a good idea to pull out1mA per mute pin or 2mA total if both pins are tied together.UNDER-VOLTAGE PROTECTIONUpon system power-up,the under-voltage protection cir-cuitry allows the power supplies and their corresponding capacitors to come up close to their full values before turning on the LM4766such that no DC output spikes occur.Upon turn-off,the output of the LM4766is brought to ground before the power supplies such that no transients occur at power-down.OVER-VOLTAGE PROTECTIONThe LM4766contains over-voltage protection circuitry that limits the output current to approximately4.0A PK while also providing voltage clamping,though not through internal clamping diodes.The clamping effect is quite the same, however,the output transistors are designed to work alter-nately by sinking large current spikes.SPiKe PROTECTIONThe LM4766is protected from instantaneous peak-temperature stressing of the power transistor array.The Safe Operating graph in the Typical Performance Characteris-tics section shows the area of device operation where SPiKe Protection Circuitry is not enabled.The waveform to the right of the SOA graph exemplifies how the dynamic protection will cause waveform distortion when enabled. Please refer to AN-898for more detailed information. THERMAL PROTECTIONThe LM4766has a sophisticated thermal protection scheme to prevent long-term thermal stress of the device.When the temperature on the die reaches165˚C,the LM4766shuts down.It starts operating again when the die temperature drops to about155˚C,but if the temperature again begins to rise,shutdown will occur again at165˚C.Therefore,the device is allowed to heat up to a relatively high temperature if the fault condition is temporary,but a sustained fault will cause the device to cycle in a Schmitt Trigger fashion be-tween the thermal shutdown temperature limits of165˚C and155˚C.This greatly reduces the stress imposed on the IC bythermal cycling,which in turn improves its reliability undersustained fault conditions.Since the die temperature is directly dependent upon theheat sink used,the heat sink should be chosen such thatthermal shutdown will not be reached during normal opera-ing the best heat sink possible within the cost andspace constraints of the system will improve the long-termreliability of any power semiconductor device,as discussedin the Determining the Correct Heat Sink Section.DETERMlNlNG MAXIMUM POWER DISSIPATIONPower dissipation within the integrated circuit package is avery important parameter requiring a thorough understand-ing if optimum power output is to be obtained.An incorrectmaximum power dissipation calculation may result in inad-equate heat sinking causing thermal shutdown and thuslimiting the output power.Equation(1)exemplifies the theoretical maximum powerdissipation point of each amplifier where V CC is the totalsupply voltage.P DMAX=V CC2/2π2R L(1) Thus by knowing the total supply voltage and rated outputload,the maximum power dissipation point can be calcu-lated.The package dissipation is twice the number whichresults from Equation(1)since there are two amplifiers ineach LM4766.Refer to the graphs of Power Dissipationversus Output Power in the Typical Performance Charac-teristics section which show the actual full range of powerdissipation not just the maximum theoretical point that re-sults from Equation(1).DETERMINING THE CORRECT HEAT SINKThe choice of a heat sink for a high-power audio amplifier ismade entirely to keep the die temperature at a level suchthat the thermal protection circuitry does not operate undernormal circumstances.The thermal resistance from the die(junction)to the outsideair(ambient)is a combination of three thermal resistances,θJC,θCS,andθSA.In addition,the thermal resistance,θJC(junction to case),of the LM4766T is1˚C/ing Thermal-loy Thermacote thermal compound,the thermal resistance,θCS(case to sink),is about0.2˚C/W.Since convection heatflow(power dissipation)is analogous to current flow,thermalresistance is analogous to electrical resistance,and tem-perature drops are analogous to voltage drops,the powerdissipation out of the LM4766is equal to the following:P DMAX=(T JMAX−T AMB)/θJA(2) where T JMAX=150˚C,T AMB is the system ambient tempera-ture andθJA=θJC+θCS+θSA.10092852Once the maximum package power dissipation has beencalculated using Equation(1),the maximum thermal resis-tance,θSA,(heat sink to ambient)in˚C/W for a heat sink canbe calculated.This calculation is made using Equation(3)which is derived by solving forθSA in Equation(2).θSA=[(T JMAX−T AMB)−P DMAX(θJC+θCS)]/P DMAX(3)LM476615Application Information(Continued)Again it must be noted that the value of θSA is dependent upon the system designer’s amplifier requirements.If the ambient temperature that the audio amplifier is to be working under is higher than 25˚C,then the thermal resistance for the heat sink,given all other things are equal,will need to be smaller.SUPPLY BYPASSINGThe LM4766has excellent power supply rejection and does not require a regulated supply.However,to improve system performance as well as eliminate possible oscillations,the LM4766should have its supply leads bypassed with low-inductance capacitors having short leads that are located close to the package terminals.Inadequate power supply bypassing will manifest itself by a low frequency oscillation known as “motorboating”or by high frequency instabilities.These instabilities can be eliminated through multiple by-passing utilizing a large tantalum or electrolytic capacitor (10µF or larger)which is used to absorb low frequency variations and a small ceramic capacitor (0.1µF)to prevent any high frequency feedback through the power supply lines.If adequate bypassing is not provided,the current in the supply leads which is a rectified component of the load current may be fed back into internal circuitry.This signal causes distortion at high frequencies requiring that the sup-plies be bypassed at the package terminals with an electro-lytic capacitor of 470µF or more.BRIDGED AMPLIFIER APPLICATIONThe LM4766has two operational amplifiers internally,allow-ing for a few different amplifier configurations.One of these configurations is referred to as “bridged mode”and involves driving the load differentially through the LM4766’s outputs.This configuration is shown in Figure 2.Bridged mode op-eration is different from the classical single-ended amplifier configuration where one side of its load is connected to ground.A bridge amplifier design has a distinct advantage over the single-ended configuration,as it provides differential drive to the load,thus doubling output swing for a specified supply voltage.Consequently,theoretically four times the output power is possible as compared to a single-ended amplifier under the same conditions.This increase in attainable output power assumes that the amplifier is not current limited or clipped.A direct consequence of the increased power delivered to the load by a bridge amplifier is an increase in internal power dissipation.For each operational amplifier in a bridge con-figuration,the internal power dissipation will increase by a factor of two over the single ended dissipation.Thus,for an audio power amplifier such as the LM4766,which has two operational amplifiers in one package,the package dissipa-tion will increase by a factor of four.To calculate the LM4766’s maximum power dissipation point for a bridged load,multiply Equation (1)by a factor of four.This value of P DMAX can be used to calculate the correct size heat sink for a bridged amplifier application.Since the inter-nal dissipation for a given power supply and load is in-creased by using bridged-mode,the heatsink’s θSA will have to decrease accordingly as shown by Equation (3).Refer to the section,Determining the Correct Heat Sink,for a more detailed discussion of proper heat sinking for a given appli-cation.SINGLE-SUPPLY AMPLIFIER APPLICATIONThe typical application of the LM4766is a split supply am-plifier.But as shown in Figure 3,the LM4766can also be used in a single power supply configuration.This involves using some external components to create a half-supply bias which is used as the reference for the inputs and outputs.Thus,the signal will swing around half-supply much like it swings around ground in a split-supply application.Along with proper circuit biasing,a few other considerations must be accounted for to take advantage of all of the LM4766functions,like the mute function.CLICKS AND POPSIn the typical application of the LM4766as a split-supply audio power amplifier,the IC exhibits excellent “click”and “pop”performance when utilizing the mute mode.In addition,the device employs Under-Voltage Protection,which elimi-nates unwanted power-up and power-down transients.The basis for these functions are a stable and constant half-supply potential.In a split-supply application,ground is the stable half-supply potential.But in a single-supply applica-tion,the half-supply needs to charge up just like the supply rail,V CC .This makes the task of attaining a clickless and popless turn-on more challenging.Any uneven charging of the amplifier inputs will result in output clicks and pops due to the differential input topology of the LM4766.To achieve a transient free power-up and power-down,the voltage seen at the input terminals should be ideally the same.Such a signal will be common-mode in nature,and will be rejected by the LM4766.In Figure 3,the resistor R INP serves to keep the inputs at the same potential by limiting the voltage difference possible between the two nodes.This should significantly reduce any type of turn-on pop,due to an uneven charging of the amplifier inputs.This charging is based on a specific application loading and thus,the system designer may need to adjust these values for optimal perfor-mance.As shown in Figure 3,the resistors labeled R BI help bias up the LM4766off the half-supply node at the emitter of the 2N3904.But due to the input and output coupling capacitors in the circuit,along with the negative feedback,there are two different values of R BI ,namely 10k Ωand 200k Ω.These resistors bring up the inputs at the same rate resulting in a popless turn-on.Adjusting these resistors values slightly may reduce pops resulting from power supplies that ramp extremely quick or exhibit overshoot during system turn-on.L M 4766 16Application Information(Continued)AUDIO POWER AMPLlFIER DESIGNDesign a30W/8ΩAudio AmplifierGiven:Power Output30WrmsLoad Impedance8ΩInput Level1Vrms(max)Input Impedance47kΩBandwidth20Hz−20kHz±0.25dBA designer must first determine the power supply require-ments in terms of both voltage and current needed to obtainthe specified output power.V OPEAK can be determined fromEquation(4)and I OPEAK from Equation(5).(4)(5)To determine the maximum supply voltage the followingconditions must be considered.Add the dropout voltage tothe peak output swing V OPEAK,to get the supply rail at acurrent of I OPEAK.The regulation of the supply determinesthe unloaded voltage which is usually about15%higher.Thesupply voltage will also rise10%during high line conditions.Therefore the maximum supply voltage is obtained from thefollowing equation.Max supplies≈±(V OPEAK+V OD)(1+regulation)(1.1)For30W of output power into an8Ωload,the requiredV OPEAK is21.91V.A minimum supply rail of25.4V resultsfrom adding V OPEAK and V OD.With regulation,the maximumsupplies are±32V and the required I OPEAK is2.74A fromEquation(5).It should be noted that for a dual30W amplifierinto an8Ωload the I OPEAK drawn from the supplies is twice2.74A PK or5.48A PK.At this point it is a good idea to checkthe Power Output vs Supply Voltage to ensure that therequired output power is obtainable from the device whilemaintaining low THD+N.In addition,the designer shouldverify that with the required power supply voltage and loadimpedance,that the required heatsink valueθSA is feasiblegiven system cost and size constraints.Once the heatsinkissues have been addressed,the required gain can be de-termined from Equation(6).(6)From Equation(6),the minimum A V is:A V≥15.5.By selecting a gain of21,and with a feedback resistor,R f=20kΩ,the value of R i follows from Equation(7).R i=R f(A V−1)(7)Thus with R i=1kΩa non-inverting gain of21will result.Since the desired input impedance was47kΩ,a value of47kΩwas selected for R IN.The final design step is toaddress the bandwidth requirements which must be statedas a pair of−3dB frequency points.Five times away from a−3dB point is0.17dB down from passband response whichis better than the required±0.25dB specified.This fact re-sults in a low and high frequency pole of4Hz and100kHzrespectively.As stated in the External Components sec-tion,R i in conjunction with C i create a high-pass filter.C i≥1/(2π*1kΩ*4Hz)=39.8µF;use39µF.The high frequency pole is determined by the product of thedesired high frequency pole,f H,and the gain,A V.With aA V=21and f H=100kHz,the resulting GBWP is2.1MHz,which is less than the guaranteed minimum GBWP of theLM4766of8MHz.This will ensure that the high frequencyresponse of the amplifier will be no worse than0.17dB downat20kHz which is well within the bandwidth requirements ofthe design.LM476617。
CPC3703CTR;中文规格书,Datasheet资料
N-Channel Depletion-Mode Vertical DMOS FET
V(BR)DSX / V(BR)DGX 250V RDS(on) (max) 4 IDSS (min) 360mA Package SOT-89
Description
The CPC3703 is an N-channel, depletion mode, field effect transistor (FET) that utilizes Clare’s proprietary third-generation vertical DMOS process. The third-generation process realizes world class, high voltage MOSFET performance in an economical silicon gate process. Our vertical DMOS process yields a robust device, with high input impedance, for use in high-power applications. The CPC3703 is a highly reliable device that has been used extensively in Clare’s Solid State Relays for industrial and telecommunications applications. This device excels in power applications that require low drain-source resistance, particularly in cold environments such as automotive ignition modules. The CPC3703 offers a low, 4 maximum, on-state resistance at 25ºC. The CPC3703 has a minimum breakdown voltage of 250V, and is available in an SOT-89 package. As with all MOS devices, the FET structure prevents thermal runaway and thermal-induced secondary breakdown.
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V alox* Resin 3706A mericas: COMMERCIALImpact modified PBT+PC resin. Outdoor enclosure. Not available in all colors.T YPICAL PROPERTIES ¹TYPICAL VALUE UNIT STANDARDM ECHANICALT ensile Stress, yld, Type I, 50 mm/min 48M Pa A STM D 638T ensile Stress, brk, Type I, 50 mm/min 39M Pa A STM D 638T ensile Strain, yld, Type I, 50 mm/min 6%A STM D 638T ensile Strain, brk, Type I, 50 mm/min 50%A STM D 638T ensile Modulus, 50 mm/min1960M Pa A STM D 638F lexural Stress, yld, 1.3 mm/min, 50 mm span 78M Pa A STM D 790F lexural Modulus, 1.3 mm/min, 50 mm span1990M Pa A STM D 790I MPACTIzod Impact, notched, 23°C667J /m A STM D 256 Instrumented Impact Total Energy, 23°C49J A STM D 3763T HERMALV icat Softening Temp, Rate B/50135°C A STM D 1525H DT, 0.45 MPa, 3.2 mm, unannealed 126°C A STM D 648H DT, 1.82 MPa, 3.2mm, unannealed 85°C A STM D 648 CTE, -40°C to 40°C, flow 7.92E-051/°C A STM E 831 CTE, -40°C to 40°C, xflow 8.64E-051/°C A STM E 831R elative Temp Index, Elec100°C U L 746B R elative Temp Index, Mech w/impact 85°C U L 746B R elative Temp Index, Mech w/o impact100°C U L 746B P HYSICALS pecific Gravity1.3-A STM D 792M old Shrinkage, flow, 3.2 mm 1.2 - 1.4%G E Method M old Shrinkage, xflow, 3.2 mm 1.2 - 1.4%G E Method Melt Flow Rate, 260°C/5.0 kgf 23g /10 min A STM D 1238 Melt Flow Rate, 266°C/5.0 kgf23g /10 min A STM D 1238E LECTRICALA rc Resistance, Tungsten {PLC}6P LC Code A STM D 495H ot Wire Ignition {PLC)2P LC Code U L 746A H igh Voltage Arc Track Rate {PLC}4P LC Code U L 746A H igh Ampere Arc Ign, surface {PLC}0P LC Code U L 746A C omparative Tracking Index (UL) {PLC}2P LC Code U L 746A F LAME CHARACTERISTICSU L Recognized, 94V-0 Flame Class Rating (3)1.49m m U L 94U L Recognized, 94-5VA Rating (3)2.48m mU L 94Source, GMD, Last Update:08/04/2005PLEASE CONTACT YOUR LOCAL SALES OFFICE FOR AVAILABILITY IN YOUR AREA DISCLAIMER : THE MATERIALS AND PRODUCTS OF THE BUSINESSES MAKING UP THE GE PLASTICS UNIT OF GENERAL ELECTRIC COMPANY, ITS SUBSIDIARIES AND AFFILIATES ("GEP"), ARE SOLD SUBJECT TO GEP' S STANDARD CONDITIONS OF SALE, WHICH ARE INCLUDED IN THE APPLICABLE DISTRIBUTOR OR OTHER SALES AGREEMENT, PRINTED ON THE BACK OF ORDER ACKNOWLEDGMENTS AND INVOICES, AND AVAILABLE UPON REQUEST. ALTHOUGH ANY INFORMATION, RECOMMENDATIONS, OR ADVICE CONTAINED HEREIN IS GIVEN IN GOOD FAITH, GEP MAKES NO WARRANTY OR GUARANTEE, EXPRESS OR IMPLIED, (I) THAT THE RESULTS DESCRIBED HEREIN WILL BE OBTAINED UNDER END-USECONDITIONS, OR (II) AS TO THE EFFECTIVENESS OR SAFETY OF ANY DESIGN INCORPORATING GEP MATERIALS, PRODUCTS, RECOMMENDATIONS OR ADVICE. EXCEPT AS PROVIDED IN GEP' S STANDARD CONDITIONS OF SALE, GEP AND ITS REPRESENTATIVES SHALL IN NO EVENT BE RESPONSIBLE FOR ANY LOSS RESULTING FROM ANY USE OF ITS MATERIALS OR PRODUCTS DESCRIBED HEREIN.Each user bears full responsibility for making its own determination as to the suitability of GEP' s materials, products, recommendations, or advice for its own particular use. Each user must identify and perform all tests and analyses necessary to assure that its finished parts incorporating GEP materials or products will be safe and suitable for use under end-use conditions. Nothing in this or any other document, nor any oral recommendation or advice, shall be deemed to alter, vary, supersede, or waive any provision of GEP' s Standard Conditions of Sale or this Disclaimer, unless any such modification is specifically agreed to in a writing signed by GEP. No statement contained herein concerning a possible or suggested use of any material, product or design is intended, or should be construed, to grant any license under any patent or other intellectual property right of General Electric Company or any of its subsidiaries or affiliates covering such use or design, or as a recommendation for the use of such material, product or design in the infringement of any patent or other intellectual property right 1) T ypical values only. Variations within normal tolerances are possible for variose colours.All values are measured at least after 48 hours s torage at 230C/50% relative humidity.All properties, expect the melt volume rate are measured on injection m oulded samples.All samples are prepared according to ISO 294.2) O nly typical data for material selection purpose.Not to be used for p art or tool design.3) T his rating is not intended to reflect hazards presented by this or any o ther material under actual fire conditions.4) O wn measurement according to UL.V alox* Resin 3706A mericas: COMMERCIALT YPICAL PROPERTIES ¹TYPICAL VALUE UNIT STANDARDF LAME CHARACTERISTICSU L Recognized, 94-5VA Rating (3)2.48m mU L 94PLEASE CONTACT YOUR LOCAL SALES OFFICE FOR AVAILABILITY IN YOUR AREA DISCLAIMER : THE MATERIALS AND PRODUCTS OF THE BUSINESSES MAKING UP THE GE PLASTICS UNIT OF GENERAL Source, GMD, Last Update:08/04/2005ELECTRIC COMPANY, ITS SUBSIDIARIES AND AFFILIATES ("GEP"), ARE SOLD SUBJECT TO GEP' S STANDARD CONDITIONS OF SALE, WHICH ARE INCLUDED IN THE APPLICABLE DISTRIBUTOR OR OTHER SALES AGREEMENT, PRINTED ON THE BACK OF ORDER ACKNOWLEDGMENTS AND INVOICES, AND AVAILABLE UPON REQUEST. ALTHOUGH ANY INFORMATION, RECOMMENDATIONS, OR ADVICE CONTAINED HEREIN IS GIVEN IN GOOD FAITH, GEP MAKES NO WARRANTY OR GUARANTEE, EXPRESS OR IMPLIED, (I) THAT THE RESULTS DESCRIBED HEREIN WILL BE OBTAINED UNDER END-USECONDITIONS, OR (II) AS TO THE EFFECTIVENESS OR SAFETY OF ANY DESIGN INCORPORATING GEP MATERIALS, PRODUCTS, RECOMMENDATIONS OR ADVICE. EXCEPT AS PROVIDED IN GEP' S STANDARD CONDITIONS OF SALE, GEP AND ITS REPRESENTATIVES SHALL IN NO EVENT BE RESPONSIBLE FOR ANY LOSS RESULTING FROM ANY USE OF ITS MATERIALS OR PRODUCTS DESCRIBED HEREIN.Each user bears full responsibility for making its own determination as to the suitability of GEP' s materials, products, recommendations, or advice for its own particular use. Each user must identify and perform all tests and analyses necessary to assure that its finished parts incorporating GEP materials or products will be safe and suitable for use under end-use conditions. Nothing in this or any other document, nor any oral recommendation or advice, shall be deemed to alter, vary, supersede, or waive any provision of GEP' s Standard Conditions of Sale or this Disclaimer, unless any such modification is specifically agreed to in a writing signed by GEP. No statement contained herein concerning a possible or suggested use of any material, product or design is intended, or should be construed, to grant any license under any patent or other intellectual property right of General Electric Company or any of its subsidiaries or affiliates covering such use or design, or as a recommendation for the use of such material, product or design in the infringement of any patent or other intellectual property right 1) T ypical values only. Variations within normal tolerances are possible for variose colours.All values are measured at least after 48 hours s torage at 230C/50% relative humidity.All properties, expect the melt volume rate are measured on injection m oulded samples.All samples are prepared according to ISO 294.2) O nly typical data for material selection purpose.Not to be used for p art or tool design.3) T his rating is not intended to reflect hazards presented by this or any o ther material under actual fire conditions.4) O wn measurement according to UL.V alox* Resin 3706A mericas: COMMERCIALP ROCESSING PARAMETERSTYPICAL VALUE UNITI njection MoldingD rying Temperature 120°C D rying Time3 - 4h rs D rying Time (Cumulative)12h rs M aximum Moisture Content 0.02%M elt Temperature 250 - 265°C N ozzle Temperature245 - 260°C F ront - Zone 3 Temperature 250 - 265°C M iddle - Zone 2 Temperature 245 - 260°C R ear - Zone 1 Temperature 240 - 255°C M old Temperature 65 - 90°C B ack Pressure 0.3 - 0.7M Pa S crew Speed50 - 80r pm S hot to Cylinder Size 40 - 80%V ent Depth0.025 - 0.038m mSource, GMD, Last Update:08/04/2005PLEASE CONTACT YOUR LOCAL SALES OFFICE FOR AVAILABILITY IN YOUR AREA DISCLAIMER : THE MATERIALS AND PRODUCTS OF THE BUSINESSES MAKING UP THE GE PLASTICS UNIT OF GENERAL ELECTRIC COMPANY, ITS SUBSIDIARIES AND AFFILIATES ("GEP"), ARE SOLD SUBJECT TO GEP' S STANDARD CONDITIONS OF SALE, WHICH ARE INCLUDED IN THE APPLICABLE DISTRIBUTOR OR OTHER SALES AGREEMENT, PRINTED ON THE BACK OF ORDER ACKNOWLEDGMENTS AND INVOICES, AND AVAILABLE UPON REQUEST. ALTHOUGH ANY INFORMATION, RECOMMENDATIONS, OR ADVICE CONTAINED HEREIN IS GIVEN IN GOOD FAITH, GEP MAKES NO WARRANTY OR GUARANTEE, EXPRESS OR IMPLIED, (I) THAT THE RESULTS DESCRIBED HEREIN WILL BE OBTAINED UNDER END-USECONDITIONS, OR (II) AS TO THE EFFECTIVENESS OR SAFETY OF ANY DESIGN INCORPORATING GEP MATERIALS, PRODUCTS, RECOMMENDATIONS OR ADVICE. EXCEPT AS PROVIDED IN GEP' S STANDARD CONDITIONS OF SALE, GEP AND ITS REPRESENTATIVES SHALL IN NO EVENT BE RESPONSIBLE FOR ANY LOSS RESULTING FROM ANY USE OF ITS MATERIALS OR PRODUCTS DESCRIBED HEREIN.Each user bears full responsibility for making its own determination as to the suitability of GEP' s materials, products, recommendations, or advice for its own particular use. Each user must identify and perform all tests and analyses necessary to assure that its finished parts incorporating GEP materials or products will be safe and suitable for use under end-use conditions. Nothing in this or any other document, nor any oral recommendation or advice, shall be deemed to alter, vary, supersede, or waive any provision of GEP' s Standard Conditions of Sale or this Disclaimer, unless any such modification is specifically agreed to in a writing signed by GEP. No statement contained herein concerning a possible or suggested use of any material, product or design is intended, or should be construed, to grant any license under any patent or other intellectual property right of General Electric Company or any of its subsidiaries or affiliates covering such use or design, or as a recommendation for the use of such material, product or design in the infringement of any patent or other intellectual property right 1) T ypical values only. Variations within normal tolerances are possible for variose colours.All values are measured at least after 48 hours s torage at 230C/50% relative humidity.All properties, expect the melt volume rate are measured on injection m oulded samples.All samples are prepared according to ISO 294.2) O nly typical data for material selection purpose.Not to be used for p art or tool design.3) T his rating is not intended to reflect hazards presented by this or any o ther material under actual fire conditions.4) O wn measurement according to UL.。