CAT24C323中文资料
串行eepromat24cxx芯片资料
串行EEPROM AT24CXX芯片资料AT24CXX是美国ATMEL公司的低功耗CMOS串行EEPROM，典型的型号有AT24C01A/02/04/08/16等5种，它们的存储容量分别是1024/2048/4096/8192/16384位；也就是128/256/512/1024/2048字节；使用电压级别有5V，2.7V,2.5V,1.8V;本文主要介绍常用的AT24C02即256字节存储器的使用；它具有工作电压宽（2.5～5.5V）、擦写次数多（大于10000次）、写入速度快（小于10ms）等特点。
外行如图：AT24C02的1、2、3脚是三条地址线，用于确定芯片的硬件地址（实验板中直接接地只有一块器件）；第8脚和第4脚分别为正、负电源。
第5脚SDA为串行数据输入/输出，数据通过这条双向I2C总线串行传送，SDA和SCL 都需要和正电源间各接一个5.1K的电阻上拉。
第7脚为WP写保护端，接地时允许芯片执行一般的读写操作。
接电源端时不允许对器件写。
24C02中带有片内地址寄存器。
每写入或读出一个数据字节后，该地址寄存器自动加1，以实现对下一个存储单元的读写。
所有字节均以单一操作方式读取。
为降低总的写入时间，一次操作可写入多达8个字节的数据。
;这是将0100H地址中以下的8个数据写到24C02的01H为首址单元中去的汇编程序可直接在实验板上实验。
ORG 0000HSCL BIT P3.7;定义24C02的串行时钟线SDA BIT P3.6;定义24C02的串行数据线LJMP STARTSTART:LCALL STAR;调用MOV R2,#08H;一个数据有8位MOV DPTR,#0100H;定义源数据的位置LOOP:MOV A,#00HMOVC A,@A+DPTRLCALL SDATALCALL ACKJC LOOPINC DPTRDJNZ R2,LOOPLCALL STOP;调用停止子程序STAR:SETB SDASETB SCLNOPNOPNOPNOPCLR SDANOPNOPNOPNOPCLR SCLRETSDATA:MOV R0,#08HLOOP0:RLC AMOV SDA,CNOPNOPSETB SCLNOPNOPNOPCLR SCLDJNZ R0,LOOP0 RETACK:SETB SDA NOPNOPSETB SCL NOPNOPNOPNOPMOV C,SDA CLR SCLRETSTOP:CLR SDA NOPNOPNOPNOPSETB SCL NOPNOPNOPNOPSETB SDANOPNOPNOPRETORG 0100HDB 0A0H,10H,01H,02H,03H,04H,05H,06HEND读写子程序如下：;写串行E2PROM子程序XEPR; R3=10100000（命令1010+器件3位地址+读/写。
CAV24C32WE-GT3;CAV24C32YE-GT3;中文规格书,Datasheet资料
CAV24C3232-Kb I2C CMOS Serial EEPROMDescriptionThe CA V24C32 is a 32−Kb CMOS Serial EEPROM devices, internally organized as 4096 words of 8 bits each.It features a 32−byte page write buffer and supports the Standard (100kHz) and Fast (400 kHz) I2C protocol.External address pins make it possible to address up to eight CA V24C32 devices on the same bus.Features•Automotive Temperature Grade 1 (−40°C to +125°C)•Supports Standard and Fast I2C Protocol•2.5 V to 5.5 V Supply V oltage Range•32−Byte Page Write Buffer•Hardware Write Protection for Entire Memory•CA V Prefix for Automotive and Other Applications Requiring Site and Change Control•Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA)•Low Power CMOS Technology•1,000,000 Program/Erase Cycles•100 Year Data Retention•SOIC, TSSOP 8−lead Packages•This Device is Pb−Free, Halogen Free/BFR Free, and RoHS CompliantFigure 1. Functional Symbol SDASCL WPV CC SSA2, A1, APIN CONFIGURATIONSSDAWPV CCV SSA2A1A01See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet.ORDERING INFORMATIONSOIC−8W SUFFIXCASE 751BDSCLSOIC (W), TSSOP (Y)TSSOP−8Y SUFFIXCASE 948ALFor the location of Pin 1, please consult thecorresponding package drawing.Device Address Input A0, A1, A2Serial Data Input/OutputSDASerial Clock InputSCLWrite Protect InputWPPower SupplyV CCGroundV SSFunctionPin NamePIN FUNCTIONDEVICE MARKINGS(SOIC−8) (TSSOP−8)C32FAYMXXXC32F= Specific Device CodeA= Assembly LocationY= Production Year (Last Digit)M= Production Month (1-9, O, N, D)XXX= Last Three Digits of Assembly Lot Number G= Pb−Free Package 24C32F= Specific Device CodeA= Assembly LocationY= Production Year (Last Digit)M= Production Month (1-9, O, N, D)XXX= Last Three Digits of Assembly Lot Number G= Pb−Free Package24C32FAYMXXXGGTable 1. ABSOLUTE MAXIMUM RATINGSParameters Ratings Units Storage Temperature–65 to +150°C Voltage on any Pin with Respect to Ground (Note 1)–0.5 to +6.5V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.1.During input transitions, voltage undershoot on any pin should not exceed −1 V for more than 20 ns. Voltage overshoot on pins A0, A1, A2and WP should not exceed V CC + 1 V for more than 20 ns, while voltage on the I2C bus pins, SCL and SDA, should not exceed the absolute maximum ratings, irrespective of V CC.Table 2. RELIABILITY CHARACTERISTICS (Note 2)Symbol Parameter Min UnitsN END (Note 3)Endurance1,000,000Program/Erase Cycles T DR Data Retention100Years2.These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100and JEDEC test methods.3.Page Mode, V CC = 5 V, 25°C.Table 3. D.C. OPERATING CHARACTERISTICS (V CC = 2.5 V to 5.5 V, T A = −40°C to +125°C, unless otherwise specified.) Symbol Parameter Test Conditions Min Max UnitsI CCR Read Current Read, f SCL = 400 kHz1mAI CCW Write Current Write, f SCL = 400 kHz2mAI SB Standby Current All I/O Pins at GND or V CC T A = −40°C to +125°C5m AI L I/O Pin Leakage Pin at GND or V CC2m AV IL Input Low Voltage−0.50.3 x V CC V V IH Input High Voltage A0, A1, A2 and WP0.7 x V CC V CC + 0.5VSCL and SDA0.7 x V CC 5.5 V OL Output Low Voltage V CC > 2.5 V, I OL = 3 mA0.4VTable 4. PIN IMPEDANCE CHARACTERISTICS (V CC = 2.5 V to 5.5 V, T A = −40°C to +125°C, unless otherwise specified.) Symbol Parameter Conditions Max Units C IN (Note 4)SDA I/O Pin Capacitance V IN = 0 V, T A = 25°C, V CC = 5.0 V8pF C IN (Note 4)Input Capacitance (other pins)V IN = 0 V, T A = 25°C, V CC = 5.0 V6pF I WP (Note 5)WP Input Current V IN< V IH, V CC = 5.5 V130m AV IN < V IH, V CC = 3.3 V120V IN < V IH, V CC = 2.5 V80V IN < V IH2I A (Note 5)Address Input Current(A0, A1, A2)Product Rev F V IN< V IH, V CC = 5.5 V50m A V IN < V IH, V CC = 3.3 V35V IN < V IH, V CC = 2.5 V25V IN > V IH24.These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100and JEDEC test methods.5.When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relativelystrong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. T o conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V CC), the strong pull−down reverts to a weak current source.Table 5. A.C. CHARACTERISTICS (V CC = 2.5 V to 5.5 V, T A = −40°C to +125°C, unless otherwise specified.) (Note 6)Symbol ParameterStandard FastUnits Min Max Min MaxF SCL Clock Frequency100400kHzt HD:STA START Condition Hold Time40.6m s t LOW Low Period of SCL Clock 4.7 1.3m s t HIGH High Period of SCL Clock40.6m s t SU:STA START Condition Setup Time 4.70.6m s t HD:DAT Data In Hold Time00m s t SU:DAT Data In Setup Time250100ns t R SDA and SCL Rise Time1000300ns t F (Note 6)SDA and SCL Fall Time300300ns t SU:STO STOP Condition Setup Time40.6m s t BUF Bus Free Time Between STOP and START 4.7 1.3m s t AA SCL Low to Data Out Valid 3.50.9m s t DH Data Out Hold Time100100ns T i (Note 6)Noise Pulse Filtered at SCL and SDA Inputs100100ns t SU:WP WP Setup Time00m s t HD:WP WP Hold Time 2.5 2.5m s t WR Write Cycle Time55ms t PU (Notes 7, 8)Power−up to Ready Mode11ms6.Test conditions according to “AC Test Conditions” table.7.Tested initially and after a design or process change that affects this parameter.8.t PU is the delay between the time V CC is stable and the device is ready to accept commands.Table 6. A.C. TEST CONDITIONSInput Drive Levels0.2 x V CC to 0.8 x V CCInput Rise and Fall Time≤ 50 nsInput Reference Levels0.3 x V CC, 0.7 x V CCOutput Reference Level0.5 x V CCOutput Test Load Current Source I OL = 3 mA; C L = 100 pFPower-On Reset (POR)Each CA V24C32 incorporates Power-On Reset (POR)circuitry which protects the internal logic against powering up in the wrong state. The device will power up into Standby mode after V CC exceeds the POR trigger level and will power down into Reset mode when V CC drops below the POR trigger level. This bi-directional POR behavior protects the device against ‘brown-out’ failure following a temporary loss of power.Pin DescriptionSCL: The Serial Clock input pin accepts the clock signal generated by the Master.SDA: The Serial Data I/O pin accepts input data and delivers output data. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL.A 0, A 1 and A 2: The Address inputs set the device address that must be matched by the corresponding Slave address bits. The Address inputs are hard-wired HIGH or LOW allowing for up to eight devices to be used (cascaded) on the same bus. When left floating, these pins are pulled LOW internally.WP: When pulled HIGH, the Write Protect input pin inhibits all write operations. When left floating, this pin is pulled LOW internally.Functional DescriptionThe CA V24C32 supports the Inter-Integrated Circuit (I 2C) Bus protocol. The protocol relies on the use of a Master device, which provides the clock and directs bus traffic, and Slave devices which execute requests. The CA V24C32operates as a Slave device. Both Master and Slave can transmit or receive, but only the Master can assign those roles.I 2C Bus ProtocolThe 2-wire I 2C bus consists of two lines, SCL and SDA,connected to the V CC supply via pull-up resistors. The Master provides the clock to the SCL line, and either the Master or the Slaves drive the SDA line. A ‘0’ is transmitted by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, SDA must remain stable while SCL is HIGH.START/STOP Condition An SDA transition while SCL is HIGH creates a START or STOP condition (Figure 2). The START consists of a HIGH to LOW SDA transition, while SCL is HIGH. Absent the START, a Slave will not respond to the Master. The STOP completes all commands, and consists of a LOW to HIGH SDA transition, while SCL is HIGH.Device AddressingThe Master addresses a Slave by creating a START condition and then broadcasting an 8-bit Slave address. For the CA V24C32, the first four bits of the Slave address are set to 1010 (Ah); the next three bits, A 2, A 1 and A 0, must match the logic state of the similarly named input pins. The R/W bit tells the Slave whether the Master intends to read (1) or write (0) data (Figure 3).AcknowledgeDuring the 9th clock cycle following every byte sent to the bus, the transmitter releases the SDA line, allowing the receiver to respond. The receiver then either acknowledges (ACK) by pulling SDA LOW, or does not acknowledge (NoACK) by letting SDA stay HIGH (Figure 4). Bus timing is illustrated in Figure 5.START CONDITIONSTOP CONDITIONSDASCLFigure 2. Start/Stop TimingFigure 3. Slave Address BitsDEVICE ADDRESSFigure 4. Acknowledge TimingSCL FROM MASTERDATA OUTPUTFROM TRANSMITTERDATA OUTPUT FROM RECEIVER≥ t SU:DAT )Figure 5. Bus TimingSCLSDA INSDA OUTWRITE OPERATIONSByte WriteTo write data to memory, the Master creates a START condition on the bus and then broadcasts a Slave address with the R/W bit set to ‘0’. The Master then sends two address bytes and a data byte and concludes the session by creating a STOP condition on the bus. The Slave responds with ACK after every byte sent by the Master (Figure 6). The STOP starts the internal Write cycle, and while this operation is in progress (t WR ), the SDA output is tri-stated and the Slave does not acknowledge the Master (Figure 7).Page WriteThe Byte Write operation can be expanded to Page Write,by sending more than one data byte to the Slave before issuing the STOP condition (Figure 8). Up to 32 distinct data bytes can be loaded into the internal Page Write Buffer starting at the address provided by the Master. The page address is latched, and as long as the Master keeps sending data, the internal byte address is incremented up to the end of page, where it then wraps around (within the page). New data can therefore replace data loaded earlier. Following the STOP, data loaded during the Page Write session will be written to memory in a single internal Write cycle (t WR ).Acknowledge PollingAs soon (and as long) as internal Write is in progress, the Slave will not acknowledge the Master. This feature enables the Master to immediately follow-up with a new Read or Write request, rather than wait for the maximum specified Write time (t WR ) to elapse. Upon receiving a NoACK response from the Slave, the Master simply repeats the request until the Slave responds with ACK.Hardware Write ProtectionWith the WP pin held HIGH, the entire memory is protected against Write operations. If the WP pin is left floating or is grounded, it has no impact on the Write operation. The state of the WP pin is strobed on the last falling edge of SCL immediately preceding the 1st data byte (Figure 9). If the WP pin is HIGH during the strobe interval,the Slave will not acknowledge the data byte and the Write request will be rejected.Delivery StateThe CA V24C32 is shipped erased, i.e., all bytes are FFh.SLAVE ADDRESSSA ****C KA C KA C KS T O P PST ARTA CKBUS ACTIVITY:MASTER SLAVEADDRESS BYTE ADDRESS BYTE DAT A BYTE Figure 6. Byte Write Sequence*a 15 − a 12 are don’t care bitsa 15 − a 8a 7 − a 0d 7 − d 0Figure 7. Write Cycle TimingSTOPCONDITIONSTARTCONDITIONADDRESSSCLSDASLAVE ADDRESSSA C K A C K C K ST ARTC K S T O C KC K C K BUSACTIVITY:MASTER SLAVEn = 1ADDRESS BYTE ADDRESS BYTEDATA BYTE DATA BYTE DATA BYTE Figure 8. Page Write SequenceP ≤ 31Figure 9. WP TimingADDRESS BYTE DATA BYTESCLSDA WPREAD OPERATIONSImmediate ReadTo read data from memory, the Master creates a START condition on the bus and then broadcasts a Slave address with the R/W bit set to ‘1’. The Slave responds with ACK and starts shifting out data residing at the current address.After receiving the data, the Master responds with NoACK and terminates the session by creating a STOP condition on the bus (Figure 10). The Slave then returns to Standby mode.Selective ReadTo read data residing at a speci fic address, the selected address must first be loaded into the internal address register.This is done by starting a Byte Write sequence, whereby the Master creates a START condition, then broadcasts a Slave address with the R/W bit set to ‘0’ and then sends two address bytes to the Slave. Rather than completing the ByteWrite sequence by sending data, the Master then creates a START condition and broadcasts a Slave address with the R/W bit set to ‘1’. The Slave responds with ACK after every byte sent by the Master and then sends out data residing at the selected address. After receiving the data, the Master responds with NoACK and then terminates the session by creating a STOP condition on the bus (Figure 11).Sequential ReadIf, after receiving data sent by the Slave, the Master responds with ACK, then the Slave will continue transmitting until the Master responds with NoACK followed by STOP (Figure 12). During Sequential Read the internal byte address is automatically incremented up to the end of memory, where it then wraps around to the beginning of memory.Figure 10. Immediate Read Sequence and TimingSCL SDA 8th Bit STOPNO ACKDATA OUT89SLAVE ADDRESSSA C KDATA BYTEN OA C K S T O P PS T A R T BUS ACTIVITYMASTERSLAVEFigure 11. Selective Read SequenceSLAVE ADDRESS SA C KA C KA C K ST ARTSLAVE SA C KS T A R T PS T O P ADDRESS BYTE ADDRESS BYTE ADDRESSN O A C KBYTEBUS ACTIVITY:MASTER SLAVEFigure 12. Sequential Read SequenceS T O SLAVE C KA C A C N O A C A C BYTE n BYTE n+1BYTE n+2BYTE n+xBUS ACTIVITY:MASTERSLAVESOIC 8, 150 mils CASE 751BD −01ISSUE OIDENTIFICATIONTOP VIEWSIDE VIEWEND VIEWNotes:(1) All dimensions are in millimeters. Angles in degrees.(2) Complies with JEDEC MS-012.SYMBOLMIN NOMMAX θA A1b cD E E1e h 0º8º0.100.330.190.254.805.803.801.27 BSC1.750.250.510.250.505.006.204.00L0.40 1.271.35TSSOP8, 4.4x3CASE 948AL −01ISSUE OA1TOP VIEWSIDE VIEWEND VIEWNotes:(1) All dimensions are in millimeters. Angles in degrees.(2) Complies with JEDEC MO-153.SYMBOLθMINNOM MAXA A1A2bc D E E1e L10º8ºL 0.050.800.190.090.502.906.304.300.65 BSC 1.00 REF1.200.151.050.300.200.753.106.504.500.900.603.006.404.40Example of Ordering InformationCAV24C32WE −GT3 (Note 11)Prefix Device #Suffix 9.All packages are RoHS-compliant (Lead-free, Halogen-free).10.The standard lead finish is NiPdAu.11.The device used in the above example is a CAV24C32WE −GT3 (SOIC, Automotive Temperature, NiPdAu, Tape & Reel, 3,000/Reel).12.For other package options, please contact your nearest ON Semiconductor Sales office.13.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.ON Semiconductor is licensed by Philips Corporation to carry the I 2C Bus Protocol.PUBLICATION ORDERING INFORMATION分销商库存信息:ONSEMICAV24C32WE-GT3CAV24C32YE-GT3。
SLE 24C32中文资料
Standard EEPROM ICs SLx 24C3232 Kbit (4096 × 8 bit)Serial CMOS-EEPROM withI2C Synchronous 2-Wire BusData Sheet1999-02-02Edition 1999-02-02Published by Siemens AG,Bereich Halbleiter, Marketing-Kommunikation, Balanstraße 73,81541 München© Siemens AG 1999.All Rights Reserved.Attention please!As far as patents or other rights of third par-ties are concerned, liability is only assumed for components, not for applications, pro-cesses and circuits implemented within components or assemblies.The information describes the type of component and shall not be considered as assured characteristics.Terms of delivery and rights to change design reserved.For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list).Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group.Siemens AG is an approved CECC manufacturer.PackingPlease use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.Components used in life-support devices or systems must be expressly authorized for such purpose!Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG.1 A critical component is a component usedin a life-support device or system whose failure can reasonably be expected tocause the failure of that life-supportdevice or system, or to affect its safety or effectiveness of that device or system.2Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintainand sustain human life. If they fail, it isreasonable to assume that the health of the user may be endangered.Page Protection Mode™ is a trademark of Siemens AG.I 2C BusPurchase of Siemens I 2C components conveys the license under the Philips I 2C patent to use the components in the I 2C system provided the system conforms to the I 2C specifications defined by Philips.SLx 24C32Revision History: Current Version: 1999-02-02Previous Version:02.98, 04.98, 07.98Page (in previous Version)Page (in current Version)Subjects (major changes since last revision)Changes in the complete document P-DIP-8-4 changed to P-DIP-8-3, P-DSO-8-3 changed to P-DSO-8-2.34Text changed to “Typical programming time 5ms for up to 32bytes”.45SLA 24C32-D-3, SLA 24C32-D-3/P, SLA 24C32-S-3 and SLA 24C32-S-3/P deleted.45Voltage changed from 4.5 V...5.5 V to 2.7 V...5.5 V.45Text “3V types with automotive temperature range (–40°C …+125°C)” deleted.45Package (TSSOP, die, wafer delivery) added.67Footnote added “Values are temperature ….”67Text changed to “The device with a voltage range of 2.7…5.5.V isavailable …”.11, 1213, 15The erase/write cycle is finished latest after 108ms.1415Text added “(see figure 10)”.1819Figure 13: “CSW” changed to “CSR”.2123The write or erase cycle is finished latest after 10 4ms.2223Figure 17: “ACK” deleted before “STOP”.2224Line “Supply voltage”: Text deleted.2324Supply current (write) 3 mA 1 mA.2324Line added “Supply current (read)”.2426The line “erase/write cycle” removed.2426Chapter 8.4 “Erase and Write Characteristics” added.32 Kbit (4096 × 8 bit) Serial CMOSEEPROMs, I 2C Synchronous 2-Wire BusSLx 24C321Overview 1.1Features•Data EEPROM internally organized as 4096 bytes and 128 pages × 32 bytes •Page Protection Mode for protecting the EEPROM against unintended data changes (SLx 24C32.../P types only)•Low power CMOS•V CC = 2.7 to 5.5 V operation•Two wire serial interface bus, I 2C-Bus compatible •Three chip select pins to address 8 devices •Filtered inputs for noise suppression with Schmitt trigger•Clock frequency up to 400 kHz •High programming flexibility –Internal programming voltage–Self timed programming cycle including erase –Byte-write and page-write programming, between 1 and 32 bytes–Typical programming time 5ms for up to 32bytes •High reliability–Endurance 106 cycles 1)–Data retention 40 years 1)–ESD protection 4000 V on all pins •8 pin DIP/DSO packages•Available for extended temperature ranges –Industrial:− 40 °C to + 85 °C –Automotive:− 40°C to + 125 °C1)Values are temperature dependent, for further information please refer to your Siemens sales office.Ordering Information Other types are available on request:–Temperature range (– 55 °C … + 150 °C)–Package (TSSOP, die, wafer delivery)1.2Pin ConfigurationFigure 1Pin Configuration (top view)TypeOrdering Code Package Temperature Voltage SLA 24C32-D SLA 24C32-D/P Q67100-H3746Q67100-H3752P-DIP-8-3– 40 °C … + 85 °C 2.7 V...5.5 V SLA 24C32-S SLA 24C32-S/P Q67100-H3748Q67100-H3753P-DSO-8-2– 40 °C … + 85 °C2.7 V...5.5 VSLE 24C32-D SLE 24C32-D/P Q67100-H3235Q67100-H3755P-DIP-8-3– 40°C … + 125 °C 2.7 V...5.5 V SLE 24C32-S SLE 24C32-S/PQ67100-H3236Q67100-H3756P-DSO-8-2– 40°C … + 125 °C 2.7 V...5.5 VPin Definitions and Functions Pin Description Serial Clock (SCL)The SCL input is used to clock data into the device on the rising edge and to clock data out of the device on the falling edge.Serial Data (SDA)SDA is a bidirectional pin used to transfer addresses, data or control information into the device or to transfer data out of the device. The output is open drain, performing a wired AND function with any number of other open drain or open collector devices. The SDA bus requires a pull-up resistor to V CC . Chip Select (CS0, CS1, CS2)The CS0, CS1 and CS2 pins are chip select inputs either hard wired or actively driven to V CC or V SS . These inputs allow the selection of one of eight possible devices sharing a common bus.Write Protection (WP)WP switched to V SS allows normal read/write operations.WP switched to V CC protects the EEPROM against changes (hardware write protection).Table 1Pin No.Symbol Function 1, 2, 3CS0, CS1, CS2Chip select inputs 4V SSGround5SDA Serial bidirectional data bus 6SCL Serial clock input 7WPWrite protection input 8V CCSupply voltage2DescriptionThe SLx 24C32 device is a serial electrically erasable and programmable read only memory (EEPROM), organized as 4096 × 8 bit. The data memory is divided into 128pages. The 32 bytes of a page can be programmed simultaneously.The device conforms to the specification of the 2-wire serial I2C-Bus. Three chip select pins allow the addressing of 8 devices on the I2C-Bus. Low voltage design permits operation down to 2.7 V with low active and standby currents. All devices have a minimum endurance of 106 erase/write cycles1).The device operates at 5.0V ± 10% with a maximum clock frequency of 400kHz and at 2.7 ... 5.5V with a maximum clock frequency of 100kHz. The device with a voltage range of 2.7…5.5.V is available in two temperature ranges for industrial and automotive applications. The EEPROMs are mounted in eight-pin DIP and DSO packages or are also supplied as chips.1)Values are temperature dependent, for further information please refer to your Siemens Sales office.Figure 2Block Diagram3I2C-Bus CharacteristicsAccess to the SLx 24C32 device is given via the I2C bus. This bidirectional bus consists of two wires SCL and SDA for clock and data. The protocol is master/slave oriented, where the serial EEPROM always takes the role of a slave.Figure 3Bus ConfigurationMaster Device that initiates the transfer of data and provides the clock for transmit and receive operations.Slave Device addressed by the master, capable of receiving and transmitting data.Transmitter The device using the SDA as output is defined as the transmitter. Due to the open drain characteristic of the SDA output the device applying a lowlevel wins.Receiver The device using the SDA as input is defined as the receiver.The conventions for the serial clock line and the bidirectional data line are shown in figure4.Figure 4I2C-Bus Timing Conventions for START Condition, STOP Condition, Data Validation and Transfer of Acknowledge ACKStandby Mode in which the bus is not busy (no serial transmission, noprogramming): both clock (SCL) and data line (SDA) are in highstate. The device enters the standby mode after a STOP conditionor after a programming cycle.START Condition High to low transition of SDA when SCL is high, preceding allcommands.STOP Condition Low to high transition of SDA when SCL is high, terminating allcommunications. A STOP condition after writing data initiates anEEPROM programming cycle. A STOP condition after readingdata from the EEPROM initiates the standby mode. Acknowledge A successful reception of eight data bits is indicated by thereceiver by pulling down the SDA line during the following clockcycle of SCL (ACK). The transmitter on the other hand has torelease the SDA line after the transmission of eight data bits.The EEPROM as the receiving device responds with anacknowledge, when addressed. The master, on the other side,acknowledges each data byte transmitted by the EEPROM andcan at any time end a read operation by releasing the SDA line (noACK) followed by a STOP condition.Data Transfer Data must change only during low SCL state, data remains validon the SDA bus during high SCL state. Nine clock pulses arerequired to transfer one data byte, the most significant bit (MSB)is transmitted first.4Device Addressing and EEPROM AddressingAfter a START condition, the master always transmits a command byte CSW or CSR. After the acknowledge of the EEPROM control bytes follow, their contents and the transmitter depend on the previous command byte. The description of the command and control bytes is shown in table 2.Command Byte Selects one of the 8 addressable slave devices: The chip select bits CS2, CS1 and CS0 (bit positions b3 to b1) are compared to theircorresponding hard wired input pins CS2, CS1 and CS0,respectively.Selects operation: the least significant bit b0 is low for a writeoperation (Chip Select Write Command Byte, CSW) or set high fora read operation (Chip Select Read Command Byte, CSR). Control Bytes Following CSW (b0 = 0): The address bytes AHI/ALO containing the address bits A0 to A11 are transmitted by the master.Following CSR (b0 = 1): The EEPROM transmits the read out data.EEPROM data are read as long as the master pulls down SDA aftereach byte in order to acknowledge the transfer. The read operationis stopped by the master by releasing SDA (no acknowledge isapplied) followed by a STOP condition.Table 2Command and Control Byte for I2C-Bus Addressing of Chip and EEPROM Command Definition Functionb7b6b5b4b3b2b1b0CSW1010CS2CS1CS00chip select for write CSR1010CS2CS1CS01chip select for read AHI0000A11A10A9A8high addressALO A7A6A5A4A3A2A1A0low addressDATA D7D6D5D4D3D2D1D0data byteThe device has an internal address counter which points to the current EEPROM address.The address counter is incremented–after a data byte to be written has been acknowledged, during entry of further data byte–during a byte read, thus the address counter points to the following address after reading a data byte.The timing conventions for read and write operations are described in figures5 and 6.Figure 5Timing of the Command Byte CSWFigure 6Timing of the Command Byte CSR5Write OperationsChanging of the EEPROM data is initiated by the master with the command byte CSW.Either one byte (Byte Write) or up to 32 byte (Page Write) are modified in one programming procedure. Setting the Write Protection pin WP to V CC activates the hardware write protection and therefore any programming is suppressed. For normal operation WP has to be set to V SS .5.1Byte WriteFigure 7Byte Write SequenceThe erase/write cycle is finished latest after 8 ms. Acknowledge polling can be used for speed enhancement in order to detect the end of the erase/write cycle. Please refer to chapter 5.3, Acknowledge Polling for further information.Address SettingAfter a START condition the master transmits the Chip Select Write byte CSW. The EEPROM acknowledges the CSW byte during the ninth clock cycle. The following two bytes AHI/ALO with the EEPROM address (A0 to A11) are loaded into the address counter of the EEPROM and acknowledged by the EEPROM.Transmission of Data Finally the master transmits the data byte which is also acknowledged by the EEPROM into the internal buffer.Programming CycleThen the master applies a STOP condition which starts the internal programming procedure. The data bytes are written in the memory location addressed in the bytes AHI (A8 to A11)and ALO (A0 to A7). The programming procedure consists of an internally timed erase/write cycle. In the first step, the selected byte is erased to “1”. With the next internal step, the addressed byte is written according to the contents of the buffer.5.2Page WriteAddress Setting The page write procedure is the same as the byte writeprocedure up to the first data byte. In a page write instructionhowever, entry of the EEPROM address bytes AHI/ALO arefollowed by a sequence of one to a maximum of 32 data byteswith the new data to be programmed. These bytes aretransferred to the internal page buffer of the EEPROM. Transmission of Data The first entered data byte will be stored according to theEEPROM address n given by AHI (A8 to A11) and ALO (A0 toA7). The internal address counter is incrementedautomatically after the entered data byte has beenacknowledged. The next data byte is then stored at the nexthigher EEPROM address. EEPROM addresses within thesame page have common page address bits A5 through A11.Only the respective five least significant address bits A0through A4 are incremented, as all data bytes to beprogrammed simultaneously have to be within the same page.Writing over the page border will cause the address counter toroll over to the first address of the page.Programming Cycle The master stops data entry by applying a STOP condition,which also starts the internally timed erase/write cycle. In thefirst step, all selected bytes are erased to “1”. With the nextinternal step, the addressed bytes are written according to thecontents of the page buffer.Those bytes of the page that have not been addressed are not included in the programming.Figure 8Page Write SequenceThe erase/write cycle is finished latest after 8 ms. Acknowledge polling can be used for speed enhancement in order to detect the end of the erase/write cycle. Please refer to chapter5.3, Acknowledge Polling for further information.5.3Acknowledge PollingDuring the erase/write cycle the EEPROM will not respond to a new command byte until the internal write procedure is completed. At the end of active programming the chip returns to the standby mode and the last entered EEPROM byte remains addressed by the address counter. To determine the end of the internal erase/write cycle acknowledge polling can be initiated by the master by sending a START condition followed by a command byte CSR or CSW (read with b0 = 1 or write with b0 = 0). If the internal erase/ write cycle is not completed, the device will not acknowledge the transmission. If the internal erase/write cycle is completed, the device acknowledges the received command byte and the protocol activities can continue (see figure10).Figure 9Flow Chart “Acknowledge Polling”Figure 10Principle of Acknowledge Polling6Read OperationsReading of the EEPROM data is initiated by the Master with the command byte CSR.6.1Random ReadRandom read operations allow the master to access any memory location.Figure 11Random ReadAddress SettingThe master generates a START condition followed by the command byte CSW. The receipt of the CSW-byte is acknowledged by the EEPROM with a low state on the SDA line. Now the master transmits the EEPROM address (AHI/ALO) to the EEPROM and the internal address counter is loaded with the desired address.Transmission of CSRAfter the acknowledge for the EEPROM address is received,the master generates a START condition, which terminates the initiated write operation. Then the master transmits the command byte CSR for read, which is acknowledged by the EEPROM.Transmission of EEPROM DataDuring the next eight clock pulses the EEPROM transmits the data byte and increments the internal address counter by one byte.STOP Condition from Master During the following clock cycle the masters releases the bus and then transmits the STOP condition.6.2Current Address ReadThe EEPROM content is read without setting an EEPROM address, in this case the current content of the address counter will be used (e.g. to continue a previous read operation after the Master has served an interrupt).Figure 12Current Address ReadTransmission of CSRFor a current address read the master generates a START condition, which is followed by the command byte CSR (Chip Select Read). The receipt of the CSR-byte is acknowledged by the EEPROM with a low on the SDA line.Transmission of EEPROM DataDuring the next eight clock pulses the EEPROM transmits the data byte and increments the internal address counter by one byte.STOP Condition from Master During the following clock cycle the masters releases the bus and then transmits the STOP condition.6.3Sequential ReadA sequential read is initiated in the same way as a current read or a random read except that the master acknowledges the data byte transmitted by the EEPROM. The EEPROM then continues the data transmission. The internal address counter is incremented by one during each data byte transmission.A sequential read allows the entire memory to be read during one read operation. After the highest addressable memory location is reached, the internal address pointer “rolls over” to the address 0 and the sequential read continues.The transmission is terminated by the master by releasing the SDA line (no acknowledge) and generating a STOP condition (see figure 13).Figure 13Sequential Read7Page Protection Mode TMThe page protection mode is supported by the SLx 24C32.../P types only. For example SLA 24C32-D/P has the same functionality as SLA 24C32-D enhanced by page protection mode.Each page (32 bytes) in the data memory can be protected against unintended data changes by an associated protection bit. The protection bit memory consists of an additional EEPROM of 128 bit (figure 14).Data in the data memory can be modified only if the assigned protection bit is erased (logical state “1”). After writing the data bytes to a page, the protection is achieved by writing the associated protection bit (logical state “0”). Further changes in the data in a protected page is possible only after erasing the protection bit.Figure 14Data Page and Assigned Protection MemoryA special procedure to write or erase a protection bit guarantees proper activation or deactivation of page protection. For protection bit write or erase all 32 data bytes of the respective page have to be entered for verification. The data then are compared internally with the data to be protected. In case of identity the protection bit is written or erased respectively.7.1Protection Bit HandlingThe bits of the protection memory can be addressed directly for reading or programming.A protection bit address corresponds to the lowest address within the respective page (A5to A11, A0 to A4 = zero). The status of each protection bit is sensed internally. A written state (“0”) prevents programming in the associated page. If an already protected memory page is accidentally addressed for programming, the programming procedure is suppressed.The conventional I2C-Bus protocol allows data bytes to be read and programmed only. Therefore an independent instruction sequence for addressing and manipulation of protection bits is implemented. For protection bit instructions the command byte CSW with its preceding START condition followed by the associated address bytes have to be entered twice (figures 15 through17). The first command byte CSW is followed by the address bytes AHI/ALO with the bit/page address A0 through A4 always at zero. The second CSW is required for entering a control byte CTx for protection bit manipulation. The three control bytes for read, write or erase of a protection bit are listed below (table3):Table 3Control Byte for Protection Bit ManipulationAddress NameDefinition Function b7b6b5b4b3b2b1b0CTR x x x x x x00Protection bit read CTW x x x x x x01Protection bit write CTE x x x x x x11Protection bit erase7.2Protection Bit Write and EraseFor writing or erasing a protection bit the data of the respective page have to be known by the master. The master has to present the page data as a reference for comparison by the EEPROM. A successful comparison is necessary in order to change the value of the protection bit.The data of the page are not affected by the write or erase procedure of the protection bit. The I 2C-Bus protocol is shown in figure 15 for protection bit write and figure 16 for protection bit erase.Figure 15Sequence for Protection Bit WriteFigure 16Sequence for Protection Bit EraseThe first command byte CSW followed by the address bytes AHI/ALO determines the page to be protected. The second command byte CSW (identical content of first CSW)is followed by the control byte CTW = 01H for protection bit write or CTE = 03H for protection bit erase. Depending on CTx, the addressed protection bit will be either written or erased.The control byte CTx is followed by 32 parameter bytes identical to the 32 data bytes of the page to be protected or unprotected. The data of the first entered byte must be identical to the data byte stored at the lowest address of the current page. The other31bytes have to be identical to the bytes stored in ascending address order within the same page.A successful verification of each byte is indicated by the EEPROM by pulling the SDA line to low (acknowledge ACK).The bit programming procedure is initiated by the STOP condition after verification of the last byte. Programming is started only if all 256 bits of a page have been verified successfully. If bit programming has taken place, the address counter points to the uppermost address of the respective page. The write or erase cycle is finished latest after 4ms. Acknowledge polling can be used for speed enhancement in order to detect the end of the write or erase cycle (refer to chapter5.3, Acknowledge Polling).7.3Protection Bit ReadThe byte sequence for random bit read is shown in figure 17.Figure 17Byte Sequence for Protection Bit ReadThe first command byte CSW followed by the address bytes AHI/ALO determine the protection bit to be read. The second command byte CSW is followed by the control byte00H for protection bit read. The first bit (MSB) of the transferred byte is the protection bitof the addressed page. The other 7 bits are not valid. The page protection status is indicated as follows:Protection Bit = 1: A normal write operation changes the data in the associated page Protection Bit = 0: The data in the associated page are protected against changes.If the master acknowledges a byte with a low state of the SDA line, the protection bit of the next page can be read as the first bit of the following byte. If the master releases the SDA line, a STOP condition has to complete the read procedure. Any number of bytes with a page protection status at the first bit position can be requested by the master. After the bit of the uppermost page has been addressed an overflow of the address counter occurs and the protection bit of the first page will be read next.8Electrical CharacteristicsThe listed characteristics are ensured over the operating range of the integrated circuit.Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at T A = 25°C and the given supplyvoltage.8.1Absolute Maximum RatingsStresses above those listed here may cause permanent damage to the device. This is astress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this data sheet is not implied.Exposure to absolute maximum ratings for extended periods may affect device reliability.ParameterLimit Values Units Operating temperature range 1 (industrial)range 2 (automotive)– 40 to + 85 – 40 to + 125 °C °C Storage temperature – 65 to + 150 °C Supply voltage– 0.3 to + 7.0 V All inputs and outputs with respect to ground – 0.3 to V CC +0.5V ESD protection (human body model)4000V8.2DC CharacteristicsParameterSymbolLimit ValuesUnits Test Conditionmin.typ.max.Supply voltageV CC2.75.5V Supply current 1) (write)I CC 1mA V CC =5V;f c =100kHz Supply current (read)I CC 0.5mA V CC =5V;f c =100kHzStandby current 2)I SB 1µA Inputs at V CC or V SSInput leakage currentI LI0.11µA V IN =V CC or V SS Output leakage currentI LO 0.11µAV OUT =V CC or V SSInput low voltage V IL– 0.30.3×V CC VInput high voltage V IH 0.7×V CCV CC +0.5VOutput low voltage V OL 0.4V I OL =3 mA; V CC =5VI OL =2.1 mA; V CC =3 V Input/output capacitance (SDA)C I/O83)pFV IN =0V;V CC =5VInputcapacitance (other pins)C IN63)pFV IN =0V;V CC =5V1)The values for I CCare maximum peak values2)Valid over the whole temperature range 3)This parameter is characterized only8.2DC Characteristics (cont’d)Parameter SymbolLimit ValuesUnits Test Conditionmin.typ.max.1)The minimum rise and fall times can be calculated as follows: (20 + (0.1/pF) × C b ) ns Example: C b = 100 pF → t R = (20 + 0.1 × 100) ns = 30 ns8.3AC CharacteristicsParameterSymbolLimit Values V CC = 2.7-5.5 V Limit Values V CC = 4.5-5.5 V Units min.max.min.max.SCL clock frequency f SCL 100400kHz Clock pulse width lowt low 4.7 1.2µs Clock pulse width hight high 4.00.6µsSDA and SCL rise timet R 10001)300ns SDA and SCL fall timet F 3001)300ns Start set-up timet SU.STA 4.70.6µs Start hold timet HD.STA 4.00.6µs Data in set-up timet SU.DAT 200100ns Data in hold timet HD.DAT 00µsSCL low to SDA data out validt AA 0.1 4.50.10.9µs Data out hold timet DH 10050ns Stop set-up timet SU.STO 4.00.6µs Time the bus must be free before a new transmission can start t BUF4.7 1.2µsSDA and SCL spike suppression time at constant inputst l 5010050100ns8.4Erase and Write CharacteristicsParameterSymbolLimit Values V CC = 2.7-5.5 V Limit Values V CC = 4.5-5.5 V Units typ.max.typ.max.Erase + write cycle (per page)t WR5858ms Erase page protection bit 2.54 2.54ms Write page protection bit2.542.54ms。
(完整word版)AT24Cxx中文数据手册
AT24C01A/02/04/08A/16A提供1024/2048/4096/8192/16384个连续的可擦除的位,以及由每8位组成一个字节的可编程只读存储器（EEPROM）,其分别提供128/256/512/1024/2048个字节.该设备适用在许多低功耗和低电压操作的工业和商业应用中。
1引脚描述1.1串行时钟（SCL）SCL输入用于正向输出边缘时钟信号到每个EEPROM设备，以及每个设备输出的反向边缘时钟数据。
1.2串行数据(SDA)SDA引脚是用于串行数据双向传输。
该引脚为开漏输出，同时可以与其他开漏极或集电极开路器件进行线或.1.3设备/页地址（A2,A1，A0）对于AT24C01A和AT24C02,A2、A1和A0引脚是配置器件的硬件地址输入。
一根总线上可以连接多达八个1K / 2K的设备（器件寻址部分详细讨论了器件寻址）.AT24C04使用A2和A1引脚作为硬件地址输入，在一根总线上有4个4K 的设备可用来寻址。
A0引脚没有连接。
AT24C08A只使用A2引脚作为硬件地址输入,在一根总线上有2个8K 的设备可用来寻址.A0和A1引脚没有连接。
AT24C16A不使用设备地址引脚,这限制了一根总线上只能挂一个设备。
A0、A1和A2引脚没有连接。
1.4写保护(WP）AT24C01A / 02 / 04 / 08A/ 16A有一个写保护引脚，提供硬件数据保护。
写保护引脚允许正常读/写操作时连接到GND。
当写保护引脚连接到VCC,写保护功能启用和操作如下表所示.2设备操作2.1时钟和数据转换SDA引脚通常情况下拉高.SDA引脚上的数据只能在SCL低时间段内更改,而启动条件或停止条件在SCL 为高时进行。
2.2启动条件在任何其他指令之前，SDA由高变为低，且SCL为高。
2.3停止条件SDA由低变为高，且SCL为高。
在读取序列之后,执行停止命令后EEPROM进入备用电源模式.2.4应答所有地址和数据字都是从EEPROM串行发送和接收8位字节。
基于FPGA的AT24C32控制电路设计
基于FPGA的AT24C32控制电路设计摘要：本文介绍了现场可编程门阵列FPGA与AT24C32器件的接口设计方法。
其特点是用VHDL语言编程，利用FPGA的普通I/O口模拟产生IIC总线协议的接口信号时序，实现FPGA与AT24C32的数据通信。
本文给出了FPGA与IIC总线存储器件AT24C32连接的硬件和软件设计的应用实例。
关键词：FPGA IIC总线VHDL I/O口1、引言现场可编程门阵列FPGA（Field Programmable Gate Array）是新一代可编程逻辑器件。
FPGA功能强大，可以实现所有数字电路功能，具有结构灵活，设计周期短，密度高，性能好等多种优点，广泛应用于数字设计和电子生产中。
IIC总线（Intel IC Bus）是由Philips公司推出的一种串行扩展总线，它与并行总线相并，有如下突出的优点：规范完整，结构简单，易于实现用户系统软硬件的模块化、标准化等，因此IIC总线在简单的数字通信中应用十分普遍。
IIC 总线器件必须由一个主器件控制，在传统设计中以单片机或CPU作为主器件，本设计中采用可编程逻辑器件FPGA作为主器件，用FPGA的普通I/O口模拟IIC 总线与器件AT24C32直接相连，实现FPGA与IIC总线器件的数据通信。
二者实现数据通信的最关键地方是需要严格遵守IIC总线协议来进行设计。
2、IIC总线协议IIC总线有严格的规范，IIC总线有两条串行接口，即SDA串行数据线和SCL 串行时钟线。
SDA是一个双向数据端口，用于传输地址和数据进入器件或从器件发出数据。
SCL串行时钟端用于同步进入器件或从器件发出数据。
（1）开始（START）和停止（STOP）数据传送当时钟线SCL为高，SDA线由高到低变化决定开始条件。
所有的命令都必须在开始条件以后进行。
当SCL线为高，SDA线由低到高变化决定停止条件。
所有的操作都必须在停止条件以前结束。
总线开始和停止数据传送的时序见图1。
AT24Cxx中文数据手册
AT24C01A/02/04/08A/16A提供1024/2048/4096/8192/16384个连续的可擦除的位，以及由每8位组成一个字节的可编程只读存储器（EEPROM），其分别提供128/256/512/1024/2048个字节。
该设备适用在许多低功耗和低电压操作的工业和商业应用中。
1引脚描述1.1串行时钟(SCL)SCL输入用于正向输出边缘时钟信号到每个EEPROM设备，以及每个设备输出的反向边缘时钟数据。
1.2串行数据(SDA)SDA引脚是用于串行数据双向传输。
该引脚为开漏输出，同时可以与其他开漏极或集电极开路器件进行线或。
1.3设备/页地址(A2,A1,A0)对于AT24C01A和AT24C02，A2、A1和A0引脚是配置器件的硬件地址输入。
一根总线上可以连接多达八个1K / 2K的设备（器件寻址部分详细讨论了器件寻址）。
AT24C04使用A2和A1引脚作为硬件地址输入，在一根总线上有4个4K 的设备可用来寻址。
A0引脚没有连接。
AT24C08A只使用A2引脚作为硬件地址输入，在一根总线上有2个8K 的设备可用来寻址。
A0和A1引脚没有连接。
AT24C16A不使用设备地址引脚，这限制了一根总线上只能挂一个设备。
A0、A1和A2引脚没有连接。
1.4写保护(WP)AT24C01A / 02 / 04 / 08A/ 16A有一个写保护引脚，提供硬件数据保护。
写保护引脚允许正常读/写操作时连接到GND。
当写保护引脚连接到VCC，写保护功能启用和操作如下表所示。
2设备操作2.1时钟和数据转换SDA引脚通常情况下拉高。
SDA引脚上的数据只能在SCL低时间段内更改，而启动条件或停止条件在SCL为高时进行。
2.2启动条件在任何其他指令之前，SDA由高变为低，且SCL为高。
2.3停止条件SDA由低变为高，且SCL为高。
在读取序列之后，执行停止命令后EEPROM进入备用电源模式。
2.4应答所有地址和数据字都是从EEPROM串行发送和接收8位字节。
EEPROM---AT24Cxx应用介绍
EEPROM---AT24Cxx应⽤介绍结论：1、读写AT24CXX芯⽚，根据容量有多种⽅式：⼀、容量为AT24C01~AT24C16，⾸先发送设备地址（8位地址），再发送数据地址（8位地址），再发送或者接受数据。
⼆、AT24C32/AT24C64~AT24C512，⾸先发送设备地址（8位地址），再发送⾼位数据地址，再发送地位数据地址，再发送或者接受数据。
三、容量AT24C1024的芯⽚,是把容量⼀和容量⼆的⽅法结合，设备地址中要⽤⼀位作为数据地址位，存储地址长度是17位。
2、它的设备地址根据容量不同有区别： 1）、AT24C01~AT24C16：这⼀类⼜分为两类，分别为AT24C01/AT24C02和AT24C04~AT24C16;他们的设备地址为⾼7位，低1位⽤来作为读写标⽰位，1为读，0为写。
*1*、AT24C01/AT24C02。
AT24C01/AT24C02的A0、A1、A2引脚作为7位设备地址的低三位，⾼4为固定为1010B，低三位A0、A1、A2确定了AT24CXX的设备地址，所以⼀根I2C线上最⼤可以接8个AT24CXX，地址为1010000B~1010111B。
*2*、AT24C04~AT24C16的 A0、A1、A2只使⽤⼀部分，不⽤的悬空或者接地（数据⼿册中写的是悬空不接）。
举例：AT24C04只⽤A2、A1引脚作为设备地址，另外⼀位A0不⽤悬空，发送地址中对应的这位（A0）⽤来写⼊页寻址的页⾯号,⼀根I2C线上最⼤可以接4个，地址为101000xB~101011xB 2）、AT24C32/AT24C64:和AT24C01/AT24C02⼀样，区别是，发送数据地址变成16位。
注意事项：对AT24C32来说，WP置⾼，则只有四分之⼀受保护，即0x0C00－0x0FFF。
也就是说保护区为1KBytes。
对于低地址的四分之三，则不保护。
所以，如果数据较多时，可以有选择地存储。
AT24C1024介绍
AT24C1024介绍AT24C10242 线串⾏EEPROM特性低电压操作：2.7（Vcc=2.7V to 5.5V）内部组织：131,072*8 位=1M2 线串⾏接⼝施密特触发器，噪声抑制滤波输⼊双向数据传输协议时钟速率：400kHz(2.7V)和1MHz(5V) 硬件写保护引脚和软件数据保护256 字节页写模式(允许部分页⾯写⼊)随机和顺序读写模式⾃定义写周期(5ms)⾼可靠性：耐久⼒：写周期/页100,000 次数据保留：40 年8 引脚PDIP，8 引脚有铅SOIC 封装，8 引脚⽆铅阵列和8 引脚球状dBGA 封装描述AT24C1024 提供1,048,567 位的串⾏可电擦除和可编程只读存储器（EEPROM），它的每8 位组成⼀个字节，共131,072 个字节。
该设备的级联功能允许多达2 个设备共亨同⼀条2- 线总线。
该设备适合⽤于许多⼯业和商业，应⽤必要的低功耗和低电压的操作。
该器件可提供节省空间的8 引脚PDIP，8 引脚有铅SOIC 封装，8 引脚⽆铅阵列和8 引脚球状dBGA 封装。
另外，这⼀系列产品允许在2.7V（2.7V~5.5V）下⼯作。
绝对最⼤额定值：⼯作温度：-55~+125存储温度：-65~+150任何引脚的对地电压：-1.0V~+7.0V最⼤⼯作电压：6.25V 直流输出电流：5.0mA注意：强制⾼出“绝对最⼤额定值”可能导致设备的永久损坏。
设备的压⼒等级和功能操作只有在这些或超出本规范所标明的其他任何条件下是不允许的。
长时间⼯作在绝对最⼤额定值的条件下可能影响设备的可靠性。
引脚描述：串⾏时钟（SCL）：SCL 的输⼊是在时钟的上升沿数据进⼊每个EEPROM 设备和下降沿数据输出每个设备。
串⾏数据（SDA）：SDA 引脚是双向串⾏数据传输的。
这个引脚是漏极输出的，可以与其它的漏极开路或集电极开路的设备线或。
器件/ 页地址（A1 ）：A1 引脚是设备的输⼊地址，它能够通过导线与不兼容的设备AT24C128/256/512 连接。
NM24C32中文资料
NM24C32 32K-Bit Extended 2-Wire Bus InterfaceDevice Address Inputs (A0, A1, A2) Device address pins A0, A1, and A2 are connected to V CC or V SS to configure the EEPROM address for multiple device configura-tion. A total of eight different devices can be attached to the same SDA bus.Write Protection (WP)If WP is tied to V CC, program WRITE operations onto the upper half of the memory will not be executed. READ operations are always available.If WP is tied to V SS, normal memory operation is enabled, READ/ WRITE over the entire memory array.This feature allows the user to assign the upper half of the memory as ROM which can be protected against accidental programming writes. When WRITE is disabled, slave address and word address will be acknowledged but data will not be acknowledged. Device OperationThe NM24C32xxx supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving devices as the receiver. The device controlling the transfer is the master and the device that is controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the NM24C32xxx is considered a slave in all applications.CLOCK AND DATA CONVENTIONSData states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH and reserved for indicating start and stop conditions. Refer to Figures 2 and 3.START CONDITIONAll commands are preceded by the start condition, which is aHIGH to LOW transition of SDA when SCL is HIGH. TheNM24C32xxx continuously monitors the SDA and SCL lines forthe start condition and will not respond to any command until this condition has been met.STOP CONDITIONAll communications are terminated by a stop condition, which is aLOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the NM24C32xxx to place the device inthe standby power mode.Write Cycle TimingACKNOWLEDGEAcknowledge is a software convention used to indicate successfuldata transfers. The transmitting device, either master or slave, willrelease the bus after transmitting eight bits. During the ninth clockcycle the receiver will pull the SDA line LOW to acknowledge thatit received the eight bits of data. Refer to Figure 4.The NM24C32xxx device will always respond with an acknowl-edge after recognition of a start condition and its slave address. Ifboth the device and a WRITE operation have been selected, theNM24C32xxx will respond with an acknowledge after the receiptof each subsequent eight bit word.In the READ mode the NM24C32xxx slave will transmit eight bitsof data, release the SDA line and monitor the line for an acknowl-edge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data.If an acknowledge is not detected, the slave will terminate furtherdata transmissions and await the stop condition to return to the standby power mode.NM24C32 32K-Bit Extended 2-Wire Bus Interface Serial EEPROM with Write ProtectNM24C32 32K-Bit Extended 2-Wire Bus InterfaceNM24C32 32K-Bit Extended 2-Wire Bus Interface Serial EEPROM with Write ProtectS T O PA C KBus Activity:Master SDA Line 10100000Bus ActivityA C KDATAA C KA C KWORD ADDRESS (1)WORD ADDRESS (0)SLAVE ADDRESSS TART DEVICE ADDRESSINGFollowing a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are those of the device type identifier. This is fixed as 1010 for all EEPROM devices.The next three bits identifies the device address. Address from 000 to 111 are acceptable thus allowing up to eight devices to be connected to the IIC bus.The last bit of the slave address defines whether a write or read condition is requested by the master. A "1" indicates that a READ operation is to be executed and a "0" initiates the WRITE mode.A simple review: After the NM24C32xxx recognizes the start condition, the devices interfaced to the IIC bus waits for a slave address to be transmitted over the SDA line. If the transitted slave address matches an address of one of the devices, the designated slave pulls the line LOW with an acknowledge. signal and awaits further transmissions.Write OperationsBYTE WRITEFor a WRITE operation, two additional address bytes, with 12active bits, are required after the SLAVE acknowledge to address the full memory array. The first byte indicates the high-order byte of the word address. Only the four least signicant bits can be changed, the other bits are pre-assigned the value "0". Following the acknowledgement from the first word address, the next byte indicates the low-order byte of the word address. Upon receipt of the word address, the NM24C32xxx responds with another ac-knowledge and waits for the next eight bits of data, again,responding with an acknowledge. The master then terminates thetransfer by generating a stop condition, at which time the NM24C32xxx begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress, the device's inputs are disabled and the device will not respond to any requests from the master. Refer to Figure 5 for the address, acknowledge and data transfer sequence.PAGE WRITEThe NM24C32xxx is capable of thirty-two byte page write opera-tion. It is initiated in the same manner as the byte write operation;but instead of termination the write cycle after the first data word is transfered, the master can transmit up to thirty-one more words.After the receipt of each word, the device responds with an acknowledge.After the receipt of each word, the internal address counter increments to the next address and the next SDA data is ac-cepted. If the master should transmit more than thirty-two words prior to generating the stop condition, the address counter will "roll over" and the previous written data will be overwritten. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 6 for the address, acknowl-edge and data transfer sequence.Acknowledge PollingOnce the stop condition is isssued to indicate the end of the host's write operation, the NM24C32xxx initiates the internal write cycle.ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation.If the NM24C32xxx is still busy with the write operation, no ACK will be returned. If the device has completed the write operation,an ACK will be returned and the host can then proceed with the next read or write operation.DS500073-8Byte Write (Figure 5)NM24C32 32K-Bit Extended 2-Wire Bus InterfaceNM24C32 32K-Bit Extended 2-Wire Bus Interface。
AT24C32AN-10SJ-1.8中文资料
1Features•Low-Voltage and Standard-Voltage Operation –2.7 (V CC = 2.7V to 5.5V)–1.8 (V CC = 1.8V to 5.5V)•Low-Power Devices (I SB = 6 µA @ 5.5V) Available •Internally Organized 4096 x 8, 8192 x 8•2-Wire Serial Interface•Schmitt Trigger, Filtered Inputs for Noise Suppression •Bidirectional Data Transfer Protocol•100 kHz (1.8V) and 400 kHz (2.5V) Clock Rate for AT24C32A •400 kHz (1.8V) Clock Rate for AT24C64A•Write Protect Pin for Hardware Data Protection•32-Byte Page Write Mode (Partial Page Writes Allowed)•Self-Timed Write Cycle (5 ms Max)•High Reliability–Endurance: 1 Million Write Cycles –Data Retention: 100 Years•Automotive Grade, Extended Temperature and Lead-free/Halogen-free Devices Available•8-lead JEDEC PDIP , 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead MAP and 8-lead TSSOP PackagesDescriptionThe AT24C32A/64A provides 32,768/65,536 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 4096/8192 words of 8 bits each. The device’s cascadable feature allows up to 8 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applica-tions where low power and low voltage operation are essential. The A T24C32A/64A is available in space saving 8-lead JEDEC PDIP , 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead MAP and 8-lead TSSOP packages and is accessed via a 2-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V(1.8V to 5.5V) versions.Pin ConfigurationsPin Name Function A0 - A2Address Inputs SDA Serial DataSCL Serial Clock Input WPWrite Protect8-lead PDIP8-lead SOIC8-lead TSSOP8-lead MAPBottom View2AT24C32A/64A3054N–SEEPR–2/04Block DiagramAbsolute Maximum Ratings*Operating Temperature.................................-55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage Temperature....................................-65°C to +150°C Voltage on Any Pinwith Respect to Ground.....................................-1.0V to +7.0V Maximum Operating Voltage ..........................................6.25V DC Output Current........................................................5.0 mA3AT24C32A/64A3054N–SEEPR–2/04Pin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices.DEVICE/ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hardwired or left not connected for hardware compatibility with other AT24Cxx devices. When the pins are hardwired, as many as eight 32K/64K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). If the pins are left floating, the A2, A1 and A0 pins will be internally pulled down to GND if the capacitive coupling to the circuit board V CC plane is <3 pF. If coupling is >3 pF, Atmel recommends connecting the address pins to GND.WRITE PROTECT (WP): The write protect input, when connected to GND, allows nor-mal write operations. When WP is connected high to V CC , all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND if the capacitive coupling to the circuit board V CC plane is <3 pF. If coupling is >3pF, Atmel recommends connecting the pin to GND. Switching WP to V CC prior to a write operation creates a software write protect function.Memory OrganizationAT24C32A/64A, 32K/64K SERIAL EEPROM: The 32K/64K is internally organized as 128/256 pages of 32 bytes each. Random word addressing requires a 12/13-bit data word address.4AT24C32A/64A3054N–SEEPR–2/04Note:1.This parameter is characterized and is not 100% tested.Note:1.V IL min and V IH max are reference only and are not tested.Pin Capacitance (1)Applicable over recommended operating range from T A = 25°C, f = 1.0 MHz, V CC = +1.8V.Symbol Test ConditionMax Units Conditions C I/O Input/Output Capacitance (SDA)8pF V I/O = 0V C IN Input Capacitance (A 0, A 1, A 2, SCL)6pFV IN = 0VDC CharacteristicsApplicable over recommended operating range from: T AI = -40°C to +85°C, V CC = +1.8V to +5.5V, T AE = -40°C to +125°C,V CC = +1.8V to +5.5V (unless otherwise noted).Symbol Parameter Test ConditionMin TypMax Units V CC1Supply Voltage 1.8 5.5V V CC2Supply Voltage 2.5 5.5V V CC3Supply Voltage 2.7 5.5V V CC4Supply Voltage 4.55.5V I CC1Supply Current V CC = 5.0V READ at 400 kHz 0.4 1.0mA I CC2Supply Current V CC = 5.0V WRITE at 400 kHz 2.0 3.0mA I SB1Standby Current (1.8V option)V CC = 1.8V V IN = V CC or V SS 1.0µA I SB2Standby Current (2.5V option)V CC = 2.5V V IN = V CC or V SS 2.0µA I SB3Standby Current (2.7V option)V CC = 2.7V V IN = V CC or V SS 2.0µA I SB4Standby Current (5V option)V CC = 4.5 - 5.5V V IN = V CC or V SS6.0µA I LI Input Leakage CurrentV IN = V CC or V SS 0.10 3.0µA I LO Output Leakage CurrentV OUT = V CC or V SS0.053.0µA V IL Input Low Level (1)-0.6V CC x 0.3V V IH Input High Level (1)V CC x 0.7V CC + 0.5V V OL2Output Low Level V CC = 3.0V I OL = 2.1 mA 0.4V V OL1Output Low LevelV CC = 1.8VI OL = 0.15 mA0.2V5AT24C32A/64A3054N–SEEPR–2/04Notes:1.This parameter is characterized and is not 100% tested (T A = 25°C).2.This parameter is characterized and is not 100% tested.3.The Write Cycle Time of 5 ms only applies to the A T24C32A/64A devices bearing the process letter “A” on the package (themark is located in the lower right corner on the top side of the package).AC CharacteristicsApplicable over recommended operating range from T AI = -40°C to +85°C, T AE = -40°C to +125°C, V CC = +1.8V to +5.5V,CL = 1 TTL Gate and100 pF (unless otherwise noted).Symbol ParameterAT24C32A AT24C64AUnits 1.8V2.5V – 5.0V 1.8V –3.6V 5.0VMinMax MinMax MinMax MinMax f SCL Clock Frequency, SCL 100400400400kHz t LOW Clock Pulse Width Low 4.7 1.3 1.3 1.2µs t HIGH Clock Pulse Width High 4.00.60.60.6µs t I Noise Suppression Time (1)1005010050ns t AA Clock Low to Data Out Valid 0.1 4.50.10.90.20.90.10.9µs t BUF Time the bus must be free before a new transmission can start (2) 4.7 1.3 1.3 1.2µs t HD.STA Start Hold Time 4.00.60.60.6µs t SU.STA Start Set-up Time 4.70.60.60.6µs t HD.DAT Data In Hold Time 0000µs t SU.DA T Data In Set-up Time 200100100100ns t R Inputs Rise Time (2) 1.00.30.30.3µs t F Inputs Fall Time (2)300300300300ns t SU.STO Stop Set-up Time 4.70.60.60.6µs t DH Data Out Hold Time 1005020050ns t WRWrite Cycle Time 20 or 5(3)10 or 5(3)20 or 5(3)10 or 5(3)ms Endurance (1) 5.0V , 25°C, Page Mode1M 1M1M1MWrite Cycles6AT24C32A/64A3054N–SEEPR–2/04Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-nal device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word.STANDBY MODE: The AT24C32A/64A features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps:(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition as SDA is high.7AT24C32A/64A3054N–SEEPR–2/04Bus TimingSCL: Serial Clock, SDA: Serial Data I/OWrite Cycle TimingSCL: Serial Clock, SDA: Serial Data I/ONote:1.The write cycle time t WRis the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.8AT24C32A/64A3054N–SEEPR–2/04Data ValidityStart and Stop DefinitionOutput Acknowledge9AT24C32A/64A3054N–SEEPR–2/04Device AddressingThe 32K/64K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 1). The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all 2-wire EEPROM devices.The 32K/64K uses the three device address bits A2, A1, A0 to allow as many as eight devices on the same bus. These bits must compare to their corresponding hardwired input pins. The A2, A1, and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.The eighth bit of the device address is the read/write operation select bit. A read opera-tion is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to standby state.NOISE PROTECTION: Special internal circuitry placed on the SDA and SCL pins pre-vent small noise spikes from activating the device.DATA SECURITY: The AT24C32A/64A has a hardware data protection scheme that allows the user to write protect the entire memory when the WP pin is at V CC .Write OperationsBYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condi-tion. At this time the EEPROM enters an internally-timed write cycle, t WR , to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 2).PAGE WRITE: The 32K/64K EEPROM is capable of 32-byte page writes.A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 31more data words. The EEPROM will respond with a zero after each data word received.The microcontroller must terminate the page write sequence with a stop condition (refer to Figure 3).The data word address lower 5 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 32 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten.ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-ing a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero, allowing the read or write sequence to continue.10AT24C32A/64A3054N–SEEPR–2/04Read OperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page, to the first byte of the first page. The address “roll over” during write is from the last byte of the cur-rent page to the first byte of the same page.Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out.The microcontroller does not respond with an input zero but does generate a following stop condition (refer to Figure 4).RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 5).SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequen-tial read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condi-tion (refer to Figure 6).11AT24C32A/64A3054N–SEEPR–2/04Figure 1. Device AddressFigure 2. Byte WriteFigure 3. Page WriteNotes:1.* = DON’T CARE bits2.† = DON’T CARE bits for the 32KFigure 4.Current Address Read12AT24C32A/64A3054N–SEEPR–2/04Figure 5. Random ReadNote: 1.* = DON’T CARE bitsFigure 6.Sequential Read13AT24C32A/64A3054N–SEEPR–2/04Note:For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables.AT24C32A Ordering InformationOrdering Code Package Operation RangeA T24C32A-10PI-2.7A T24C32AN-10SI-2.7A T24C32AW-10SI-2.7A T24C32A-10TI-2.7A T24C32AY1-10YI-2.78P38S18S28A28Y1Industrial Temperature (-40°C to 85°C)A T24C32A-10PI-1.8A T24C32AN-10SI-1.8A T24C32AW-10SI-1.8A T24C32A-10TI-1.8A T24C32AY1-10YI-1.88P38S18S28A28Y1Industrial Temperature (-40°C to 85°C)A T24C32AN-10SU-2.7A T24C32AN-10SU-1.8A T24C32A-10TU-2.7A T24C32A-10TU-1.88S18S18A28A2Lead-free/Halogen-free/Industrial Temperature (-40°C to 85°C)A T24C32AN-10SQ-2.78S1Lead-free/Halogen-free/High Grade/Extended Temperature(-40°C to 125°C))A T24C32AN-10SE-2.78S1High Grade/Extended Temperature(-40°C to 125°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8S28-lead, 0.209" Body, Plastic Small Outline (EIAJ SOIC)8A28-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)Options-2.7Low Voltage (2.7V to 5.5V)-1.8Low Voltage (1.8V to 5.5V)14AT24C32A/64A3054N–SEEPR–2/04Note:For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables.AT24C64A Ordering InformationOrdering Code Package Operation RangeA T24C64A-10PI-2.7A T24C64AN-10SI-2.7A T24C64AW-10SI-2.7A T24C64A-10TI-2.7A T24C64AY1-10YI-2.78P38S18S28A28Y1Industrial Temperature (-40°C to 85°C)A T24C64A-10PI-1.8A T24C64AN-10SI-1.8A T24C64AW-10SI-1.8A T24C64A-10TI-1.8A T24C64AY1-10YI-1.88P38S18S28A28Y1Industrial Temperature (-40°C to 85°C)A T24C64AN-10SU-2.7A T24C64AN-10SU-1.8A T24C64A-10TU-2.7A T24C64A-10TU-1.88S18S18A28A2Lead-free/Halogen-free/Industrial Temperature (-40°C to 85°C)A T24C64AN-10SQ-2.78S1Lead-free/Halogen-free/High Grade/Extended Temperature(-40°C to 125°C))A T24C64AN-10SE-2.78S1High Grade/Extended Temperature(-40°C to 125°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8S28-lead, 0.209" Body, Plastic Small Outline (EIAJ SOIC)8A28-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)Options-2.7Low Voltage (2.7V to 5.5V)-1.8Low Voltage (1.8V to 5.5V)15AT24C32A/64A3054N–SEEPR–2/04Package Drawings8P3 – PDIP16AT24C32A/64A3054N–SEEPR–2/048S1 – JEDEC SOIC17AT24C32A/64A3054N–SEEPR–2/048S2 – EIAJ SOIC18AT24C32A/64A3054N–SEEPR–2/048A2 – TSSOP19AT24C32A/64A3054N–SEEPR–2/048Y1 – MAP3054N–SEEPR–2/04xMDisclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.Atmel CorporationAtmel Operations2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 487-2600Regional HeadquartersEuropeAtmel SarlRoute des Arsenaux 41Case Postale 80CH-1705 Fribourg SwitzerlandTel: (41) 26-426-5555Fax: (41) 26-426-5500AsiaRoom 1219Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong KongTel: (852) 2721-9778Fax: (852) 2722-1369Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Memory2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314Microcontrollers2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314La Chantrerie BP 7060244306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18Fax: (33) 2-40-18-19-60ASIC/ASSP/Smart CardsZone Industrielle13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00Fax: (33) 4-42-53-60-011150 East Cheyenne Mtn. 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AT24C1024 中文说明书
AT24C10242线串行EEPROM特性低电压操作：2.7（Vcc=2.7V to 5.5V）内部组织：131,072*8位=1M2线串行接口施密特触发器，噪声抑制滤波输入双向数据传输协议时钟速率：400kHz(2.7V)和1MHz(5V)硬件写保护引脚和软件数据保护256字节页写模式(允许部分页面写入)随机和顺序读写模式自定义写周期(5ms)高可靠性：耐久力：写周期/页100,000次数据保留：40年8引脚PDIP，8引脚有铅SOIC封装，8引脚无铅阵列和8引脚球状dBGA封装描述AT24C1024提供1,048,567位的串行可电擦除和可编程只读存储器（EEPROM），它的每8位组成一个字节，共131,072个字节。
该设备的级联功能允许多达2个设备共亨同一条2-线总线。
该设备适合用于许多工业和商业，应用必要的低功耗和低电压的操作。
该器件可提供节省空间的8引脚PDIP，8引脚有铅SOIC封装，8引脚无铅阵列和8引脚球状dBGA封装。
另外，这一系列产品允许在2.7V（2.7V~5.5V）下工作。
绝对最大额定值：工作温度：-55~+125存储温度：-65~+150任何引脚的对地电压：-1.0V~+7.0V最大工作电压：6.25V直流输出电流：5.0mA注意：强制高出“绝对最大额定值”可能导致设备的永久损坏。
设备的压力等级和功能操作只有在这些或超出本规范所标明的其他任何条件下是不允许的。
长时间工作在绝对最大额定值的条件下可能影响设备的可靠性。
引脚描述：：引脚描述串行时钟（SCL）：SCL的输入是在时钟的上升沿数据进入每个EEPROM设备和下降沿数据输出每个设备。
串行数据（SDA）：SDA引脚是双向串行数据传输的。
这个引脚是漏极输出的，可以与其它的漏极开路或集电极开路的设备线或。
器件/页地址（A1）：A1引脚是设备的输入地址，它能够通过导线与不兼容的设备AT24C128/256/512连接。
当A1通过硬件连接时，2个以上的1024K设备可以在同一条系统总路线上寻址（下面会详细谈论设备的地址选择）。
中文数据手册AT24C系列
020 38730976 38730977 Fax 38730925
直流操作特性
Vcc=+1.8V +6.0V 除非特别说明
符号
参数
最小
ICC ISB ILI ILO VIL VIH VOL1 VOL2
电源电流 备用电流(Vcc=5.0V) 输入漏电流 输出漏电流 输入低电压 输入高电压 输出低电压 输出低电压
广州周立功单片机发展有限公司 Tel
020 38730976 38730977 Fax 38730925
目录
1 CSI24WC0 1/02/04/08/16 ……………………………….2-10 2 CSI24WC32/64…………………………………………...11-18 3 CSI24WC128. ……………………………..…………….19-26 4 CSI24WC256. ………………………….….…………….27-34
符号
测试项
CI/O
I/O 电容 SDA 脚
CIN
输出电容 A0 A1 A2 SCL WP
最大 8 6
单位 PF PF
条件 VI/O=0V VIN=0V
交流特性 Vcc=+1.8V +6.0V 除非特别说明 输出负载能力为 1 个 TTL 门和 100pF
读写周期范围
符号
参数
FSCL TI tAA tBUF tHD: STA tLOW tHIGH tSU: STA tHD: DAT tSUl: DAT tR tF tSU: STO tDH
1 Vcc 0.7
典型
最大 3 0 10 10
Vcc 0.3 Vcc+0.5
0.4 0.5
安特尔AT24C32D 32K Serial EEPROM数据手册说明书
AT24C32DI2C-Compatible (2-Wire) Serial EEPROM32-Kbit (4,096 x 8)DATASHEET Features●Low-voltage and Standard-voltage OperationV CC = 1.7V to 5.5V●Internally Organized as 4,096 x 8 (32K)●I2C-compatible (2-Wire) Serial Interface●Schmitt Trigger, Filtered Inputs for Noise Suppression●Bidirectional Data Transfer Protocol●400kHz (1.7V) and 1MHz (2.5V, 2.7V, 5.0V) Compatibility●Write Protect Pin for Hardware Protection●32-byte Page Write ModePartial Page Writes Allowed●Self-timed Write cycle (5ms Max)●High ReliabilityEndurance: 1,000,000 Write CyclesData Retention: 100 Years●Lead-free/Halogen-free devices Available●Green Package Options (Pb/Halide-free/RoHS Compliant)8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 8-pad XDFN, 5-leadSOT23, 5-ball WLCSP, and 8-ball VFBGA packages●Die Sale Options: Wafer Form, Waffle Pack, and Bumped Wafers DescriptionThe Atmel® AT24C32D provides 32,768 bits of Serial Electrically Erasable and Programmable Read-Only Memory (EEPROM) organized as 4,096 words of 8 bits each. The device’s cascading feature allows up to eight devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 8-pad XDFN, 5-lead SOT23, 5-ball WLCSP, and 8-ball VFBGA packages. In addition, this device operates from 1.7V to 5.5V.AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_12201621.Pin Configurations and PinoutsTable 1-1.Pin Configuration Note:When using the 5-lead SOT-23 or the 5-ball WLCSP , the software bits A2, A1, and A0 must be set to Logic 0 to properly communicate with the device.2.Absolute Maximum Ratings*8-pad UDFN/XDFNV CC WP SCL SDAA 0A 1A 2GND123487658-ball VFBGABottom View8-lead SOIC8-lead TSSOPTop View12348765A 0A 1A 2GNDV CC WP SCL SDATop View Top ViewA 0A 1A 2GND V CC WP SCL SDA87651234SCL GND SDA123545-lead SOT23WPV CC* Note: Drawings are not to scale5-ball WLCSPBall Side View(1)A 0A 1A 2GNDV CC WP SCL SDA12348765(1)Operating Temperature . . . . . . . . . . .-55°C to +125°C Storage Temperature . . . . . . . . . . . . -65°C to + 150°C Voltage on any pinwith respect to ground . . . . . . . . . . . . . . .-1.0 V +7.0V Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V DC Output Current. . . . . . . . . . . . . . . . . . . . . . .5.0mA*Notice:Stresses beyond those listed under “AbsoluteMaximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions forextended periods may affect device reliability.3AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_1220163.Block Diagram4.Pin DescriptionsSerial Clock (SCL): The SCL input is used to positive-edge clock data into each EEPROM device and negative-edge clock data out of each device.Serial Data (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open drain driven and may be wire-ORed with any number of other open-drain or open-collector devices.Device Addresses (A 2, A 1, A 0): The A 2, A 1, and A 0 pins are device address inputs that are hard wired (directly to GND or to V CC ) for compatibility with other Atmel AT24C devices. When the pins are hard wired, as many as eight 32K devices may be addressed on a single bus system. (Device addressing is discussed in detail in Section 7., “Device Addressing” on page 9). A device is selected when a corresponding hardware and software match is true. If these pins are left floating, the A 2, A 1, and A 0 pins will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends using 10k Ω or less.Write Protect (WP): The Write Protect input, when connected to GND, allows normal write operations. When WP is connected directly to V CC , all Write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND; however, due to capacitive coupling that may appear during customerapplications, Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using 10k Ω or less.Table 4-1.Write ProtectV CC GND WP SCL SDAA 2A 1A 0AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_12201645.Memory OrganizationAT24C32D, 32K Serial EEPROM : The 32K is internally organized as 128 pages of 32-bytes each. Random word addressing requires a 12-bit data word address.5.1Pin CapacitanceTable 5-1.Pin Capacitance (1)Note:1.This parameter is characterized and is not 100% tested.5.2DC CharacteristicsTable 5-2.DC CharacteristicsNote:1.V IL min and V IH max are reference only and are not tested.Applicable over recommended operating range from: T A = 25°C, f = 1.0MHz, V CC = 5.5V.Applicable over recommended operating range from: T AI = -40°C to +85°C, V CC = 1.7V to 5.5V (unless otherwise noted).5AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_1220165.3AC CharacteristicsTable 5-3.AC Characteristics (Industrial Temperature)Notes:1.This parameter is ensured by characterization and is not 100% tested.2.AC measurement conditions:●R L (connects to V CC ): 1.3k Ω (2.5V, 5.5V), 10k Ω (1.7V)●Input pulse voltages: 0.3V CC to 0.7V CC ●Input rise and fall times: ≤ 50ns ●Input and output timing reference voltages: 0.5 x V CCApplicable over recommended operating range from: T AI = -40°C to +85°C, V CC = 1.7V to 5.5V, CL = 100pF (unless otherwise noted). Test conditions are listed in Note 2.AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_12201666.Device OperationClock and Data Transitions: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods. Data changes during SCL high periods will indicate a Start or Stop condition as defined below.Figure 6-1.Data ValidityStart Condition : A high-to-low transition of SDA with SCL high is a Start condition that must precede every command.Stop Condition: A low-to-high transition of SDA with SCL high is a Stop condition. After a Read sequence, the Stop condition will place the EEPROM in a standby power mode.Figure 6-2.Start Condition and Stop Condition DefinitionSDASCLData ChangeData StableData StableSDASCLStart Condition Stop Condition7AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_122016Acknowledge: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The receiving device sends a zero during the ninth clock cycle to acknowledge that it has received each word. This zero response is referred to as an Acknowledge.Figure 6-3.Output AcknowledgeStandby Mode: AT24C32D features a low-power standby mode that is enabled upon power-up and after the receipt of the Stop condition and the completion of any internal operations.Software Reset : After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset by following these steps:1.Create a Start condition (if possible).2.Clock nine cycles.3.Create another Start condition followed by Stop condition as shown below.The device should be ready for the next communication after above steps have been completed. In the event that the device is still non-responsive or remains active on the SDA bus, a power cycle must be used to reset the device.Figure 6-4.Software ResetSCLData InData OutStart ConditionAcknowledge981SCLSDAAT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_1220168Figure 6-5.Bus TimingFigure 6-6.Write Cycle TimingNote: 1.The Write cycle time t WR is the time from a valid Stop condition of a Write sequence to the end ofthe internal Clear/Write cycle.SCLSDA InSDA OutSCLSDAStop ConditionStart Condition9AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_1220167.Device AddressingThe 32K EEPROM requires an 8-bit device address word following a Start condition to enable the chip for a Read or Write operation. The device address word consists of a mandatory ‘1010’ sequence for the first four most significant bits which is known as the device type identifier. These four bits are bit 7, bit 6, bit 5, and bit 4 as seen in Figure 7-1. This is common to all 2-wire Serial EEPROM devices.The next three bits are the A2, A1, and A0 hardware address select bits which allow as many as eight devices on the same bus. These bits must compare to their corresponding hard wired input pins, A 2, A 1, and A 0. The A 2, A 1, and A 0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.When utilizing the 5-ball WLCSP or the 5-lead SOT-23 packages, the A 2, A 1, and A 0 pins are not available. The A 2, A 1, and A 0 pins are internally pulled to ground and thus the A2, A1, and A0 device address bits must always be set to a Logic 0 to communicate with the device. This condition is depicted in Figure 7-1 below.The eighth bit of the device address is the Read/write operation select bit. A Read operation is initiated if this bit is a Logic 1, and a Write operation is initiated if this bit is a Logic 0.Upon a successful comparison of the device address, the EEPROM will output a zero during the following clock cycle. If a compare is not made, the device will not acknowledge and will instead return to a standby state.Figure 7-1.Device AddressingData Security: The AT24C32D has a hardware data protection scheme that allows the user to write protect the whole memory when the WP pin is at V CC .AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_122016108.Write OperationsByte Write : A Write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero. The addressing device, such as a microcontroller, must then terminate the write sequence with a Stop condition. At this time, the EEPROM enters an internally-timed Write cycle, t WR , to the nonvolatile memory (See Figure 6-6). All inputs are disabled during this Write cycle and the EEPROM will not respond until the Write is complete.Figure 8-1.Byte WriteNote:* = Don’t care bit.Page Write: The 32K EEPROM is capable of 32-byte Page Writes.A Page Write is initiated the same way as a Byte Write, but the microcontroller does not send a Stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 31 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the Page Write sequence with a Stop condition.The data word address lower five bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 32 data words are transmitted to the EEPROM, the data word address will roll-over and the previously loaded data will be altered. The address roll-over during Write is from the last byte of the current page to the first byte of the same page.Figure 8-2.Page WriteNote:* = Don’t care bit.Acknowledge Polling : Once the internally-timed Write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a Start condition followed by the device address word. The Read/Write bit is representative of the operation desired. Only if the internal Write cycle has completed will the EEPROM respond with a zero, allowing the Read or Write sequence to continue.S T A R TW R I T ES T O PDevice Address FirstWord Address Second Word AddressDataSDA LineM S BA C KR /W A C KA C KA CKSDA LineS T A W R I BK/W KKKKS T9.Read OperationsRead operations are initiated the same way as Write operations with the exception that the Read/Write select bit in the device address word is set to one. There are three Read operations:●Current Address Read ●Random Address Read ●Sequential ReadCurrent Address Read : The internal data word address counter maintains the last address accessed during the last Read or Write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address roll-over during read is from the last byte of the last memory page, to the first byte of the first page.Once the device address with the Read/Write select bit set to one is clocked in and acknowledged by theEEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an zero but does generate a Stop condition.Figure 9-1.Current Address ReadRandom Read: A Random Read requires a dummy Byte Write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another Start condition. The microcontroller now initiates a Current Address Read by sending a device address with the Read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a Stop condition.Figure 9-2.Random ReadNote:* = Don’t care bit.SDA LineS T A R TDevice AddressR E A DS T O PM S BA C KR /W N O A C KDataSDA LINES T A R TS T A R TR E A DW R I T ES T O PDevice Address Second Word Address Device AddressFirst Word Address Data (n)M S BA C KA C KAC KL S B A C KN O A C KR /W Dummy WriteR /W12Sequential Read: Sequential Reads are initiated by either a Current Address Read or a Random Address Read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address maximum address is reached, the data word address will roll-over and the Sequential Read will continue from the beginning of the array. The Sequential Read operation is terminated when the microcontroller does not respond with a zero but does generate a Stop condition.Figure 9-3.Sequential ReadNote:* = Don’t care bit.SDA LINESTARTSTARTREADWRITESTOP DeviceAddressSecond WordAddressDeviceAddressFirst WordAddressData (n + 1)Data (n + 2)Data (n + x)Data (n)MSBACKACKACKLSBACKACKACKACKNOACKR/WDummy Write. . .. . .R/AT24C32D [DATASHEET]10.Ordering Code DetailAtmel DesignatorProduct FamilyDevice DensityDevice RevisionShipping Carrier OptionOperating VoltagePackage Option32 = 32K24C = Standard I 2C-compatibleSerial EEPROMB = Bulk (Tubes)T = Tape and Reel, Standard Quantity Option E = Tape and Reel, Expanded Quantity OptionM = 1.7V to 5.5VSS = JEDEC SOIC X = TSSOP MA = UDFN ME = XDFN ST = SOT23U = 5-ball, 3x3 Grid Array, WLCSP C = VFBG A WWU = Wafer UnsawnWDT = Die in Tape and ReelPackage Device Grade or Wafer/Die ThicknessH = Green, NiPdAu Lead Finish, Industrial Temperature Range (-40°C to +85°C)U = Green, Matte Sn Lead Finish or SnAgCu Solder Ball Finish, Industrial Temperature Range (-40°C to +85°C)11= 11mil Wafer ThicknessA T 24C 32D -S S H M -TAT24C32D [DATASHEET]1411.Part MarkingsNotes: 1.WLCSP Package: CAUTION: Exposure to ultraviolet (UV) light can degrade the data stored in the EEPROM cells. Therefore, customers who use a WLCSP product must ensure that exposure to ultraviolet lightdoes not occur.2.Contact Atmel Sales for Wafer sales.13.18S1 — 8-lead JEDEC SOICAT24C32D [DATASHEET]1613.28X — 8-lead TSSOP13.38MA2 — 8-pad UDFNAT24C32D [DATASHEET] 1813.48ME1 — 8-pad XDFNAT24C32D [DATASHEET]2013.55TS1 — 5-lead SOT2321AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_12201613.65U-3 — 5-ball, WLCSPAT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_1220162213.78U2-1 — 8-ball VFBGA23AT24C32D [DATASHEET]Atmel-8866D-SEEPROM-AT24C32D-Datasheet_12201614.Revision HistoryX X X X X XAtmel Corporation1600 Technology Drive, San Jose, CA 95110 USAT: (+1)(408) 441.0311F: (+1)(408) 436.4200|© 2015 Atmel Corporation. / Rev.: Atmel-8866D-SEEPROM-AT24C32D-Datasheet_122016.Atmel ®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities ®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others.DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended,authorized, or warranted for use as components in applications intended to support or sustain life.SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any applications where the failure of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without an Atmel officer's specific written consent. Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapons systems.Atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by Atmel as military-grade. Atmel products are not designed nor intended for use in automotive applications unless specifically designated by Atmel as automotive-grade.。
AT24C01资料的中文翻译
ATMEL®AT24C01——两线式串行总线电可擦只读存储器1K（128*8）产品特性：•标准电压或低电压操作—5.0（Vcc=4.5V至5.5V ）—2.7（Vcc=2.7V至5.5V ）—2.5（Vcc=2.5V至5.5V ）—1.8（Vcc=1.8V至5.5V ）•内部结构128*8•两线式串行接口•双向数据传送协议•兼容100kHz（2.7V 2.5 V 1.8V）和400kHz（5V）•每页4Byte写模式•自我定时写周期（最大10ms）•可靠性高—100万次擦写—数据保存100年—静电保护大于3000V•自动等级分划、可扩张温度元件•8引脚双列直插，8引脚超小型外形封装，8引脚超薄紧缩小型封装和8引脚JEDEC小外型集成电路封装性能描述：AT24C01提供128*8的1024bit可擦出编程只读存储器。
被广泛应用于低电压、低耗能要求的工业和商业。
可在8引脚PDIP, 8引脚MSOP, 8引脚TSSOP, and 8引脚JEDEC SOIC封装下进行存储，通过两线式串行总线进行读取。
这个芯片系列均支持2.7V（2.7V to 5.5V）、2.5 V(2.5V to 5.5V) 、1.8 (1.8V to 5.5V)和5V(4.5V to 5.5V)。
引脚名称功能NC 无连接SDA 串行数据SCL 串行时钟输入Test 测试输入(接地或接电压)绝对最大功率：运行温度…………-55°至+125°存储温度…………-65°至+150°引脚承受最高电压…………-1V至+7V运行最大电压…………6.25V直流最大电流…………5.0mA*注意：超过上述参数工作会损坏本元件，这是唯一的功能操作参数，超过此功率将不被支持。
按照额定功率工作将使元件更加可靠。
模块图引脚描述：SERIAL CLOCK (SCL):SCL引脚在电压上升沿时输入数据，下降沿时输出数据SERIAL DATA (SDA):SDA引脚用作双向传送数据，高电平驱动可能与其它任何引脚或元件进行线或运算。
IS24C32C中文资料
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.IS24C32C32K-bit2-WIRE SERIAL CMOS EEPROMJANUARY 2008DESCRIPTIONThe IS24C32C is electrically erasable PROM devices that use the standard 2-wire interface for communications. The IS24C32C contains amemory array of 32K-bits (4K x 8). Each device is organized into 32 byte pages for page write mode.This EEPROM operates in a wide voltage range of 1.8V to 5.5V to be compatible with most application voltages. ISSI designed this device family to be a practical, low-power 2-wire EEPROM solution.The devices are available in 8-pin PDIP, 8-pinSOIC, 8-pin TSSOP, 8-pad DFN, and 8-pin MSOP packages.The IS24C32C maintains compatibility with the popular 2-wire bus protocol, so it is easy to use in applications implementing this bus type. Thesimple bus consists of the Serial Clock wire (SCL)and the Serial Data wire (SDA). Using the bus, a Master device such as a microcontroller is usually connected to one or more Slave devices such as this device. The bit stream over the SDA line includes a series of bytes, which identifies aparticular Slave device, an instruction, an address within that Slave device, and a series of data, if appropriate. The IS24C32C has a Write Protect pin (WP) to allow blocking of any write instruction transmitted over the bus.FEATURES•Two-Wire Serial Interface, I 2C TM Compatible– Bi-directional data transfer protocol •Wide Voltage Operation– Vcc = 1.8V to 5.5V•400 KHz (2.5V) and 1MHz (5.0V) Compatible •Low Power CMOS Technology– Standby Current: 1 µA or less (1.8V)– Read Current: 2 mA or less (5.0V)– Write Current: 3 mA or less (5.0V)•Hardware Data Protection– protects entire array •Sequential Read Feature•Filtered Inputs for Noise Suppression •Self time write cycle with auto clear 5 ms max.@ 2.5V •Organization:– 4Kx8 (128 pages of 32 bytes)•32 Byte Page Write Buffer •High Reliability– Endurance: 1,000,000 Cycles – Data Retention: 100 Years•Automotive and Industrial temperature ranges •8-pin PDIP, 8-pin SOIC, 8-pin SOP, 8-pinTSSOP, 8-pad DFN, and 8-pin MSOP packages •Lead-free AvailableIS24C32CFUNCTIONAL BLOCK DIAGRAM2Integrated Silicon Solution, Inc.Rev.BIS24C32CPIN DESCRIPTIONSA0-A2Address InputsSDA Serial Address/Data I/O SCL Serial Clock Input WP Write Protect Input Vcc Power Supply GNDGroundSCLThis input clock pin is used to synchronize the data transfer to and from the device.SDAThe SDA is a Bi-directional pin used to transfer addresses and data into and out of the device. The SDA pin is an open drain output and can be wire-Ored with other open drain or open collector outputs. The SDA bus requires a pullup resistor to Vcc.A0, A1, A2The A0, A1 and A2 are the device address inputs that are hardwired or left not connected for hardware compatibility with the 24C16. When pins are hardwired, as many as eight 32K devices may be addressed on a single bus system.When the pins are not hardwired, the default values of A0,A1, and A2 are zero.WPWP is the Write Protect pin. The input level determines if all or none of the array is protected from modifications.PIN CONFIGURATION8-Pin DIP, SOIC, TSSOP, and MSOP12348765A0A1A2GNDVCC WP SCL SDAWrite ProtectionArray A ddresses P rotectedWPIS24C32C GND o r f loating N o n e VccEntire A rray8-pad DFN(Top View)12348765A0A1A2GND VCC WP SCL SDAIS24C32CDEVICE OPERATIONIS24C32C features serial communication and supports a bi-directional 2-wire bus transmission protocol called I2C TM. 2-WIRE BUSThe two-wire bus is defined as a Serial Data line (SDA), and a Serial Clock line (SCL).The protocol defines any device that sends data onto the SDA bus as a transmitter, and the receiving devices as receivers.The bus is controlled by a Master device that generates the SCL, controls the bus access, and generates the Stop and Start conditions.The IS24C32C is the Slave device on the bus.The Bus Protocol:–Data transfer may be initiated only when the bus is not busy–During a data transfer, the SDA line must remain stable whenever the SCL line is high.Any changes in the SDA line while the SCL line is high will be interpreted as a Start or Stop condition.The state of the SDA line represents valid data after a Start condition. The SDA line must be stable for the duration of the High period of the clock signal.The data on the SDA line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data.Each data transfer is initiated with a Start condition and terminated with a Stop condition.Start ConditionThe Start condition precedes all commands to the device and is defined as a H igh to Low transition of SDA when SCL is H igh. The EEPROM monitors the SDA and SCL lines and will not respond until the Start condition is met.Stop ConditionThe Stop condition is defined as a Low to High transition of SDA when SCL is H igh. All operations must end with a Stop condition.Acknowledge (ACK)After a successful data transfer, each receiving device is required to generate an ACK.The Acknowledging device pulls down the SDA line.ResetThe IS24C32C contains a reset function in case the 2-wire bus transmission is accidentally interrupted (eg. a power loss), or needs to be terminated mid-stream. The reset is caused when the Master device creates a Start condition. To do this, it may be necessary for the Master device to monitor the SDA line while cycling the SCL up to nine times. (For each clock signal transition to High, the Master checks for a High level on SDA.)Standby ModePower consumption is reduced in standby mode. The IS24C32C will enter standby mode: a) At Power-up, and remain in it until SCL or SDA toggles; b) Following the Stop signal if a no write operation is initiated; or c) Following any internal write operation.4Integrated Silicon Solution, Inc.Rev.BIS24C32CWRITE OPERATION Byte WriteIn the Byte Write mode, the Master device sends the Start condition and the Slave address information (with the R/W set to Zero) to the Slave device.After the Slave generates an ACK, the Master sends the two byte address that is to be written into the address pointer of the IS24C32C.After receiving another ACK from the Slave, the Master device transmits the data byte to be written into the address memory location.The IS24C32C acknowledges once more and the Master generates the Stop condition, at which time the device begins its internal programming cycle.While this internal cycle is in progress, the device will not respond to any request from the Master device.Page WriteThe IS24C32C is capable of 32-byte Page-Write operation.A Page-Write is initiated in the same manner as a Byte Write,but instead of terminating the internal Write cycle after the first data word is transferred, the Master device can transmit up to 31 more bytes.After the receipt of each data word, the EEPROM responds immediately with an ACK on SDA line,and the five lower order data word address bits are internally incremented by one, while the higher order bits of the data word address remain constant. If a byte address is incremented from the last byte of a page, it returns to the first byte of that page. If the Master device should transmit more than 32 bytes prior to issuing the Stop condition, the address counter will “roll over,” and the previously written data will be overwritten.Once all 32 bytes are received and the Stop condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the IS24C32C in a single Write cycle. All inputs are disabled until completion of the internal Write cycle.Acknowledge (ACK) PollingThe disabling of the inputs can be used to take advantage of the typical Write cycle time.Once the Stop condition is issued to indicate the end of the host's Write operation, the IS24C32C initiates the internal Write cycle. ACK polling can be initiated immediately.This involves issuing the Start condition followed by the Slave address for a Write operation.If the EEPROM is still busy with the Write operation, no ACK will be returned.If the IS24C32C has completed the Write operation, an ACK will be returned and the host can then proceed with the next Read or Write operation.DEVICE ADDRESSINGThe Master begins a transmission by sending a Start condition.The Master then sends the address of the particular Slave devices it is requesting. The Slave device (Fig. 5) address is 8 bits.The four most significant bits of the Slave address are fixed as 1010 for the IS24C32C.The next three bits of the Slave address are A0, A1, and A2,and are used in comparison with the hard-wired input values on the A0, A1, and A2 pins. Up to eight IS24C32C units may share the 2-wire bus.The last bit of the Slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected.After the Master transmits the Start condition and Slave address byte (Fig. 5), the appropriate 2-wire Slave,IS24C32C, will respond with ACK on the SDA line. The Slave will pull down the SDA on the ninth clock cycle,signaling that it received the eight bits of data. The selected EEPROM then prepares for a Read or Write operation by monitoring the bus.IS24C32CREAD OPERATIONRead operations are initiated in the same manner as Write operations, except that the (R/W) bit of the Slave address is set to “1”.There are three Read operation options: current address read, random address read and sequential read. Current Address ReadThe IS24C32C contains an internal address counter which maintains the address of the last byte accessed, incremented by one.For example, if the previous operation is either a Read or Write operation addressed to the address location n, the internal address counter would increment to address location n+1.When the EEPROM receives the Slave Addressing Byte with a Read operation (R/W bit set to “1”), it will respond an ACK and transmit the 8-bit data byte stored at address location n+1.The Master should not acknowledge the transfer but should generate a Stop condition so the IS24C32C discontinues transmission.If 'n' is the last byte of the memory, the data from location '0' will be transmitted. (Refer to Figure 8. Current Address Read Diagram.)Random Address ReadSelective Read operations allow the Master device to select at random any memory location for a Read operation.The Master device first performs a 'dummy' Write operation by sending the Start condition, Slave address and byte address of the location it wishes to read. After the IS24C32C acknowledges the byte address, the Master device resends the Start condition and the Slave address, this time with the R/W bit set to one.The EEPROM then responds with its ACK and sends the data requested.The Master device does not send an ACK but will generate a Stop condition.(Refer to Figure 9. Random Address Read Diagram.)Sequential ReadSequential Reads can be initiated as either a Current Address Read or Random Address Read.After the IS24C32C sends the initial byte sequence, the Master device now responds with an ACK indicating it requires additional data from the IS24C32C. The EEPROM continues to output data for each ACK received.The Master device terminates the sequential Read operation by pulling SDA High (no ACK) indicating the last data word to be read, followed by a Stop condition.The data output is sequential, with the data from address n followed by the data from address n+1, n+2 ... etc.The address counter increments by one automatically, allowing the entire memory contents to be serially read during sequential Read operation.When the memory address boundary of 8191 for IS24C32C is reached, the address counter “rolls over” to address 0, and the device continues to output data. (Refer to Figure 10. Sequential Read Diagram).6Integrated Silicon Solution, Inc.Rev.BIS24C32CFigure 1. Typical System Bus ConfigurationFigure 2. Output AcknowledgeFigure 3. START and STOP ConditionsIS24C32CFigure 4. Data Validity ProtocolFigure 6. Byte WriteFigure 7. Page Write8Integrated Silicon Solution, Inc.Rev.BIS24C32CFigure 8. Current Address Read ArrayFigure 9. Random Address ReadFigure 10. Sequential Read10Integrated Silicon Solution, Inc.Rev.BIS24C32CABSOLUTE MAXIMUM RATINGS (1)Symbol Parameter Value Unit V S Supply Voltage –0.5 to +6.5V V P Voltage on Any Pin–0.5 to Vcc + 0.5V T BIAS Temperature Under Bias –55 to +125°C T STG Storage Temperature –65 to +150°C I OUTOutput Current5mANotes:1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may causepermanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.OPERATING RANGE (IS24C32C-2)Range Ambient TemperatureV CCIndustrial–40°C to +85°C1.8V to 5.5VNote: ISSI offers Industrial grade for Commerical applications (0o C to +70o C).CAPACITANCE (1,2)Symbol ParameterConditions Max.Unit C IN Input Capacitance V IN = 0V 6pF C OUTOutput CapacitanceV OUT = 0V8pFNotes:1.Tested initially and after any design or process changes that may affect these parameters.2.Test conditions: T A = 25°C, f = 1 MHz, Vcc = 5.0V.OPERATING RANGE (IS24C32C-3)RangeAmbient Temperature V CCAutomotive–40°C to +125°C2.5V to 5.5VAC WAVEFORMSFigure 11. Bus TimingFigure 12. Write Cycle TimingDC ELECTRICAL CHARACTERISTICS Industrial (T A = -40o C to +85o C), Automotive (T A = -40o C to +125o C) Symbol Parameter Test Conditions Min.Max.Unit V OL1Output Low Voltage V CC = 1.8V, I OL = 0.15 mA—0.2V V OL2Output Low Voltage V CC = 2.5V, I OL = 3 mA—0.4V V IH Input High Voltage V CC X 0.7V CC + 0.5V V IL Input Low Voltage–1.0V CC X 0.3VI LI Input Leakage Current V IN = V CC max.—3µAI LO Output Leakage Current—3µA Notes:V IL min and V IH max are reference only and are not tested.POWER SUPPLY CHARACTERISTICS Industrial (T A = -40o C to +85o C), Automotive (T A = -40o C to +125o C) Symbol Parameter Test Conditions Min.Max.UnitI CC1Operating Current Read at 400 KHz (Vcc = 5V)— 2.0mAI CC2Operating Current Write at 400 KHz (Vcc = 5V)— 3.0mAI SB1Standby Current Vcc = 1.8V—1µAI SB2Standby Current Vcc = 2.5V—2µAI SB3Standby Current Vcc = 5.0V—6µAAC ELECTRICAL CHARACTERISTICS Industrial (T A = -40o C to +85o C)1.8V ≤Vcc <2.5V 2.5V ≤Vcc < 4.5V 4.5V ≤Vcc ≤ 5.5V(1) Symbol Parameter Min.Max.Min.Max.Min.Max.Unit f SCL SCL Clock Frequency0100040001000KHz T Noise Suppression Time(1)—100—50—50nst Low Clock Low Period 4.7— 1.2—0.6—µst High Clock H igh Period4—0.6—0.4—µst BUF Bus Free Time Before New Transmission(1) 4.7— 1.2—0.5—µst SU:STA Start Condition Setup Time4—0.6—0.25—µst SU:STO Stop Condition Setup Time4—0.6—0.25—µst HD:STA Start Condition H old Time4—0.6—0.25—µst HD:STO Stop Condition H old Time4—0.6—0.25—µst SU:DAT Data In Setup Time100—100—100—nst HD:DAT Data In H old Time0—0—0—nst SU:WP WP pin Setup Time4—0.6—0.6—µst HD:WP WP pin H old Time 4.7— 1.2— 1.2—µst DH Data Out H old Time100—50—50—ns (SCL Low to SDA Data Out Change)t AA Clock to Output10035005090050400ns (SCL Low to SDA Data Out Valid)t R SCL and SDA Rise Time(1)—1000—300—300nst F SCL and SDA Fall Time(1)—300—300—100nst WR Write Cycle Time—5—5—5ms Note:1. These parameters are characterized but not 100% tested.12Integrated Silicon Solution, Inc.Rev.BAC ELECTRICAL CHARACTERISTICS Automotive (T A = -40o C to +125o C)2.5V ≤Vcc < 4.5V 4.5V ≤Vcc ≤ 5.5V(1) Symbol Parameter Min.Max.Min.Max.Unit f SCL SCL Clock Frequency040001000KH z T Noise Suppression Time(1)—50—50ns t Low Clock Low Period 1.2—0.6—µs t High Clock High Period0.6—0.4—µs t BUF Bus Free Time Before New Transmission(1) 1.2—0.5—µs t SU:STA Start Condition Setup Time0.6—0.25—µs t SU:STO Stop Condition Setup Time0.6—0.25—µs t HD:STA Start Condition Hold Time0.6—0.25—µs t HD:STO Stop Condition Hold Time0.6—0.25—µs t SU:DAT Data In Setup Time100—100—ns t HD:DAT Data In Hold Time0—0—ns t SU:WP WP pin Setup Time0.6—0.6—µs t HD:WP WP pin Hold Time 1.2— 1.2—µs t DH Data Out Hold Time (SCL Low to SDA Data Out Change)50—50—ns t AA Clock to Output (SCL Low to SDA Data Out Valid)5090050550ns t R SCL and SDA Rise Time(1)—300—300ns t F SCL and SDA Fall Time(1)—300—100ns t WR Write Cycle Time—10—5ms Note:1. These parameters are characterized but not 100% tested.ORDERING INFORMATIONIndustrial Range: -40°C to +85°C, Lead-freeVoltageRange Part Number Package1.8V IS24C32C-2DLI*8-pad 2x3 mm DFNIS24C32C-2PLI*8-pin 300-mil Plastic DIPto 5.5V IS24C32C-2GLI8-pin 150-mil SOIC (JEDEC STD)IS24C32C-2ZLI8-pin 3x4.4 mm TSSOPIS24C32C-2SLI*8-pin 120-mil MSOPORDERING INFORMATIONAutomotive Range: -40°C to +125°C, Lead-freeVoltageRange Part Number Package2.5V IS24C32C-3PLA3*8-pin 300-mil Plastic DIPto 5.5V IS24C32C-3GLA38-pin 150-mil SOIC (JEDEC STD)IS24C32C-3ZLA38-pin 3x4.4 mm TSSOP* Please contact ISSI Sales Rep for availability.14Integrated Silicon Solution, Inc.Rev.BDual Flat No-Lead Package Code: D (8-pad)300-mil Plastic DIPPackage Code: N,P16Integrated Silicon Solution, Inc.Rev.B150-mil Plastic SOPThin Shrink Small Outline TSSOPPackage Code: Z (8 pin, 14 pin)18Integrated Silicon Solution, Inc.Rev.BPlastic M S OP Package Code: SREVISION HISTORYRev.Date DescriptionA April 2007Draft versionB January 2008Initial version for product launch20Integrated Silicon Solution, Inc.Rev.B。
AT24C32AN-10SJ-1.8中文资料
1Features•Low-Voltage and Standard-Voltage Operation –2.7 (V CC = 2.7V to 5.5V)–1.8 (V CC = 1.8V to 5.5V)•Low-Power Devices (I SB = 6 µA @ 5.5V) Available •Internally Organized 4096 x 8, 8192 x 8•2-Wire Serial Interface•Schmitt Trigger, Filtered Inputs for Noise Suppression •Bidirectional Data Transfer Protocol•100 kHz (1.8V) and 400 kHz (2.5V) Clock Rate for AT24C32A •400 kHz (1.8V) Clock Rate for AT24C64A•Write Protect Pin for Hardware Data Protection•32-Byte Page Write Mode (Partial Page Writes Allowed)•Self-Timed Write Cycle (5 ms Max)•High Reliability–Endurance: 1 Million Write Cycles –Data Retention: 100 Years•Automotive Grade, Extended Temperature and Lead-free/Halogen-free Devices Available•8-lead JEDEC PDIP , 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead MAP and 8-lead TSSOP PackagesDescriptionThe AT24C32A/64A provides 32,768/65,536 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 4096/8192 words of 8 bits each. The device’s cascadable feature allows up to 8 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applica-tions where low power and low voltage operation are essential. The A T24C32A/64A is available in space saving 8-lead JEDEC PDIP , 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead MAP and 8-lead TSSOP packages and is accessed via a 2-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V(1.8V to 5.5V) versions.Pin ConfigurationsPin Name Function A0 - A2Address Inputs SDA Serial DataSCL Serial Clock Input WPWrite Protect8-lead PDIP8-lead SOIC8-lead TSSOP8-lead MAPBottom View2AT24C32A/64A3054N–SEEPR–2/04Block DiagramAbsolute Maximum Ratings*Operating Temperature.................................-55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam-age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage Temperature....................................-65°C to +150°C Voltage on Any Pinwith Respect to Ground.....................................-1.0V to +7.0V Maximum Operating Voltage ..........................................6.25V DC Output Current........................................................5.0 mA3AT24C32A/64A3054N–SEEPR–2/04Pin DescriptionSERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices.DEVICE/ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hardwired or left not connected for hardware compatibility with other AT24Cxx devices. When the pins are hardwired, as many as eight 32K/64K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). If the pins are left floating, the A2, A1 and A0 pins will be internally pulled down to GND if the capacitive coupling to the circuit board V CC plane is <3 pF. If coupling is >3 pF, Atmel recommends connecting the address pins to GND.WRITE PROTECT (WP): The write protect input, when connected to GND, allows nor-mal write operations. When WP is connected high to V CC , all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND if the capacitive coupling to the circuit board V CC plane is <3 pF. If coupling is >3pF, Atmel recommends connecting the pin to GND. Switching WP to V CC prior to a write operation creates a software write protect function.Memory OrganizationAT24C32A/64A, 32K/64K SERIAL EEPROM: The 32K/64K is internally organized as 128/256 pages of 32 bytes each. Random word addressing requires a 12/13-bit data word address.4AT24C32A/64A3054N–SEEPR–2/04Note:1.This parameter is characterized and is not 100% tested.Note:1.V IL min and V IH max are reference only and are not tested.Pin Capacitance (1)Applicable over recommended operating range from T A = 25°C, f = 1.0 MHz, V CC = +1.8V.Symbol Test ConditionMax Units Conditions C I/O Input/Output Capacitance (SDA)8pF V I/O = 0V C IN Input Capacitance (A 0, A 1, A 2, SCL)6pFV IN = 0VDC CharacteristicsApplicable over recommended operating range from: T AI = -40°C to +85°C, V CC = +1.8V to +5.5V, T AE = -40°C to +125°C,V CC = +1.8V to +5.5V (unless otherwise noted).Symbol Parameter Test ConditionMin TypMax Units V CC1Supply Voltage 1.8 5.5V V CC2Supply Voltage 2.5 5.5V V CC3Supply Voltage 2.7 5.5V V CC4Supply Voltage 4.55.5V I CC1Supply Current V CC = 5.0V READ at 400 kHz 0.4 1.0mA I CC2Supply Current V CC = 5.0V WRITE at 400 kHz 2.0 3.0mA I SB1Standby Current (1.8V option)V CC = 1.8V V IN = V CC or V SS 1.0µA I SB2Standby Current (2.5V option)V CC = 2.5V V IN = V CC or V SS 2.0µA I SB3Standby Current (2.7V option)V CC = 2.7V V IN = V CC or V SS 2.0µA I SB4Standby Current (5V option)V CC = 4.5 - 5.5V V IN = V CC or V SS6.0µA I LI Input Leakage CurrentV IN = V CC or V SS 0.10 3.0µA I LO Output Leakage CurrentV OUT = V CC or V SS0.053.0µA V IL Input Low Level (1)-0.6V CC x 0.3V V IH Input High Level (1)V CC x 0.7V CC + 0.5V V OL2Output Low Level V CC = 3.0V I OL = 2.1 mA 0.4V V OL1Output Low LevelV CC = 1.8VI OL = 0.15 mA0.2V5AT24C32A/64A3054N–SEEPR–2/04Notes:1.This parameter is characterized and is not 100% tested (T A = 25°C).2.This parameter is characterized and is not 100% tested.3.The Write Cycle Time of 5 ms only applies to the A T24C32A/64A devices bearing the process letter “A” on the package (themark is located in the lower right corner on the top side of the package).AC CharacteristicsApplicable over recommended operating range from T AI = -40°C to +85°C, T AE = -40°C to +125°C, V CC = +1.8V to +5.5V,CL = 1 TTL Gate and100 pF (unless otherwise noted).Symbol ParameterAT24C32A AT24C64AUnits 1.8V2.5V – 5.0V 1.8V –3.6V 5.0VMinMax MinMax MinMax MinMax f SCL Clock Frequency, SCL 100400400400kHz t LOW Clock Pulse Width Low 4.7 1.3 1.3 1.2µs t HIGH Clock Pulse Width High 4.00.60.60.6µs t I Noise Suppression Time (1)1005010050ns t AA Clock Low to Data Out Valid 0.1 4.50.10.90.20.90.10.9µs t BUF Time the bus must be free before a new transmission can start (2) 4.7 1.3 1.3 1.2µs t HD.STA Start Hold Time 4.00.60.60.6µs t SU.STA Start Set-up Time 4.70.60.60.6µs t HD.DAT Data In Hold Time 0000µs t SU.DA T Data In Set-up Time 200100100100ns t R Inputs Rise Time (2) 1.00.30.30.3µs t F Inputs Fall Time (2)300300300300ns t SU.STO Stop Set-up Time 4.70.60.60.6µs t DH Data Out Hold Time 1005020050ns t WRWrite Cycle Time 20 or 5(3)10 or 5(3)20 or 5(3)10 or 5(3)ms Endurance (1) 5.0V , 25°C, Page Mode1M 1M1M1MWrite Cycles6AT24C32A/64A3054N–SEEPR–2/04Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-nal device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word.STANDBY MODE: The AT24C32A/64A features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps:(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition as SDA is high.7AT24C32A/64A3054N–SEEPR–2/04Bus TimingSCL: Serial Clock, SDA: Serial Data I/OWrite Cycle TimingSCL: Serial Clock, SDA: Serial Data I/ONote:1.The write cycle time t WRis the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.8AT24C32A/64A3054N–SEEPR–2/04Data ValidityStart and Stop DefinitionOutput Acknowledge9AT24C32A/64A3054N–SEEPR–2/04Device AddressingThe 32K/64K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 1). The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all 2-wire EEPROM devices.The 32K/64K uses the three device address bits A2, A1, A0 to allow as many as eight devices on the same bus. These bits must compare to their corresponding hardwired input pins. The A2, A1, and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.The eighth bit of the device address is the read/write operation select bit. A read opera-tion is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to standby state.NOISE PROTECTION: Special internal circuitry placed on the SDA and SCL pins pre-vent small noise spikes from activating the device.DATA SECURITY: The AT24C32A/64A has a hardware data protection scheme that allows the user to write protect the entire memory when the WP pin is at V CC .Write OperationsBYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condi-tion. At this time the EEPROM enters an internally-timed write cycle, t WR , to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 2).PAGE WRITE: The 32K/64K EEPROM is capable of 32-byte page writes.A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 31more data words. The EEPROM will respond with a zero after each data word received.The microcontroller must terminate the page write sequence with a stop condition (refer to Figure 3).The data word address lower 5 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 32 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten.ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-ing a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero, allowing the read or write sequence to continue.10AT24C32A/64A3054N–SEEPR–2/04Read OperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read.CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page, to the first byte of the first page. The address “roll over” during write is from the last byte of the cur-rent page to the first byte of the same page.Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out.The microcontroller does not respond with an input zero but does generate a following stop condition (refer to Figure 4).RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 5).SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequen-tial read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condi-tion (refer to Figure 6).11AT24C32A/64A3054N–SEEPR–2/04Figure 1. Device AddressFigure 2. Byte WriteFigure 3. Page WriteNotes:1.* = DON’T CARE bits2.† = DON’T CARE bits for the 32KFigure 4.Current Address Read12AT24C32A/64A3054N–SEEPR–2/04Figure 5. Random ReadNote: 1.* = DON’T CARE bitsFigure 6.Sequential Read13AT24C32A/64A3054N–SEEPR–2/04Note:For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables.AT24C32A Ordering InformationOrdering Code Package Operation RangeA T24C32A-10PI-2.7A T24C32AN-10SI-2.7A T24C32AW-10SI-2.7A T24C32A-10TI-2.7A T24C32AY1-10YI-2.78P38S18S28A28Y1Industrial Temperature (-40°C to 85°C)A T24C32A-10PI-1.8A T24C32AN-10SI-1.8A T24C32AW-10SI-1.8A T24C32A-10TI-1.8A T24C32AY1-10YI-1.88P38S18S28A28Y1Industrial Temperature (-40°C to 85°C)A T24C32AN-10SU-2.7A T24C32AN-10SU-1.8A T24C32A-10TU-2.7A T24C32A-10TU-1.88S18S18A28A2Lead-free/Halogen-free/Industrial Temperature (-40°C to 85°C)A T24C32AN-10SQ-2.78S1Lead-free/Halogen-free/High Grade/Extended Temperature(-40°C to 125°C))A T24C32AN-10SE-2.78S1High Grade/Extended Temperature(-40°C to 125°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8S28-lead, 0.209" Body, Plastic Small Outline (EIAJ SOIC)8A28-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)Options-2.7Low Voltage (2.7V to 5.5V)-1.8Low Voltage (1.8V to 5.5V)14AT24C32A/64A3054N–SEEPR–2/04Note:For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables.AT24C64A Ordering InformationOrdering Code Package Operation RangeA T24C64A-10PI-2.7A T24C64AN-10SI-2.7A T24C64AW-10SI-2.7A T24C64A-10TI-2.7A T24C64AY1-10YI-2.78P38S18S28A28Y1Industrial Temperature (-40°C to 85°C)A T24C64A-10PI-1.8A T24C64AN-10SI-1.8A T24C64AW-10SI-1.8A T24C64A-10TI-1.8A T24C64AY1-10YI-1.88P38S18S28A28Y1Industrial Temperature (-40°C to 85°C)A T24C64AN-10SU-2.7A T24C64AN-10SU-1.8A T24C64A-10TU-2.7A T24C64A-10TU-1.88S18S18A28A2Lead-free/Halogen-free/Industrial Temperature (-40°C to 85°C)A T24C64AN-10SQ-2.78S1Lead-free/Halogen-free/High Grade/Extended Temperature(-40°C to 125°C))A T24C64AN-10SE-2.78S1High Grade/Extended Temperature(-40°C to 125°C)Package Type8P38-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)8S18-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)8S28-lead, 0.209" Body, Plastic Small Outline (EIAJ SOIC)8A28-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)8Y18-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)Options-2.7Low Voltage (2.7V to 5.5V)-1.8Low Voltage (1.8V to 5.5V)15AT24C32A/64A3054N–SEEPR–2/04Package Drawings8P3 – PDIP16AT24C32A/64A3054N–SEEPR–2/048S1 – JEDEC SOIC17AT24C32A/64A3054N–SEEPR–2/048S2 – EIAJ SOIC18AT24C32A/64A3054N–SEEPR–2/048A2 – TSSOP19AT24C32A/64A3054N–SEEPR–2/048Y1 – MAP3054N–SEEPR–2/04xMDisclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.Atmel CorporationAtmel Operations2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 487-2600Regional HeadquartersEuropeAtmel SarlRoute des Arsenaux 41Case Postale 80CH-1705 Fribourg SwitzerlandTel: (41) 26-426-5555Fax: (41) 26-426-5500AsiaRoom 1219Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong KongTel: (852) 2721-9778Fax: (852) 2722-1369Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Memory2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314Microcontrollers2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314La Chantrerie BP 7060244306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18Fax: (33) 2-40-18-19-60ASIC/ASSP/Smart CardsZone Industrielle13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00Fax: (33) 4-42-53-60-011150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300Fax: 1(719) 540-1759Scottish Enterprise Technology Park Maxwell BuildingEast Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000Fax: (44) 1355-242-743RF/AutomotiveTheresienstrasse 2Postfach 353574025 Heilbronn, Germany Tel: (49) 71-31-67-0Fax: (49) 71-31-67-23401150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300Fax: 1(719) 540-1759Biometrics/Imaging/Hi-Rel MPU/High Speed Converters/RF DatacomAvenue de Rochepleine BP 12338521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00Fax: (33) 4-76-58-34-80Literature Requests/literature© Atmel Corporation 2004. All rights reserved. Atmel ® and combinations thereof, are the registered trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others.。
AT24C32AT24C56读写程序
转载一个AT24C01～AT24C256读写通用程序（只做了少许改动），附件里面有关于AT24系列读写资料！希望对大家有所帮助，共同进步！/* 以下为AT24C01～A T24C256的读写程序，各人可根据自己的需要应用。
在bu f1中填入需要写入的内容，bu f2的大小可根据需要定义。
a ddr可根据使用的芯片选择，可从任何位置读写，只要在该芯片的范围内。
enume r=ATx xx，根据使用的芯片赋值。
各函数中的形式参数不需改变。
本程序只要在调用的程序中定义实际参数即可，下述各子程序不必改动。
*/#inclu de <r eg52.h>#i nclud e <in trins.h>#defin e ER ROR 10 //允许ERROR的最大次数sb it SDA=P3^0;sbi t SCL=P3^1;enum eep romty pe{A T2401,AT2402,AT2404,AT2408,AT2416,A T2432,AT2464,AT24128,AT24256};/*器件的型号*/enum eepr omtyp e enu mer; //定义一个枚举变量un signe d cha r cod e buf1 []={1,3,5,7,9,10,11,12,13,15}; /*发送缓冲区 */unsig ned c har b uf2 [10];/* 接收缓冲区*//*一个通用的24C01－24C256共9种EEPR OM的字节读写操作程序，此程序有五个入口条件，分别为读写数据缓冲区指针,进行读写的字节数，EEP ROM首址，EEPR OM控制字节，以及EEPRO M类型。
AT24C32使用方法总结
A T24C32使用方法总结(总2页)-CAL-FENGHAI.-(YICAI)-Company One1-CAL-本页仅作为文档封面，使用请直接删除AT24C32使用方法总结 2011-04-29 16:56:58分类：LINUXAT24C32是2-Wire Serial EEPROM，容量为32Kbits（4096*8）。
利用该芯片可以模拟I2C总线，如果采用IO口来进行模拟，可以采用二线制（SCL、SDA），也可以采用三线制（WP、SCL、SDA）。
在编写驱动程序时，要分为两个层次。
第一、针对IIC总线的驱动部分。
第二、针对AT24C32的驱动部分。
Dynamic C里面的IO模拟IIC函数库采用的是二线制，针对的芯片是24C02。
如果要用，就需要进行相应的改进。
下面把使用该芯片时注意的地方总结如下：1、各个引脚的含义A0-A2：地址线，用来选择slave器件。
WP：Write Protect写保护，高电平拒绝写入，低电平可以写入，即低电平有效。
SCL：Serial Clock 串行时钟，用来指示什么时候数据线上是有效数据。
SDA：Serial Data串行数据，用于数据传送2、关于WP脚二线制没有WP，也就是把WP置为低电平，始终写有效。
这样的问题是，在上电或调电的时候，可能会发生异常情况，对EEPROM内数据有所改动。
所以，如果有重要的数据，还是要采用WP引脚比较安全。
对AT24C32来说，WP置高，则只有四分之一受保护，即0x0C00－0x0FFF。
也就是说保护区为1KBytes。
对于低地址的四分之三，则不保护。
所以，如果数据较多时，可以有选择地存储。
不重要的数据则放在低四分之三区域，重要的数据则放在高四分之一区域。
看IC Datasheet，一定要仔细。
初次写测试程序时，发现WP不起作用，常有效。
用万用表测试，确实是高电平。
经过仔细阅读WP引脚说明，发现只有高四分之一区域可以写保护。
【Z】TC32使用方法总结413
AT24C32使用方法汇总报告 2011-04-29 16:56:58分类：LINUXAT24C32是2-Wire Serial EEPROM，容量为32Kbits（4096*8）。
利用该芯片可以模拟I2C总线，如果采用IO口来进行模拟，可以采用二线制（SCL、SDA），也可以采用三线制（WP、SCL、SDA）。
在编写驱动程序时，要分为两个层次。
第一、针对IIC总线的驱动部分。
第二、针对AT24C32的驱动部分。
Dynamic C里面的IO模拟IIC函数库采用的是二线制，针对的芯片是24C02。
如果要用，就需要进行相应的改进。
下面把使用该芯片时注意的地方汇总报告如下：1、各个引脚的含义A0-A2：地址线，用来选择slave器件。
WP：Write Protect写保护，高电平拒绝写入，低电平可以写入，即低电平有效。
SCL：Serial Clock 串行时钟，用来指示什么时候数据线上是有效数据。
SDA：Serial Data 串行数据，用于数据传送2、关于WP脚二线制没有WP，也就是把WP置为低电平，始终写有效。
这样的问题是，在上电或调电的时候，可能会发生异常情况，对EEPROM内数据有所改动。
所以，如果有重要的数据，还是要采用WP引脚比较安全。
对AT24C32来说，WP置高，则只有四分之一受保护，即0x0C00－0x0FFF。
也就是说保护区为1KBytes。
对于低地址的四分之三，则不保护。
所以，如果数据较多时，可以有选择地存储。
不重要的数据则放在低四分之三区域，重要的数据则放在高四分之一区域。
看IC Datasheet，一定要仔细。
初次写测试程序时，发现WP不起作用，常有效。
用万用表测试，确实是高电平。
经过仔细阅读WP引脚说明，发现只有高四分之一区域可以写保护。
改变地址后，测试成功。
整个驱动函数也就修改成功了。
WP：The write protect input, when tied to GND, allows normal write operations.When WP is tied high to Vcc, all write operations to the upperquandrant(8Kbits) of memory are inhibited. If left unconnected, WP is internally pulled down to GND.3、关于读写进程安排AT24C32的数据地址必须要先发高字节地址，再发低字节地址。
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© 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without noticeDoc. No. 25083-00 12/989-1CAT24C321/322/641/6422AdvancedDoc. No. 25083-00 12/98ABSOLUTE MAXIMUM RATINGS*Temperature Under Bias....................–55°C to +125°C Storage Temperature........................ –65°C to +150°C Voltage on Any Pin withRespect to Ground (1) ..............–2.0V to +V CC + 2.0V V CC with Respect to Ground..................–2.0V to +7.0V Package Power DissipationCapability (Ta = 25°C)1.0W.................................1.0W Lead Soldering Temperature (10 secs)...............300°C Output Short Circuit Current (2) ..........................100mACOMMENTStresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specifica-tion is not implied. Exposure to any absolute maximum rating for extended periods may affect device perfor-mance and reliability.RELIABILITY CHARACTERISTICSSymbol Parameter Min.Max. Units Reference Test MethodN END (3)Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033 T DR (3)Data Retention 100 Years MIL-STD-883, Test Method 1008 V ZAP (3)ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 I LTH (3)(4)Latch-up 100 mAJEDEC Standard 17D.C. OPERATING CHARACTERISTICSV CC = +2.7V to +6.0V, unless otherwise specified.Symbol Parameter Min. Typ. Max. Units Test Conditions I CC Power Supply Current 3mA f SCL = 100 KHzIsbStandby Current40 µAVcc=3.3V50 µA Vcc=5I LI Input Leakage Current 2 µA V IN =G ND or V CC I LO Output Leakage Current10µA V IN =G ND or V CCV IL Input Low Voltage –1 V CC x 0.3 V V IH Input High Voltage V CC x 0.7 V CC + 0.5 VV OLOutput Low Voltage (SDA)0.4 V I OL = 3 mA ,V CC =3.0VLimitsCAPACITANCE T A = 25°C, f = 1.0 MHz, V CC = 5V Symbol Test Max.Units Conditions C I/O (3) Input/Output Capacitance (SDA)8pF V I/O = 0V C IN (3)Input Capacitance (SCL)6pFV IN = 0VNote:(1)The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DCvoltage on output pins is V CC +0.5V, which may overshoot to V CC + 2.0V for periods of less than 20ns.(2)Output shorted for no more than one second. No more than one output shorted at a time.(3)This parameter is tested initially and after a design or process change that affects the parameter.(4)Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V CC +1V.CAT24C321/322/641/6423AdvancedDoc. No. 25083-00 12/98A.C. CHARACTERISTICSV CC =2.7V to 6.0V unless otherwise specified.Output Load is 1 TTL Gate and 100pFRead & Write Cycle Limits SymbolParameterV CC =2.7V - 6V V CC =4.5V - 5.5V Min.Max.Min.Max.Units F SCL Clock Frequency100400kHz T I (1)Noise Suppression Time200200ns Constant at SCL, SDA Inputs t AA SCL Low to SDA Data Out 3.51µs and ACK Outt BUF (1)Time the Bus Must be Free Before 4.7 1.2µs a New Transmission Can Start t HD:STA Start Condition Hold Time 40.6µs t LOW Clock Low Period 4.7 1.2µs t HIGH Clock High Period40.6µs t SU:STA Start Condition Setup Time4.70.6µs (for a Repeated Start Condition)t HD:DAT Data In Hold Time 00ns t SU:DAT Data In Setup Time 5050ns t R (1)SDA and SCL Rise Time 10.3µs t F (1)SDA and SCL Fall Time 300300ns t SU:STO Stop Condition Setup Time 40.6µs t DHData Out Hold Time100100nsPower-Up Timing (1)(2)Symbol ParameterMax.Units t PUR Power-up to Read Operation 1ms t PUWPower-up to Write Operation1msNote:(1)This parameter is tested initially and after a design or process change that affects the parameter.(2)t PUR and t PUW are the delays required from the time V CC is stable until the specified operation can be initiated.Write Cycle Limits Symbol Parameter Min.Typ.Max Units t WRWrite Cycle Time10msThe write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.CAT24C321/322/641/6424AdvancedDoc. No. 25083-00 12/98RESET CIRCUIT CHARACTERISTICSCAT24C321/322/641/6425AdvancedDoc. No. 25083-00 12/98PIN DESCRIPTIONSWP : WRITE PROTECTIf the pin is tied to V CC the entire memory array becomes Write Protected (READ only). When the pin is tied to V SS or left floating normal read/write operations are allowed to the device.SCL : SERIAL CLOCKThe serial clock input clocks all data transferred into or out of the device.RESET/RESET : RESET I/OThese are open drain pins and can be used as reset trigger inputs. By forcing a reset condition on the pins the device will initiate and maintain a reset condition for approximately 200ms. RESET pin must be connected through a pull-down and RESET pin must be connected through a pull-up device.SDA: SERIAL DATA/ADDRESSThe bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. In the 24C321/641, the SDA line is also used as the Watchdog Timer Monitor.Reset Controller DescriptionThe CAT24CXXX provides a precision RESET control-ler that ensures correct system operation during brown-out and power-up/down conditions. It is configured with open drain RESET outputs. During power-up, the RESET outputs remain active until V CC reaches the V TH threshold and will continue driving the outputs for approximately 200ms (t PURST ) after reaching V TH. After the t PURST timeout interval, the device will cease to drive reset outputs. At this point the reset outputs will be pulled up or down by their respective pull up/pull down devices. During power-down, the RESET outputs will begin driving active when V CC falls below V TH. The RESET outputs will be valid so long as V CC is >1.0V (V RVALID ).The RESET pins are I/Os; therefore, the CAT24CXXX can act as a signal conditioning circuit for an externally applied reset. The inputs are level triggered; that is, the RESET input in the 24CXXX will initiate a reset timeout after detecting a high and the RESET input in the 24CXXX will initiate a reset timeout after detecting a low.Watchdog TimerThe Watchdog Timer provides an independent protec-tion for microcontrollers. During a system failure, the CAT24C321/641 will respond with a reset signal after a time-out interval of 1.6 seconds for lack of activity.24CXX1 is designed with the Watchdog Timer feature on the SDA input. For the 24C321/641, if the microcontroller does not toggle the SDA input pin within 1.6 seconds the Watchdog Timer times out. This will generate a reset condition on reset outputs. The Watch-dog Timer is cleared by any transition on SDA.As long as the reset signal is asserted, the Watchdog Timer will not count and will stay cleared. 24C322/642does not feature the Watchdog Timer function.DEVICE OPERATIONV CCV RESETCAT24C321/322/641/6426AdvancedDoc. No. 25083-00 12/98Hardware Data ProtectionThe 24CXXX is designed with the following hardware data protection features to provide a high degree of data integrity.(1) The 24CXXX features a WP pin. When WP pin is tied high the entire memory array becomes write protected (read only).(2) The V CC sense provides write protection when V CC falls below the reset threshold value (V TH ). The V CC lock out inhibits writes to the serial EEPROM whenever V CC falls below (power down) V TH or until V CC reaches the reset threshold (power up) V TH .Reset Threshold VoltageFrom the factory the 24CXXX is offered in five different variations of reset threshold voltages. They are 4.50-4.75V, 4.25-4.50V, 3.00-3.15V, 2.85-3.00V and 2.55-2.70V. To provide added flexibility to design engineers using this product, the 24CXXX is designed with an additional feature of programming the reset threshold voltage. This allows the user to change the existing reset threshold voltage to one of the other four reset threshold voltages. Once the reset threshold voltage is selected it will not change even after cycling the power,unless the user uses the programmer to change the reset threshold voltage. However, the programming function is available only through third party programmer manufacturers. Please call Catalyst for a list of program-mer manufacturers who support this function.STOPCONDITIONSTARTCONDITIONADDRESSSCLSDAFigure 3. Write Cycle TimingSTART BITSDASTOP BITSCLFigure 4. Start/Stop TimingSCLSDA INSDA OUTFigure 2. Bus TimingCAT24C321/322/641/6427AdvancedDoc. No. 25083-00 12/98ACKNOWLEDGESTARTSCL FROM MASTERDATA OUTPUTFROM TRANSMITTERDATA OUTPUT FROM RECEIVERFigure 5. Acknowledge TimingFigure 6. Slave Address BitsFUNCTIONAL DESCRIPTIONThe CAT24CXXX supports the I 2C Bus data transmis-sion protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a re-ceiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24CXXX operates as a Slave device. Both the Master device and Slave device can operate as either transmitter or re-ceiver, but the Master device controls which mode is activated.I 2C BUS PROTOCOLThe features of the I 2C bus protocol are defined as follows:(1) Data transfer may be initiated only when the bus is not busy.(2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition.START ConditionThe START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24CXXX monitors the SDA and SCL lines and will not respond until this condition is met.STOP ConditionA LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition.DEVICE ADDRESSINGThe Master begins a transmission by sending a START condition. The Master sends the address of the particu-lar slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1010.The next three bits are don't care. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write opera-tion is selected.After the Master sends a START condition and the slave address byte, the CAT24CXXX monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT24CXXX then performs a Read or Write operation depending on the state of the R/W bit.1010X R/WX XCAT24C321/322/641/6428AdvancedDoc. No. 25083-00 12/98Figure 7. Byte Write TimingFigure 8. Page Write TimingACKNOWLEDGEAfter a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledg-ing device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data.The CAT24CXXX responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation,it responds with an acknowledge after receiving each 8-bit byte.When the CAT24CXXX begins a READ mode it trans-mits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this ac-knowledge, the CAT24CXXX will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition.WRITE OPERATIONSByte WriteIn the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After t he Slave generates an acknowledge, the Master sends a 8-bit address that is to be written into the address pointers of the CAT24CXXX. After receiving another acknowledge from the Slave, the Master device trans-mits the data to be written into the addressed memory location. The CAT24CXXX acknowledges once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to nonvolatile memory. While the cycle is in progress, the device will not respond to any request from the Master device.Page WriteThe 24CXXX writes up to 32 bytes of data in a single write cycle, using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 31 additional bytes. After each byte has been transmitted, CAT24CXXX will respond with an acknowledge, and internally increment the lower order address bits by one. The high order bits remain un-changed.If the Master transmits more than 32 bytes before sending the STOP condition, the address counter ‘wraps around’, and previously transmitted data will be overwrit-ten.When all 32 bytes are received, and the STOP condi tion has been sent by the Master, the internal program-ming cycle begins. At this point, all received data is written to the CAT24CXXX in a single write cycle.* = Don't care bit for 24C321/322X= Don't care bitA 15–A 8SLAVE ADDRESSSA C KAC KDATAA C KS T O P P BUS ACTIVITY:MASTERSDA LINES T A R T A 7–A 0BYTE ADDRESS A C K*X X XSLAVE C KC KC KBUS ACTIVITY:MASTERSDA LINES T A BYTE ADDRESS C KS T C K C KC KCAT24C321/322/641/6429AdvancedDoc. No. 25083-00 12/98Figure 9. Immediate Address Read TimingAcknowledge PollingDisabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation,CAT24CXXX initiates the internal write cycle. ACK poll-ing can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If CAT24CXXX is still busy with the write operation, no ACK will be returned. If CAT24CXXX has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation.WRITE PROTECTIONThe Write Protection feature allows the user to protect against inadvertent programming of the memory array.If the WP pin is tied to V CC , the entire memory array is protected and becomes read only. The CAT24CXXX will accept both slave and byte addresses, but the memory location accessed is protected from program-ming by the device's failure to send an acknowledge after the first byte of data is received.READ OPERATIONSThe READ operation for the CAT24CXXX is initiated in the same manner as the write operation with one excep-tion, that R/W bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ.SCL SDA 8TH BIT STOPNO ACKDATA OUT89SLAVE ADDRESSSA C KBUS ACTIVITY:MASTERSDA LINES T A R T N O A C KDATAS T O P PCAT24C321/322/641/64210AdvancedDoc. No. 25083-00 12/98Figure 10. Selective Read TimingFigure 11. Sequential Read TimingImmediate/Current Address ReadThe CAT24CXXX’s address counter contains the ad-dress of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would ac-cess data from address N+1. If N=E (where E=4095 for 24C321/322 and E=8191 for 24C641/642), then the counter will ‘wrap around’ to address 0 and continue to clock out data. After the CAT24CXXX receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8-bit byte requested. The master device does not send an ac-knowledge, but will generate a STOP condition.Selective/Random ReadSelective/Random READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condi-tion, slave address and byte addresses of the location it wishes to read. After CAT24CXXX acknowledges, the Master device sends the START condition and the slave address again, this time with the R/W bit set to one.The CAT24CXXX then responds with its acknowledge and sends the 8-bit byte requested. The master deviceSequential ReadThe Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT24CXXX sends the initial 8-bit byte requested, the Master will respond with an acknowledge which tells the device it requires more data. The CAT24CXXX will continue to output an 8-bit byte for each acknowledge sent by the Master. The operation will terminate when the Master fails to respond with an acknowledge, thus sending the STOP condition.The data being transmitted from CAT24CXXX is output-ted sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT24CXXX address bits so that the entire memory array can be read during one operation. If more than E (where E= 4095 for 24C321/322, E=511 and E=8191 for 24C641/642) bytes are read out, the counter will ‘wrap around’ and continue to clock out data bytes.does not send an acknowledge but will generate a STOP condition.BUS ACTIVITY:MASTERSDA LINEDATA n+xDATA nC KC KDATA n+1C KS T O O A C KDATA n+2C KSLAVE ADDRESS* = Don't care bit for 24C321/322X= Don't care bitA 15–A 8SLAVE ADDRESSSA C KA C KA C KBUS ACTIVITY:MASTERSDA LINES T A R T A 7–A 0BYTE ADDRESS SLAVEADDRESSSA C KN O A C KS T A R T DATAPS T O P X X X *CAT24C321/322/641/64211Advanced Doc. No. 25083-00 12/98Ordering InformationNote:(1) The device used in the above example is a CAT24C322JI-30TE13 (32K I 2C Memory, SOIC, Industrial Temperature, 3.0-3.15V ResetThreshold Voltage, Tape and Reel)CAT24C321/322/641/64212AdvancedDoc. No. 25083-00 12/98。