测量大功率LDMOS晶体管特性的TRL校准方法研究2
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Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
Abstract: The impedance and output power measurements of LDMOS transistors are always a problem due to their low impedance and lead widths. An improved thru-reflect-line (TRL) calibration algorithm for measuring the characteristics of L-band high power LDMOS transistors is presented. According to the TRL algorithm, the individual two-port S parameters of each fixture half can be obtained. By de-embedding these S parameters of the test fixture, an accurate calibration can be made. The improved TRL calibration algorithm is successfully utilized to measure the characteristics of an L-band LDMOS transistor with a 90 mm gate width. The impedance of the transistor is obtained, and output power at 1 dB compression point can reach as much as 109.4 W at 1.2 GHz, achieving 1.2 W/mm power density. From the results, it is seen that the presented TRL calibration algorithm works well. Key words: thru-reflect-line; lateral double-diffused MOSFET; low impedance test fixture; impedance; output power DOI: 10.1088/1674-4926/34/3/034005 EEACC: 2570 the mechanics. The present paper describes the improved TRL algorithm and the impedance of the high power LDMOS transistors is obtained.
1. Introduction
High power LDMOS transistors are widely used in the base station nowadays, nevertheless the measurements of their input and output impedance still remain a difficult issue, due to the very low impedance and lead widths. Generally, the impedance of high power LDMOS transistors is measured with the test fixture. However, when using the 50 test fixture, low frequency oscillation phenomenon usually appears, which damages the device seriously. In order to eliminate this oscillation and make it convenient for impedance and power testing, the low impedance test fixture may be an alternative. In the vector network analyzer (VNA) test system, the measured results include the S parameters of both the test fixture and the transistor. The S parameters of the input and output low impedance test fixture are essential to obtain the impedances of the transistor. However, for the low impedance test fixture, it is difficult to build a calibration kit to measure the wide microstrip lines and the measured results are also not accurate enough. The thru-reflect-line (TRL) method is widely used for VNA calibration and two-port characterization. The usefulness of the TRL methodŒ1 stems primarily from how the calibration reference impedance is defined. Of the standard VNA calibration techniques, TRL offers the best source- and load-match and lowest residual directivity, in addition to enabling simple reference-plane shifting, calculation of the complex propagation constant, and use of dispersive calibration standards. Although widely used, there are no detailed publications which go through a systematic derivation of the TRL solution and its insertion into a VNA as an error-box model in terms of the equivalent error-terms. The seminal TRL paper by Engen and HoerŒ2 describes the essence of the TRL algorithm, but not
2. Algorithm
2.1. Significance of the TRL calibration algorithm In order to determine the performance of a device, it is necessary to have a method to use measurements on the ports of the VNA to describe the RF state at the device-under-test (DUT). Typically, components are modeled as matrix blocks and deembedded to the desired reference plane. The test fixture model is shown in Fig. 1. With the help of VNA, S parameters of both the fixture and transistor are obtained. In order to get the performance of the DUT, the method
Vol. 34, No. 3
Journal of Semiconductors
March 2013
A thru-reflect-line calibration for measuring the characteristics of high power LDMOS transistors
Wang Shuai(王帅), Li Ke(李科), Jiang Yibo(姜一波), Cong Mifang(丛密芳), Du Huan(杜寰), and Han Zhengsheng(韩郑生)
034005-1
J. Semical. TMT D TA TTHRU TB D TA TB : (8)
The notations A and B represent error box BLOCKA and BLOCKB respectively, and ML represents the measured delay line and MT for the measured thru connection. Likewise, the delay line equation can be represented by
1 TLT D TML TMT :
(9)
used to de-embed the error box of the BLOCKA and BLOCKB is needed. The key to this method is the algorithm to obtain the S parameter of BLOCKA and BLOCKB. 2.2. Improved algorithm for TRL The two-port network is described in Fig. 2. The transmission matrixŒ3 is given as  à  Ã à b1 T11 T12 a2 D : (1) a1 T21 T22 b2 The scattering matrix and transmission matrix are related as follows.  à  à 1 S12 S21 S11 S22 S11 T11 T12 ; (2) D S22 1 T21 T22 S21  à 1 D T22  T12 1 Ã
Fig. 1. Test fixture model.
† Corresponding author. Email: zshan@ Received 20 August 2012, revised manuscript received 14 September 2012
© 2013 Chinese Institute of Electronics
Fig. 2. Two ports network.
TML D TA TLINE TB : Equation (8) can be written as TB D TA 1 TMT : Using Eq. (10) to eliminate TB from Eq. (9) gives TLT TA D TA TLINE ; where TLT is defined as
Abstract: The impedance and output power measurements of LDMOS transistors are always a problem due to their low impedance and lead widths. An improved thru-reflect-line (TRL) calibration algorithm for measuring the characteristics of L-band high power LDMOS transistors is presented. According to the TRL algorithm, the individual two-port S parameters of each fixture half can be obtained. By de-embedding these S parameters of the test fixture, an accurate calibration can be made. The improved TRL calibration algorithm is successfully utilized to measure the characteristics of an L-band LDMOS transistor with a 90 mm gate width. The impedance of the transistor is obtained, and output power at 1 dB compression point can reach as much as 109.4 W at 1.2 GHz, achieving 1.2 W/mm power density. From the results, it is seen that the presented TRL calibration algorithm works well. Key words: thru-reflect-line; lateral double-diffused MOSFET; low impedance test fixture; impedance; output power DOI: 10.1088/1674-4926/34/3/034005 EEACC: 2570 the mechanics. The present paper describes the improved TRL algorithm and the impedance of the high power LDMOS transistors is obtained.
1. Introduction
High power LDMOS transistors are widely used in the base station nowadays, nevertheless the measurements of their input and output impedance still remain a difficult issue, due to the very low impedance and lead widths. Generally, the impedance of high power LDMOS transistors is measured with the test fixture. However, when using the 50 test fixture, low frequency oscillation phenomenon usually appears, which damages the device seriously. In order to eliminate this oscillation and make it convenient for impedance and power testing, the low impedance test fixture may be an alternative. In the vector network analyzer (VNA) test system, the measured results include the S parameters of both the test fixture and the transistor. The S parameters of the input and output low impedance test fixture are essential to obtain the impedances of the transistor. However, for the low impedance test fixture, it is difficult to build a calibration kit to measure the wide microstrip lines and the measured results are also not accurate enough. The thru-reflect-line (TRL) method is widely used for VNA calibration and two-port characterization. The usefulness of the TRL methodŒ1 stems primarily from how the calibration reference impedance is defined. Of the standard VNA calibration techniques, TRL offers the best source- and load-match and lowest residual directivity, in addition to enabling simple reference-plane shifting, calculation of the complex propagation constant, and use of dispersive calibration standards. Although widely used, there are no detailed publications which go through a systematic derivation of the TRL solution and its insertion into a VNA as an error-box model in terms of the equivalent error-terms. The seminal TRL paper by Engen and HoerŒ2 describes the essence of the TRL algorithm, but not
2. Algorithm
2.1. Significance of the TRL calibration algorithm In order to determine the performance of a device, it is necessary to have a method to use measurements on the ports of the VNA to describe the RF state at the device-under-test (DUT). Typically, components are modeled as matrix blocks and deembedded to the desired reference plane. The test fixture model is shown in Fig. 1. With the help of VNA, S parameters of both the fixture and transistor are obtained. In order to get the performance of the DUT, the method
Vol. 34, No. 3
Journal of Semiconductors
March 2013
A thru-reflect-line calibration for measuring the characteristics of high power LDMOS transistors
Wang Shuai(王帅), Li Ke(李科), Jiang Yibo(姜一波), Cong Mifang(丛密芳), Du Huan(杜寰), and Han Zhengsheng(韩郑生)
034005-1
J. Semical. TMT D TA TTHRU TB D TA TB : (8)
The notations A and B represent error box BLOCKA and BLOCKB respectively, and ML represents the measured delay line and MT for the measured thru connection. Likewise, the delay line equation can be represented by
1 TLT D TML TMT :
(9)
used to de-embed the error box of the BLOCKA and BLOCKB is needed. The key to this method is the algorithm to obtain the S parameter of BLOCKA and BLOCKB. 2.2. Improved algorithm for TRL The two-port network is described in Fig. 2. The transmission matrixŒ3 is given as  à  Ã à b1 T11 T12 a2 D : (1) a1 T21 T22 b2 The scattering matrix and transmission matrix are related as follows.  à  à 1 S12 S21 S11 S22 S11 T11 T12 ; (2) D S22 1 T21 T22 S21  à 1 D T22  T12 1 Ã
Fig. 1. Test fixture model.
† Corresponding author. Email: zshan@ Received 20 August 2012, revised manuscript received 14 September 2012
© 2013 Chinese Institute of Electronics
Fig. 2. Two ports network.
TML D TA TLINE TB : Equation (8) can be written as TB D TA 1 TMT : Using Eq. (10) to eliminate TB from Eq. (9) gives TLT TA D TA TLINE ; where TLT is defined as