Memory Compiler

SEC ASIC
5-1
STDL80
MEMORY COMPILERS SELECTION GUIDE
MEMORY COMPILERS
In 0.5µm CMOS standard cell memory compilers, the y-mux type selecting option was added to give the customers freedom selecting aspect ratio of the memory layout. Many of the characteristics of a memory cell are depend on its y-mux type. So, when you change the y-mux type from one to the other to change the aspect ratio, you have to know that it will change many major characteristics, such as access time, area and power consumption, of the memory. < Figure 1. Example of Y-mux Types and Aspect Ratio >
y-mux ቤተ መጻሕፍቲ ባይዱ 4
y-mux = 8
y-mux = 16
Dual Banks
In some of 0.5µm CMOS standard cell memory compilers is a generator option which defines the number of bit array banks. This dual bank scheme doubles the maximum capacity of the memory compilers.
MEMORY COMPILERS
OVERVIEW
OVERVIEW
This chapter contains information for memory compilers available in STDL80 cell library. These are complete compilers that consist of various generators to satisfy the requirements of the circuit at hand. Each of the final building block, the physical layout, will be implemented as a stand-alone, densely packed, pitch-matched array. Using this complex layout generator and adopting state-of-the-art logic and circuit design technique, these memory cells can realize extreme density and performance. In each layout generator, we added an option which makes the aspect ratio of the physical layout selectable so that the ASIC designers can choose the aspect ratio according to the convenience of the chip level layout. In the STDL80 cell library, there are 4 groups of memory compilers — ROMs; Static RAMs; Register File; FIFO.
Advanced Design Technique
All of 0.5µm CMOS standard cell memory compilers adopt very advanced design technique to obtain extremely high performance in terms of both speed and power consumption. Below are major techniques. For reducing power consumption • Minimized bit-line precharge/discharge voltage swing • Zero static current consuming sense amplifier • Automatic power down after an access For optimizing and minimizing the read access time • Size sensitive self-timer delay • Extremely simple tri-state output circuit
MEMORY COMPILERS SELECTION GUIDE
Memory Group ROM Cell Name CROM Gen DROM Gen Static RAM SPSRAM Gen SPSRAMA Gen Function Description Contact Programmable Synchronous ROM Generator Diffusion Programmable Synchronous ROM Generator Single-Port Synchronous RAM Generator – Reads and writes at the same edge of clock Single-Port Synchronous RAM Generator – Alternative – Reads and writes at different edges of clock Single-Port Asynchronous RAM Generator – Fully asynchronous read, WEN synchronized write Dual-Port Synchronous RAM Generator – Reads and writes at the same edge of clock Dual-Port Asynchronous RAM Generator – Fully asynchronous read, WEN synchronized write Dual-Port Synchronous RAM Generator – Alternative – Reads and writes at different edges of clock 1 Read Port, 1 Write Port Synchronous Register File Synchronous FIFO
Flexible Aspect Ratio
The size of a memory cell is defined by its number of words (WORDS) and number of bits per word (BPW). But, this size is only a logical size. The physical size of a memory is defined by the number of rows (ROWS) and the number of columns (COLS) of its bit cell array. Usually, we can't make the bit cell array with WORDS and BPW because the range of WORDS is much larger than the range of BPW. If we make the bit cell array with WORDS and BPW, most of memory layouts will have too tall and too thin aspect ratio. Therefore, column decoder and y-mux circuit are included in most of memory cells to adjust the aspect ratio.
Memory Compilers
5
Contents
Overview .............................................................................................................................. 5-1 Memory Compilers Selection Guide..................................................................................... 5-2 CROM Gen........................................................................................................................... 5-3 DROM Gen........................................................................................................................... 5-9 SPSRAM Gen ...................................................................................................................... 5-15 SPSRAMA Gen .................................................................................................................... 5-22 SPARAM Gen....................................................................................................................... 5-31 DPSRAM Gen ...................................................................................................................... 5-38 DPSRAMA Gen.................................................................................................................... 5-47