STM32_引脚排列xls格式
(完整版)stm32f407引脚分配表
OLED/CAMERA接口的D1脚
98
PC8
SDIO_D0
DCMI_D2
N
1，SD卡接口的D0
2，OLED/CAMERA接口的D2脚
99
PC9
SDIO_D1
DCMI_D3
N
1，SD卡接口的D1
2，OLED/CAMERA接口的D3脚
111
PC10
SDIO_D2
N
SD卡接口的D2
112
PC11
SDIO_D3
PF6
GBC_KEY
Y
接ATK-MODULE接口的KEY脚
19
PF7
LIGHT_SENSOR
N
接光敏传感器(LS1)
20
PF8
BEEP
N
接蜂鸣器(BEEP)
21
PF9
LED0
N
接DS0 LED灯(红色)
22
PF10
LED1
N
接DS1 LED灯(绿色)
49
PF11
T_MOSI
Y
TFTLCD接口触摸屏MOSI信号
如不用LAN8720，并去掉P9跳线帽，可以做普通IO用
该IO通过P9选择连接RS232还是RS485，并同时连接了PWM_DAC, 这里的RS232 TX脚是指SP3232芯片的TX脚，接STM32的RX脚
去掉P9跳线帽，可以做普通IO用
该IO可做DAC输出，同时也连接在OLED/CAMERA接口，如不插外设在OLED/CAMERA接口，
137
PB7
DCMI_VSYNC
Y
OLED/CAMERA接口的VSYNC脚
139
PB8
IIC_SCL
stm32f407IO引脚分配表讲课讲稿
140 PB9 IIC_SDA
N 接24C02&MPU6050&WM8978的SDA
69 PB10 USART3_TX
Y
1，RS232串口3(COM3)RX脚(P10设置) 2，ATK-MODULE接口的RXD脚(P10设置)
70 PB11 USART3_RX
Y
1，RS232串口3(COM3)TX脚(P10设置) 2，ATK-MODULE接口的TXD脚(P10设置)
68 PE15 FSMC_D12
10 PF0 FSMC_A0
N
1，ATK-MODULE接口的LED引脚 2，MPU6050模块的中断脚
N 接LAN8720的MDC脚
N WM8978的SDOUT信号
N WM8978的SDIN信号
N 接LAN8720的RXD0脚
N 接LAN8720的RXD1脚
N
1，WM8978的SDIN信号 2，OLED/CAMERA接口的D0脚
109 PA14 JTCK
SWDCLK N JTAG/SWD仿真接口,没接任何外设
110 PA15 JTDI
USB_PWR
N
1，JTAG仿真口(JTDI) 2，USB_HOST接口供电控制脚
46 PB0 T_SCK
Y TFTLCD接口触摸屏SCK信号
47 PB1 T_PEN
Y TFTLCD接口触摸屏PEN信号
2 PE3 KEY1
3 PE4 KEY0
4 PE5 DCMI_D6
5 PE6 DCMI_D7
58 PE7 FSMC_D4
59 PE8 FSMC_D5
60 PE9 FSMC_D6
63 PE10 FSMC_D7
64 PE11 FSMC_D8
STM32_引脚排列
TIM1_CH2N TIM1_CH2 TIM1_CH3N TIM1_CH3 TIM1_CH4 TIM1_BKIN TIM2_CH3 TIM2_CH4
TIM4_CH1 TIM4_CH2
USART3_TX USART3_RX USART3_CK USART3_CTS USART3_RTS
TIM4_CH3 TIM4_CH4
PG13 PG14 VSS_11 VDD_11 PG15 JTDO NJTRST PB05 PB06 PB07 BOOT0 PB08 PB09 PE00 PE01 VSS_3 VDD_3
FSMC_A24 FSMC_A25
FSMC_NADV
FSMC_NBL0 FSMC_NBL1
制作：谭志平 EMAIL: knight# 版本： V20130727
128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
89 90 91 92 93 94 95 96 97 98 99 100
55 56 57 58 59 60 61 62
63 64
PG13 PG14 VSS_11 VDD_11 PG15 PB03 PB04 PB05 PB06 PB07 BOOT0 PB08 PB09 PE00 PE01 VSS_3 VDD_3
USART3_CK USART3_CTS USART3_RTS
USART1_CK USART1_TX USART1_RX USART1_CTS USART1_RTS
SPI3_NSS UART4_TX UART4_RX UART5_TX
UART5_RX
SPI3_SCK SPI3_MISO SPI3_MOSI
STM32F103C8T6中文资料_引脚图_最小系统
Contents STM32F103x8,STM32F103xB Contents1Introduction (9)2Description (9)2.1Device overview (10)2.2Full compatibility throughout the family (13)2.3Overview (14)2.3.1ARM®Cortex™-M3core with embedded Flash and SRAM (14)2.3.2Embedded Flash memory (14)2.3.3CRC(cyclic redundancy check)calculation unit (14)2.3.4Embedded SRAM (14)2.3.5Nested vectored interrupt controller(NVIC) (14)2.3.6External interrupt/event controller(EXTI) (15)2.3.7Clocks and startup (15)2.3.8Boot modes (15)2.3.9Power supply schemes (15)2.3.10Power supply supervisor (15)2.3.11Voltage regulator (16)2.3.12Low-power modes (16)2.3.13DMA (17)2.3.14RTC(real-time clock)and backup registers (17)2.3.15Timers and watchdogs (17)2.3.16I²C bus (19)2.3.17Universal synchronous/asynchronous receiver transmitter(USART)..192.3.18Serial peripheral interface(SPI) (19)2.3.19Controller area network(CAN) (19)2.3.20Universal serial bus(USB) (19)2.3.21GPIOs(general-purpose inputs/outputs) (20)2.3.22ADC(analog-to-digital converter) (20)2.3.23T emperature sensor (20)2.3.24Serial wire JTAG debug port(SWJ-DP) (20)3Pinouts and pin description (21)4Memory mapping (34)2/105DocID13587Rev16STM32F103x8,STM32F103xB Contents5Electrical characteristics (35)5.1Parameter conditions (35)5.1.1Minimum and maximum values (35)5.1.2Typical values (35)5.1.3Typical curves (35)5.1.4Loading capacitor (35)5.1.5Pin input voltage (35)5.1.6Power supply scheme (36)5.1.7Current consumption measurement (37)5.2Absolute maximum ratings (37)5.3Operating conditions (38)5.3.1General operating conditions (38)5.3.2Operating conditions at power-up/power-down (39)5.3.3Embedded reset and power control block characteristics (40)5.3.4Embedded reference voltage (41)5.3.5Supply current characteristics (41)5.3.6External clock source characteristics (51)5.3.7Internal clock source characteristics (55)5.3.8PLL characteristics (57)5.3.9Memory characteristics (57)5.3.10EMC characteristics (58)5.3.11Absolute maximum ratings(electrical sensitivity) (60)5.3.12I/O current injection characteristics (61)5.3.13I/O port characteristics (62)5.3.14NRST pin characteristics (68)5.3.15TIM timer characteristics (69)5.3.16Communications interfaces (70)5.3.17CAN(controller area network)interface (75)5.3.1812-bit ADC characteristics (76)5.3.19T emperature sensor characteristics (80)6Package characteristics (81)6.1Package mechanical data (81)6.2Thermal characteristics (93)6.2.1Reference document (93)6.2.2Selecting the product temperature range (94)DocID13587Rev163/105Contents STM32F103x8,STM32F103xB7Ordering information scheme (96)8Revision history (97)4/105DocID13587Rev16STM32F103x8,STM32F103xB List of tables List of tablesT able1.Device summary (1)T able2.STM32F103xx medium-density device features and peripheral counts (10)T able3.STM32F103xx family (13)T able4.Timer feature comparison (17)T able5.Medium-density STM32F103xx pin definitions (28)T able6.Voltage characteristics (37)T able7.Current characteristics (38)T able8.Thermal characteristics (38)T able9.General operating conditions (38)T able10.Operating conditions at power-up/power-down (39)T able11.Embedded reset and power control block characteristics (40)T able12.Embedded internal reference voltage (41)T able13.Maximum current consumption in Run mode,code with data processingrunning from Flash (42)T able14.Maximum current consumption in Run mode,code with data processingrunning from RAM (42)T able15.Maximum current consumption in Sleep mode,code running from Flash or RAM (44)T able16.Typical and maximum current consumptions in Stop and Standby modes (45)T able17.Typical current consumption in Run mode,code with data processingrunning from Flash (48)T able18.Typical current consumption in Sleep mode,code running from Flash orRAM (49)T able19.Peripheral current consumption (50)T able20.High-speed external user clock characteristics (51)T able21.Low-speed external user clock characteristics (51)T able22.HSE4-16MHz oscillator characteristics (53)T able23.LSE oscillator characteristics(f LSE=32.768kHz) (54)T able24.HSI oscillator characteristics (55)T able25.LSI oscillator characteristics (56)T able26.Low-power mode wakeup timings (57)T able27.PLL characteristics (57)T able28.Flash memory characteristics (57)T able29.Flash memory endurance and data retention (58)T able30.EMS characteristics (59)T able31.EMI characteristics (59)T able32.ESD absolute maximum ratings (60)T able33.Electrical sensitivities (60)T able34.I/O current injection susceptibility (61)T able35.I/O static characteristics (62)T able36.Output voltage characteristics (66)T able37.I/O AC characteristics (67)T able38.NRST pin characteristics (68)T able39.TIMx characteristics (69)T able40.I2C characteristics (70)T able41.SCL frequency(f PCLK1=36MHz.,V DD_I2C=3.3V) (71)T able42.SPI characteristics (72)T B startup time (74)T B DC electrical characteristics (75)DocID13587Rev165/105List of tables STM32F103x8,STM32F103xBT B:Full-speed electrical characteristics (75)T able46.ADC characteristics (76)T able47.R AIN max for f ADC=14MHz (77)T able48.ADC accuracy-limited test conditions (77)T able49.ADC accuracy (78)T able50.TS characteristics (80)T able51.VFQFPN366x6mm,0.5mm pitch,package mechanical data (82)T able52.UFQFPN487x7mm,0.5mm pitch,package mechanical data (83)T able53.LFBGA100-10x10mm low profile fine pitch ball grid array packagemechanical data (85)T able54.LQPF100,14x14mm100-pin low-profile quad flat package mechanical data (87)T able55.UFBGA100-ultra fine pitch ball grid array,7x7mm,0.50mm pitch,packagemechanical data (88)T able56.LQFP64,10x10mm,64-pin low-profile quad flat package mechanical data (89)T able57.TFBGA64-8x8active ball array,5x5mm,0.5mm pitch,package mechanical data (90)T able58.LQFP48,7x7mm,48-pin low-profile quad flat package mechanical data (92)T able59.Package thermal characteristics (93)T able60.Ordering information scheme (96)T able61.Document revision history (97)6/105DocID13587Rev16STM32F103x8,STM32F103xB List of figures List of figuresFigure1.STM32F103xx performance line block diagram (11)Figure2.Clock tree (12)Figure3.STM32F103xx performance line LFBGA100ballout (21)Figure4.STM32F103xx performance line LQFP100pinout (22)Figure5.STM32F103xx performance line UFBGA100pinout (23)Figure6.STM32F103xx performance line LQFP64pinout (24)Figure7.STM32F103xx performance line TFBGA64ballout (25)Figure8.STM32F103xx performance line LQFP48pinout (26)Figure9.STM32F103xx performance line UFQFPN48pinout (26)Figure10.STM32F103xx performance line VFQFPN36pinout (27)Figure11.Memory map (34)Figure12.Pin loading conditions (36)Figure13.Pin input voltage (36)Figure14.Power supply scheme (36)Figure15.Current consumption measurement scheme (37)Figure16.Typical current consumption in Run mode versus frequency(at3.6V)-code with data processing running from RAM,peripherals enabled (43)Figure17.Typical current consumption in Run mode versus frequency(at3.6V)-code with data processing running from RAM,peripherals disabled (43)Figure18.Typical current consumption on V BAT with RTC on versus temperature at differentV BAT values (45)Figure19.Typical current consumption in Stop mode with regulator in Run mode versustemperature at V DD=3.3V and3.6V (46)Figure20.Typical current consumption in Stop mode with regulator in Low-power mode versustemperature at V DD=3.3V and3.6V (46)Figure21.Typical current consumption in Standby mode versus temperature atV DD=3.3V and3.6V (47)Figure22.High-speed external clock source AC timing diagram (52)Figure23.Low-speed external clock source AC timing diagram (52)Figure24.Typical application with an8MHz crystal (53)Figure25.Typical application with a32.768kHz crystal (55)Figure26.Standard I/O input characteristics-CMOS port (64)Figure27.Standard I/O input characteristics-TTL port (64)Figure28.5V tolerant I/O input characteristics-CMOS port (65)Figure29.5V tolerant I/O input characteristics-TTL port (65)Figure30.I/O AC characteristics definition (68)Figure31.Recommended NRST pin protection (69)Figure32.I2C bus AC waveforms and measurement circuit (71)Figure33.SPI timing diagram-slave mode and CPHA=0 (73)Figure34.SPI timing diagram-slave mode and CPHA=1(1) (73)Figure35.SPI timing diagram-master mode(1) (74)B timings:definition of data signal rise and fall time (75)Figure37.ADC accuracy characteristics (78)Figure38.Typical connection diagram using the ADC (79)Figure39.Power supply and reference decoupling(V REF+not connected to V DDA) (79)Figure40.Power supply and reference decoupling(V REF+connected to V DDA) (80)Figure41.VFQFPN366x6mm,0.5mm pitch,package outline(1) (82)Figure42.VFQFPN36recommended footprint(dimensions in mm)(1)(2) (82)DocID13587Rev167/105List of figures STM32F103x8,STM32F103xBFigure43.UFQFPN487x7mm,0.5mm pitch,package outline (83)Figure44.UFQFPN48recommended footprint (84)Figure45.LFBGA100-10x10mm low profile fine pitch ball grid array packageoutline (85)Figure46.Recommended PCB design rules(0.80/0.75mm pitch BGA) (86)Figure47.LQFP100,14x14mm100-pin low-profile quad flat package outline (87)Figure48.LQFP100recommended footprint(1) (87)Figure49.UFBGA100-ultra fine pitch ball grid array,7x7mm,0.50mm pitch,package outline (88)Figure50.LQFP64,10x10mm,64-pin low-profile quad flat package outline (89)Figure51.LQFP64recommended footprint(1) (89)Figure52.TFBGA64-8x8active ball array,5x5mm,0.5mm pitch,package outline (90)Figure53.Recommended PCB design rules for pads(0.5mm pitch BGA) (91)Figure54.LQFP48,7x7mm,48-pin low-profile quad flat package outline (92)Figure55.LQFP48recommended footprint(1) (92)Figure56.LQFP100P D max vs.T A (95)8/105DocID13587Rev16STM32F103x8,STM32F103xB Introduction 1IntroductionThis datasheet provides the ordering information and mechanical device characteristics ofthe STM32F103x8and STM32F103xB medium-density performance line microcontrollers.For more details on the whole STMicroelectronics STM32F103xx family,please refer toSection2.2:Full compatibility throughout the family.The medium-density STM32F103xx datasheet should be read in conjunction with the low-,medium-and high-density STM32F10xxx reference manual.The reference and Flash programming manuals are both available from theSTMicroelectronics website .For information on the Cortex™-M3core please refer to the Cortex™-M3T echnicalReference Manual,available from the website at the following address:/help/index.jsp?topic=/com.arm.doc.ddi0337e/2DescriptionThe STM32F103xx medium-density performance line family incorporates the high-performance ARM Cortex™-M332-bit RISC core operating at a72MHz frequency,high-speed embedded memories(Flash memory up to128Kbytes and SRAM up to20Kbytes),and an extensive range of enhanced I/Os and peripherals connected to two APB buses.Alldevices offer two12-bit ADCs,three general purpose16-bit timers plus one PWM timer,aswell as standard and advanced communication interfaces:up to two I2Cs and SPIs,threeUSART s,an USB and a CAN.The devices operate from a2.0to3.6V power supply.They are available in both the–40to+85°C temperature range and the–40to+105°C extended temperature range.Acomprehensive set of power-saving mode allows the design of low-power applications.The STM32F103xx medium-density performance line family includes devices in six differentpackage types:from36pins to100pins.Depending on the device chosen,different sets ofperipherals are included,the description below gives an overview of the complete range ofperipherals proposed in this family.These features make the STM32F103xx medium-density performance line microcontrollerfamily suitable for a wide range of applications such as motor drives,application control,medical and handheld equipment,PC and gaming peripherals,GPS platforms,industrialapplications,PLCs,inverters,printers,scanners,alarm systems,video intercoms,andHVACs.DocID13587Rev169/105TimersCommunicationDescription STM32F103x8,STM32F103xB 2.1Device overviewTable2.STM32F103xx medium-density device features and peripheral1.On the TFBGA64package only15channels are available(one analog input pin has been replaced by‘Vref+’).10/105DocID13587Rev16Peripheral STM32F103Tx STM32F103Cx STM32F103Rx STM32F103Vx Flash-Kbytes64128641286412864128SRAM-Kbytes20202020 General-purpose3333Advanced-control1111SPI12222I C1222USART2333USB1111CAN1111 GPIOs2637518012-bit synchronized ADCNumber of channels210channels210channels2(1)16channels216channels CPU frequency72MHzOperating voltage 2.0to3.6VOperating temperaturesAmbient temperatures:-40to+85°C/-40to+105°C(see Table9)Junction temperature:-40to+125°C(see Table9)Packages VFQFPN36LQFP48,UFQFPN48LQFP64,TFBGA64LQFP100,LFBGA100,UFBGA100f l a s ho b lI n t e r f a c eB u s M a t r i xA HB :F m a x =48/72M H zA PB 2:F m a x =48/72M H zA PB 1:F m a x =24/36M H zpbusPCLK2 HCLK CLOCK RTC AWUTAMPER -RTCSTM32F103x8, STM32F103xBDescriptionFigure 1. STM32F103xx performance line block diagramTRACECLKTRACED[0:3] as ASNJTRSTTRSTJTDIJTCK/SWCLK JTMS/SWDIOJTDO as AFTPIUTrace/trigSW/JTAGCortex -M3 CPUIbusF max : 7 2M Hz DbusTraceControlle rFlash 128 KB64 bitPOWERVOLT. REG. 3.3V TO 1.8V@VDDV DD = 2 to 3.6VV SSNVICSystemSRAM20 KB@VDDGP DMA7 channelsPCLK1 FCLKPLL &MANAGTXTAL OSC4-16 MHzOSC_INOSC_OUTRC 8 MHzNRST @VDDASUPPLYSUPERVISIONRC 40 kHz @VDDA@VBATIWDG Standby interfaceV BATVDDA VSSA 80AF PA[15:0] PB[15:0]POR / PDRPVDEXTIWAKEUPGPIOAGPIOBRstIntAHB2 AHB2APB2 APB1XTAL 32 kHzBackup reg Backu p i nterf ace TIM2 TIM3OSC32_IN OSC32_OUT4 Channels 4 ChannelsPC[15:0]GPIOCTIM 44 ChannelsPD[15:0]GPIOD PE[15:0] GPIOEUSART2USART3RX,TX, CTS, RTS,CK, SmartCard as AFRX,TX, CTS, RTS, CK, SmartCard as AF4 Channels3 compl. ChannelsETR and BKINMOSI,MISO, SCK,NSS as AFRX,TX, CTS, RTS,TIM1SPI12x(8x16bit)SPI2I2C1 I2C2MOSI,MISO,SCK,NSS as AFSCL,SDA,SMBA as AFSCL,SDA as AFSmartCard as AFUSART1@VDDAbxCANUSBDP/CAN_TXUSB 2.0 FSUSBDM/CAN_RX16AF V REF+ V REF -12bit ADC1 IF12bit ADC2 IFSRAM 512BWWDGTemp sensorai14390d1. T A = –40 °C to +105 °C (junction temperature up to 125 °C).2. AF = alternate function on I/O port pin.DocID13587 Rev 1611/105peripheralsIf (APB2 prescaler =1) x1 ADC /2, 4, 6, 8 ADCCLKDescriptionSTM32F103x8, STM32F103xBFigure 2. Clock treeFLITFCLKto Flash programming interface8 MHz HSI RCHSIUSBPrescaler 48 MHzUSBCLKto USB interface/2/1, 1.572 MHz maxClockHCLKto AHB bus, core, memory and DMA PLLSRCSWPLLMUL/8Enable (3 bits)to Cortex System timerFCLK Cortex..., x16 x2, x3, x4 PLLHSIPLLCLK HSESYSCLK72 MHz max AHB Prescaler /1, 2..512 APB1Prescaler/1, 2, 4, 8, 16free running clock36 MHz max PCLK1to APB1Peripheral Clock Enable (13 bits)TIM2,3, 4to TIM2, 3and 4CSSIf (APB1 prescaler =1) x1 TIMXCLKelse x2 Peripheral ClockEnable (3 bits)OSC_OUTOSC_IN4-16 MHzHSE OSCPLLXTPRE/2APB2Prescaler/1, 2, 4, 8, 16TIM1 timer 72 MHz maxPeripheral ClockEnable (11 bits) PCLK2peripherals to APB2to TIM1 TIM1CLK else x2 Peripheral ClockOSC32_INOSC32_OUTLSE OSC32.768 kHz/128LSERTCCLKto RTCPrescaler Enable (1 bit) to ADCRTCSEL[1:0]LSI RCLSIto Independent Watchdog (IWDG)40 kHzIWDGCLKLegend:HSE = high -speed external clock signalHSI = high -speed internal clock signalMCOMainClock Output/2PLLCLKHSI LSI = low -speed internal clock signal LSE = low -speed external clock signalHSESYSCLKMCOai149031. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz.2. For the USB function to be available, both HSE and PLL must be enabled, with USBCLK running at 48 MHz.3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz.12/105DocID13587 Rev 16STM32F103x8, STM32F103xBDescription2.2 Full compatibility throughout the familyThe STM32F103xx is a complete family whose members are fully pin -to -pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low -density devices, the STM32F103x8 and STM32F103xB are referred to as medium -density devices, and the STM32F103xC, STM32F103xD and STM32F103xE are referred to as high -density devices.Low - and high -density devices are an extension of the STM32F103x8/B devices, they are specified in the STM32F103x4/6 and STM32F103xC/D/E datasheets, respectively. Low - density devices feature lower Flash memory and RAM capacities, less timers and peripherals. High -density devices have higher Flash memory and RAM capacities, and additional peripherals like SDIO, FSMC, I 2S and DAC, while remaining fully compatible with the other members of the STM32F103xx family .The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD and STM32F103xE are a drop -in replacement for STM32F103x8/B medium -density devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle.Moreover, the STM32F103xx performance line family is fully compatible with all existing STM32F101xx access line and STM32F102xx USB access line devices.1.For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7),the reference datasheet for electrical characteristics is that of the STM32F103x8/B medium -density devices.DocID13587 Rev 16 13/105PinoutLow -density devicesMedium -density devices High -density devices 16 KB Flash 32 KB Flash (1) 64 KB Flash 128 KB Flash 256 KB Flash 384 KB Flash 512 KB Flash6 KB RAM 10 KB RAM 20 KB RAM 20 KB RAM 48 KB RAM 64 KB RAM 64 KB RAM144 5 × USART s 4 × 16-bit timers, 2 × basic timers2 3 × SPIs, 2 × I Ss, 2 × I2Cs USB, CAN, 2 × PWM timers 3 × ADCs, 2 × DACs, 1 × SDIOFSMC (100 and 144 pins) 100 3 × USART s 3 × 16-bit timers 2 2 × SPIs, 2 × I Cs, USB, CAN, 1 × PWM timer2 × ADCs 64 2 × USART s 2 × 16-bit timers 2 1 × SPI, 1 × I C, USB, CAN, 1 × PWM timer 2 × ADCs 48 36Description STM32F103x8,STM32F103xB 2.3Overview2.3.1ARM®Cortex™-M3core with embedded Flash and SRAMThe ARM Cortex™-M3processor is the latest generation of ARM processors for embeddedsystems.It has been developed to provide a low-cost platform that meets the needs of MCUimplementation,with a reduced pin count and low-power consumption,while deliveringoutstanding computational performance and an advanced system response to interrupts.The ARM Cortex™-M332-bit RISC processor features exceptional code-efficiency,delivering the high-performance expected from an ARM core in the memory size usuallyassociated with8-and16-bit devices.The STM32F103xx performance line family having an embedded ARM core,is thereforecompatible with all ARM tools and software.Figure1shows the general block diagram of the device family.2.3.2Embedded Flash memory64or128Kbytes of embedded Flash is available for storing programs and data.2.3.3CRC(cyclic redundancy check)calculation unitThe CRC(cyclic redundancy check)calculation unit is used to get a CRC code from a32-bitdata word and a fixed generator polynomial.Among other applications,CRC-based techniques are used to verify data transmission orstorage integrity.In the scope of the EN/IEC60335-1standard,they offer a means ofverifying the Flash memory integrity.The CRC calculation unit helps compute a signature ofthe software during runtime,to be compared with a reference signature generated at link-time and stored at a given memory location.2.3.4Embedded SRAMTwenty Kbytes of embedded SRAM accessed(read/write)at CPU clock speed with0waitstates.2.3.5Nested vectored interrupt controller(NVIC)The STM32F103xx performance line embeds a nested vectored interrupt controller able tohandle up to43maskable interrupt channels(not including the16interrupt lines ofCortex™-M3)and16priority levels.•Closely coupled NVIC gives low-latency interrupt processing•Interrupt entry vector table address passed directly to the core•Closely coupled NVIC core interface•Allows early processing of interrupts•Processing of late arriving higher priority interrupts•Support for tail-chaining•Processor state automatically saved•Interrupt entry restored on interrupt exit with no instruction overhead14/105DocID13587Rev16万联芯城专注电子元器件配单服务，只售原装现货库存，万联芯城电子元器件全国供应，专为终端生产，研发企业提供现货物料，价格优势明显，BOM配单采购可节省逐个搜索购买环节，只需提交BOM物料清单，商城即可为您报价，解决客户采购烦恼，为客户节省采购成本，点击进入万联芯城。
Excel格式的STM32F20x系列引脚表
2. FT = 5 V tolerant; TT =3.6 V tolerant.3. Function availability depends on the chosen device.4. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the u5. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after reset (because6. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).7. If the device is delivered in an UFBGA176 package and if the REGOFF pin is set to V DD (Regulator OFF), then PA0 is used as an internal Reset (active low8. FSMC_NL pin is also named FSMC_NADV on memory devices.9. RFU means “reserved for future use”. This pin can be tied to V DD,V SS or left unconnected.the use of GPIOs PC13 to PC15 and PI8 in output modause these registers are not reset by the main reset). Fo used as an internal Reset (active low).t mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive et). For details on how to manage these I/Os, refer to the RTC register description sections in the STM32F20x and STM32F21x reference manual, availo drive an LED)., available from the STMicroelectronics website: .。
MiniSTM32 V3 IO引脚分配表
接任何其他外设，且不接任何上拉/下拉电阻）
个IO口的使用
子科技有限公司（ALIENTEK）
使用提示 只要KEY_UP不按下，该IO完全独立 可通过跳线帽连接1820和PA0，实现连接DS18B20传感器接口，从而连接数字温度传感器 注意：PA0和1820用跳线帽连接后，WK_UP按键将"失灵",所有按键相关例程都将失效 该IO直接接NRF24L01模块接口的IRQ引脚，还可以通过跳线帽连接HS0038红外接收头(短 接RMT和PA1，有4.7K上拉电阻)，当断开该跳线帽,且不接NRF24L01模块时，则可以完全 该IO接W25Q64的片选信号，不建议做普通IO使用 仅连接SD卡接口的片选脚，有47K上拉电阻，当不使用SD卡时，可做普通IO使用 接NRF24L01接口的CE脚，当不使用NRF24L01接口时，该IO完全独立 当不使用W25Q64(片选禁止)、SD卡和NRF24L01接口时，该IO可做普通IO使用（有47K上 当不使用W25Q64(片选禁止)、SD卡和NRF24L01接口时，该IO可做普通IO使用（有47K上 当不使用W25Q64(片选禁止)、SD卡和NRF24L01接口时，该IO可做普通IO使用（有47K上 该IO连接DS0，即红色LED灯。如做普通IO用，则DS0也受控制，建议：仅做输出用 该IO通过P4选择是否连接CH340的RXD，如果不连接，则该IO完全独立 该IO通过P4选择是否连接CH340的TXD，如果不连接，则该IO完全独立 该IO直接接USB D-脚，如果USB接口不接线，则该IO完全独立 该IO直接接USB D+脚，如果USB接口不接线，则该IO完全独立 JTAG/SWD仿真接口，没连外设。建议仿真器选择SWD调试，这样仅SWDIO和SWDCLK两个信 号即可仿真。该IO做普通IO用(有10K上/下拉电阻)，需先禁止JTAG&SWD！此时无法仿 真！ 库函数全禁止方法：GPIO_PinRemapConfig(GPIO_Remap_SWJ_Disable) JTAG仿真口，也接PS/2接口的CLK信号和按键KEY1，如不用JTAG&PS/2接口&KEY1按键， 则可做普通IO用(有10K上拉电阻)。做普通IO用，需先禁止JTAG。此时可SWD仿真，但 JTAG无法仿真。 库函数禁止JTAG方法：GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable) 寄存器禁止JTAG方法:JTAG_Set(SWD_ENABLE) 该IO接TFTLCD模块接口的D0，当不插TFTLCD模块时，该IO完全独立 该IO接TFTLCD模块接口的D1，当不插TFTLCD模块时，该IO完全独立 该IO在上电时，作BOOT1用(由B1控制上拉/下拉，设置启动模式)，同时作为TFTLCD模块 接口的D2，当不插TFTLCD模块时，则可做普通IO用(有10K上拉/下拉,B0控制) JTAG仿真口，同时作为TFTLCD模块接口的D3，如不用JTAG和TFTLCD模块接口，则可做普 通IO用(有10K上拉电阻)。做普通IO用时，需先禁止JTAG。此时可用SWD仿真，但JTAG无 法仿真。设置方法参考PA15的用法。 JTAG仿真口，同时作为TFTLCD模块接口的D4，如不用JTAG和TFTLCD模块接口，则可做普 通IO用(有10K上拉电阻)。做普通IO用时，需先禁止JTAG。此时可用SWD仿真，但JTAG无 法仿真。设置方法参考PA15的用法。 该IO接TFTLCD模块接口的D5，当不插TFTLCD模块时，该IO完全独立 该IO接TFTLCD模块接口的D6，当不插TFTLCD模块时，该IO完全独立 该IO接TFTLCD模块接口的D7，当不插TFTLCD模块时，该IO完全独立 该IO接TFTLCD模块接口的D8，当不插TFTLCD模块时，该IO完全独立 该IO接TFTLCD模块接口的D9，当不插TFTLCD模块时，该IO完全独立 该IO接TFTLCD模块接口的D10，当不插TFTLCD模块时，该IO完全独立 该IO接TFTLCD模块接口的D11，当不插TFTLCD模块时，该IO完全独立 该IO接TFTLCD模块接口的D12，当不插TFTLCD模块时，该IO完全独立 该IO接TFTLCD模块接口的D13，当不插TFTLCD模块时，该IO完全独立 该IO接TFTLCD模块接口的D14，当不插TFTLCD模块时，该IO完全独立 该IO接TFTLCD模块接口的D15，当不插TFTLCD模块时，该IO完全独立 该IO接TFTLCD模块接口的触摸屏SCK信号，当不插TFTLCD模块时，该IO完全独立 该IO接TFTLCD模块接口的触摸屏PEN信号(中断)，当不插TFTLCD模块时，该IO完全独立
STM32F439系列引脚封装EXCEL表(原创)
85 P10 PE11 86 R10 PE12 87 R12 PE13 88 P11 PE14 89 R11 PE15 90 P12 PB10 91 R13 PB11 92 L11 VCAP_1 93 94 K9 VSS L10 VDD
95 M14 PJ5 96 P13 PH6 97 N13 PH7 98 P14 PH8 99 N14 PH9 100 P15 PH10 101 N15 PH11 102 M15 PH12 K10 VSS
FT FT FT RS T FT FT FT FT
30 H10 33 31 H9 34 32 H8 35 33 K11 36 34 J10 37 35 36 J9 G7 38 39 -
37 K10 40 38 39 40 41 42 43 44 45 46 L11 41 L10 42 K9 K8 L9 43 44 45 46 47 48 49
78 K13 P14 97 79 K11 N15 98 80 H10 N14 99 81 83 84
M1 109 L14 PD9 H4 110 K15 PD10
K2 111 N10 PD11 J13 N13 100 H6 112 M10 PD12 82 K12 M15 101 H5 113 M11 PD13 F7 102 J2 J13 103 L1 114 J10 VSS 115 J11 VDD 116 L12 PD14
62 G10 N9
M8 P10 74 N8 R10 75 H9 N11 76 J9 P11 77 K9 R11 78 L9 R12 79 M9 R13 80 N9 M10 81 F8 N10 82 N10 M11 83 M10 N12 84 L10 M12 85 K10 M13 86 N11 L13 87 M11 L12 88 L11 K12 89 E7 H12 90 H8 J12 91
stm32f030f4p6数据手册_引脚图_参数
3.10.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.11 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Up to 10 timers – One 16-bit 7-channel advanced-control timer for 6 channels PWM output, with deadtime generation and emergency stop – One 16-bit timer, with up to 4 IC/OC, usable for IR control decoding – One 16-bit timer, with 2 IC/OC, 1 OCN, deadtime generation and emergency stop – Two 16-bit timers, each with IC/OC and OCN, deadtime generation, emergency stop and modulator gate for IR control – One 16-bit timer with 1 IC/OC
Datasheet target specification
LQFP64 10x10 mm LQFP48 7x7 mm LQFP32 7x7 mm
TSSOP20
– One 16-bit basic timer – Independent and system watchdog timers – SysTick timer: 24-bit downcounter
STM32_引脚排列xls格式
FSMC_A00 FSMC_A01 FSMC_A02 FSMC_A03 FSMC_A04 FSMC_A05
FSMC_NIORD FSMC_NREG FSMC_NIOWR FSMC_CD FSMC_INT
42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
封装 P144 P100 P64 1 1 2 2 3 3 4 4 5 5 6 6 1 7 7 2 8 8 3 9 9 4 10 11 12 13 14 15 16 10 17 11 18 19 20 21 22 23 12 5 24 13 6 25 14 7 26 15 8 27 16 9 28 17 10 29 18 11 30 19 12 31 20 32 21 33 22 13 34 23 14 35 24 15 36 25 16 37 26 17 38 27 18 39 28 19 40 29 20 41 30 21
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
TIM3_CH3/TIM8_CH2N TIM3_CH4/TIM8_CH3N
I2C2_SCL I2C2_SDA
TIM1_BKIN TIM1_CH1N TIM1_CH2N TIM1_CH3N
I2S2_WS/I2C2_SMBA I2S2_CK I2S2_CD
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定义 P48 pin name PE02 PE03 PE04 PE05 PE06 VBAT PC13(5) PC14(5) PC15(5) PF00 PF01 PF02 PF03 PF04 PF05 VSS_5 VDD_5 PF06 PF07 PF08 PF09 PF10 OSC_IN OSC_OUT NRST PC00 PC01 PC02 PC03 VSSA VREFVREF+ VDDA PA00 PA01 PA02 PA03 VSS_4 VDD_4 PA04 PA05 main(3) PE02 PE03 PE04 PE05 PE06 VBAT PC13(6) PC14(6) PC15(6) PF00 PF01 PF02 PF03 PF04 PF05 VSS_5 VDD_5 PF06 PF07 PF08 PF09 PF10 OSC_IN OSC_OUT NRST PC00 PC01 PC02 PC03 VSSA VREFVREF+ VDDA PA00 PA01 PA02 PA03 VSS_4 VDD_4 PA04 PA05 FSMC FSMC_A23 FSMC_A19 FSMC_A20 FSMC_A21 FSMC_A22
USART3_CK USART3_CTS USART3_RTS
USART1_CK USART1_TX USART1_RX USART1_CTS USART1_RTS
SPI3_NSS UART4_TX UART4_RX UART5_TX
UART5_RX
SPI3_SCK SPI3_MISO SPI3_MOSI
PG13 PG14 VSS_11 VDD_11 PG15 JTDO NJTRST PB05 PB06 PB07 BOOT0 PB08 PB09 PE00 PE01 VSS_3 VDD_3
FSMC_A24 FSMC_A25
FSMC_NADV
FSMC_NBL0 FSMC_NBL1
制作：谭志平 EMAIL: knight# 版本： V20130727
te functions(4) TIMER OTERS
TIM5_CH1/TIM2_CH1_ETR/TIM8_ETR TIM5_CH2/TIM2_CH2(8) TIM5_CH3/TIM2_CH3(8) TIM5_CH4/TIM2_CH4(8)
DAC_OUT1 DAC_OUT2
TIM3_CH1(8)/TIM8_BKIN TIM3_CH2(H1 TIM3_CH2 TIM3_CH3 TIM3_CH4
PA13
TIM2_CH1_ETR USART3_TX USART3_RX USART3_CK CAN_RX CAN_TX USART2_CTS USART2_RTS USART2_TX
SPI1_NSS(8) SPI1_SCK(8)
USART2_CK(8)
ADC12_IN6 ADC12_IN7 ADC12_IN14 ADC12_IN15 ADC12_IN8 ADC12_IN9
SPI1_MISO(8) SPI1_MOSI(8)
USART3_TX(8) USART3_RX(8)
SPI2_NSS SPI2_SCK SPI2_MISO SPI2_MOSI
封装 P144 P100 P64 1 1 2 2 3 3 4 4 5 5 6 6 1 7 7 2 8 8 3 9 9 4 10 11 12 13 14 15 16 10 17 11 18 19 20 21 22 23 12 5 24 13 6 25 14 7 26 15 8 27 16 9 28 17 10 29 18 11 30 19 12 31 20 32 21 33 22 13 34 23 14 35 24 15 36 25 16 37 26 17 38 27 18 39 28 19 40 29 20 41 30 21
61 62
63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 5 6 54
87 88
PD14 PD15 PG02 PG03 PG04 PG05 PG06 PG07 PG08 VSS_9 VDD_9 PC06 PC07 PC08 PC09 PA08 PA09 PA10 PA11 PA12 PA13 NC VSS_2 VDD_2 PA14 PA15 PC10 PC11 PC12 PD00 PD01 PD02 PD03 PD04 PD05 VSS_10 VDD_10 PD06 PD07 PG09 PG10 PG11 PG12
31 32 33 34 35 36 37
22 23 24 25 26 27 28
38 39 40
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
29 30 31 32 33 34 35 36
PA06 PA07 PC04 PC05 PB00 PB01 PB02 PF11 PF12 VSS_6 VDD_6 PF13 PF14 PF15 PG00 PG01 PE07 PE08 PE09 VSS_7 VDD_7 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 PB12 PB13 PB14 PB15 PD08 PD09 PD10 PD11 PD12 PD13 VSS_8 VDD_8
FSMC_D00 FSMC_D01 FSMC_A12 FSMC_A13 FSMC_A14 FSMC_A15 FSMC_INT2 FSMC_INT3
FSMC_D02 FSMC_D03 FSMC_CLK FSMC_NOE FSMC_NWE
FSMC_NWAIT FSMC_NE1/NCE2 FSMC_NE2/NCE3 FSMC_NE3/NCE4_1 FSMC_NCE4_2 FSMC_NCE4
PD14 PD15 PG02 PG03 PG04 PG05 PG06 PG07 PG08 VSS_9 VDD_9 PC06 PC07 PC08 PC09 PA08 PA09 PA10 PA11 PA12 JTMS/SWDIO NC VSS_2 VDD_2 JTCLK/SWCLK JTDI PC10 PC11 PC12 OSC_IN(9) OSC_OUT(9) PD02 PD03 PD04 PD05 VSS_10 VDD_10 PD06 PD07 PG09 PG10 PG11 PG12
nput / O--output / S--supply
的可用性取决于所选择的器件型号 多个外设共用同一个引脚，为避免冲突，应该在同一时间内仅使能一个外设和其外设时钟 \PC14\PC15由可关开的电源供电，其供电电流限制在3mA以内，所这几个GPIO在输出模式使用有以下限制： a、速度<2MHz (30pf) b、驱动能力小，比如：不能驱动LED
TIM4_CH1 TIM4_CH2 TIM4_CH3 TIM4_CH4 TIM4_ETR
能一个外设和其外设时钟 ，所这几个GPIO在输出模式使用有以下限制：
TIMER
remap USART
OTHERS
TIM1_BKIN TIM1_CH1N
TIM1_CH2N TIM1_CH3N
TIM1_ETR TIM1_CH1N TIM1_CH1
FSMC_NIOS16 FSMC_A06
FSMC_A07 FSMC_A08 FSMC_A09 FSMC_A10 FSMC_A11 FSMC_D04 FSMC_D05 FSMC_D06
FSMC_D07 FSMC_D08 FSMC_D09 FSMC_D10 FSMC_D11 FSMC_D12
FSMC_D13 FSMC_D14 FSMC_D15 FSMC_A16 FSMC_A17 FSMC_A18
I2S2_MCK/SDIO_D6 I2S3_MCK/SDIO_D7 SDIO_D0 SDIO_D1 MCO
USBDM/CAN_RX(8) USBDP/CAN_TX(8)
I2S3_WS SDIO_D2 SDIO_D3 SDIO_CK
TIM3_ETR
SDIO_CMD
I2S3_CK I2S3_SD/I2C1_SMBA I2C1_SCL I2C1_SDA SDIO_D4 SDIO_D5
TIM1_CH2N TIM1_CH2 TIM1_CH3N TIM1_CH3 TIM1_CH4 TIM1_BKIN TIM2_CH3 TIM2_CH4
TIM4_CH1 TIM4_CH2
USART3_TX USART3_RX USART3_CK USART3_CTS USART3_RTS
TIM4_CH3 TIM4_CH4
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
TIM3_CH3/TIM8_CH2N TIM3_CH4/TIM8_CH3N
I2C2_SCL I2C2_SDA
TIM1_BKIN TIM1_CH1N TIM1_CH2N TIM1_CH3N
I2S2_WS/I2C2_SMBA I2S2_CK I2S2_CD
TIM8_CH1 TIM8_CH2 TIM8_CH3 TIM8_CH4 TIM1_CH1(8) TIM1_CH2(8) TIM1_CH3(8) TIM1_CH4(8) TIM1_ETR(8)
PA06 PA07 PC04 PC05 PB00 PB01 PB02/BOOT1 PF11 PF12 VSS_6 VDD_6 PF13 PF14 PF15 PG00 PG01 PE07 PE08 PE09 VSS_7 VDD_7 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 PB12 PB13 PB14 PB15 PD08 PD09 PD10 PD11 PD12 PD13 VSS_8 VDD_8