(基于双层MoS2晶体管的集成电路)文献翻译
1-Few-Layer MoS2,ACS Nano,2014
are highlighted.transition metal dichalcogenides.2D.nanosheetsFigure1.Crystal structure of MoS2.(a)Top view of mono-layer hexagonal crystal structure of MoS2.(b)Trigonal prismatic(2H)and octahedral(1T)unit cell structures.Panel a reprinted by permission from Macmillan Publishers Ltd: Nature Photonics,ref53,copyright2012.Panel b reproducedFigure2.Raman and IR-active phonons.(a)Illustrations of the four Raman-active phonon modes(E1g,E2g1,A1g,and E2g2)and one IR-active phonon mode(E1u)and their interlayer interactions.(b)Illustrations of the interlayer breathing and shear modes.(c)E2g1and A1g Raman peaks in few-layerflakes.(d,e)Evolution of low-frequency spectra with increasing layer number of the interlayer breathing(B1and B2)and shear(S1and S2)modes using(d)the(xx)z polarization configuration and the(xy)z polarization configuration.Panels a and c reprinted from ref49.Copyright2010American Chemical Society. Panels b,d,and e reprinted from ref65.Copyright2013American Chemical Society.Figure3.Band structure of MoS2(a)showing the direct and indirect band gap,as well as the A and B excitons.(b)Transition of the band structure of MoS2from indirect to direct band gap(a f d).Panel a reprinted with permission from ref50.Copyright 2010American Physical Society.Panel b reprinted from ref80.Copyright2010American Chemical Society.Figure4.Variation of band structure properties with strain.(a,c,d)Shift of absorbance and photoluminescence peaks with application of uniaxial tensile strain.(b)Evolution of the band structure of monolayer MoS2under various values of biaxial strain and consequent lattice constants as measured using different calculation models(DFT-PBE,G0W0,SCGW0).Panels a,c, and d reprinted from ref128.Copyright2013American Chemical Society.Panel b reprinted with permission from ref124. Copyright2013American Physical Society.Carrier Physics.The effective mass for electrons almost charge-neutral pair and are less susceptible toFigure5.Optical characterization.(a)Photoluminescence spectra for monolayer and bilayer MoS2.(b)Normalized photo-luminescence spectra of MoS2with increasing number of layers,showing evolution of A and B excitons as well as the I peak of indirect transition.(c)Evolution of band gap with layer number of MoS2.Reproduced with permission from ref50.Copyright 2010American Physical Society.The photoluminescence spectra for MoS 2show two exciton peaks (see Figure 5b)called exciton A ∼1.92eV)and B (∼2.08eV)at the K point 50,80and polarization of incident light.140The ability to a ffect trion movement through the application of electric fields could be of great use in optoelectronics toward Figure 6.Trion behavior with gate-induced doping.(a)Absorbance and photoluminescence spectra of A excitons and Àtrions with variation of indicated gate voltages.(b)Threshold energies of the trions ωA À(black dots)and neutral exciton A (red dots)plotted against gate voltage (above)and Fermi energy (below).(c)Plot of di fference in energies between trions and excitons (ωA ÀωA À)as a function of Fermi energy.Reprinted by permission from Macmillan Publishers Ltd:Nature Materials,ref 140,copyright 2012.a smooth narrowing of band gap.This is a very appealing concept and requires extensive practical experimentation to realize.A recent strain-engineered experiment129did show signs of a funnelling effect of excitons in MoS2.Spintronics and Valleytronics.Traditionally,a flow spin degeneracy along theΓÀK line of the conduction as well the valence bands,resulting in a band splitting of148eV.156Spin relaxation length was predicted to be quite large at about0.4μm at room temperature.157 The band structure of monolayer MoS2displays two valleys,KþandÀK(or KÀ),at the extreme corners ofFigure7.Strain-induced optical funnel.(a,b)Illustrations of the possible physical setups of a varying strain system.(c)Spectra of the band transition peaks with varying strain.(d)Variation of band structure with applied strain.Reprinted by permission from Macmillan Publishers Ltd:Nature Photonics,ref152,copyright2012.Figure8.Valley polarization.(a)Illustration of the K(or Kþ,shown in red)andÀK(or KÀ,shown in teal)valleys in the bottomof the conduction band(purple)and the top of the valence band(blue);ηis the k-resolved degree of optical polarizationbetween the top of the valence bands and the bottom of the conduction bands.(b)Data points of observed out-of-plane right(black)or left(red)polarized luminescence from monolayer MoS2when incident with correspondingly polarized light,where Pσþis the degree of right-circular polarization and PσÀis the degree of left-circular polarization.Panel a reprinted by permission from Macmillan Publishers Ltd:Nature Communications,ref153,copyright2012.Panel b reproduced withpermission from ref53.Copyright2012Nature Publishing Group.Figure9.Spin and valley coupling.Illustration of the K(orK0(or KÀ)coupled with left-circular(blue)and right-circular(red)spin-polarization.Reprinted by permission fromMacmillan Publishers Ltd:Nature Nanotechnology,refThis causes ultrathin material layers to be left on the substrate.2has been known much earlier than mechanical exfoliation.40,181Chemical exfoliation has recently gainedFigure10.Exfoliation of MoS2.(a)Optical and(b)AFM height image of multilayer sections of a MoS2flake on a285nm silicon oxide substrate.(c)Height profile of a MoS2flake measured along the dotted line in(b).(d)Chemically exfoliated MoS2flakes, roughly segregated according toflake size at different rpm through centrifugation.(e)Illustration of controlled lithiation and subsequent exfoliation using an electrochemical setup.Panels aÀc reproduced with permission from ref71.Copyright2012 Wiley-VCH Verlag GmbH&Co.KGaA.Panel d reproduced from ref178.Copyright2012American Chemical Society.Panel e reproduced with permission from ref179.Copyright2011Wiley-VCH Verlag GmbH&Co.KGaA.into MoS2,S,H2S,and NH3gases,and MoS2was depos-ited onto the substrate.Sulfur in powder form could also graphene did influence the growth process.In sharp contrast,bare Cu did not show hexagonal MoS2islandFigure11.Growth techniques.MoS2growth using(a)ammonium thiomolybdate,(b)elemental molybdenum,and (c)molybdenum trioxide as the precursors.Panel a reproduced from ref108.Copyright2012American Chemical Society.Panel b reproduced with permission from ref111.Copyright2013AIP Publishing LLC.Panel c reproduced with permission from ref 116.Copyright2012The Royal Society of Chemistry.through layers to travel across layers.The simulation predicted the presence of a“hot spot”,that is,a particular layer or set of adjacent layers through which studies.82,100,109,110,112,113,119,121,201,205,207À211High-κgate dielectrics and dielectric engineering in general have been proposed105to suppress Coulomb scatter-Figure12.MoS2device and performance.(a)Illustration of a top-gate monolayer MoS2FET with a high-κHfO2gate dielectric.V g device characteristics measured using(b)top gate and(c)back gate.(d)I dsÀV ds characteristics plot.Reprinted permission from Macmillan Publishers Ltd:Nature Nanotechnology,ref82,copyright2011.Figure13.Currentflow in MoS2layers.(a)Movement of conduction“hot spot”in multilayer MoS2devices with variation of gate voltage.(b)Illustration of series-parallel resistor model for multilayer MoS2devices.Reproduced from ref206.Copyright 2013American Chemical Society.Figure14.Other device variants and applications.(a)Illustration of MoS2/grapheneflash memory cell.(b)Illustration of a flexible MoS2device fabricated on aflexible substrate.Panel a reproduced from(a)ref213.Copyrightª2013American Chemical Society.Panel b reproduced from ref210.Copyright2013American Chemical Society.Figure15.Optoelectronic devices.(a)Illustration and(b)optical image of a high-performance rugged metalÀsemiconductorÀmetal photodetector(MSM-PD)along with its on/offratio characteristics(c,d).(e)Illustration of a monolayer optoelectronic device with a high-κAl2O3gate dielectric and an ITO top gate.Panels a-d reproduced from ref134.Copyrightª2013American Chemical Society.Panel e reproduced from ref218.Copyright2012American Chemical Society.Figure16.GMG heterostructure and band diagrams.(a,b)Illustrations of the graphene/MoS2/graphene(GMG)structure.(c) CurrentÀvoltage characteristics of a GMG device in the dark(blue)and when illuminated(red).(dÀg)Evolution of the device's band alignment and photogenerated electrons and holes(in the case of laser illumination)for V BG=0(d),V BG<0(e),V BG>0(f), and V BG.0(g).Reprinted by permission from Macmillan Publishers Ltd:Nature Nanotechnology,ref222,copyright2013. spectrum range were achieved.Importantly,the devices of a few tens of nanometers.The source,drain,andnanoribbon(AGNR)as Gr T.The DOS of graphene nanoribbons had a one-dimensional dependence which manifested in the form of repetitive current peaks in the IÀV b curves corresponding with changes in the AGNR's DOS at E as V was varied.GMG variable control of the degree of photogenerated carrier separation and thus photogenerated current.A top-gated device allowed for greater electricfield within the structure and thus greater band bending for V.0causing photocurrent inversion due toFigure17.Photoresponsive memory heterostructure.(a)Illustration showing the change in carrier distribution with time. Illumination pulse is given at time t=0.(b)Photoresponse graph with gate pulses and applied negative back-gate voltages.(c)Illustration of carrierflow and Fermi level positions of graphene and MoS2with negative(left)and positive(right)gate voltages applied.Reprinted by permission from Macmillan Publishers Ltd:Nature Nanotechnology,ref227,copyright2013.T half-metal T magnetic metal)with stability,showing a wide range of tunability and magnetic properties.236The band gap MoS2sheets,albeit with a slight red shift as those seen in few-layer MoS2sheets due effects.242Lithium-doped MNTs were foundNanoribbons and nanotubes.Illustrations of(a)zigzag and(b)armchair MoS2nanoribbons.magnetic moments at the edges of a zigzag MoS2nanoribbon.Simulated diffraction patterns (middle),and c-axis(bottom)of(d)zigzag and(e)armchair MoS2nanotubes.Panels aÀc reproduced 2008American Chemical Society.Panels d and e reproduced from ref240.Copyright2000American。
文献翻译(二次电流层)
激光等离子体相互作用中磁重联引起的等离子体与二次电流层生成的研究摘要:以尼尔逊[物理学家、列托人,97,255001,(2006)]为代表的科学家首次对等离子体相互作用引起的磁重联进行了研究,该研究在固体等离子体层上进行,在两个激光脉冲中间设置一定间隔,在两个激光斑点之间可以发现一条细长的电流层(CS),为了更加贴切的模拟磁重联过程,我们应该设置两个并列的目标薄层。
实验过程中发现,细长的电流层的一端出现一个折叠的电子流出区域,该区域中含有三条平行的电子喷射线,电子射线末端能量分布符合幂律法则。
电子主导磁重联区域强烈的感应电场增强了电子加速,当感应电场处于快速移动的等离子体状态时还会进一步加速,另外弹射过程会引起一个二级电流层。
正文:等离子体的磁重联与爆炸过程磁能量进入等离子体动能和热能能量的相互转换有关。
发生磁重联的薄层区域加速并释放等离子体[1-5]。
实验中磁重联速度与太阳能的观察结果大于Sweet-Parker与相关模型[4-6]的标准值,这是由霍尔电流和湍流[7-12]引起的。
二级磁岛以及该区域释放的等离子体可以提高磁重联速度,当伦德奎斯特数S﹥104[13]时二级磁导很不稳定。
这些理论预测值与近地磁尾离子扩散区域中心附近的二级磁岛观察值相符[14],激光束与物质的相互作用的过程中,正压机制激发兆高斯磁场(▽ne×▽Te)生成[15-16]。
以尼尔逊[17]为代表的科学家首次运用两个类似的的激光产生的等离子体模拟磁重联过程。
尼尔逊[17]与Li[18]等人实验测量数据为磁重联的存在提供了决定性的证据,他们运用了随时间推移的质子偏转技术来研究磁拓扑变化,除此之外尼尔逊[17]等人观察到高度平行双向等离子喷射线与预期的磁重联平面成40°夹角。
本次研究调查了自发磁场的无碰撞重联,激光等离子体相互作用产生等离子体,为了防止磁场与等离子体连接在一起实验过程使用了两个共面有一定间隔的等离子体。
集成电路专业英语词汇
Abrupt junction 突变结Accelerated testing 加速实验Acceptor 受主Acceptor atom 受主原子Accumulation 积累、堆积Accumulating contact 积累接触Accumulation region 积累区Accumulation layer 积累层Active region 有源区Active component 有源元Active device 有源器件Activation 激活Activation energy 激活能Active region 有源(放大)区Admittance 导纳Allowed band 允带Alloy-junction device合金结器件Aluminum(Aluminium) 铝Aluminum – oxide 铝氧化物Aluminum passivation 铝钝化Ambipolar 双极的Ambient temperature 环境温度Amorphous 无定形的,非晶体的Amplifier 功放扩音器放大器Analogue(Analog) comparator 模拟比较器Angstrom 埃Anneal 退火Anisotropic 各向异性的Anode 阳极Arsenic (AS) 砷Auger 俄歇Auger process 俄歇过程Avalanche 雪崩Avalanche breakdown 雪崩击穿Avalanche excitation雪崩激发Background carrier 本底载流子Background doping 本底掺杂Backward 反向Backward bias 反向偏置Ballasting resistor 整流电阻Ball bond 球形键合Band 能带Band gap 能带间隙Barrier 势垒Barrier layer 势垒层Barrier width 势垒宽度Base 基极Base contact 基区接触Base stretching 基区扩展效应Base transit time 基区渡越时间Base transport efficiency基区输运系数Base-width modulation基区宽度调制Basis vector 基矢Bias 偏置Bilateral switch 双向开关Binary code 二进制代码Binary compound semiconductor 二元化合物半导体Bipolar 双极性的Bipolar Junction Transistor (BJT)双极晶体管Bloch 布洛赫Blocking band 阻挡能带Blocking contact 阻挡接触Body - centered 体心立方Body-centred cubic structure 体立心结构Boltzmann 波尔兹曼Bond 键、键合Bonding electron 价电子Bonding pad 键合点Bootstrap circuit 自举电路Bootstrapped emitter follower 自举射极跟随器Boron 硼Borosilicate glass 硼硅玻璃Boundary condition 边界条件Bound electron 束缚电子Breadboard 模拟板、实验板Break down 击穿Break over 转折Brillouin 布里渊Brillouin zone 布里渊区Built-in 内建的Build-in electric field 内建电场Bulk 体/体内Bulk absorption 体吸收Bulk generation 体产生Bulk recombination 体复合Burn - in 老化Burn out 烧毁Buried channel 埋沟Buried diffusion region 隐埋扩散区Can 外壳Capacitance 电容Capture cross section 俘获截面Capture carrier 俘获载流子Carrier 载流子、载波Carry bit 进位位Carry-in bit 进位输入Carry-out bit 进位输出Cascade 级联Case 管壳Cathode 阴极Center 中心Ceramic 陶瓷(的)Channel 沟道Channel breakdown 沟道击穿Channel current 沟道电流Channel doping 沟道掺杂Channel shortening 沟道缩短Channel width 沟道宽度Characteristic impedance 特征阻抗Charge 电荷、充电Charge-compensation effects 电荷补偿效应Charge conservation 电荷守恒Charge neutrality condition 电中性条件Charge drive/exchange/sharing/transfer/storage 电荷驱动/交换/共享/转移/存储Chemmical etching 化学腐蚀法Chemically-Polish 化学抛光Chemmically-Mechanically Polish (CMP) 化学机械抛光Chip 芯片Chip yield 芯片成品率Clamped 箝位Clamping diode 箝位二极管Cleavage plane 解理面Clock rate 时钟频率Clock generator 时钟发生器Clock flip-flop 时钟触发器Close-packed structure 密堆积结构Close-loop gain 闭环增益Collector 集电极Collision 碰撞Compensated OP-AMP 补偿运放Common-base/collector/emitter connection 共基极/集电极/发射极连接Common-gate/drain/source connection 共栅/漏/源连接Common-mode gain 共模增益Common-mode input 共模输入Common-mode rejection ratio (CMRR) 共模抑制比Compatibility 兼容性Compensation 补偿Compensated impurities 补偿杂质Compensated semiconductor 补偿半导体Complementary Darlington circuit 互补达林顿电路Complementary Metal-Oxide-Semiconductor Field-Effect-Transistor(CMOS)互补金属氧化物半导体场效应晶体管Complementary error function 余误差函数Computer-aided design (CAD)/test(CAT)/manufacture(CAM) 计算机辅助设计/ 测试/制造Compound Semiconductor 化合物半导体Conductance 电导Conduction band (edge) 导带(底) Conduction level/state 导带态Conductor 导体Conductivity 电导率Configuration 组态Conlomb 库仑Conpled Configuration Devices 结构组态Constants 物理常数Constant energy surface 等能面Constant-source diffusion恒定源扩散Contact 接触Contamination 治污Continuity equation 连续性方程Contact hole 接触孔Contact potential 接触电势Continuity condition 连续性条件Contra doping 反掺杂Controlled 受控的Converter 转换器Conveyer 传输器Copper interconnection system 铜互连系统Couping 耦合Covalent 共阶的Crossover 跨交Critical 临界的Crossunder 穿交Crucible坩埚Crystal defect/face/orientation/lattice 晶体缺陷/晶面/晶向/晶格Current density 电流密度Curvature 曲率Cut off 截止Current drift/dirve/sharing 电流漂移/驱动/共享Current Sense 电流取样Curvature 弯曲Custom integrated circuit 定制集成电路Cylindrical 柱面的Czochralshicrystal 直立单晶Czochralski technique 切克劳斯基技术(Cz法直拉晶体J)Dangling bonds 悬挂键Dark current 暗电流Dead time 空载时间Debye length 德拜长度De.broglie 德布洛意Decderate 减速Decibel (dB) 分贝Decode 译码Deep acceptor level 深受主能级Deep donor level 深施主能级Deep impurity level 深度杂质能级Deep trap 深陷阱Defeat 缺陷Degenerate semiconductor 简并半导体Degeneracy 简并度Degradation 退化Degree Celsius(centigrade) /Kelvin 摄氏/开氏温度Delay 延迟Density 密度Density of states 态密度Depletion 耗尽Depletion approximation 耗尽近似Depletion contact 耗尽接触Depletion depth 耗尽深度Depletion effect 耗尽效应Depletion layer 耗尽层Depletion MOS 耗尽MOS Depletion region 耗尽区Deposited film 淀积薄膜Deposition process 淀积工艺Design rules 设计规则Die 芯片(复数dice)Diode 二极管Dielectric 介电的Dielectric isolation 介质隔离Difference-mode input 差模输入Differential amplifier 差分放大器Differential capacitance 微分电容Diffused junction 扩散结Diffusion 扩散Diffusion coefficient 扩散系数Diffusion constant 扩散常数Diffusivity 扩散率Diffusion capacitance/barrier/current/furnace 扩散电容/势垒/电流/炉Digital circuit 数字电路Dipole domain 偶极畴Dipole layer 偶极层Direct-coupling 直接耦合Direct-gap semiconductor 直接带隙半导体Direct transition 直接跃迁Discharge 放电Discrete component 分立元件Dissipation 耗散Distribution 分布Distributed capacitance 分布电容Distributed model 分布模型Displacement 位移Dislocation 位错Domain 畴Donor 施主Donor exhaustion 施主耗尽Dopant 掺杂剂Doped semiconductor 掺杂半导体Doping concentration 掺杂浓度Double-diffusive MOS(DMOS)双扩散MOS.Drift 漂移Drift field 漂移电场Drift mobility 迁移率Dry etching 干法腐蚀Dry/wet oxidation 干/湿法氧化Dose 剂量Duty cycle 工作周期Dual-in-line package (DIP)双列直插式封装Dynamics 动态Dynamic characteristics 动态属性Dynamic impedance 动态阻抗Early effect 厄利效应Early failure 早期失效Effective mass 有效质量Einstein relation(ship) 爱因斯坦关系Electric Erase Programmable Read Only Memory(E2PROM) 一次性电可擦除只读存储器Electrode 电极Electrominggratim 电迁移Electron affinity 电子亲和势Electronic -grade 电子能Electron-beam photo-resist exposure 光致抗蚀剂的电子束曝光Electron gas 电子气Electron-grade water 电子级纯水Electron trapping center 电子俘获中心Electron Volt (eV) 电子伏Electrostatic 静电的Element 元素/元件/配件Elemental semiconductor 元素半导体Ellipse 椭圆Ellipsoid 椭球Emitter 发射极Emitter-coupled logic 发射极耦合逻辑Emitter-coupled pair 发射极耦合对Emitter follower 射随器Empty band 空带Emitter crowding effect 发射极集边(拥挤)效应Endurance test =life test 寿命测试Energy state 能态Energy momentum diagram 能量-动量(E-K)图Enhancement mode 增强型模式Enhancement MOS 增强性MOS Entefic (低)共溶的Environmental test 环境测试Epitaxial 外延的Epitaxial layer 外延层Epitaxial slice 外延片Expitaxy 外延Equivalent curcuit 等效电路Equilibrium majority /minority carriers 平衡多数/少数载流子Erasable Programmable ROM (EPROM)可搽取(编程)存储器Error function complement 余误差函数Etch 刻蚀Etchant 刻蚀剂Etching mask 抗蚀剂掩模Excess carrier 过剩载流子Excitation energy 激发能Excited state 激发态Exciton 激子Extrapolation 外推法Extrinsic 非本征的Extrinsic semiconductor 杂质半导体Face - centered 面心立方Fall time 下降时间Fan-in 扇入Fan-out 扇出Fast recovery 快恢复Fast surface states 快界面态Feedback 反馈Fermi level 费米能级Fermi-Dirac Distribution 费米-狄拉克分布Femi potential 费米势Fick equation 菲克方程(扩散)Field effect transistor 场效应晶体管Field oxide 场氧化层Filled band 满带Film 薄膜Flash memory 闪烁存储器Flat band 平带Flat pack 扁平封装Flicker noise 闪烁(变)噪声Flip-flop toggle 触发器翻转Floating gate 浮栅Fluoride etch 氟化氢刻蚀Forbidden band 禁带Forward bias 正向偏置Forward blocking /conducting正向阻断/导通Frequency deviation noise频率漂移噪声Frequency response 频率响应Function 函数Gain 增益Gallium-Arsenide(GaAs) 砷化钾Gamy ray r 射线Gate 门、栅、控制极Gate oxide 栅氧化层Gauss(ian)高斯Gaussian distribution profile 高斯掺杂分布Generation-recombination 产生-复合Geometries 几何尺寸Germanium(Ge) 锗Graded 缓变的Graded (gradual) channel 缓变沟道Graded junction 缓变结Grain 晶粒Gradient 梯度Grown junction 生长结Guard ring 保护环Gummel-Poom model 葛谋-潘模型Gunn - effect 狄氏效应Hardened device 辐射加固器件Heat of formation 形成热Heat sink 散热器、热沉Heavy/light hole band 重/轻空穴带Heavy saturation 重掺杂Hell - effect 霍尔效应Heterojunction 异质结Heterojunction structure 异质结结构Heterojunction Bipolar Transistor(HBT)异质结双极型晶体High field property 高场特性High-performance MOS.( H-MOS)高性能MOS. Hormalized 归一化Horizontal epitaxial reactor 卧式外延反应器Hot carrior 热载流子Hybrid integration 混合集成Image - force 镜象力Impact ionization 碰撞电离Impedance 阻抗Imperfect structure 不完整结构Implantation dose 注入剂量Implanted ion 注入离子Impurity 杂质Impurity scattering 杂志散射Incremental resistance 电阻增量(微分电阻)In-contact mask 接触式掩模Indium tin oxide (ITO) 铟锡氧化物Induced channel 感应沟道Infrared 红外的Injection 注入Input offset voltage 输入失调电压Insulator 绝缘体Insulated Gate FET(IGFET)绝缘栅FET Integrated injection logic集成注入逻辑Integration 集成、积分Interconnection 互连Interconnection time delay 互连延时Interdigitated structure 交互式结构Interface 界面Interference 干涉International system of unions国际单位制Internally scattering 谷间散射Interpolation 内插法Intrinsic 本征的Intrinsic semiconductor 本征半导体Inverse operation 反向工作Inversion 反型Inverter 倒相器Ion 离子Ion beam 离子束Ion etching 离子刻蚀Ion implantation 离子注入Ionization 电离Ionization energy 电离能Irradiation 辐照Isolation land 隔离岛Isotropic 各向同性Junction FET(JFET) 结型场效应管Junction isolation 结隔离Junction spacing 结间距Junction side-wall 结侧壁Latch up 闭锁Lateral 横向的Lattice 晶格Layout 版图Lattice binding/cell/constant/defect/distortion 晶格结合力/晶胞/晶格/晶格常熟/晶格缺陷/晶格畸变Leakage current (泄)漏电流Level shifting 电平移动Life time 寿命linearity 线性度Linked bond 共价键Liquid Nitrogen 液氮Liquid-phase epitaxial growth technique 液相外延生长技术Lithography 光刻Light Emitting Diode(LED) 发光二极管Load line or Variable 负载线Locating and Wiring 布局布线Longitudinal 纵向的Logic swing 逻辑摆幅Lorentz 洛沦兹Lumped model 集总模型Majority carrier 多数载流子Mask 掩膜板,光刻板Mask level 掩模序号Mask set 掩模组Mass - action law质量守恒定律Master-slave D flip-flop主从D触发器Matching 匹配Maxwell 麦克斯韦Mean free path 平均自由程Meandered emitter junction梳状发射极结Mean time before failure (MTBF) 平均工作时间Megeto - resistance 磁阻Mesa 台面MESFET-Metal Semiconductor金属半导体FETMetallization 金属化Microelectronic technique 微电子技术Microelectronics 微电子学Millen indices 密勒指数Minority carrier 少数载流子Misfit 失配Mismatching 失配Mobile ions 可动离子Mobility 迁移率Module 模块Modulate 调制Molecular crystal分子晶体Monolithic IC 单片IC MOSFET金属氧化物半导体场效应晶体管Mos. Transistor(MOST )MOS. 晶体管Multiplication 倍增Modulator 调制Multi-chip IC 多芯片ICMulti-chip module(MCM) 多芯片模块Multiplication coefficient倍增因子Naked chip 未封装的芯片(裸片)Negative feedback 负反馈Negative resistance 负阻Nesting 套刻Negative-temperature-coefficient 负温度系数Noise margin 噪声容限Nonequilibrium 非平衡Nonrolatile 非挥发(易失)性Normally off/on 常闭/开Numerical analysis 数值分析Occupied band 满带Officienay 功率Offset 偏移、失调On standby 待命状态Ohmic contact 欧姆接触Open circuit 开路Operating point 工作点Operating bias 工作偏置Operational amplifier (OPAMP)运算放大器Optical photon =photon 光子Optical quenching光猝灭Optical transition 光跃迁Optical-coupled isolator光耦合隔离器Organic semiconductor有机半导体Orientation 晶向、定向Outline 外形Out-of-contact mask非接触式掩模Output characteristic 输出特性Output voltage swing 输出电压摆幅Overcompensation 过补偿Over-current protection 过流保护Over shoot 过冲Over-voltage protection 过压保护Overlap 交迭Overload 过载Oscillator 振荡器Oxide 氧化物Oxidation 氧化Oxide passivation 氧化层钝化Package 封装Pad 压焊点Parameter 参数Parasitic effect 寄生效应Parasitic oscillation 寄生振荡Passination 钝化Passive component 无源元件Passive device 无源器件Passive surface 钝化界面Parasitic transistor 寄生晶体管Peak-point voltage 峰点电压Peak voltage 峰值电压Permanent-storage circuit 永久存储电路Period 周期Periodic table 周期表Permeable - base 可渗透基区Phase-lock loop 锁相环Phase drift 相移Phonon spectra 声子谱Photo conduction 光电导Photo diode 光电二极管Photoelectric cell 光电池Photoelectric effect 光电效应Photoenic devices 光子器件Photolithographic process 光刻工艺(photo) resist (光敏)抗腐蚀剂Pin 管脚Pinch off 夹断Pinning of Fermi level 费米能级的钉扎(效应)Planar process 平面工艺Planar transistor 平面晶体管Plasma 等离子体Plezoelectric effect 压电效应Poisson equation 泊松方程Point contact 点接触Polarity 极性Polycrystal 多晶Polymer semiconductor聚合物半导体Poly-silicon 多晶硅Potential (电)势Potential barrier 势垒Potential well 势阱Power dissipation 功耗Power transistor 功率晶体管Preamplifier 前置放大器Primary flat 主平面Principal axes 主轴Print-circuit board(PCB) 印制电路板Probability 几率Probe 探针Process 工艺Propagation delay 传输延时Pseudopotential method 膺势发Punch through 穿通Pulse triggering/modulating 脉冲触发/调制PulseWiden Modulator(PWM) 脉冲宽度调制Punchthrough 穿通Push-pull stage 推挽级Quality factor 品质因子Quantization 量子化Quantum 量子Quantum efficiency量子效应Quantum mechanics 量子力学Quasi – Fermi-level准费米能级Quartz 石英Radiation conductivity 辐射电导率Radiation damage 辐射损伤Radiation flux density 辐射通量密度Radiation hardening 辐射加固Radiation protection 辐射保护Radiative - recombination辐照复合Radioactive 放射性Reach through 穿通Reactive sputtering source 反应溅射源Read diode 里德二极管Recombination 复合Recovery diode 恢复二极管Reciprocal lattice 倒核子Recovery time 恢复时间Rectifier 整流器(管)Rectifying contact 整流接触Reference 基准点基准参考点Refractive index 折射率Register 寄存器Registration 对准Regulate 控制调整Relaxation lifetime 驰豫时间Reliability 可靠性Resonance 谐振Resistance 电阻Resistor 电阻器Resistivity 电阻率Regulator 稳压管(器)Relaxation 驰豫Resonant frequency共射频率Response time 响应时间Reverse 反向的Reverse bias 反向偏置Sampling circuit 取样电路Sapphire 蓝宝石(Al2O3)Satellite valley 卫星谷Saturated current range电流饱和区Saturation region 饱和区Saturation 饱和的Scaled down 按比例缩小Scattering 散射Schockley diode 肖克莱二极管Schottky 肖特基Schottky barrier 肖特基势垒Schottky contact 肖特基接触Schrodingen 薛定厄Scribing grid 划片格Secondary flat 次平面Seed crystal 籽晶Segregation 分凝Selectivity 选择性Self aligned 自对准的Self diffusion 自扩散Semiconductor 半导体Semiconductor-controlled rectifier 可控硅Sendsitivity 灵敏度Serial 串行/串联Series inductance 串联电感Settle time 建立时间Sheet resistance 薄层电阻Shield 屏蔽Short circuit 短路Shot noise 散粒噪声Shunt 分流Sidewall capacitance 边墙电容Signal 信号Silica glass 石英玻璃Silicon 硅Silicon carbide 碳化硅Silicon dioxide (SiO2) 二氧化硅Silicon Nitride(Si3N4) 氮化硅Silicon On Insulator 绝缘硅Siliver whiskers 银须Simple cubic 简立方Single crystal 单晶Sink 沉Skin effect 趋肤效应Snap time 急变时间Sneak path 潜行通路Sulethreshold 亚阈的Solar battery/cell 太阳能电池Solid circuit 固体电路Solid Solubility 固溶度Sonband 子带Source 源极Source follower 源随器Space charge 空间电荷Specific heat(PT) 热Speed-power product 速度功耗乘积Spherical 球面的Spin 自旋Split 分裂Spontaneous emission 自发发射Spreading resistance扩展电阻Sputter 溅射Stacking fault 层错Static characteristic 静态特性Stimulated emission 受激发射Stimulated recombination 受激复合Storage time 存储时间Stress 应力Straggle 偏差Sublimation 升华Substrate 衬底Substitutional 替位式的Superlattice 超晶格Supply 电源Surface 表面Surge capacity 浪涌能力Subscript 下标Switching time 开关时间Switch 开关Tailing 扩展Terminal 终端Tensor 张量Tensorial 张量的Thermal activation 热激发Thermal conductivity 热导率Thermal equilibrium 热平衡Thermal Oxidation 热氧化Thermal resistance 热阻Thermal sink 热沉Thermal velocity 热运动Thermoelectricpovoer 温差电动势率Thick-film technique 厚膜技术Thin-film hybrid IC薄膜混合集成电路Thin-Film Transistor(TFT) 薄膜晶体Threshlod 阈值Thyistor 晶闸管Transconductance 跨导Transfer characteristic 转移特性Transfer electron 转移电子Transfer function 传输函数Transient 瞬态的Transistor aging(stress) 晶体管老化Transit time 渡越时间Transition 跃迁Transition-metal silica 过度金属硅化物Transition probability 跃迁几率Transition region 过渡区Transport 输运Transverse 横向的Trap 陷阱Trapping 俘获Trapped charge 陷阱电荷Triangle generator 三角波发生器Triboelectricity 摩擦电Trigger 触发Trim 调配调整Triple diffusion 三重扩散Truth table 真值表Tolerahce 容差Tunnel(ing) 隧道(穿)Tunnel current 隧道电流Turn over 转折Turn - off time 关断时间Ultraviolet 紫外的Unijunction 单结的Unipolar 单极的Unit cell 原(元)胞Unity-gain frequency 单位增益频率Unilateral-switch单向开关Vacancy 空位Vacuum 真空Valence(value) band 价带Value band edge 价带顶Valence bond 价键Vapour phase 汽相Varactor 变容管Varistor 变阻器Vibration 振动Voltage 电压Wafer 晶片Wave equation 波动方程Wave guide 波导Wave number 波数Wave-particle duality 波粒二相性Wear-out 烧毁Wire routing 布线Work function 功函数Worst-case device 最坏情况器件Yield 成品率Zener breakdown 齐纳击穿Zone melting 区熔法。
Integrated Circuits集成电路(英汉翻译)
Integrated Circuits集成电路The Integrated CircuitDigital logic and electronic circuits derive their functionality from electronic switches called transistor. (数字逻辑和电子电路由称为晶体管的电子开关得到它们的(各种)功能。
)Roughly speaking, the transistor can be likened to an electronically controlled valve whereby ener gy applied to one connection of the valve enables energy to flow between two other connections .By combining multiple transistors, digital logic building blocks such as AND gates and flip-flops ar e formed. Transistors, in turn, are made from semiconductors. (粗略地说,晶体管好似一种电子控制阀,由此加在阀一端的能量可以使能量在另外两个连接端之间流动。
通过多个晶体管的组合就可以构成数字逻辑模块,如与门和触发电路等。
而晶体管是由半导体构成的。
)Consult a periodic table of elements in a college chemistry textbook, and you will locate semicon ductors as a group of elements separating the metals and nonmetals.They are called semiconduct ors because of their ability to behave as both metals and nonmetals.(查阅大学化学书中的元素周期表,你会查到半导体是介于金属与非金属之间的一类元素。
多晶硅太阳能电池 毕业论文文献翻译 中英文对照
英文翻译Polycrystalline silicon solar cellsAs we all know, solar energy has many advantages, photovoltaic power generation will provide the main energy of mankind, but at present it, to make solar power a large market, is the general consumer acceptance, increased solar cell efficiency and reduce production costs should be our overriding goal, from the current development of the international solar cell can see the trend of its silicon, polycrystalline silicon, ribbon silicon, thin film materials (including trend of its silicon, polycrystalline silicon, ribbon silicon, thin film materials (including microcrystalline silicon thin films, compound-based thin film and dye film).From industrial development, it has been the focus of the direction of single crystal to polycrystalline, mainly due to;(1)the beginning and end of solar cell materials can supply less and less;(2)in terms of the solar cell, a square substrate is more cost-effective, by direct coagulation casting method and obtained direct access to a square polysilicon materials;(3)of polysilicon production technology continue to make progress, casting furnace automatic production cycle of each (50 hours) can produce over 200 kg ingots, grain size to achieve centimeter level;(4)in recent years as research and development of silicon technology quickly, in which technology has been applied to the production of polycrystalline silicon cells, such as selective etching the emitter, back surface field, corrosion suede , surface and bulk passivation, thin metal gate electrode, using screen-printing technology enables the gate electrode width down to 50 microns to 15 microns high, rapid thermal annealing technology for polysilicon production process can significantly shorten the time, single time of thermal process can be completed within a minute using this technology in the 100 square centimeters of silicon chip to make the cell conversion efficiency of over 14%. It was reported in 50 to 60 micron silicon substrate produced more than 16% cell efficiency.Mechanical groove, screen printing technology in polycrystalline on the efficiency of more than 17%, no mechanical groove in the same area on the efficiency of 16%, with buried gate structure, mechanical groove 130 on a square centimeter of polycrystalline cell efficiency of 15.8%.The following two aspects of the polysilicon to discuss battery technology.Laboratory efficient battery technology Laboratory techniques often do not consider the cost of battery production and mass production can only achieve maximum efficiency of the method and means to provide specific materials and processes that can achieve the limit.1.On the absorption of lightFor the optical absorption is mainly:(1)reduce the surface reflection;(2)Change the path of light in the cell body;(3)using the back reflection.For silicon, anisotropic chemical etching method applied in (100) surfaceproduced textured pyramid-shaped, lower surface light reflection. But silicon crystal to deviate from the (100) surface, using the above methods can not make even the suede, the current use of the following methods:(1)laser grooveGroove with a laser method can be produced in the polysilicon surface, inverted pyramid structure, in 500~900nm wavelength range, reflectance was 4 to 6%, with double-layer antireflection coating surface produced considerable. In the (100) reflection of silicon chemical production rate of 11% of the flock. Produced by laser textured surface than in the smooth double-layer antireflection coating film (ZnS/MgF2) short circuit current to increase by about 4%, mainly long-wave light (wavelength greater than 800nm) the reasons for slanting into the battery. Laser production of suede problems in etching, surface damage caused by the introduction of a number of impurities at the same time, through chemical treatment to remove surface damage layer. Solar cells made by this method are usually higher short circuit current, open circuit voltage is not high, mainly due to cell surface area increased, the recombination current increase.(2)Chemical grooveApplication of mask (Si3N4or SiO2) isotropic corrosion, etching solutions for acid etching solutions, but also for the higher concentration of sodium hydroxide or potassium hydroxide solution, the method can not create the kind formed by anisotropic etching cone-like structure. According to reports, the approach down the face of the formation of micron spectral range 700 to 1030 significantly reduced reflex. But the mask layer will be formed at higher temperatures, causing decreased performance polysilicon materials, especially for lower quality polycrystalline materials, reduce the minority carrier lifetime. Application of the technology made of polysilicon in cell conversion efficiency of 16.4%. Mask layer screen printing method can also be formed.(3)reactive ion corrosion (RIE)This method is a non-mask etching process, the formation of suede particularly low reflectivity in the spectral range 450 to 1000 micron reflectivity can be less than 2%. Only from the optical point of view, is an ideal method, but problem is serious silicon surface damage, the battery open circuit voltage and fill factor decreased.(4)produced antireflection filmFor efficient solar cells, the most common and most effective way is to double-layer antireflection coatings deposited ZnS/MgF2, its optimal thickness depends on the thickness of the oxide layer below the surface characteristics and battery, for example, the surface is smooth or textured surface,anti-reflection technology has evaporated Ta2O5, PECVD deposition Si3N3 so. ZnO conductive film can be used as anti-reflective material.2.MetallizationIn the efficient production of the battery, the metal electrode to the battery design parameters such as surface doping concentration, PN junction depth, the metal material to match. General area of small laboratory cell (area less than 4cm2), so they need small metal gate line (less than 10 microns), the general approach to lithography,electron beam evaporation, rge-scale production of industrial plating process is also used, but the combination of evaporation and lithography, do not belong to low-cost technology.3.PN junction formation technology(1)emitter formation and phosphorus getteringFor efficient solar cells, emitter diffusion formation of choice commonly used in the formation of heavy metal impurities in the region below the electrode in the spread between the electrodes to achieve light levels, the shallow emitter diffusion is increased concentration of cell response to blue light, and also allows silicon surface easily passivated. Two-step diffusion method diffusion process, diffusion process and increase corrosion buried diffusion process. Currently used selection proliferation, 15 × 15 cell conversion efficiency of 16.4%, n + +, n + sheet resistance of the surface region were 20Ω and 80Ω.For Mc-Si materials, expansion of phosphorus gettering effect on the battery has been widely studied, a longer period of phosphorus gettering process (usually 3 to 4 hours), make some of Mc-Si of the minority carrier diffusion length increase of two orders of magnitude.(2)the formation of back surface field and aluminum getteringIn Mc-Si cell, the back p + p junction by the formation of uniform diffusion of aluminum or boron, boron source is generally BN, BBr, APCVD SiO2: B2O8 such as evaporation or diffusion of aluminum screen printing of aluminum, 800 degrees completed sintering , on the role of aluminum gettering carried out extensive research, and in different phosphorus diffusion gettering, aluminum gettering at a relatively low temperature. Physical defects which also involved the dissolution and deposition of impurities, while in higher temperatures, the deposition of impurities easily dissolve into the silicon, on the Mc-Si have a negative impact. Far, to the regional background field has been applied to silicon solar cell technology, but in the polysilicon, the application of aluminum or the back surface field structure.(3)Double Mc-Si cellsMc-Si double the battery positive side for the conventional structure, on the back for the N + and P + cross-cutting structure, so that generated a positive light, but in the back of the photo birth rate near the back electrode can be effectively absorbed. Back electrode as an effective complement to the positive electrode, also planted as an independent flow of sub-collector on the back of the light and the scattered light to be effective, it was reported in the AM1.5 conditions, the conversion efficiency of over 19%.360毕业设计网4.Surface and bulk passivationFor Mc-Si, due to higher grain boundary exist, point defects (vacancies, interstitial atoms, metal impurities, oxygen and nitrogen and their compounds) and in vivo defect on the surface passivation is particularly important, in addition to the previously mentioned The gettering, the passivation process has a number of ways, by thermal oxidation to silicon dangling bonds saturated is a relatively common method, make Si-SiO2interface recombination velocity greatly decreased, the passivation effect depends on the launching area surfaceconcentration, the interface state density and the electron and hole cross sections were floating. Annealed in hydrogen atmosphere can passivation effect is more obvious. Nitride deposited by PECVD the recent positive is very effective because the process of film has the effect of hydrogenation. The process can also be applied to large scale production. Application of Remote PECVD Si3N4 surface recombination velocity is less than can 20cm / s.多晶硅太阳能电池众所周知,利用太阳能有许多优点,光伏发电将为人类提供主要的能源,但目前来讲,要使太阳能发电具有较大的市场,被广大的消费者接受,提高太阳电池的光电转换效率,降低生产成本应该是我们追求的最大目标,从目前国际太阳电池的发展过程可以看出其发展趋势为单晶硅、多晶硅、带状硅、薄膜材料(包括微晶硅基薄膜、化合物基薄膜及染料薄膜)。
双层MoS2
斯异质结。 基于密度泛函理论的第一性原理计算结果表明,ML MoS2 / VS2 和 BL MoS2 / VS2 异质结均表现出 p
型肖特基势垒,但在由 BL MoS2 构成的异质结中,肖特基势垒高度显著降低,仅为 0. 08 eV,十分接近于欧姆
接触的形成。 此外,通过对两种异质结光吸收光谱的计算,发现 BL MoS2 / VS2 异质结的介电函数的实部和虚
膜材料 [9-11] 。 目前为止,基于二维 MoS2 纳米片的场效应晶体管和数字电路已被成功制造。 值得关注的是,
在纳米电子器件中引入二维 MoS2 纳米片不可避免地涉及到与金属的接触,而相应的接触性质将会显著影响
器件的性能 [12-14] 。 因此,如何在金属半导体界面有效地降低接触电阻,对设计高性能纳米电子器件具有重
Key words: density functional theory; MoS2 ; electronic structure; van der Waals heterojunction; Schottky barrier;
light absorption
0 引 言
近年来,以石墨烯为代表的二维纳米材料因其独特的机械和电子性能而得到了广泛的研究与应用 [1-5] 。
用于描述交换关联作用 [18] ,投影缀加平面波方法被用来考虑离子与电子间相互作用。 平面波展开的截断能
被设置为 500 eV,采用 11 × 11 × 1 的 K 点网格在布里渊区进行取样,能量和力的收敛标准分别为 10 - 5 eV、
0. 01 eV / Å。 为避免相邻晶格之间的相互作用,真空层被设定为 15 Å 以确保消除层间的相互影响。 在非对
that the heterojunction composed of bilayer MoS2 has higher absorption peaks. The research results provide a theoretical basis
mos2 thin film deposited by R.F. magnetion sputtering
.
Film-substrate adhesion is believed to occur mainly through M0S2 edge plane sites and should strongly mfluence the wear life of the f l : stronger the adhesion, the longer the wear life. MoS2film i m the orientation should affect the coefficient of friction.
Fig. 1 Schematic diagram of sputtering system
Two types specimen were prepared with SKDll tool steel; normal specimen 21.5” in thickness and wear specimen 28.5” in diameter, 5mm in thickness.
Most Thin Films Deposited by R.F Magnetron Sputtering Sun Kyu Kim, Young Hwan Ahn School of Materials and Metallurgical Eng. University of Ulsan, Korea, 680-749 Te1:+82(52)2592228, Fax:+82m@uou.ulsan. ac.kr
MoS2 is formed by stacking ‘sandwiches’ of a layer of transition metalwo) with two layers of
mos2 场效应晶体管 nature
mos2场效应晶体管naturemos2场效应晶体管是近期在科研领域取得的一项重要成果。
在2022年3月,清华大学的研究人员在《Nature》杂志上发表了一项关于mos2场效应晶体管的研究成果。
这项工作刷新了迄今为止已报道的场效应晶体管的最短栅极长度,其最短沟长仅为0.34nm,这是基于现有认知的极限长度。
mos2场效应晶体管的工作原理主要依赖于其栅极长度,这一长度决定了晶体管的开关状态以及电流的传输能力。
栅极越短,晶体管的开关控制能力越强,其性能也就越优秀。
该项研究的突破点在于利用石墨烯的独特性质。
石墨烯作为目前已知的最导电的材料,其原子层厚度极薄,仅为一个碳原子。
通过将mos2沉积于台阶的侧壁上,研究团队成功地实现了石墨烯栅极对沟道的控制。
当在栅极上施加电压时,电场能够从各个方向辐射,实现对沟道的精确控制。
这项研究的成功不仅刷新了场效应晶体管的栅极长度记录,而且为未来的电子器件设计提供了新的思路。
通过利用石墨烯等超薄材料,我们可以实现更小、更高效的电子器件,推动科技的发展。
在具体操作上,该研究团队首先沉积图案化mos2材料,然后使用喷墨打印技术制备电介质层、接触和连接层,从而完成晶体管和电路的制备。
他们通过将源极和漏极接触打印在mos2条带上,以定义晶体管的沟道区域。
接着,他们将hBN 薄膜打印在mos2沟道上,这种2D绝缘材料具有显著的介电性能和可忽略的漏电流。
最后,在hBN的顶部打印一个顶栅电极。
银或石墨烯墨水被用于打印源极和漏极接触以及顶栅接触。
该团队还对制备的mos2场效应晶体管进行了电学特性测试。
结果表明,该晶体管具有优异的性能表现,其平均ION/IOFF值为8×103,最大值为5×104;迁移率为5.5cm2V-1s-1,最大值为26cm2V-1s-1。
此外,该晶体管在低电压下工作,阈值电压范围为±1V。
这项研究的成功得益于科研人员对材料的深入理解和精细操作技术的掌握。
电子信息 外文文献译文
XXXX学院毕业设计(论文)外文参考文献译文本2012届原文出处A Novel Cross-layer Quality-of-service ModelFor Mobile AD hoc Network毕业设计(论文)题目基于COMNETIII的局域网的规划与设计院(系)电气与电子信息学院专业名称电子信息工程学生姓名学生学号指导教师A Novel Cross-layer Quality-of-service ModelFor Mobile AD hoc NetworkLeichun Wang, Shihong Chen, Kun Xiao, Ruimin Hu National Engineering Research Center of Multimedia Software, Wuhan UniversityWuhan 430072, Hubei, chinaEmail:******************Abstract:The divided-layer protocol architecture for Mobile ad hoc Networks (simply MANETs) can only provide partial stack. This leads to treat difficulties in QoS guarantee of multimedia information transmission in MANETs, this paper proposes Across-layers QoS Model for MANETs, CQMM. In CQMM, a core component was added network status repository (NSR), which was the center of information exchange and share among different protocol layers in the stack. At the same time, CQMM carried out all kinds of unified QoS controls. It is advantageous that CQMM avoids redundancy functions among the different protocol layers in the stack and performs effective QoS controls and overall improvements on the network performances.Keyword: Cross-layers QoS Model, Mobile Ad hoc Networks (MANETs), Network Status Repository (NSR), QoS Controls.1 introductionWith the rapid development of multimedia technologies and the great increase of his bandwidth for personal communication, video and video services begin to be deployed in MANETs. Different from static networks and Internet, multimedia communications in MANETs such as V oice and Video services require strict QoS guarantee, especially the delay guarantee. In addition, communication among different users can be integrated services with different QoS requirements. These lead to great challenges in QoS guarantee of multimedia communication in MANETs. There are two main reasons in these: 1) MANETs runs in atypical wireless environment with time-varying and unreliable physical link, broadcast channel, and dynamic and limited bandwidth and so forth. Therefore, it can only provide limited capability for differentiated services with strict QoS requirements [1].2) It is difficult that traditional flow project and access control mechanism are implemented because of mobility, multiple hops and self-organization of MANETs.At present, most researches on QoS based on traditional divided-layer protocol architecture for MANETs focus on MAC protocol supporting QoS [2], QoS routingprotocol [3] and adaptive application layer protocol with QoS support [4], and so on. It is avoid less that there will be some redundancies on functions among the different protocol layers in the stack. This will increase the complexity of QoS implementation and cause some difficulties in overall improvement on the network performances. Therefore, it is not suitable for MANETs with low processing abilityIn recent years, the cross-layers design based on the partial protocol layers in MANETs was put forward.[1] proposed the mechanism with QoS guarantee for heterogeneous flow MAC layer.[5,6,7,8] did some researches on implementing video communication with QoS guarantee by exchange and cooperation of information among a few layers in MANETs. These can improve QoS in MANETs’communication to some extent. However, MANETs is much more complex than wired system and static network, and improvements on QoS guarantee depend on full cooperation among all layers in the protocol stack. Therefore, it is difficult for the design to provide efficient QoS guarantee for communication and overall improvements on the network performances in MANETs.To make good use of limited resources and optimize overall performances in MANETs, this paper proposes a novel cross-layer QoS model, CQMM, where different layers can exchange information fully and unified QoS managements and controls can be performed.The rest of the paper is organized as follows. CQMM is described in section 2 in detail. In section 3, we analyze CQMM by the comparison with DQMM.The section 4 concludes the paper.2. A CROSS-LAYER QOS MODEL FOR MANETS-CQMM2.1 Architecture of CQMMIn MANETs, present researches on QoS are mostly based on traditional divided-layer protocol architecture, where signals and algorithms supporting QoS are designed and implemented in different layers respectively, such as MAC protocol supporting QoS in data link layer [9], routing protocol with QoS support in network layer[10.11],and so forth. It can be summarized as A Divided-layer QoS Model for MANETs, DQMM (see fig.1).In DQMM, different layers in the protocol stack are designed and work independently; there are only static interfaces between different layers that are neighboring in logic; and each protocol layer has some QoS controls such as error control in logic link layer, congestion control in network, etc. On the one hand, DQMM can simplify the design of MANETs greatly and gain the protocols with high reliability and extensibility. On the other one, DQMM also has some shortcomings: 1) due to the independent design among he different protocol layers, there are some redundancy functions among the different protocollayers in the stack, 2) it is difficult that information is exchanged among different layers that are not neighboring in logic, which leads to some problems in unified managements, QoS controls and overall improvements on the network performances.Fig.1Therefore, it is necessary that more attention are focused on the cooperation among physical layer data link layer, network layer and higher when attempting to optimize performances of each of layer in MANETs. For this reason, we combine parameters dispersed in different layers and design a novel cross-layer QoS model, CQMM, to improve the QoS guarantee and the overall network performances. The architecture of CQMM is provided in fig 2From fig.2, it can be seen that CQMM keeps the core functions and relative independence of each protocol layer in the stack and allows direct information exchange between two neighboring layers in logics to maintain advantages of the modular architecture .On the basic of these, a core component is added in CQMM, Network Status Repository (simply NSR).NSR is the center, by which different layers can exchange and share information fully. On the one hand, each protocol layer can read the status information of other protocol layers from NSR to determine its functions and implementation mechanisms. On the other one, each protocol layer can write its status information to NSR that can be provided with other layers in the protocol stack. In CQMM, the protocol layers that are neighboring in logics can exchange information directly orindirectly by NSR, and the protocol layers that are not neighboring in logics can exchange information using cross-layer ways via NSR. Therefore, information exchange is flexible in CQMM.All kinds of QoS controls in CQMM such as management and scheduling of network resources, network lifetime, error control, and congestion control and performance optimization and so on are not carried out independently. On the contrary, CQMM is in charge of the unified management and all QoS controls by the cooperation among different protocol layers in the stack. Each QoS control in MANETs is related to all layers in the protocol stack, and also constrained by all layers in the stack. The results of all QoS operations and managements are fed back to the different layers and written back to NSR, which will become the parameters of all kinds of QoS controls in MANETs.2.2 protocol design in CQMMIn CQMM, the protocol designs aims at the full and free information exchange and cooperation among different protocol layers to avoid possible redundancy functions when maintaining the relative independence among different layers and the advantages of the modular architecture.Physical layer: Physical layer is responsible for modulation, transmission and receiving of data, and also the key to the size, the cost and the energy consumption of each node in MANETs. In CQMM, the design of physical layer is to choose the transmission media, the frequency range and the modulation algorithm wit the low cost, power and complexity, big channel capability and so on, according to the cost of implementation, energy constraint, and capability and QoS requirements from high layer.Data link layer: The layer is low layer in the protocol stack and can be divided into two sub-layers: logic link sub-layer and MAC sub-layer. Compared with high layers, data link layer can sense network status in MANETs earlier such as the change of channel quality, the network congestion and so on. Therefore, on the one hand data link layer can perform the basic QoS controls such as error control and management of communication channel. On the other one, the layer can be combined with high layers to establish, choose and maintain the routing faster, prevent the congestion of the network earlier, and choose appropriate transport mechanisms and control strategies for transport layer.Network layer: The design and implementation of network layer protocol in CQMM is to establish, choose and maintain appropriate routings by taking into consideration the power, the cache, the reliability of each node in a routing. QoS requirements of services from high layer such as the bandwidth and the delay, and implementation strategies oferror control in logic link sub-layer and the way of the channel management in MAC sub-layer.Transport layer: In CQMM, the protocol design of transport layer needs to be aware of both functions and implementation mechanism of lower layers such as the way of error control in data link layer, the means to establish, choose and maintain routing in the network layer, and QoS requirements from the application layer, to determine corresponding transmission strategies. In addition, the transport layer also needs to analyze all kinds of events from low layers such as the interrupt and change of the routing and the network congestion, and then respond properly to avoid useless sending data.Application layer: There are two different strategies in the design of the application layer: 1) differentiated services. According to the functions provided by the low layers applications are classed as the different ones with different priority levels. 2) Application-aware design. Analyze specific requirements of different applications such as the bandwidth, the delay and the delay twitter and so on, and then assign and implement the functions for each layer in the protocol stack according to the requirements.2.3 QoS Cooperation and Management in CQMMIn CQM, the core of QoS cooperation and management is that NSR acts as the exchange and share center of status information in protocol stack, and by the full exchange and share of network status among different protocol layers the management and scheduling of the network resources and the overall optimization of the network performances can be implemented effectively. The management and scheduling of the network resources, the cross-layer QoS cooperation and the overall optimization of the network performances.Management and scheduling of network resources: Network resources include all kinds of resources such as the cache, the energy and the queue in each node, and the communication channel among nodes and so froth. In CQMM, the management and scheduling of the network resources are not to the unified management and scheduling of the network resources and full utilization of limited resources in order to increase the QoS of all kinds of communication.QoS cooperation and control: In CQMM, all kinds of QoS controls and cooperation such as the rate adaptation, the delay guarantee and the congestion control and so on, are not implemented by each layer alone, but completed through the operation of all layers in the protocol stack. For example, the congestion in MANETs can be earlier prevented and controlled by the cooperation among different layers such as ACK from MAC sub-layer,the routing information and the loss rate and delay of package from network layer, and the information of rate adaptation in transport layer and so on.Performances Optimization: In CQMM, the optimization of the network performances aims to establish a network optimization model constrained by all layers in the protocol architecture and finds the “best”ways according to the model in order to improve the overall performances in MANETs.3. ANALYSIS OF CQMMPresent QoS models for MANETs can mainly be classed as a QoS model based on traditional divided-layer architecture DQMM and a cross-layer QoS model proposed by this paper CQMM. QoS model used by [1, 5-8] is to some extent extended on the basis of DQMM in nature. Here, we only compare CQMM with DQMM3.1 Information ExchangeDifferent protocol architecture and principle between CQMM lead to great differences in the means, the frequency, the time and the requirement of the information exchange, (see table 1)From Table 1, it can be seen that compared wit DQMM CQMM has some advantages: 1) more flexible information exchange. Neighboring layers can information by the interfaces between layers or NSR, and crossing layers may exchange information through NSR; 2) simpler transform in information format. Different layers can exchange information by NSR, so these layers only need to deal with the format transform between the layers and NSR;3)lower requirements. The protocol layers can read them in proper time Information from different protocol layers temporarily stored in NSR, so the layers exchanging information are not required to be synchronous in time;4) more accurate control. NSR in CQMM can store information of some time from the different layers, which is advantageous to master the network status and manage the network more accurately. However, these require higher information exchange frequencies among the different layers,, more processing time of each node, and more communication among them.。
Controlled Synthesis of Highly Crystalline MoS2 Flakes by Chemical
用化学气相沉积法合成二硫化钼薄片摘要:控制合成高结晶度的MoS2原子层对于新型材料的应用来说依然是一个不小的挑战。
在这里,我们开发了一种运用层层硫化MoO2的方法来控制合成菱形的MoS2片。
用这种方法得到的MoS2片显现出高结晶度,结晶尺寸约为10nm,这明显要比用其他方法生长出来的MoS2片的尺寸大。
由于结晶度高,用这种方法生产的MoS2背栅极式场效应管(FETs)的性能要比得上用传统的机械剥离的方式生产的性能。
这种简单的方法开启了一个具有价值的生产MoS2原子层的新方法,这将使得这种高度结晶的材料能更容易得到在功能材料和其他方面的应用。
硫族半导体过渡金属,例如MoS2,最近已经成为与0能带隙石墨原子层互补的2-D材料的一员1-4。
MoS2原子层的内在大禁带(1.2-1.8eV)和灵活性容许其做为纳米电子以及电子设备应用于常规或者灵活的基板上。
机械剥落单原子层MoS2片得顶栅晶体管具有优良的开/关电流比率约为108并且其迁移率大于200cm2V-1s-1。
5MoS2片制造的逻辑电路用于演示证明它的集成多功能性6、8。
生产高质量的,能够控制层数的MoS2片对于MoS2在电子产品中的实际应用迫在眉睫。
最近,单层以及多层的MoS2已经能够用“自上而下”剥离和“自下而上”合成的方法合成。
类似于石墨烯,机械剥落的MoS2片显示出了最好的性质,但是其尺寸却很小(只有几微米)而且不能控制形状3。
用片状剥落13、14或者水热一体化15、16研制的MoS2有望保持着大规模的生产,但是用这些方法做出来的低质量的MoS2材料在电子方面的应用是有限的。
最近,VCD法成功的发展了高质量的石墨烯,并一直在绝缘基板如SiO2和蓝宝石上合成MoS2薄片17-22。
然而,运用VCD法获得高结晶且能控制数量的MoS2比获得石墨烯要难一些,这是由于石墨烯的几何形状,厚度以及结晶度能够用催化设计法来控制21、22,但是合成MoS2却不能用催化来实现。
文献翻译 2(DOC)
文献翻译(二)无机曾欣0843014053 碳包覆对LiNi0.5Mn1.5O4的正极材料倍率性能的提高关键词:5V尖晶石阴极碳涂层倍率性能锂离子电池摘要为了增强LiNi0.5Mn1.5O4正极材料的倍率性能,用蔗糖作碳源在其表面涂覆一层导电炭。
碳涂层对材料物理性能,电化学性能方面的影响由XRD,SEM,TEM,XPS(X射线光电子能谱),CV(伏安循环),EIS(电化学阻抗谱)以及循环性能和倍率性能的测定来获知。
结果表明,表面包覆碳后,可以大大提高放电比容量,倍率性能和循环性能,而且不会降低尖晶石结构。
在掺碳量的质量分数为1%是,样品的性能最佳。
该样品在以1C的放电率循环100次后,仍有130mAhg-1的容量,保持率高达92%;在以5C的放电率循环后仍保持114130mAhg-1的稳定容量。
碳包覆后样品的倍率性能显著提高,这是由于固体电解质层得发展受到阻碍,以及Li+的扩散和电荷转移反应的加快。
1简介目前对能源的有限问题以及减少温室气体的排放的关注,对混合动力电动汽车中的锂离子电池,光能的储存以及风力发电的商业化提供了便利,增强了在便携式电子产品中的主导地位。
增强了在便携式电子产品中的霸主地位。
诸如此类设备的日益增长的能源和动力需要促进了锂离子电池的发展。
这些发展改进关键取决于电极材料的创新方法。
由于尖晶石型LiNi0.5Mn1.5O4的大容量以及非常高的放电潜能,被认为是非常有前途的锂离子电池正极材料而被广泛研究。
它惊人的放电电压可以为电池提供更大的工作潜能,更高的能量以及潜在的更高的功率密度。
但是不幸的是,LiNi0.5Mn1.5O4在大电流时是较低的放电性能和循环性能阻碍的它的应用。
其中一个原因就是LiNi0.5Mn1.5O4和电解液在高电压下的表面反应导致了SEI膜的形成。
而SEI膜极大的阻碍了Li+离子的嵌入和提取反应,电荷转移,以及此后的电化学过程的反应动力学。
另一个原因是起内在的较低的电子电导率。
Method of improving a dual gate CMOS transistor to
专利名称:Method of improving a dual gate CMOStransistor to resist the boron-penetratingeffect发明人:Chi-Chun Chen,Horng-Chih Lin,Chun-YenChang,Tiao-Yuan Huang申请号:US09834268申请日:20010412公开号:US20020022329A1公开日:20020221专利内容由知识产权出版社提供专利附图:摘要:A method of reducing the boron-penetrating effect in a CMOS transistorprovides a silicon substrate, which comprises an isolating area, an active area and a gate oxide layer formed on the active layer. A polysilicon layer is then deposited on the silicon substrate. Next, the boron ion (B) is doped into the polysilicon layer. Next, a gate photoresist with a predetermined gate pattern is formed on the polysilicon layer. The polysilicon not covered by the gate photoresist is then etched to from a polysilicon gate. The gate photoresist is used as a mask to dope the boron-fluorine ion (BF) into the silicon substrate. Finally, after removing the gate photoresist, a tempering procedure is performed to form a shallow junction area of a source/drain on the silicon substrate.申请人:NATIONAL SCIENCE COUNCIL更多信息请下载全文后查看。
COMPLEMENTARY MOS LOGIC CIRCUIT
更多信息请下载全文后查看ห้องสมุดไป่ตู้
专利内容由知识产权出版社提供
专利名称:COMPLEMENTARY MOS LOGIC CIRCUIT 发明人:BABA AKIRA 申请号:J P 4 100689 申请日:19890221 公开号:J P H 022204 69A 公开日:19900903
摘要:PURPOSE:To enhance a utilization rate of C-MOS logic elements by installing the following: a diode connected between a second complementary MOS logic element to which a power supply is always supplied and a first complementary MOS logic element; a pull-up resistance connected to the first complementary MOS logic element. CONSTITUTION:A diode 5 is installed between a second complementary MOS logic element 4 to which a power source is always supplied and a first complementary MOS logic element 3b to which a supply of the power source may be stopped; a pull-up resistance 6 is installed at the fist complementary MOS logic element 3b. Accordingly, when a first power source 1 is operated, an output signal of the second complementary MOS logic element 4 is supplied to the first complementary MOS logic element 3b; when an operation of the first power source 1 is stopped, the diode 5 is cut off; it is possible to prevent the output signal of the second complementary MOS logic element 4 from flowing to the power source 1. Thereby, it is possible to constitute a logic circuit in which the first and second complementary MOS logic elements 3b, 4 have been combined; it is possible to effectively utilize the logic elements.
Antibacterial activity of two-dimensional MoS2 sheets
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Antibacterial activity of two-dimensional MoS2 sheets†
Xi Yang,a Jie Li,b Tao Liang,a Chunyan Ma,a Yingying Zhang,a Hongzheng Chen,*a Nobutaka Hanagata,*b Huanxing Su*c and Mingsheng Xu*a
a
State Key Laboratory of Silicon Materials, MOE Key Laboratory of Macromolecular Synthesis and Functionalization, Department of Polymer Science and Engineering, Zhejiang University, Hangzhou 310027, P. R. China. E-mail: msxu@; hzchen@ Interdisciplinary Laboratory for Nanoscale Science and Technology, National Institute for Materials Science, 1-2-1 Sengen, Tsukuba, Ibaraki 305-0047, Japan. E-mail: Hanagata.nobutaka@nims.go.jp
外文翻译--集成电路(IC)外文翻译中英文对照
外文翻译--集成电路(IC)外文翻译中英文对照Integrated circuit (IC)IntroducionIntegrated circuit also called microelectronic circuit or chip an assembly of electronic components, fabricated as a single unit, in which miniaturized active devices (e.g., transistors and diodes) and passive devices (e.g., capacitors and resistors) and their interconnections are built up on a thin substrate of semiconductor material (typically silicon). The resulting circuit is thus a small monolithic “chip,” which may be as small as a few square centimetres or only a few square millimetres. The individual circuit components are generally microscopic in size.Integrated circuits have their origin in the invention of the transistor in 1947 by William B. Shockley and his team at the American Telephone and Telegraph Company's Bell Laboratories. Shockley's team (including John Bardeen and Walter H. Brattain) found that, under the right circumstances, electrons would form a barrier at the surface of certain crystals, and they learned to control the flow of electricity through the crystal by manipulating this barrier. Controlling electron flow through a crystal allowed the team to create a device that could perform certain electrical operations, such as signal amplification, that were previously done by vacuum tubes. They named this device a transistor, from a combination of the words transfer and resistor (see photograph). The study of methods of creating electronic devices using solid materials became known as solid-state electronics. Solid-state devices proved to bemuch sturdier, easier to work with, more reliable, much smaller, and less expensive than vacuum tubes.Using the same principles and materials, engineers soon learned to create other electrical components, such as resistors and capacitors. Now that electrical devices could be made so small, the largest part of a circuit was the awkward wiring between the devices.In 1958 Jack Kilby of T exas Instruments, Inc., and Robert Noyce of Fairchild Semiconductor Corporation independently thought of a way to reduce circuit size further. They laid very thin paths of metal (usually aluminum or copper) directly on the same piece of material as their devices. These small paths acted as wi res. With this technique an entire circuit could be “integrated” on a single piece of sol id material and an integrated circuit (IC) thus created. ICs can contain hundreds of thousands of individual transistors on a single piece of material the size of a pea. Working with that many vacuum tubes would have been unrealistically awkward and expensive. The invention of the integrated circuit made technologies of the Information Age feasible. ICs are now used extensively in all walks of life, from cars to toasters to amusement park rides.Basic IC typesAnalog versus digital circuitsAnalog, or linear, circuits typically use only a few components and are thus some of the simplest types of ICs. Generally, analog circuits are connected to devices that collect signals from the environment or send signals back to theenvironment. For example, a microphone converts fluctuating vocal sounds into an electrical signal of varying voltage. An analog circuit then modifies the signal in some useful way—such as amplifying it or filtering it of undesirable noise. Such a signal might then be fed back to a loudspeaker, whichwould reproduce the tones originally picked up by the microphone.Another typical use for an analog circuit is to control some device in response to continual changes in the environment. For example, a temperature sensor sends a varying signal to a thermostat, which can be programmed to turn an air conditioner, heater, or oven on and off once the signal has reached a certain value.A digital circuit, on the other hand, is designed to accept only voltages of specific given values. A circuit that uses only two states is known as a binary circuit. Circuit design with binary quantities, “on” and “off” representing 1 and 0 (i.e., true and false), uses the logic of Boolean algebra. The three basic logic functions—NOT, AND, and OR—together with their truth tables are given in the figure. (Arithmetic is also performed in the binary number system employing Boolean algebra.) These basic elements are combined in the design of ICs for digital computers and associated devices to perform the desired functions.Microprocessor circuitsMicroprocessors are the most complicated ICs. They are composed of millions of transistors that have been configured as thousands of individual digital circuits, each of which performs some specific logic function. A microprocessor is built entirely of these logic circuits synchronized to each other.Just like a marching band, the circuits perform their logic function only on direction by the bandmaster. The bandmaster in a microprocessor, so to speak, is called the clock. The clock is a signal that quickly alternates between two logic states. Every time the clock changes state, every logic circuit in the microprocessor does something. Calculations can be made very quickly,depending on the speed (“clock frequency”) of the microprocessor.Microprocessors contain some circuits, known as registers, that store information. Registers are predetermined memory locations. Each processor has many different types of registers. Permanent registers are used to store the preprogrammed instructions required for various operations (such as addition and multiplication). Temporary registers store numbers that are to be operated on and also the result. Other examples of registers include the “program counter,” the “stack pointer,” and the “address” register.Microprocessors can perform millions of operations per second on data. In addition to computers, microprocessors are common in video game systems, televisions, cameras, and automobiles.Memory circuitsMicroprocessors typically have to store more data than can be held in a few registers. This additional information is relocated to special memory circuits. Memory is composed of dense arrays of parallel circuits that use their voltage states to store information. Memory also stores the temporary sequence of instructions, or program, for the microprocessor. Manufacturers continually strive to reduce the size of memory circuits—to increase capability without increasing space. In addition, smaller components typically use less power, operate more efficiently, and cost less to manufacture.Digital signal processorsA signal is an analog waveform—anything in the environment that can be captured electronically. A digital signal is an analog waveform that has been converted into a series ofbinary numbers for quick manipulation. As the name implies, a digital signal processor (DSP) processes signals digitally, as patterns of 1s and 0s. For instance, using an analog-to-digital converter, commonly called an A-to-D or A/D converter, a recording of someone's voice can be converted into digital 1s and 0s. The digital representation of the voice can then be modified by a DSP using complex mathematical formulas. For example, the DSP algorithm in the circuit may be configured to recognize gaps between spoken words as background noise and digitally remove ambient noise from the waveform. Finally, the processed signal can be converted back (by a D/A converter) into an analog signal for listening. Digital processing can filter out background noise so fast that there is no discernible delay and the signal appears to be heard in “real time.” For instance, such processing enables “live” televisionbroadcasts to focus on a quarterback's signals in an American gridiron football game. DSPs are also used to produce digital effects on live television. For example, the yellow marker lines displayed during the football game are not really on the field; a DSP adds the lines after the cameras shoot the picture but before it is broadcast. Similarly, some of the advertisements seen on stadium fences and billboards during televised sporting events are not really there.Application-specific ICsAn application-specific IC (ASIC) can be either a digital or an analog circuit. As their name implies, ASICs are not reconfigurable; they perform only one specific function. For example, a speed controller IC for a remote control car is hard-wired to do one job and could never become a microprocessor. An ASIC does not contain any ability to follow alternateinstructions.Radio-frequency ICsRadio-frequency ICs (RFICs) are rapidly gaining importance in cellular telephones and pagers. RFICs are analog circuits that usually run in the frequency range of 900 MHz to 2.4 GHz (900 million hertz to 2.4 billion hertz). They are usually thought of as ASICs even though some may be configurable for several similar applications. Most semiconductor circuits that operate above 500 MHz cause the electronic components and their connecting paths to interferewith each other in unusual ways. Engineers must use special design techniques to deal with the physics of high-frequency microelectronic interactions.Microwave monolithic ICsA special type of RFIC is known as a microwave monolithic IC (MMIC). These circuits run in the 2.4- to 20-GHz range, or microwave frequencies, and are used in radar systems, in satellite communications, and as power amplifiers for cellular telephones.Just as sound travels faster through water than through air, electron velocity is different through each type of semiconductor material. Silicon offers too much resistance for microwave-frequency circuits, and so the compound gallium arsenide (GaAs) is often used for MMICs. Unfortunately, GaAs is mechanically much less sound than silicon. It breaks easily, so GaAs wafers are usually much more expensive to build than silicon wafers.Basic semiconductor designAny material can be classified as one of three types: conductor, insulator, or semiconductor. A conductor (such as copper or salt water) can easily conduct electricity because it has an abundance of free electrons. An insulator (such as ceramic ordry air) conducts electricity very poorly because it has few or no free electrons. A semiconductor (such as silicon or gallium arsenide) is somewhere between a conductor and an insulator. It is capable of conducting some electricity, but not much.Basic semiconductor designDoping siliconMost ICs are made of silicon, which is abundant in ordinary beach sand. Pure crystalline silicon, as with other semiconducting materials, has a very high resistance to electrical current at normal room temperature. However, with the addition of certain impurities, known as dopants, the silicon can be made to conduct usable currents. In particular, the doped silicon can be used as a switch, turning current off and on as desired.The process of introducing impurities is known as doping or implantation. Depending on a dopant's atomic structure, the result of implantation will be either an n-type (negative) or a p-type (positive) semiconductor. An n-type semiconductor results from implanting dopant atoms that have more electrons in their outer (bonding) shell than silicon, as shown in the figure. The resulting semiconductor crystal contains excess, or free, electrons that are available for conducting current. A p-type semiconductor results from implanting dopant atoms that have fewer electrons in their outer shell than silicon. The resulting crystal contains “holes” in its bonding structure where electrons would normally be located. In essence, such holes can move through the crystal conducting positive charges.Basic semiconductor designThe p-n junctionA p-type or an n-type semiconductor is not very useful on itsown. However, joining these opposite materials creates what is called a p-n junction. A p-n junction forms a barrier to conduction between the materials. Although the electrons in the n-type material are attracted to the holes in the p-type material, the electrons are not normally energetic enough to overcome the intervening barrier. However, if additional energy is provided to the electrons in the n-type material, they will be capable of crossing the barrier into the p-type material—and current will flow. This additional energy can be supplied by applying a positive voltage to the p-type material,as shown in the figure. The negatively charged electrons will then be highly attracted to the positive voltage across the junction.A p-n junction that conducts electricity when energy is added to the n material is called forward-biased because the electrons move forward into the holes. If voltage is applied in the opposite direction—a positive voltage connected to the n side of the junction—no current will flow. The electrons in the n material will still be attracted to the positive voltage, but the voltage will now be on the same side of the barrier as the electrons. In this state a junction is said to be reverse-biased. Since p-n junctions conduct electricity in only one direction, they are a type of diode. Diodes are essential building blocks of semiconductor switches.Basic semiconductor designField-effect transistorsBringing a negative voltage close to the centre of a long strip of n-type material will repel nearby electrons in the material and thus form holes—that is, transform some of the strip in the middle to p-type material. This change in polarity utilizing an electric field gives the field-effect transistor its name. (See animation.) While the voltage is being applied, there will existtwo p-n junctions along the strip, from n to p and then from p back to n. One of the two junctions will always be reverse-biased. Since reverse-biased junctions cannot conduct, current cannot flow through the strip. The field effect can be used to create a switch (transistor) to turn current off and on, simply by applying and removing a small voltage nearby in order to create or destroy reverse-biased diodes in the material.A transistor created by using the field effect is called a field-effect transistor (FET).The location where the voltage is applied is known as a gate. The gate is separated from the transistor strip by a thin layer of insulation to prevent it from short-circuiting the flow of electrons through the semiconductor from an input (source) electrode to an output (drain) electrode. Similarly, a switch can be made by placing a positive gate voltage near a strip of p-type material. A positive voltage attracts electrons and thus forms a region of n within a strip of p. This again creates two p-n junctions, or diodes. As before, one of the diodes will always be reverse-biased and will stop current from flowing. FETs are good for building logic circuits because they require only a small current during switching. No current is required for holding the transistor in an on or off state; a voltage will。
电子科学与技术专业外语全译文样本
Semiconductor Materials• 1.1 Energy Bands and Carrier Concentration• 1.1.1 Semiconductor Materials固态材料可分为三种: 绝缘体、半导体和导体。
图1-1 给出了在三种材料中一些重要材料相关的电阻值( 相应电导率ρ≡1/δ)。
绝缘体如熔融石英和玻璃具有很低电导率, 在10-18 到10-8 S/cm;导体如铝和银有高的电导率, 典型值从104到106S/cm;而半导体具有的电导率介乎于两者之间。
半导体的电导率一般对温度、光照、磁场和小的杂质原子非常敏感。
在电导率上的敏感变化使得半导体材料称为在电学应用上为最重要的材料。
早在19世纪人们已经开始研究半导体材料。
多年来人们研究了很多半导体材料。
表1给出了与半导体相关的周期表中的部分元素。
由单种元素组成的单质半导体如硅和锗在第Ⅳ族。
而大量的化合物半导体有两个甚至更多元素组成。
如GaAs是Ⅲ-Ⅴ化合物是由Ⅲ族的Ga和Ⅴ族的As化合而得。
在1947年双极晶体管创造之前, 半导体仅用作双极型器件如整流器和光敏二极管。
早在20世纪50年代, 锗是主要的半导体材料。
然而锗不太适合在很多方面应用因为温度适当提高后锗器件会产生高的漏电流。
另外, 锗的氧化物是水溶性的不适合器件制作。
因此20世纪60年代实际上锗被硅所取代, 事实上硅替代锗成为半导体制作的材料之一。
我们用硅材料的主要原因有硅器件存在非常低的漏电流且能够经过热法生长出高质量的二氧化硅。
器件级硅成本远少于其它半导体材料。
硅以硅石和硅酸盐形式存在并占地球地表层的25%, 而且硅元素在分布中排在氧之后的第二位。
当今硅是在元素周期表中研究最多的元素; 硅技术是在所有半导体技术中最先进的。
有很多化合物半导体具有硅所缺少的电光性能。
这些半导体特别是GaAs主要用作微波和光学应用。
虽然我们了解化合物半导体技术不如硅材料的多, 但化合物半导体技术由于硅技术的发展而发展。
半导体物理与器件——Terms汉译英.docx
半导体物理与器件--- Terms(术语)U1 Terms:Semic on ductor physics and devices 半导体物理与器件,Space lattice 空间晶格'unit cell 晶胞'primitive cell 原胞,basic crystal structures 基本晶格结构(five), Miller indices 密勒指数' atomic bonding 原子价键U2 Terms:quantum mechanics 量了力学'energy quanta 能量子,wave-particle duality 波粒二象性,the uncertainty principle测不准原理/海森堡不确定原理Schrodinger's wave equation 薛定灣波动方程,eletrons in free Space 自由空间中的电子the infinite potential well 无限深势阱,the step potential function 阶跃势函数,the potential barrier 势垒.U3 Terms:Pauli exclusion principle 泡利不相容原理,quantum state 量了态. allowed energy band 允带'forbidden energy band 禁带. con ducti on band 导带'vale nee band 价带,hole 空穴'electron 电子.effective mass 有效质量.density of states function 状态密度函数,the Fermi-Dirac probability function 费米■狄拉克概率函数' the Boltzmann approximation 波尔兹曼近彳以‘ the Fermi energy 费米能级.U4 Terms:charge carriers 载流子'effective density of states function 有效族犬态密度函数,intrinsic 本征的,the intrinsic carrier concentration 本征载流子浓度'the intrinsic Fermi level 本征费米能级.charge n eutrality 电中性状态'compe nsated semic on ductor 补偿半导体‘ degenerate 简并的,non-degenerate 非简并的'position of E F费米能级的位置U5 Terms:drift current 漂移电流,diffusion current 扩散电流,mobility 迁移率,lattice scattering 晶格散身寸,ionized impurity scattering 电离杂质散射'velocity saturation饱和速度’conductivity 电导率‘resistivity 电阻率.graded impurity distribution 杂质梯度分布'the induced electric field 感生电场'the Einstein relation 爱因斯坦关系, the hall effect 霍尔效应U6 Terms:non equilibrium excess carriers 非平衡过剩载流子'carrier generation and recombination 载流子的产生与复合'excess minority carrier 过剩少子,lifetime 寿命'low-level injection 小注入,ambipolar transport 双极输运'quasi-Fermi energy 准费米能级.U7 Terms:the space charge region 空间电荷区'the built-in potential 内建电势,the built-in potential barrier 内建电势差,the space charge width 空间电荷区宽度,zero applied bias 零偏压,reverse applied bias 反偏'on esided jun ction 单边突变结.U8 Terms:the PN junction diode PN 结二极管,minority carrier distribution 少数载流子分布'the ideal-diode equation 理想二极管方程,the reverse saturation current density 反向饱和电流密度.a short diode 短二极管,generation-recombination current 产生・复合电流,the Zener effect 齐纳效应,the avalanche effect 雪崩效应,breakdown 击穿.U9 Terms:Schottky barrier diode (SBD)肖特基势垒二极管,Schottky barrier height 肖特基势垒高度.Ohomic contact 欧姆接触'heterojunction 异质纟吉'homojunction 单质纟吉,turn-on voltage 开启电压,narrow-bandgap 窄带隙'wide-bandgap 宽带隙,2-D electron gas 二维电子气U10 Terms:bipolar transistor 双极晶体管,base基极,emitter发射极,collector集电极. forward active regi on 正向有源区'in verse active region 反向有源区' cut-off 截止,saturation 饱和,current gain电流增益'common・base 共基,commorvemitter 共身寸.base width modulation 基区宽度调制效应,Early effect 厄利效应'Early voltage厄利电压Ull Terms:Gate 栅极,source 源极,drain 漏极'substrate 基底. work function difference 功函数差threshold voltage 阈值电压'flat-band voltage 半带电压enhancement mode 增强型'depletion mode 耗尽型strong inversion 强反型'weak inversion 弱反型,transconductance 跨导'l-V relationship 电流■电压关系。
Chemical Vapor Sensing with Monolayer MoS2
S Supporting Information *
ABSTRACT: Two-dimensional materials such as graphene show great potential for future nanoscale electronic devices. The high surface-to-volume ratio is a natural asset for applications such as chemical sensing, where perturbations to the surface resulting in charge redistribution are readily manifested in the transport characteristics. Here we show that single monolayer MoS2 functions effectively as a chemical sensor, exhibiting highly selective reactivity to a range of analytes and providing sensitive transduction of transient surface physisorption events to the conductance of the monolayer channel. We find strong response upon exposure to triethylamine, a decomposition product of the V-series nerve gas agents. We discuss these results in the context of analyte/sensor interaction in which the analyte serves as either an electron donor or acceptor, producing a temporary charge perturbation of the sensor material. We find highly selective response to electron donors and little response to electron acceptors, consistent with the weak n-type character of our MoS2. The MoS2 sensor exhibits a much higher selectivity than carbon nanotube-based sensors. KEYWORDS: Chemical sensor, MoS2, molybdenum disulfide, two-dimensional materials, vapor sensing he planar habit of two-dimensional (2D) materials is attractive for the ultimate size scaling envisioned by Moore’s Law and beyond1,2 and offers relative ease of fabrication, the requisite large-scale integration, and exceedingly low power consumption. The very high surface-to-volume ratio of such single or few monolayer materials enables highly efficient gating of charge transport via surface gates, obviating the need for the more complex growth and fabrication procedures required for wrapped-gate nanowire transistors. Graphene has captivated attention since the first measurements of high mobility transport were reported in single layer flakes.3 Progress toward monolithic graphene circuits was recently demonstrated by the fabrication of wafer-scale inductor/transistor circuits,4 vertically integrated graphene/ graphite transistor arrays,5 and transistors with improved on/off ratios.6 Recent effort has focused on other 2D materials such as the transition metal dichalcogenides, and field effect transistors with a monolayer of MoS2 as the active channel were shown to exhibit high on/o ff ratios at room temperature, ultralow standby power dissipation, and well-de fi ned photoresponse. 7−9 Very recent work has demonstrated fabrication of complex integrated logic circuits based on bilayer MoS2 transistors,10 and significant advances have been made in large area growth of MoS2 on several substrates.11−13 The high surface-to-volume ratio is also important for new sensor materials which must exhibit selective reactivity upon exposure to a range of analytes (determined by the character of surface physisorption sites), rapid response and recovery, and sensitive transduction of the perturbation to the output parameter measured. The conductivity of graphene near the charge neutrality point has been shown to change with
Adv.Mater.清华大学-CVD可控制备高质量多层MoS2
Adv.Mater.清华大学-CVD可控制备高质量多层MoS2【引言】具有本征带隙的二维MoS2由于其在电子和光电子器件方面的显著潜力而引起了极大的关注。
但是,由于这种材料的迁移率相对较低(甚至低于多晶硅),这大大地阻碍了其迈向实际应用。
目前已经有一系列针对单层MoS2的研究,但是与此同时多层MoS2的研究相应的有所缺失。
然而实际上,由于具有较高的态密度,多层MoS2具有比单层MoS2高得多的迁移率和驱动电流,这使得多层MoS2在薄膜晶体管、逻辑器件和传感器等方面更具应用前景。
然而,到目前为止报道的多层MoS2的优异性能是通过机械剥离获得的,这并不适合实际应用,而目前化学气相沉积(CVD)合成的多晶多层MoS2薄膜,显示出低得多的迁移率。
【成果简介】为了推进多层为了推进多层MoS2的实际应用,清华大学焦丽颖教授(通讯作者)等人通过CVD方法生长出高度结晶的多层MoS2薄片解决了上述问题。
可以实现高达20层的MoS2以良好限定的AA顺序堆叠在一起,而且每层的边缘是原子级平滑的Mo原子锯齿形结构。
多层沟道、原子级有序的边缘以及理想的接触几何形状使得这些CVD 生长的多层MoS2薄片表现出优于机械剥离多层MoS2的电性能。
除了场效应晶体管之外,这些多层MoS2晶体管也适合于构建基于单层-多层MoS2结的整流二极管。
文章中的制备方法使高品质多层MoS2更易于构建多功能高性能电子设备,从而使二维MoS2在未来的电子器件中更具竞争力。
该成果以“High-Mobility Multilayered MoS2 Flakes with Low Contact Resistance Grown by Chemical Vapor Deposition”为题于2017年2月发表在期刊Advanced Materials上。
【图文简介】图1 合成不同层数的MoS2薄片a)使用拱形氧化Mo箔作为反应前体CVD生长MoS2的示意图。
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3
*Corresponding author E-mail: hanw@, tpalacios@.
ϯ
H. W. and L. Y. contributed equally to this work.
Abstract Two-dimensional (2D) materials, such as molybdenum disulfide (MoS2), have been shown to exhibit excellent electrical and optical properties. The semiconducting nature of MoS2 allows it to overcome the shortcomings of zero-bandgap graphene, while still sharing many of graphene’s advantages for electronic and optoelectronic applications. Discrete electronic and optoelectronic components, such as field-effect transistors, sensors and photodetectors made from few-layer MoS2 show promising performance as potential substitute of Si in conventional electronics and of organic and amorphous Si semiconductors in ubiquitous systems and display applications. An important next step is the fabrication of fully integrated multi-stage circuits and logic building blocks on MoS2 to demonstrate its capability for complex digital logic and high-frequency ac applications. This paper demonstrates an inverter, a NAND gate, a static random access memory, and a five-stage ring oscillator based on a direct-coupled transistor logic technology. The circuits comprise between two to twelve transistors seamlessly integrated side-byside on a single sheet of bilayer MoS2. Both enhancement-mode and depletion-mode transistors were fabricated thanks to the use of gate metals with different work functions. Keywords: molybdenum disulfide (MoS2), transition metal dichalcogenides (TMD), Two-dimensional (2D) electronics, integrated circuits, ring oscillator.
2
United States Army Research Laboratory, 2800 Powder Mill Road, Adelphi, MD 20783-1197, USA. Institute of Atomic and Molecular Sciences, Academia Sinica, Taipei, 11529, Taiwan.
1
Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, 77
Massachusetts Avenue, Cambridge MA 02139, USA. Tel: +1 (617) 324-2395.
பைடு நூலகம்
1
Two-dimensional (2D) materials, such as molybdenum disulfide (MoS 2)1 and other members of the transition metal dichalcogenides family, represents the ultimate scaling of material dimension in the vertical direction. Nano-electronic devices built on 2D materials offer many benefits for further miniaturization beyond Moore’s Law2,3 and as a high-mobility option in the emerging field of large-area and low-cost electronics that is currently dominated by low-mobility amorphous silicon4 and organic semiconductors5,6. MoS2, a 2D semiconductor material, is also attractive as a potential complement to graphene 7,8,9 for constructing digital circuits on flexible and transparent substrates, while its 1.8 eV bandgap10,11 is advantageous over silicon for suppressing the source-to-drain tunneling at the scaling limit of transistors12. Recently, various basic electronic components have been demonstrated based on few-layer MoS2, such as field-effect transistors (FETs)13,14,15, sensors16 and phototransistors17. However, until now, only primitive circuits involving one or two discrete MoS2 transistors connected through external wiring have been reported18. These devices also have mismatched input and output logic levels, making them unsuitable for cascading multiple logic stages. This paper addresses the next challenge in the development of 2D nanoelectronics and optoelectronics on MoS2, that is the construction of fully integrated multi-stage logic circuits based on this material to demonstrate its capability for complex digital logic. These circuits were fabricated entirely on the same chip for the first time thanks to the seamless integration of both depletionmode (D-mode) and enhancement-mode (E-mode) MoS2 transistors. The transistors show multiple state-ofthe-art characteristics, such as current saturation, high on/off ratio (>10 7), and record on-state current density (>23 A/m). This demonstration of integrated logic gates, memory elements and a ring oscillator operating at 1.6 MHz represents an important step towards developing 2D electronics for both conventional and ubiquitous applications, offering materials that can combine silicon-like performance with the mechanical flexibility and integration versatility of organic semiconductors. Molybdenum disulfide (MoS2) is a layered semiconductor from the transition metal dichalcogenides material family (TMD), MX2 (M=Mo, W; X=S, Se, Te)10,11,19,20. A single molecular layer of MoS2 consists of a layer of Mo atoms sandwiched between two layers of sulfur atoms by covalent bonds10. The strong intra-layer covalent bonds confer MoS2 crystals excellent mechanical strength, thermal stability up to 1090 C in inert environment21, and a surface free of dangling bonds. On the other hand, the weak inter-layer Van der Waal’s force allows single- or fewlayer MoS2 thin films to be created through micro-mechanical cleavage technique22 and through anisotropic 2D