AD7798BRUZ中文资料

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半导体传感器AD7794BRUZ中文规格书

AD7708/AD7718PIN FUNCTION DESCRIPTIONSPin No Mnemonic Function1AIN7Analog Input Channel 7. Programmable-gain analog input that can be used as a pseudo-differential input when used with AINCOM, or as the positive input of a fully-differential inputpair when used with AIN8. (See ADC Control Register section.)2AIN8Analog Input Channel 8. Programmable-gain analog input that can be used as a pseudo-differential input when used with AINCOM, or as the negative input of a fully-differential inputpair when used with AIN7. (See ADC Control Register section.)3AV DD Analog Supply Voltage4AGND Analog Ground5REFIN1(–)Negative Reference Input. This reference input can lie anywhere between AGND and AV DD – 1 V. 6REFIN1(+)Positive reference input. REFIN(+) can lie anywhere between AV DD and AGND. The nominalreference voltage [REFIN(+)–REFIN(–)] is 2.5 V but the part is functional with a referencerange from 1 V to AV DD.7AIN1Analog Input Channel 1. Programmable-gain analog input that can be used as a pseudo-differential input when used with AINCOM, or as the positive input of a fully-differential inputpair when used with AIN2. (See ADC Control Register Section.)8AIN2Analog Input Channel 2. Programmable-gain analog input that can be used as a pseudo-differential input when used with AINCOM, or as the negative input of a fully-differential inputpair when used with AIN1. (See ADC Control Register section.)9AIN3Analog Input Channel 3. Programmable-gain analog input that can be used as a pseudo-differential input when used with AINCOM, or as the positive input of a fully-differential inputpair when used with AIN4. (See ADC Control Register section.)10AIN4Analog Input Channel 4. Programmable-gain analog input that can be used as a pseudo-differential input when used with AINCOM, or as the negative input of a fully-differential inputpair when used with AIN3. (See ADC Control Register section.)11AIN5Analog Input Channel 5. Programmable-gain analog input that can be used as a pseudo-differential input when used with AINCOM, or as the positive input of a fully-differential inputpair when used with AIN6. (See ADC Control Register section ADCCON.)12AINCOM All analog inputs are referenced to this input when configured in pseudo-differential input mode. 13REFIN2(+)/AIN9Positive reference input/analog input. This input can be configured as a reference input with thesame characteristics as REFIN1(+) or as an additional analog input. When configured as ananalog input this pin provides a programmable-gain analog input that can be used as a pseudo-differential input when used with AINCOM, or as the positive input of a fully-differential inputpair when used with AIN10. (See ADC Control Register section.)14REFIN2(–)/AIN10Negative reference input/analog input. This pin can be configured as a reference or analog input.When configured as a reference input it provides the negative reference input for REFIN2.When configured as an analog input it provides a programmable-gain analog input that can beused as a pseudo-differential input when used with AINCOM, or as the negative input of a fully-differential input pair when used with AIN9. (See ADC Control Register section.)15AIN6Analog Input Channel 6. Programmable-gain analog input that can be used as a pseudo-differential input when used with AINCOM, or as the negative input of a fully-differential inputpair when used with AIN5. (See ADC Control Register section.)16P2P2 can act as a general-purpose Input/Output bit referenced between AV DD and AGND. Thereis a weak pull-up to AV DD internally on this pin.17AGND It is recommended that this pin be tied directly to AGND.18P1P1 can act as a general-purpose Input/Output bit referenced between AV DD and AGND. Thereis a weak pull-up to AV DD internally on this pin.19RESET Digital input used to reset the ADC to its power-on-reset status. This pin has a weak pull-upinternally to DV DD.20SCLK Serial clock input for data transfers to and from the ADC. The SCLK has a Schmitt-triggerinput making an opto-isolated interface more robust. The serial clock can be continuous with alldata transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clockwith the information being transmitted to or from the AD7708/AD7718 in smaller batches of data.–12–REV. 0REV. 0AD7708/AD7718–15–ADC CIRCUIT INFORMATIONThe AD7708/AD7718 incorporates a 10-channel multiplexerwith a sigma-delta ADC, on-chip programmable gain amplifierand digital filtering intended for the measurement of widedynamic range, low frequency signals such as those in weigh-scale,strain-gauge, pressure transducer, or temperature measurementapplications. The AD7708 offers 16-bit resolution while theAD7718 offers 24-bit resolution. The AD7718 is a pin-for-pincompatible version of the AD7708. The AD7718 offers a directupgradable path from a 16-bit to a 24-bit system without requiringany hardware changes and only minimal software changes.These parts can be configured as four/five fully-differentialinput channels or as eight/ten pseudo-differential input chan-nels referenced to AINCOM. The channel is buffered and canbe programmed for one of eight input ranges from ±20 mV to±2.56V. Buffering the input channel means that the part can handle significant source impedances on the analog input andthat R, C filtering (for noise rejection or RFI reduction) can beplaced on the analog inputs if required. These input channelsare intended to convert signals directly from sensors without theneed for external signal conditioning.The ADC employs a sigma-delta conversion technique to realizeup to 24 bits of no missing codes performance. The sigma-deltamodulator converts the sampled input signal into a digital pulsetrain whose duty cycle contains the digital information. A Sinc 3programmable low-pass filter is then employed to decimate themodulator output data stream to give a valid data conversion resultat programmable output rates. The signal chain has two modesof operation, CHOP enabled and CHOP disabled. The CHOP bitin the mode register enables and disables the chopping scheme.Signal Chain Overview (CHOP Enabled, CHOP = 0)With CHOP = 0, chopping is enabled, this is the default and givesoptimum performance in terms of drift performance. With choppingenabled, the available output rates vary from 5.35Hz (186.77 ms)to 105.03 Hz (9.52 ms).A block diagram of the ADC inputchannel with chop enabled is shown in Figure 4.The sampling frequency of the modulator loop is many timeshigher than the bandwidth of the input signal. The integrator inthe modulator shapes the quantization noise (which results fromthe analog-to-digital conversion) so that the noise is pushedtoward one-half of the modulator frequency. The output of thesigma-delta modulator feeds directly into the digital filter. Thedigital filter then band-limits the response to a frequency signifi-cantly lower than one-half of the modulator frequency. In thismanner, the 1-bit output of the comparator is translated into aband limited, low noise output from the AD7708/AD7718 ADC.The AD7708/AD7718 filter is a low-pass, Sinc 3 or (sinx/x)3filter whose primary function is to remove the quantization noise introduced at the modulator. The cutoff frequency and deci-mated output data rate of the filter are programmable via the SF word loaded to the filter register. The complete signal chain is chopped resulting in excellent dc offset and offset drift specifica-tions and is extremely beneficial in applications where drift, noise rejection, and optimum EMI rejection are important factors.With chopping, the ADC repeatedly reverses its inputs. The decimated digital output words from the Sinc 3 filters, therefore,have a positive offset and negative offset term included. As a result, a final summing stage is included so that each output word from the filter is summed and averaged with the previous filter output to produce a new valid output result to be written to the ADC data register. The programming of the Sinc 3 deci-mation factor is restricted to an 8-bit register SF, the actual decimation factor is the register value times 8. The decimated output rate from the Sinc 3 filter (and the ADC conversion rate)will therefore be f SF f ADC MOD =×××1318where f ADC in the ADC conversion rate.SF is the decimal equivalent of the word loaded to the filter register.f MOD is the modulator sampling rate of 32.768 kHz.The chop rate of the channel is half the output data rate:f f CHOP ADC=×12As shown in the block diagram, the Sinc 3 filter outputs alter-nately contain +V OS and –V OS , where V OS is the respective channel offset. This offset is removed by performing a running average of two. This average by two means that the settling time to any change in programming of the ADC will be twice the normal conversion time, while an asynchronous step change on the analog input will not be fully reflected until the third subse-quent output.t f t SETTLE ADC ADC ==×22The allowable range for SF is 13 to 255 with a default of 69(45H). The corresponding conversion rates, conversion times,and settling times are shown in Table I. Note that the conver-sion time increases by 0.732 ms for each increment in SF.ANALOGINPUT DIGITAL OUTPUTIN OSA IN – V OSFigure 4.ADC Channel Block Diagram with CHOP Enabled。

AD7888AR资料

–80
–80
Peak Harmonic or Spurious Noise2
–80
–80
Intermodulation Distortion2 (IMD)
Second Order Terms
–78
–78
Third Order Terms
–78
–78
Channel-to-Channel Isolation2
CMOS construction ensures low power dissipation of typically 2 mW for normal operation and 3 µW in power-down mode. The part is available in a 16-lead narrow body small outline (SOIC) and a 16-lead thin shrink small outline (TSSOP) package.
Compatible 16-Lead Narrow SOIC and TSSOP Packages
APPLICATIONS Battery-Powered Systems (Personal Digital Assistants,
Medical Instruments, Mobile Communications) Instrumentation and Control Systems High Speed Modems
FUNCTIONAL BLOCK DIAGRAM
AIN1 AIN8
I/P
MUX
T/H
AD7888
VDD
2.5V REF
COMP
REF IN/REF OUT

AD7790BRMZ;AD7790BRMZ-REEL;AD7790BRM;中文规格书,Datasheet资料

Low Power, 16-BitBuffered Sigma-Delta ADCAD7790 Rev.0Information furnished by Analog Devices is believed to be accurate and reliable.However, no responsibility is assumed by Analog Devices for its use, nor for anyinfringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: Fax: 781.326.8703© 2003 Analog Devices, Inc. All rights reserved.FEATURESPowerSupply: 2.5 V to 5.25 V operationNormal: 75 µA maximumPower-down: 1 µA maximumRMS noise: 1.1 µV at 9.5 Hz update rate16-bit p-p resolutionIntegral nonlinearity: 3.5 ppm typical Simultaneous 50 Hz and 60 Hz rejection Internal clock oscillatorProgrammable gain amplifierRail-to-rail input bufferV DD monitor channelTemperature range: –40°C to +105°C10-lead MSOPINTERFACE3-wire serialSPI®, QSPI™, MICROWIRE™, and DSP compatible Schmitt trigger on SCLKAPPLICATIONSSmart transmittersBattery applicationsPortable instrumentationSensor measurementTemperature measurementPressure measurementWeigh scales4 to 20 mA loops FUNCTIONAL BLOCK DIAGRAM03538-0-001Figure 1.GENERAL DESCRIPTIONThe AD7790 is a low power, complete analog front end for low frequency measurement applications. It contains a low noise 16-bit ∑-∆ ADC with one differential input that can be buffered or unbuffered along with a digital PGA, which allows gains of 1, 2, 4, and 8.The device operates from an internal clock. Therefore, the user does not have to supply a clock source to the device. The output data rate from the part is software programmable and can be varied from 9.5 Hz to 120 Hz, with the rms noise equal to1.1 µV at the lower update rate. The internal clock frequency can be divided by a factor of 2, 4, or 8, which leads to a reduc-tion in the current consumption. The update rate, cutoff frequency, and settling time will scale with the clock frequency. The part operates with a power supply from2.5 V to 5.25 V. When operating from a 3 V supply, the power dissipation for the part is 225 µW maximum. It is housed in a 10-lead MSOP.AD7790Rev. 0 | Page 2 of 20TABLE OF CONTENTSAD7790—Specifications..................................................................3 Timing Characteristics.....................................................................5 Absolute Maximum Ratings............................................................7 Pin Configuration and Function Descriptions.............................8 Typical Performance Characteristics.............................................9 On-Chip Registers..........................................................................10 Communications Register(RS1, RS0 = 0, 0).........................................................................10 Status Register(RS1, RS0 = 0, 0; Power-on/Reset = 0x88)...............................11 Mode Register(RS1, RS0 = 0, 1; Power-on/Reset = 0x02)...............................11 Filter Register(RS1, RS0 = 1, 0; Power-on/Reset = 0x04)...............................12 Data Register(RS1, RS0 = 1, 1; Power-on/Reset = 0x0000) (12)ADC Circuit Information..............................................................13 Overview.....................................................................................13 Noise Performance.....................................................................13 Reduced Current Modes...........................................................13 Digital Interface..........................................................................14 Single Conversion Mode.......................................................15 Continuous Conversion Mode.............................................15 Continuous Read Mode........................................................16 Circuit Description.........................................................................17 Analog Input Channel...............................................................17 Programmable Gain Amplifier.................................................17 Bipolar Configuration................................................................17 Data Output Coding..................................................................17 Reference Input...........................................................................17 V DD Monitor................................................................................18 Grounding and Layout..............................................................18 Outline Dimensions.. (19)REVISION HISTORYRevision 0: Initial VersionAD7790Rev. 0 | Page 3 of 20AD7790—SPECIFICATIONS 1Table 1. (V DD = 2.5 V to 5.25 V; REFIN(+) = 2.5 V; REFIN(–) = GND; CDIV1 = CDIV0 = 0; GND = 0 V; all specifications T MIN to T MAX , unless otherwise noted.)Parameter AD7790B Unit Test Conditions/CommentsADC C H ANNEL SPECIFICATIONOutput Update Rate 9.5 Hz min nom 120 Hz max nomADC C H ANNELNo Missing Codes 2 16 Bits min ±V REF Range, Update Rate ≤ 20 Hz Resolution 16 Bits p-p 9.5 Hz Update Rate Output Noise 1.1 µV rms typ Integral Nonlinearity ±15 ppm of FSR max 3.5 ppm typ Offset Error ±3 µV typ Offset Error Drift vs. Temperature ±10 nV/°C typFull-Scale Error 3±10 µV typ Gain Drift vs. Temperature ±0.5 ppm/°C typ Power Supply Rejection 90 dB min Input Range = ±REFIN, 100 dB typ ANALOG INPUTS Differential Input Voltage Ranges ±REFIN/GAIN V nom REFIN = REFIN(+) – REFIN(–); GAIN = 1, 2, 4, or 8Absolute AIN Voltage Limits 2GND + 100 mV V min Buffered Mode of Operation V DD – 100 mV V max Analog Input Current Buffered Mode of OperationAverage Input Current 2±1 nA max Average Input Current Drift ±5 pA/°C typAbsolute AIN Voltage Limits 2GND – 30 mV V min Unbuffered Mode of Operation V DD + 30 mV V max Analog Input Current Unbuffered Mode of OperationInput current varies with input voltage.Average Input Current ±400 nA/V typ Average Input Current Drift ±50 pA/V/°C typ Normal Mode Rejection 2 @ 50 Hz, 60 Hz 65 dB min 73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 1004 @ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[2:0] = 1014 @ 60 Hz 80 dB min 90 dB typ, 60 ± 1 Hz, FS[2:0] = 0114 Common Mode Rejection Input Range = ±REFIN, AIN = 1 V @ DC 90 dB min 100 dB typ (FS[2:0] = 1004) @ 50 Hz, 60 Hz 2 100 dB min 50 ± 1 Hz (FS[2:0] = 1014), 60 ± 1 Hz (FS[2:0] = 0114) REFERENCE INPUT REFIN = REFIN(+) – REFIN(–) REFIN Voltage 2.5 V nomReference Voltage Range 20.1 V min V DDV max Absolute REFIN Voltage Limits 2GND – 30 mV V min V DD + 30 mV V max Average Reference Input Current 0.5 µA/V typ Average Reference Input Current Drift ±0.03 nA/V/°C typ1 Temperature Range –40°C to +105°C.2Specification is not production tested, but is supported by characterization data at initial product release. 3Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (V DD = 4 V). 4FS[2:0] are the three bits used in the filter register to select the output word rate.AD7790Rev. 0 | Page 4 of 20SPECIFICATIONS (continued)1Parameter AD7790B Unit Test Conditions/Comments REFERENCE INPUT (continued)Normal Mode Rejection 2@ 50 Hz, 60 Hz 65 dB min 73 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[2:0] = 1004 @ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[2:0] = 1014 @ 60 Hz 80 dB min 90 dB typ, 60 ± 1 Hz, FS[2:0] = 0114 Common Mode Rejection Input Range = ±2.5 V, AIN = 1 V @ DC 100 dB typ FS[2:0] = 1004 @ 50 Hz, 60 Hz 110 dB typ 50 ± 1 Hz (FS[2:0] = 1014), 60 ± 1 Hz (FS[2:0] = 0114) LOGIC INPUTS All Inputs Except SCLK 2 V INL , Input Low Voltage 0.8 V max V DD = 5 V 0.4 V max V DD = 3 VV INH , Input High Voltage 2.0 V min V DD = 3 V or 5 VSCLK Only (Schmitt-Triggered Input)2V T (+) 1.4/2 V min/V max V DD = 5 V V T (–) 0.8/1.4 V min/V max V DD = 5 V V T (+) – V T (–) 0.3/0.85 V min/V max V DD = 5 V V T (+) 0.9/2 V min/V max V DD = 3 V V T (–) 0.4/1.1 V min/V max V DD = 3 V V T (+) - V T (–) 0.3/0.85 V min/V max V DD = 3 V Input Currents ±1 µA max V IN = V DD or GND Input Capacitance 10 pF typ All Digital Inputs LOGIC OUTPUTSV OH , Output High Voltage 2V DD – 0.6 V min V DD = 3 V, I SOURCE = 100 µA V OL , Output Low Voltage 2 0.4 V max V DD = 3 V, I SINK = 100 µAV OH , Output High Voltage 24 V min V DD =5 V, I SOURCE = 200 µA V OL , Output Low Voltage 2 0.4 V max V DD = 5 V, I SINK = 1.6 mA Floating-State Leakage Current ±1 µA max Floating-State Output Capacitance 10 pF typ Data Output Coding Offset BinaryPOWER REQUIREMENTS 5Power Supply Voltage V DD – GND 2.5/5.25 V min/max Power Supply CurrentsI DD Current 675 µA max 65 µA typ, V DD = 3.6 V, Unbuffered Mode 145 µA max 130 µA typ, V DD = 3.6 V, Buffered Mode 80 µA max 73 µA typ, V DD = 5.25 V, Unbuffered Mode 160 µA max 145 µA typ, V DD = 5.25 V, Buffered ModeI DD (Power-Down Mode) 1 µA max5 Digital inputs equal to V DD or GND.6The current consumption can be further reduced by using the ADC in one of the low power modes (see Table 15).AD7790 TIMING CHARACTERISTICS1, 2Table 2. (V DD = 2.5 V to 5.25 V; GND = 0 V, REFIN(+) = 2.5 V, REFIN(–) = GND, CDIV1 = CDIV0 = 0, Input Logic 0 = 0 V,1 Sample tested during initial release to ensure compliance. All input signals are specified with t R = t F = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V.2 See Figure3 and Figure 4.3 These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the V OL or V OH limits.4 SCLK active edge is falling edge of SCLK.5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.6RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once.Rev. 0 | Page 5 of 20AD7790Rev. 0 | Page 6 of 2003538-0-002DD = 5V,DD = 3V)µA WITH V DD = 5V,DD = 3V)1.6VTO OUTPUTPINFigure 2. Load Circuit for Timing CharacterizationCS (I)I = INPUT, O = OUTPUTFigure 3. Read Cycle Timing DiagramI = INPUT, O = OUTPUTSCLK (I)DIN (I)Figure 4. Write Cycle Timing DiagramAD7790Rev. 0 | Page 7 of 20ABSOLUTE MAXIMUM RATINGSTable 3. (T A = 25°C, unless otherwise noted.)Parameter Rating V DD to GND –0.3 V to +7 V Analog Input Voltage to GND –0.3 V to V DD + 0.3 V Reference Input Voltage to GND –0.3 V to V DD + 0.3 V Total AIN/REFIN Current (Indefinite) 30 mA Digital Input Voltage to GND –0.3 V to V DD + 0.3 V Digital Output Voltage to GND –0.3 V to V DD + 0.3 V Operating Temperature Range –40°C to +105°CStorage Temperature Range –65°C to +150°CMaximum Junction Temperature 150°CMSOP θJA Thermal Impedance 206°C/W θJC Thermal Impedance 44°C/WLead Temperature, Soldering (10 sec) 300°CIR Reflow, Peak Temperature 220°CStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.AD7790Rev. 0 | Page 8 of 20PIN CONFIGURATION AND FUNCTION DESCRIPTIONS03538-0-005DIN DOUT/RDYV DD GNDREF(–)Figure 5. Pin ConfigurationAD7790Rev. 0 | Page 9 of 20TYPICAL PERFORMANCE CHARACTERISTICS03538-0-007–120–110–100–90–80–70–60–50–40–30–20–10040802060100120140d B1600FREQUENCY (Hz)Figure 6. Frequency Response for a 16.6 Hz Update Rate03538-0-0130.51.01.52.02.53.0 3.54.0 4.5R M S N O I S E (µV )5.0V REF (V)Figure 7. RMS Noise vs. Reference VoltageAD7790Rev. 0 | Page 10 of 20ON-CHIP REGISTERSThe ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise stated.COMMUNICATIONS REGISTER (RS1, RS0 = 0, 0)The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the com-munications register. The data written to the communications register determines whether the next operation is a read or write operation, and to which register this operation takes place. For read or write operations, once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the communications register. This is the default state of the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications regis-ter. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the ADC to this default state by resetting the entire part. Table 5 outlines the bit designations for the communications register. CR0 through CR7 indi-cate the bit location, CR denoting the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit.Table 6. Register SelectionRS1 RS0 RegisterRegister Size0 0 Communications Registerduring a Write Operation8-Bit 0 0 Status Register during aRead Operation8-Bit 0 1 Mode Register 8-Bit 1 0 Filter Register 8-Bit 1 1 Data Register16-BitTable 7. Channel SelectionCH1 CH0 Channel 0 0 AIN(+) – AIN(–) 0 1 Reserved 1 0 AIN(–) – AIN(–) 1 1 V DD Monitor分销商库存信息:ANALOG-DEVICESAD7790BRMZ AD7790BRMZ-REEL AD7790BRM。

半导体传感器AD7792BRUZ中文规格书

AD7741–SPECIFICATIONS(V DD = +4.75 V to +5.25 V; V REF = +2.5 V; f CLKIN = 6.144 MHz; all specifications T MIN toT MAX unless otherwise noted.)B and Y Version1Parameter2Min Typ Max Units Conditions/CommentsDC PERFORMANCEIntegral Nonlinearityf CLKIN = 200 kHz3±0.012% of Span4f CLKIN = 3 MHz3±0.012% of Spanf CLKIN = 6.144 MHz±0.024% of Span V DD > 4.8 VOffset Error±40mVGain Error0+0.8+1.6% of SpanOffset Error Drift3±30μV/°CGain Error Drift3±16ppm of Span/°CPower Supply Rejection Ratio3–63dBΔV DD = ±5%ANALOG INPUT5Input Current±50±100nAInput Voltage Range0V REF V+2.5 V REFERENCE (REFIN/OUT)REFINNominal Input Voltage 2.5VInput Impedance6N/AREFOUTOutput Voltage 2.38 2.50 2.60VOutput Impedance31kΩReference Drift3±50ppm/°CLine Rejection–60dBReference Noise (0.1 Hz to 10 Hz)3100μV p-pLOGIC OUTPUTOutput High Voltage, V OH 4.0V Output Sourcing 800 μA7Output Low Voltage, V OL0.4V Output Sinking 1.6 mA7 Minimum Output Frequency0.05 f CLKIN Hz V IN = 0 VMaximum Output Frequency0.45 f CLKIN Hz V IN = V REFLOGIC INPUTPD ONLYInput High Voltage, V IH 2.4VInput Low Voltage, V IL0.8VInput Current±100nAPin Capacitance610pFCLKIN ONLYInput High Voltage, V IH 3.5VInput Low Voltage, V IL0.8VInput Current±2μAPin Capacitance610pFCLOCK FREQUENCYInput Frequency 6.144MHz For Specified Performance POWER REQUIREMENTSV DD 4.75 5.25VI DD (Normal Mode)8mA Output UnloadedI DD (Power-Down)1535μAPower-Up Time330μs Coming Out of Power-Down ModeNOTES1Temperature ranges: B Version –40°C to +85°C: Y Version: –40°C to +105°C.2See Terminology.3Guaranteed by design and characterization, not production tested.4Span = Maximum Output Frequency–Minimum Output Frequency.5The absolute voltage on the input pin must not go more positive than VDD – 2.25 V or more negative than GND.6Because this pin is bidirectional, any external reference must be capable of sinking/sourcing 400 μA in order to overdrive the internal reference.7These logic levels apply to CLKOUT only when it is loaded with one CMOS load.Specifications subject to change without notice.REV. A–2–REV. AAD7741–6–AD7742 PIN FUNCTION DESCRIPTION Pin No.Mnemonic Function 1f OUT Frequency Output. This pin provides the output of the synchronous VFC.2VDD Power Supply Input. These parts can be operated from +4.75 V to +5.25 V and the supply should be adequately decoupled to GND.3GND Ground reference point for all circuitry on the part.4–5A1, A0Address Inputs used to select the input channel configuration.6CLKOUT External Clock Output. When the master clock for the device is a crystal, the crystal is connected be-tween CLKIN and CLKOUT. When an external clock is applied to CLKIN, the CLKOUT pinprovides an inverted clock signal. This clock should be buffered if it is to be used as a clock sourceelsewhere in the system.7CLKIN External Clock Input. The master clock for the device can be provided in the form of a crystal or anexternal clock. A crystal may be tied across the CLKIN and CLKOUT pins. Alternatively, the CLKINpin may be driven by a CMOS-compatible clock and CLKOUT left unconnected. The frequency of themaster clock may be as high as 6 MHz.8UNI/BIP Control input which determines whether the device operates with differential bipolar analog inputsignals or differential unipolar analog input signals.9REFOUT 2.5 V Voltage Reference Output. This can be tied directly to REFIN. It may also be used as a referenceto other parts of the system provided it is buffered first.10REFIN This is the Reference Input to the core of the VFC and defines the span of the VFC. A 2.5 V referenceis required at this pin. This may be provided by connecting it directly to REFOUT or by using a preci-sion external reference (e.g., REF192).11V IN 1Buffered Analog Input Channel 1. This is either a pseudo-differential input with respect to V IN 4 or it isthe positive input of a truly-differential input pair with respect to V IN 2.12V IN 2Buffered Analog Input Channel 2. This is either a pseudo-differential input with respect to V IN 4 or it isthe negative input of a truly-differential input pair with respect to V IN 1.13V IN 3Buffered Analog Input Channel 3. This is the positive input of a truly-differential input pair with re-spect to V IN 4.14V IN 4Buffered Analog Input Channel 4. This is either the common for pseudo-differential input with respectto V IN 1 or V IN 2 or it is the negative input of a truly-differential input pair with respect to V IN 3.15GAIN Gain Select input that controls whether the gain on the analog front-end is X1 or X2.16PDActive Low Power-Down pin. When this input is low, the part enters power-down mode where it typi-cally consumes 25 μA of current.PIN CONFIGURATIONf OUT PD V DD GAIN GND V IN 4A1V IN 3A0V IN 2CLKOUT V IN 1CLKIN REFIN UNI/BIP REFOUT。

AD7799中文资料.

写入 01011100；当 RDY 变为低时，向通信寄存器中写入
01011000，退出连续可读模式。当在连续可读模式下，ADC
检测到 DIN 脚的有效活动，也会退出连续可读模式。另外，
如果在 DIN 管脚上连续输入 32 位的高电平，AD 被复位。因
此，当在连续读模式下 DIN 脚应被置为低电平直到一个新的
参考输入电压 GND
输入数字电压 GND
输出数字电压 GND
Rating −0.3 V to +7 V −0.3 V to +7 V −0.3 V to AVDD +
0.3 V −0.3 V to AVDD +
0.3 V −0.3 V to DVDD +
0.3 V −0.3 V to DVDD +
0.3 V
11.33
9.44 3.132
1.773
1.107பைடு நூலகம்
0.5
0.413
0.374
AD7799在2.5V参考电源下其典型分辨率（BIT）与增益和输出更新速率之间的关
系
更新速率Gain=1 Gain=2 Gain=3 Gain=4 Gain=5 Gain=6 Gain=7 Gain=8
4.17 Hz
23(20.5) 22(19.5) 22.5(20) 22.5(20) 22(19.5) 22(19.5) 21.5(19) 20.5(18)
应用
电子磅秤压力测量应变传感器血气分析工业过程控制仪器仪表便携式仪表血液分析智能变送器液体/气体色谱 6 位数字电压表
概述：
AD7798/AD7799 适合在低功耗，低噪音，完成模拟前端高精度测量应用。

AD779资料

4. RELIABILITY: The AD779 utilizes Analog Devices’ monolithic BiMOS technology. This ensures long term reliability compared to multichip and hybrid designs.
元器件交易网
a
FEATURES AC and DC Characterized and Specified (K, B, T
Grades) 128k Conversions per Second 1 MHz Full Power Bandwidth 500 kHz Full Linear Bandwidth 80 dB S/N+D (K, B, T Grades) Twos Complement Data Format (Bipolar Mode) Straight Binary Data Format (Unipolar Mode) 10 M⍀ Input Impedance 16-Bit Bus Interface (See AD679 for 8-Bit Interface) Onboard Reference and Clock 10 V Unipolar or Bipolar Input Range MIL-STD-883 Compliant Versions Available
2. SPECIFICATIONS: The AD779K, B and T grades provide fully specified and tested ac and dc parameters. The AD779J, A and S grades are specified and tested for ac parameters; dc accuracy specifications are shown as typicals. DC specifications (such as INL, gain and offset) are important in control and measurement applications. AC specifications (such as S/N+D ratio, THD and IMD) are of value in signal processing applications.

半导体传感器AD7327BRUZ中文规格书

Core ArchitectureFigure 1-1: Processor Core ArchitectureThe compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multi-ported register file and instruction constant fields.Each 16-bit MAC can perform a 16- by 16-bit multiply per cycle, with accumulation to a 40-bit result. The 32-bit MAC can perform a 32- by 32-bit multiply, with accumulation to 72-bits, or a 16-bit complex multiplication. Sign-ed and unsigned formats, rounding, and saturation are supported.The ALUs perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. Many special in-structions are included to accelerate various signal processing tasks, including bit operations such as field extract and population count, divide primitives, saturation and rounding, and sign/exponent detection. The set of video instruc-tions include byte-alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit Subtract/Absolute value/Accumulate (SAA) operations. Also provided are the compare/select and vector search instructions. For some instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a compute register). By also using the second ALU, quad-16-bit operations are possible.The 40-bit shifter can deposit data and perform shifting, rotating, normalization, and extraction operations.A program sequencer controls the instruction execution flow, including instruction alignment and decoding. For program flow control, the sequencer supports PC-relative and indirect conditional jumps (with static branch predic-tion) and subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully inter-locked, meaning there are no visible pipeline effects when executing instructions with data dependencies.Memory Architecture The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multi-ported register file consisting of four sets of 32-bit index, modify, length, and base registers (for circular buffering)and eight additional 32-bit pointer registers (for C-style indexed stack manipulation).Blackfin+ processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories typically operate at the full processor speed with little or no latency. At the L1 level, the instruction memory holds instructions only. The two data memories hold data, and a dedicated scratchpad data memory can be used to store stack and local variable information.In addition, multiple L1 memory blocks are provided, which may be configured as a mix of SRAM and cache. The Memory Management Unit (MMU) provides memory protection for individual tasks that may be operating on the core.The architecture provides three modes of operation: User, Supervisor, and Emulation. User mode has restricted ac-cess to a subset of system resources, thus providing a protected software environment. Supervisor and Emulation modes have unrestricted access to the system and core resources.The Blackfin+ processor instruction set is optimized so that 16-bit opcodes represent the most frequently used in-structions. Complex DSP instructions are encoded into 32-bit opcodes as multi-function instructions, and some in-structions with very large immediate values are encoded into 64-bit opcodes. Blackfin+ products support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions. This allows the programmer to use many of the core resources in a single instruction cycle.The Blackfin+ processor assembly language uses an algebraic syntax. The architecture is optimized for use with the C compiler.Memory ArchitectureThe Blackfin+ processor architecture structures memory as a single, unified 4 GB address space using 32-bit address-es. All resources, including internal memory, external memory, and I/O control registers, occupy separate sections of this common address space. The memory portions of this address space are arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low-latency on-chip memory (as cache or SRAM) and larger, lower-cost and lower-performance off-chip memory systems.The memory DMA controller provides high-bandwidth data movement capabilities. It can perform block transfers of code or data between the internal and external memory spaces.Internal MemoryThe L1 memory system is the primary, highest-performance memory available to the core. At a minimum, each Blackfin+ processor has two blocks of on-chip memory that provide high-bandwidth access to the core:•L1 instruction memory, consisting of SRAM and/or an instruction cache. This memory is accessed at the full core clock rate.•L1 data memory, consisting of SRAM and/or a data cache. This memory block is also accessed at the full core clock rate.Memory ArchitectureOn-chip Level 2 (L2) memory forms an on-chip memory hierarchy with L1 memory and provides much more ca-pacity, but the latency is higher. The on-chip L2 memory may be made cacheable in L1 and is capable of storing both instructions and data.External MemoryExternal (off-chip) memory is accessed via on-chip memory peripherals such as DDR controllers.I/O Memory SpaceBlackfin+ processors do not define a separate I/O space. All resources are mapped through the flat 32-bit address space. Control registers for on-chip I/O devices are mapped into memory-mapped registers (MMRs) at addresses in a reserved part of the 4 GB address space. These are separated into two smaller blocks, one containing the control MMRs for all core functions (core MMRs) and the other containing the registers needed for setup and control of the on-chip peripherals outside of the core (system MMRs). All MMRs are accessible only in Supervisor mode. Event HandlingThe event controller on the Blackfin+ processor handles all asynchronous and synchronous events in the system. It supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously, and prioritization ensures that servicing a higher-priority event takes precedence over servicing a lower-priority event. The controller provides support for five different types of events:•Emulation - causes the processor to enter Emulation mode, allowing command and control of the processor via the JTAG interface.•Reset - resets the processor.•Non-Maskable Interrupt (NMI) - the software watchdog timer or the NMI input signal to the processor can generate this event. The NMI event is frequently used as a power-down indicator to initiate an orderly shut-down of the system.•Exceptions - synchronous to program flow, an exception is taken before the instruction is allowed to complete.Conditions such as data alignment violations and undefined instructions cause exceptions.•Interrupts - asynchronous to program flow. These events can be caused by input pins, timers, other peripherals, and software.Each event has an associated register to hold the return address and an associated return-from-event instruction. When an event is triggered, the state of the processor is saved on the supervisor stack.The processor event controller consists of two stages, the Core Event Controller (CEC) and the System Event Con-troller (SEC). The CEC works with the SEC to prioritize and control all system events. Conceptually, interrupts from the peripherals arrive at the SEC and are routed directly into a general-purpose interrupt of the CEC.。

AD9832BRUZ资料

3.9kΩ 10nF
REFOUT
REFIN
FS ADJUST COMP
AVDD 10nF
ON-BOARD REFERENCE
FULL-SCALE CONTROL
12
SIN ROM
10-BIT DAC
IOUT 300Ω 50pF
AD9832
Figure 1. Test Circuit with Which Specifications Are Tested –2–
Test Conditions/Comments MCLK Period MCLK High Duration MCLK Low Duration SCLK Period SCLK High Duration SCLK Low Duration FSYNC to SCLK Falling Edge Setup Time FSYNC to SCLK Hold Time Data Setup Time Data Hold Time FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge
CMOS Complete DDS AD9832
The AD9832 is a numerically controlled oscillator employing a phase accumulator, a sine look-up table and a 10-bit D/A converter integrated on a single CMOS chip. Modulation capabilities are provided for phase modulation and frequency modulation. Clock rates up to 25 MHz are supported. Frequency accuracy can be controlled to one part in 4 billion. Modulation is effected by loading registers through the serial interface. A power-down bit allows the user to power down the AD9832 when it is not in use, the power consumption being reduced to 5 mW (5 V) or 3 mW (3 V). The part is available in a 16-lead TSSOP package.

AD7792BRUZ;AD7793BRUZ;AD7792BRUZ-REEL;AD7793BRUZ-REEL;AD7792BRU;中文规格书,Datasheet资料

3-Channel, Low Noise, Low Power, 16-/24-Bit∑-ΔADC with On-Chip In-Amp and ReferenceAD7792/AD7793 Rev. BInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, M A 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2004–2007 Analog Devices, Inc. All rights reserved.FEATURESUp to 23 bits effective resolutionRMS noise40 nV @ 4.17 Hz85 nV @ 16.7 HzCurrent: 400 μA typicalPower-down: 1 μA maximumLow noise programmable gain instrumentation amp Band gap reference with 4 ppm/°C drift typical Update rate: 4.17 Hz to 470 Hz3 differential inputsInternal clock oscillatorSimultaneous 50 Hz/60 Hz rejection Programmable current sourcesOn-chip bias voltage generatorBurnout currentsPower supply: 2.7 V to 5.25 V–40°C to +105°C temperature rangeIndependent interface power supply16-lead TSSOP packageInterface3-wire serialSPI®, QSPI™, MICROWIRE™, and DSP compatible Schmitt trigger on SCLKAPPLICATIONSThermocouple measurementsRTD measurementsThermistor measurementsGas analysisIndustrial process controlInstrumentationPortable instrumentationBlood analysisSmart transmittersLiquid/gas chromatography6-digit DVMFUNCTIONAL BLOCK DIAGRAM4Figure 1.GENERAL DESCRIPTIONThe AD7792/AD7793 are low power, low noise, complete analog front ends for high precision measurement applications. The AD7792/AD7793 contain a low noise 16-/24-bit ∑-Δ ADC with three differential analog inputs. The on-chip, low noise instrumentation amplifier means that signals of small ampli-tude can be interfaced directly to the ADC. With a gain setting of 64, the rms noise is 40 nV when the update rate equals 4.17 Hz.The devices contain a precision low noise, low drift internal band gap reference and can accept an external differential reference. Other on-chip features include programmable excitation current sources, burnout currents, and a bias voltage generator. The bias voltage generator sets the common-mode voltage of a channel to AV DD/2.The devices can be operated with either the internal clock or an external clock. The output data rate from the parts is software-programmable and can be varied from 4.17 Hz to 470 Hz. The parts operate with a power supply from 2.7 V to 5.25 V. They consume a current of 400 μA typical and are housed in a 16-lead TSSOP package.AD7792/AD7793Rev. B | Page 2 of 32TABLE OF CONTENTSFeatures..............................................................................................1 Applications.......................................................................................1 Functional Block Diagram..............................................................1 General Description.........................................................................1 Revision History...............................................................................2 Specifications.....................................................................................3 Timing Characteristics.....................................................................6 Timing Diagrams..........................................................................7 Absolute Maximum Ratings............................................................8 ESD Caution..................................................................................8 Pin Configuration and Function Descriptions.............................9 Output Noise and Resolution Specifications..............................11 External Reference......................................................................11 Internal Reference......................................................................12 Typical Performance Characteristics...........................................13 On-Chip Registers..........................................................................14 Communications Register.........................................................14 Status Register.............................................................................15 Mode Register.............................................................................15 Configuration Register..............................................................17 Data Register...............................................................................18 ID Register...................................................................................18 IO Register...................................................................................18 Offset Register............................................................................19 Full-Scale Register......................................................................19 ADC Circuit Information..............................................................20 Overview.....................................................................................20 Digital Interface..........................................................................21 Circuit Description.........................................................................24 Analog Input Channel...............................................................24 Instrumentation Amplifier........................................................24 Bipolar/Unipolar Configuration..............................................24 Data Output Coding..................................................................24 Burnout Currents.......................................................................25 Excitation Currents....................................................................25 Bias Voltage Generator..............................................................25 Reference.....................................................................................25 Reset.............................................................................................25 AV DD Monitor.............................................................................26 Calibration...................................................................................26 Grounding and Layout..............................................................26 Applications Information..............................................................28 Temperature Measurement using a Thermocouple...............28 Temperature Measurement using an RTD..............................29 Outline Dimensions.......................................................................30 Ordering Guide.. (30)REVISION HISTORY3/07—Rev. A to Rev. BUpdated Format..................................................................Universal Change to Functional Block Diagram...........................................1 Changes to Specifications Section..................................................3 Changes to Specifications Endnote 1.............................................5 Changes to Table 5, Table 6, and Table 7.....................................11 Changes to Table 8, Table 9, and Table 10...................................12 Changes to Table 16........................................................................16 Changes to Overview Section.......................................................20 Renamed Applications Section to Applications Information...29 Changes to Ordering Guide..........................................................30 4/05—Rev. 0 to Rev. AChanges to Absolute Maximum Ratings........................................8 Changes to Figure 17.......................................................................22 Changes to Data Output Coding Section.....................................24 Changes to Calibration Section.....................................................26 Changes to Ordering Guide...........................................................30 10/04—Revision 0: Initial VersionAD7792/AD7793Rev. B | Page 3 of 32SPECIFICATIONSAV DD = 2.7 V to 5.25 V; DV DD = 2.7 V to 5.25 V; GND = 0 V; all specifications T MIN to T MAX , unless otherwise noted. Table 1.Parameter AD7792B/AD7793B 1 Unit Test Conditions/Comments ADC CHANNEL Output Update Rate 4.17 to 470 Hz nom No Missing Codes 224 Bits min f ADC < 242 Hz, AD7793 16 Bits min AD7792 Resolution See Output Noise and Resolution Specifications Output Noise and Update Rates See Output Noise and Resolution Specifications Integral Nonlinearity ±15 ppm of FSR max Offset Error 3±1 μV typOffset Error Drift vs. Temperature 4±10 nV/°C typ Full-Scale Error 3, 5±10 μV typGain Drift vs. Temperature 4±1 ppm/°C typ Gain = 1 to 16, external reference ±3 ppm/°C typ Gain = 32 to 128, external reference Power Supply Rejection 100 dB min AIN = 1 V/gain, gain ≥ 4, external reference ANALOG INPUTS Differential Input Voltage Ranges ±V REF /Gain V nom V REF = REFIN(+) − REFIN(−) or internal reference,gain = 1 to 128Absolute AIN Voltage Limits 2 Unbuffered Mode GND – 30 mV V min Gain = 1 or 2 AV DD + 30 mV V max Buffered Mode GND + 100 mV V min Gain = 1 or 2 AV DD – 100 mV V max In-Amp Active GND + 300 mV V min Gain = 4 to 128 AV DD – 1.1 V max Common-Mode Voltage, V CM 0.5 V min V CM = (AIN(+) + AIN(−))/2, gain = 4 to 128 Analog Input Current Buffered Mode or In-Amp Active Average Input Current 2±1 nA max Gain = 1 or 2, update rate < 100 Hz ±250 pA max Gain = 4 to 128, update rate < 100 HzAverage Input Current Drift ±2 pA/°C typ Unbuffered Mode Gain = 1 or 2. Average Input Current ±400 nA/V typ Input current varies with input voltage Average Input Current Drift ±50 pA/V/°C typNormal Mode Rejection 2Internal Clock @ 50 Hz, 60 Hz 65 dB min 80 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 10106@ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, FS[3:0] = 10016@ 60 Hz 90 dB min 100 dB typ, 60 ± 1 Hz, FS[3:0] = 10006External Clock @ 50 Hz, 60 Hz 80 dB min 90 dB typ, 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 10106@ 50 Hz 94 dB min 100 dB typ, 50 ± 1 Hz, FS[3:0] = 10016@ 60 Hz 90 dB min 100 dB typ, 60 ± 1 Hz, FS[3:0] = 10006Common-Mode Rejection @ DC 100 dB min AIN = 1 V/gain, gain ≥ 4@ 50 Hz, 60 Hz 2100 dB min 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 10106@ 50 Hz, 60 Hz 2100 dB min 50 ± 1 Hz (FS[3:0] = 1001)6, 60 ± 1 Hz(FS[3:0] = 1000)6AD7792/AD7793Rev. B | Page 4 of 32AD7792/AD77931 Temperature range is –40°C to +105°C. At the 19.6 Hz and 39.2 Hz update rates, the INL, power supply rejection (PSR), common-mode rejection (CMR), and normal mode rejection (NMR) do not meet the data sheet specification if the voltage on the AIN(+) or AIN(−) pins exceed AV DD − 16 V typically. When this voltage is exceeded, the INL, for example, is reduced to 18 ppm of FS typically while the PSR is reduced to 69 dB typically. Therefore, for guaranteed performance at these update rates, the absolute voltage on the analog input pins needs to be below AV DD − 1.6 V.2 Specification is not production tested, but is supported by characterization data at initial product release.3 Following a calibration, this error is in the order of the noise for the programmed gain and update rate selected.4 Recalibration at any temperature removes these errors.5 Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AV DD = 4 V, gain = 1, T A = 25°C).6 FS[3:0] are the four bits used in the mode register to select the output word rate.7 Digital inputs equal to DV DD or GND with excitation currents and bias voltage generator disabled.Rev. B | Page 5 of 32AD7792/AD7793Rev. B | Page 6 of 32TIMING CHARACTERISTICSAV DD = 2.7 V to 5.25 V , DV DD = 2.7 V to 5.25 V , GND = 0 V , Input Logic 0 = 0 V , Input Logic 1 = DV DD , unless otherwise noted.1 Sample tested during initial release to ensure compliance. All input signals are specified with t R = t F = 5 ns (10% to 90% of DV DD ) and timed from a voltage level of 1.6 V. 2See Figure 3 and Figure 4. 3These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the V OL or V OH limits. 4SCLK active edge is falling edge of SCLK. 5These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 6 RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once.04855-002DD = 5V,DD = 3V)DD = 5V,DD = 3V)1.6VTO OUTPUTPINAD7792/AD7793Rev. B | Page 7 of 32TIMING DIAGRAMS048CS (I)NOTES1. I = INPUT, O = OUTPUTFigure 3. Read Cycle Timing Diagram04855NOTES1. I = INPUT, O = OUTPUTCS (I)SCLK (I)DIN (I)Figure 4. Write Cycle Timing DiagramAD7792/AD7793Rev. B | Page 8 of 32ABSOLUTE MAXIMUM RATINGST A = 25°C, unless otherwise noted. Table 3.Parameter RatingsAV DD to GND −0.3 V to +7 V DV DD to GND−0.3 V to +7 VAnalog Input Voltage to GND −0.3 V to AV DD + 0.3 V Reference Input Voltage to GND −0.3 V to AV DD + 0.3 V Digital Input Voltage to GND −0.3 V to DV DD + 0.3 V Digital Output Voltage to GND −0.3 V to DV DD + 0.3 V AIN/Digital Input Current10 mAOperating Temperature Range −40°C to +105°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C TSSOPθJA Thermal Impedance 128°C/W θJC Thermal Impedance 14°C/W Lead Temperature, SolderingVapor Phase (60 sec) 215°C Infrared (15 sec)220°CStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.ESD CAUTIONAD7792/AD7793Rev. B | Page 9 of 32PIN CONFIGURATION AND FUNCTION DESCRIPTIONS04855-005CLK CS IOUT1AIN2(+)AIN1(–)AIN1(+)SCLK DOUT/RDY DV DD AV DD REFIN(–)/AIN3(–)AIN2(–)REFIN(+)/AIN3(+)IOUT2GND DINAD7792/AD7793Rev. B | Page 10 of 32分销商库存信息:ANALOG-DEVICESAD7792BRUZ AD7793BRUZ AD7792BRUZ-REEL AD7793BRUZ-REEL AD7792BRU AD7793BRUEVAL-AD7792EBZ。

AD7798BRUZ;AD7799BRUZ;AD7798BRUZ-REEL;AD7799BRUZ-REEL;AD7799BRU-REEL;中文规格书,Datasheet资料

AD7788ARMZ;AD7788BRMZ;AD7789BRMZ;AD7788ARMZ-REEL;AD7788ARM-REEL;中文规格书,Datasheet资料

Low Power, 16-/24-Bit,Sigma-Delta ADCsAD7788/AD7789 Rev. BInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. O ne Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.FEATURESAD7788: 16-bit resolutionAD7789: 24-bit resolutionPowerSupply: 2.5 V to 5.25 V operationNormal: 75 μA maximumPower-down: 1 μA maximumRMS noise: 1.5 μVAD7788: 16-bit p-p resolutionAD7789: 19-bit p-p resolution (21.5 bits effective) Integral nonlinearity: 3.5 ppm typical Simultaneous 50 Hz and 60 Hz rejectionInternal clock oscillatorV DD monitor channel10-lead MSOPINTERFACE3-wire serialSPI®-, QSPI™-, MICROWIRE™-, and DSP-compatible Schmitt trigger on SCLKAPPLICATIONSSmart transmittersBattery applicationsPortable instrumentationSensor measurementTemperature measurementPressure measurementWeigh scales4 to 20 mA loopsFUNCTIONAL BLOCK DIAGRAM3539-1*AD7788: 16-BIT ADCAD7789: 24-BIT ADCGNDREFIN(+)REFIN(–)VDOUT/RDYDINSCLKFigure 1.GENERAL DESCRIPTIONThe AD7788/AD7789 are low power, low noise, analog front ends for low frequency measurement applications. The AD7789 contains a low noise, 24-bit, ∑-Δ ADC with one differential input. The AD7788 is a 16-bit version of the AD7789.The devices operate from an internal clock. Therefore, the user does not have to supply a clock source to the devices. The output data rate is 16.6 Hz, which gives simultaneous50 Hz/60 Hz rejection.The parts operate with a single power supply from 2.5 V to 5.25 V. When operating from a 3 V supply, the power dissi-pation for the part is 225 μW maximum. The AD7788/AD7789 are available in a 10-lead MSOP.AD7788/AD7789Rev. B | Page 2 of 20TABLE OF CONTENTSFeatures..............................................................................................1 Interface.............................................................................................1 Applications.......................................................................................1 Functional Block Diagram..............................................................1 General Description.........................................................................1 Revision History...............................................................................2 Specifications.....................................................................................3 AD7789..........................................................................................3 AD7788..........................................................................................4 AD7788/AD7789..........................................................................5 Timing Characteristics................................................................6 Timing Diagrams..........................................................................7 Absolute Maximum Ratings............................................................8 ESD Caution..................................................................................8 Pin Configuration and Function Descriptions.............................9 Typical Performance Characteristics...........................................10 On-Chip Registers..........................................................................11 Communications Register.........................................................11 Status Register.............................................................................12 Mode Register.............................................................................13 Data Register...............................................................................13 ADC Circuit Information..............................................................14 Noise Performance.....................................................................14 Digital Interface..........................................................................14 Circuit Description.........................................................................17 Analog Input Channel...............................................................17 Bipolar/Unipolar Configuration..............................................17 Data Output Coding..................................................................17 Reference Input...........................................................................17 V DD Monitor................................................................................18 Grounding and Layout..............................................................18 Outline Dimensions.......................................................................19 Ordering Guide.. (19)REVISION HISTORY3/06—Rev. A to Rev. BChanges to Ordering Guide..........................................................19 11/04—Rev. 0 to Rev. AUpdated Format..................................................................Universal Added Footnote 2 to Integral Nonlinearity A Grade...................4 Changes to Figure 5..........................................................................9 Updated Outline Dimensions.......................................................19 Changes to Ordering Guide..........................................................19 8/03—Revision 0: Initial VersionAD7788/AD7789Rev. B | Page 3 of 20SPECIFICATIONSAD7789V DD = 2.5 V to 5.25 V; REFIN(+) = 2.5 V; REFIN(−) = GND; GND = 0 V; all specifications T MIN to T MAX , unless otherwise noted. Table 1.Parameter 1AD7789B Unit Test Conditions/Comments ADC CHANNEL SPECIFICATIONOutput Update Rate 16.6 Hz nom ADC CHANNELNo Missing Codes 224 Bits min Resolution 19 Bits p-p Output Noise1.5 μV rms typIntegral Nonlinearity ±15 ppm of FSR max Offset Error±3 μV typ Offset Error Drift vs. Temperature ±10 nV/°C typ Full-Scale Error 3±10 μV typGain Drift vs. Temperature ±0.5 ppm/°C typPower Supply Rejection 90 dB min 100 dB typ, AIN = 1 V ANALOG INPUTSDifferential Input Voltage Ranges ±REFINV nom REFIN = REFIN(+) − REFIN(−) Absolute AIN Voltage Limits 2GND − 30 mV V minV DD + 30 mV V maxAnalog Input CurrentInput current varies with input voltage Average Input Current 2±400 nA/V typ Average Input Current Drift ±50 pA/V/°C typ Normal-Mode Rejection 2@ 50 Hz, 60 Hz65 dB min 50 Hz ± 1 Hz, 60 Hz ± 1 Hz Common-Mode RejectionAIN = 1 V @ DC90 dB min 100 dB typ@ 50 Hz, 60 Hz 2100 dB min 50 Hz ± 1 Hz, 60 Hz ± 1 Hz REFERENCE INPUTREFIN Voltage2.5 V nom REFIN = REFIN(+) − REFIN(−) Reference Voltage Range 20.1 V minV DDV max Absolute REFIN Voltage Limits 2GND − 30 mV V minV DD + 30 mV V max Average Reference Input Current0.5 μA/V typ Average Reference Input Current Drift ±0.03 nA/V/°C typ Normal-Mode Rejection 2@ 50 Hz, 60 Hz65 dB min 50 Hz ± 1 Hz, 60 Hz ± 1 Hz Common-Mode RejectionAIN = 1 V @ DC110 dB typ@ 50 Hz, 60 Hz110 dB typ 50 Hz ± 1 Hz, 60 Hz ± 1 Hz1 Temperature range: −40°C to +105°C.2Specification is not production tested but is supported by characterization data at initial product release. 3Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (V DD = 4 V).AD7788/AD7789Rev. B | Page 4 of 20AD7788V DD = 2.5 V to 5.25 V (B grade); V DD = 2.7 V to 5.25 V (A grade); REFIN(+) = 2.5 V; REFIN(−) = GND; GND = 0 V; all specifications T MIN to T MAX , unless otherwise noted. Table 2.Parameter 1AD7788 A, AD7788B Unit Test Conditions/Comments ADC CHANNEL SPECIFICATIONOutput Update Rate 16.6 Hz nom ADC CHANNELNo Missing Codes 216 Bits min Resolution 16 Bits p-p Output Noise1.5 μV rms typIntegral Nonlinearity ±15 ppm of FSR max B grade±50 ppm of FSR max A grade 2Offset Error±3 μV typ Offset Error Drift vs. Temperature ±10 nV/°C typ Full-Scale Error 3±10 μV typGain Drift vs. Temperature ±0.5 ppm/°C typPower Supply Rejection 90 dB min B grade90 dB typ A grade ANALOG INPUTSDifferential Input Voltage Ranges ±REFINV nom REFIN = REFIN(+) − REFIN(−) Absolute AIN Voltage Limits 2GND − 30 mV V minV DD + 30 mV V maxAnalog Input CurrentInput current varies with input voltage Average Input Current 2±400 nA/V typ Average Input Current Drift ±50 pA/V/°C typ Normal-Mode Rejection 2@ 50 Hz, 60 Hz 65 dB min B grade, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz60 dB min A grade, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz Common-Mode RejectionAIN = 1 V@ DC 90 dB min B grade, 100 dB typ90 dB typ A grade@ 50 Hz, 60 Hz 2100 dB min B grade, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz100 dB typ A grade, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz REFERENCE INPUTREFIN Voltage2.5 V nom REFIN = REFIN(+) − REFIN(−) Reference Voltage Range 20.1 V minV DDV max Absolute REFIN Voltage Limits 2GND − 30 mV V minV DD + 30 mV V max Average Reference Input Current0.5 μA/V typ Average Reference Input Current Drift ±0.03 nA/V/°C typ Normal-Mode Rejection 2@ 50 Hz, 60 Hz 65 dB min B grade, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz60 dB min A grade Common-Mode RejectionAIN = 1 V @ DC100 dB typ@ 50 Hz, 60 Hz110dB typ 50 Hz ± 1 Hz, 60 Hz ± 1 Hz1 Temperature range: B grade: −40°C to +105°C; A grade: −40°C to +85°C.2Specification is not production tested but is supported by characterization data at initial product release. 3Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (V DD = 4 V).AD7788/AD7789 AD7788/AD7789Table 3.Parameter AD7788A, AD7788B/AD7789B Unit Test Conditions/Comments LOGIC INPUTSAll Inputs Except SCLK1V INL, Input Low Voltage 0.8 V max V DD = 5 V0.4 V max V DD = 3 VV INH, Input High Voltage 2.0 V min V DD = 3 V or 5 VSCLK Only (Schmitt-Triggered Input)1V T(+) 1.4/2 V min/V max V DD = 5 VV T(−) 0.8/1.4 V min/V max V DD = 5 VV T(+) − V T(−) 0.3/0.85 V min/V max V DD = 5 VV T(+) 0.9/2 V min/V max V DD = 3 VV T(−) 0.4/1.1 V min/V max V DD = 3 VV T(+) − V T(−) 0.3/0.85 V min/V max V DD = 3 VInput Currents ±1 μA max V IN = V DDInput Capacitance 10 pF typ All digital inputsLOGIC OUTPUTSV OH, Output High Voltage1V DD− 0.6 V min V DD = 3 V, I SOURCE = 100 μAV OL, Output Low Voltage10.4 V max V DD = 3 V, I SINK = 100 μAV OH, Output High Voltage1 4 V min V DD = 5 V, I SOURCE = 200 μAV OL, Output Low Voltage10.4 V max V DD = 5 V, I SINK = 1.6 mA Floating-State Leakage Current ±1 μA maxFloating-State Output Capacitance 10 pF typData Output Coding Offset binaryPOWER REQUIREMENTS2Power Supply VoltageV DD− GND 2.5/5.25 V min/max AD7789, AD7788 B grade2.7/5.25 V min/max AD7788 A gradePower Supply CurrentsI DD Current 75 μA max 65 μA typ, V DD = 3.6 V80 μA max 73 μA typ, V DD = 5.25 VI DD (Power-Down Mode) 1 μA max1 Specification is not production tested but is supported by characterization data at initial product release.2 Digital inputs equal to V DD or GND.Rev. B | Page 5 of 20AD7788/AD7789TIMING CHARACTERISTICSV DD = 2.5 V to 5.25 V (AD7788B and AD7789); V DD = 2.7 V to 5.25 V (AD7788A); GND = 0 V; REFIN(+) = 2.5 V; REFIN(−) = GND; Input Logic 0 = 0 V; Input Logic 1 = V DD, unless otherwise noted.1 Sample tested during initial release to ensure compliance. All input signals are specified with t R = t F = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V.2 See Figure3 and Figure 4.3 These numbers are measured with the load circuit of, and defined as, the time required for the output to cross the V OL or V OH limits.4 SCLK active edge is the falling edge of SCLK.5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances.6RDY returns high after a read of the ADC. In single-conversion mode and continuous-conversion mode, the same data can be read again, if required, while RDY is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once.Rev. B | Page 6 of 20AD7788/AD7789Rev. B | Page 7 of 20TIMING DIAGRAMS03539-002DD = 5V,DD = 3V)DD = 5V,DD = 3V)1.6VPINFigure 2. Load Circuit for Timing Characterization035CS (I)I = INPUT, O = OUTPUTFigure 3. Read Cycle Timing Diagram03539I = INPUT, O = OUTPUTCS (I)SCLK (I)DIN (I)Figure 4. Write Cycle Timing DiagramAD7788/AD7789Rev. B | Page 8 of 20ABSOLUTE MAXIMUM RATINGST A = 25°C, unless otherwise noted. Table 5.Parameter RatingV DD to GND−0.3 V to +7 VAnalog Input Voltage to GND −0.3 V to V DD + 0.3 V Reference Input Voltage to GND −0.3 V to V DD + 0.3 V Total AIN/REFIN Current (Indefinite) 30 mADigital Input Voltage to GND −0.3 V to V DD + 0.3 V Digital Output Voltage to GND −0.3 V to V DD + 0.3 V Operating Temperature RangeB Grade −40°C to +105°C A Grade−40°C to +85°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C 10-Lead MSOPθJA Thermal Impedance 206°C/W θJC Thermal Impedance44°C/W Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature220°CStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affectdevice reliability.ESD CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.AD7788/AD7789Rev. B | Page 9 of 20PIN CONFIGURATION AND FUNCTION DESCRIPTIONS03539-005DOUT/RDYDDFigure 5. Pin ConfigurationAD7788/AD7789Rev. B | Page 10 of 20TYPICAL PERFORMANCE CHARACTERISTICS03539-007–120–110–100–90–80–70–60–50–40–30–20–10040802060100120140d B1600FREQUENCY (Hz)Figure 6. Frequency Response with 16.6 Hz Update Rate03539-008102030405060708388591O C C U R E N C E8388625CODEFigure 7. AD7789 Noise Histogram 03539-0098388591200400600800C OD E10008388625READ NO.V DD = 3V, V REF = 2.048V,T A = 25°C, RMS NOISE = 1.25µVFigure 8. AD7789 Noise Plot03539-0130.51.01.500.5 1.0 1.5 2.02.53.03.54.0 4.5R M S N O I S E (µV )5.03.02.52.0V REF (V)Figure 9. AD7788/AD7789 Noise vs. V REF分销商库存信息:ANALOG-DEVICESAD7788ARMZ AD7788BRMZ AD7789BRMZAD7788ARMZ-REEL AD7788ARM-REEL AD7788BRMZ-REEL AD7789BRMZ-REEL AD7789BRM-REEL AD7788ARMAD7788BRM AD7789BRM。

AD7798,AD7799调试程序电路及pdf中文资料下载

AD7798,AD7799调试程序电路及pdf中文资料下载AD7798/AD7799均为适合高精度测量应用的低功耗、低噪声、完整模拟前端,内置一个低噪声16位/24位Σ-Δ型ADC,其中含有3个差分模拟输入,还集成了片内低噪声仪表放大器,因而可直接输入小信号。

当增益设置为64、更新速率为4.17 Hz时,AD7799的均方根（RMS）噪声为27 nV,AD7798的均方根（RMS）噪声为40 nV。

AD7798/A D7799片内特性包括一个低端电源开关、基准电压检测、可编程数字输出引脚、熔断电流控制和一个内部时钟振荡器。

输出数据速率可通过软件编程设置,可在4.17 Hz至470 Hz的范围内变化。

AD7798/AD 7799采用2.7 V至5.25 V电源供电,AD7798的典型功耗为300 μA,而AD7799的典型功耗为380 μA,两款器件均采用16引脚TSSOP封装。

AD7798,AD7799芯片的特性AD7798,AD7799芯片的概述AD7798,AD7799引脚图，采用16引脚TSSOP封装。

采用2.7V 至5.25V电源供电，AD7799的典型功耗为380μA。

AD7798,AD7799管脚功能介绍AD7798,AD7799 pdf中文资料下载：/f/AD7799_ad7798中文资料.pdf经历了四天的挣扎，AD7799终于调试成功啦说说我遇到的问题一、不判忙的状态下，读出数据是ffffff解决办法：设置CONFIGURATION REGISTER 的con5为1，然后检测STA TUS REGISTER 的NOREF位是否为1，如果为1说明内部基准低于0. 5v，也就是说没有基准。

我检测到NOREF位为1，用万用表检测ref +为2.5，不是虚焊。

检测来检测去没有问题，开始怀疑芯片，网上刚好也有说这个问题的，他说是芯片基准坏啦。

我没办法重新焊了一块板子，问题依旧。

没法硬着头皮看datasheet，最后发现还是设置的事。

常用AD芯片介绍共7页word资料

目前生产AD/DA的主要厂家有ADI、TI、BB、PHILIP、MOTOROLA等，武汉力源公司拥有多年从事电子产品的经验和雄厚的技术力量支持，已取得排名世界前列的模拟IC生产厂家ADI、TI 公司代理权，经营全系列适用各种领域/场合的AD/DA器件。

1. AD公司AD/DA器件AD公司生产的各种模数转换器(ADC)和数模转换器(DAC)(统称数据转换器)一直保持市场领导地位，包括高速、高精度数据转换器和目前流行的微转换器系统（MicroConvertersTM )。

1）带信号调理、1mW功耗、双通道16位AD转换器：AD7705AD7705是AD公司出品的适用于低频测量仪器的AD转换器。

它能将从传感器接收到的很弱的输入信号直接转换成串行数字信号输出，而无需外部仪表放大器。

采用Σ-Δ的ADC，实现16位无误码的良好性能，片内可编程放大器可设置输入信号增益。

通过片内控制寄存器调整内部数字滤波器的关闭时间和更新速率，可设置数字滤波器的第一个凹口。

在+3V电源和1MHz主时钟时， AD7705功耗仅是1mW。

AD7705是基于微控制器（MCU）、数字信号处理器（DSP）系统的理想电路，能够进一步节省成本、缩小体积、减小系统的复杂性。

应用于微处理器（MCU）、数字信号处理（DSP）系统，手持式仪器，分布式数据采集系统。

2）3V/5V CMOS信号调节AD转换器：AD7714AD7714是一个完整的用于低频测量应用场合的模拟前端，用于直接从传感器接收小信号并输出串行数字量。

它使用Σ-Δ转换技术实现高达24位精度的代码而不会丢失。

输入信号加至位于模拟调制器前端的专用可编程增益放大器。

调制器的输出经片内数字滤波器进行处理。

数字滤波器的第一次陷波通过片内控制寄存器来编程，此寄存器可以调节滤波的截止时间和建立时间。

AD7714有3个差分模拟输入（也可以是5个伪差分模拟输入）和一个差分基准输入。

单电源工作（+3V或+5V）。

4.1 ad7708

采样/保持器
A/D 转换器
计算机
控制逻辑
图3.2（b）多路同步采集分时输入结构
二、分散(分布式)采集式
分布式数据采集系
传感器调理电路采样/ 保持器采样/ 保持器
. . .
计算机
A/D转换器
传感器
. . .
调理电路
. . .
A/D转换器 A/D转换器
统的
典型结构
传感器
调理电路
采样/ 保持器
•微分线性度极好，不会有非单调性。因为积分
输出是连续的，因此，计数必然是依次进行的,
即从本质上说，不会发生丢码现象。
•积分电路为抑制噪声提供了有利条件。双积分
式ADC是测量输入电压在定时积分时间T1内的平
均值，对干扰有很强的抑制作用，尤其对正负波
形对称的干扰信号抑制效果更好。
(三) Δ-Σ型ADC
量是指电压而言的。在数字系统中，数字
量是离散的，一般用一个称为量子Q的基本单位来度量。
输出
3Q 2Q Q
输出
3Q 2Q Q Q 2Q 3Q
0
输入
0
Q
2Q （c）
3Q
输入
（a） e Q +Q/2 0 -Q/2
输入
（d）
0
（b）
输入
图3.15 量化特性及量化误差
输出
3Q 2Q Q 0 Q
输出
3Q 2Q Q
控制逻辑
图3.3 (a) 分布式单机数据采集结构
分布式数据采集系统的典型结构
上位机通信接口
数据采集站1 … …
数据采集站2 … …
数据采集站3
……
数据采集站N … …

AD7908BRUZ资料

8-Channel, 1 MSPS, 8-/10-/12-Bit ADCswith Sequencer in 20-Lead TSSOPAD7908/AD7918/AD7928 Rev. BInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, N orwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.FEATURESFast throughput rate: 1 MSPSSpecified for AV DD of 2.7 V to 5.25 VLow power6.0 mW max at 1 MSPS with 3 V supply13.5 mW max at 1 MSPS with 5 V supplyEight (single-ended) inputs with sequencerWide input bandwidthAD7928, 70 dB min SINAD at 50 kHz input frequency Flexible power/serial clock speed managementNo pipeline delaysHigh speed serial interface SPI®/QSPI™/MICROWIRE™/DSP compatibleShutdown mode: 0.5 μA max20-lead TSSOP packageGENERAL DESCRIPTIONThe AD7908/AD7918/AD7928 are, respectively, 8-bit, 10-bit, and 12-bit, high speed, low power, 8-channel, successive approximation ADCs. The parts operate from a single 2.7 V to 5.25 V power supply and feature throughput rates up to 1 MSPS. The parts contain a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 8 MHz.The conversion process and data acquisition are controlled using CS and the serial clock signal, allowing the device to easily interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and conversion is also initiated at this point. There are no pipeline delays associated with the part.The AD7908/AD7918/AD7928 use advanced design techniques to achieve very low power dissipation at maximum throughput rates. At maximum throughput rates, the AD7908/AD7918/AD7928 consume 2 mA maximum with 3 V supplies; with 5 V supplies, the current consumption is 2.7 mA maximum.Through the configuration of the control register, the analog input range for the part can be selected as 0 V to REF IN or 0 V to 2 × REF IN, with either straight binary or twos complement output coding. The AD7908/AD7918/AD7928 each feature eight single-ended analog inputs with a channel sequencer to allow a preprogrammed selection of channels to be converted sequentially. The conversion time for the AD7908/AD7918/AD7928 is determined by the SCLK frequency, which is also used as the master clock to control the conversion.FUNCTIONAL BLOCK DIAGRAM •••••••••••••REFV INV IN389-1Figure 1.PRODUCT HIGHLIGHTS1. High Throughput with Low Power Consumption. The AD7908/ AD7918/AD7928 offer up to 1 MSPS throughput rates. At the maximum throughput rate with 3 V supplies, the AD7908/AD7918/AD7928 dissipate just 6 mW of power maximum.2. Eight Single-Ended Inputs with a Channel Sequencer.A sequence of channels can be selected, through whichthe ADC cycles and converts on.3. Single-Supply Operation with V DRIVE Function. The AD7908/ AD7918/AD7928 operate from a single 2.7 V to 5.25 V supply. The V DRIVE function allows the serial interface to connect directly to either 3 V or 5 V processor systems independent of AV DD.4. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. The parts also feature various shutdown modes to maximize power efficiency at lower throughput rates. Current consumption is 0.5 μA max when in full shutdown.5. No Pipeline Delay. The parts feature a standard successive approximation ADC with accurate control of the sampling instant via a CS input and once off conversion control.AD7908/AD7918/AD7928Rev. B | Page 2 of 28TABLE OF CONTENTSFeatures..............................................................................................1 General Description.........................................................................1 Functional Block Diagram..............................................................1 Product Highlights...........................................................................1 Revision History...............................................................................2 Specifications.....................................................................................3 AD7908 Specifications.................................................................3 AD7918 Specifications.................................................................5 AD7928 Specifications.................................................................7 Timing Specifications..................................................................9 Absolute Maximum Ratings..........................................................10 ESD Caution................................................................................10 Pin Configuration and Function Descriptions...........................11 Terminology....................................................................................12 Typical Performance Characteristics...........................................13 Performance Curves. (13)Control Register..............................................................................15 Sequencer Operation.................................................................16 SHADOW Register....................................................................17 Circuit Information....................................................................18 Converter Operation..................................................................18 ADC Transfer Function.............................................................19 Handling Bipolar Input Signals................................................19 Typical Connection Diagram...................................................19 Modes of Operation...................................................................21 Power vs. Throughput Rate.......................................................23 Serial Interface............................................................................23 Microprocessor Interfacing.......................................................24 Application Hints.......................................................................27 Outline Dimensions.......................................................................28 Ordering Guide.. (28)REVISION HISTORY6/06—Rev. A to Rev. BUpdated Format..................................................................Universal Changes to Reference Section.......................................................21 9/03—Rev. 0 to Rev. AChanges to Figure 3........................................................................15 Changes to Reference section. (18)AD7908/AD7918/AD7928Rev. B | Page 3 of 28SPECIFICATIONSAD7908 SPECIFICATIONSAV DD = V DRIVE = 2.7 V to 5.25 V , REF IN = 2.5 V , f SCLK = 20 MHz, T A = T MIN to T MAX , unless otherwise noted. Table 1.ParameterB Version 1 Unit Test Conditions/Comments DYNAMIC PERFORMANCEf IN = 50 kHz sine wave, f SCLK = 20 MHz Signal-to-(Noise + Distortion) (SINAD)2 49 dB min Signal-to-Noise Ratio (SNR)249 dB min Total Harmonic Distortion (THD)2−66 dB max Peak Harmonic or Spurious Noise (SFDR)2−64 dB max Intermodulation Distortion (IMD)2 fa = 40.1 kHz, fb = 41.5 kHz Second-Order Terms −90 dB typ Third-Order Terms −90 dB typ Aperture Delay 10 ns typ Aperture Jitter50 ps typ Channel-to-Channel Isolation 2 −85 dB typ f IN = 400 kHz Full Power Bandwidth 8.2 MHz typ @ 3 dB1.6 MHz typ @ 0.1 dB DC ACCURACY 2 Resolution8 Bits Integral Nonlinearity ±0.2 LSB max Differential Nonlinearity ±0.2 LSB max Guaranteed no missed codes to 8 bits 0 V to REF IN Input Range Straight binary output coding Offset Error±0.5 LSB max Offset Error Match ±0.05 LSB max Gain Error±0.2 LSB max Gain Error Match±0.05 LSB max 0 V to 2 × REF IN Input Range −REF IN to +REF IN biased about REF IN withtwos complement output codingPositive Gain Error±0.2 LSB max Positive Gain Error Match ±0.05 LSB max Zero Code Error±0.5 LSB max Zero Code Error Match ±0.1 LSB max Negative Gain Error±0.2 LSB max Negative Gain Error Match ±0.05 LSB max ANALOG INPUTInput Voltage Ranges 0 to REF IN V RANGE bit set to 1 0 to 2 × REF IN V RANGE bit set to 0, AV DD /V DRIVE = 4.75 V to5.25 VDC Leakage Current ±1 μA max Input Capacitance 20 pF typ REFERENCE INPUT REF IN Input Voltage 2.5 V ±1% specified performance DC Leakage Current ±1 μA max REF IN Input Impedance 36 kΩ typ f SAMPLE = 1 MSPS LOGIC INPUTSInput High Voltage, V INH 0.7 × V DRIVE V min Input Low Voltage, V INL 0.3 × V DRIVE V max Input Current, I IN±1 μA max Typically 10 nA, V IN = 0 V or V DRIVE Input Capacitance, C IN 3 10 pF maxAD7908/AD7918/AD7928Parameter B Version1Unit Test Conditions/Comments LOGIC OUTPUTSOutput High Voltage, V OH V DRIVE − 0.2 V min I SOURCE = 200 μA, AV DD = 2.7 V to 5.25 V Output Low Voltage, V OL0.4 V max I SINK = 200 μAFloating-State Leakage Current ±1 μA maxFloating-State Output Capacitance310 pF maxOutput Coding Straight (natural) binary Coding bit set to 1Twos complement Coding bit set to 0 CONVERSION RATEConversion Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time 300 ns max Sine wave input300 ns max Full-scale step inputThroughput Rate 1 MSPS max See Serial Interface section POWER REQUIREMENTSAV DD 2.7/5.25 V min/maxV DRIVE 2.7/5.25 V min/maxI DD4Digital inputs = 0 V or V DRIVENormal Mode (Static) 600 μA typ AV DD = 2.7 V to 5.25 V, SCLK On or Off Normal Mode (Operational) 2.7 mA max AV DD = 4.75 V to 5.25 V, f SCLK = 20 MHz2 mA max AV DD = 2.7 V to 3.6 V, f SCLK = 20 MHzUsing Auto Shutdown Mode 960 μA typ f SAMPLE = 250 kSPS0.5 μA max (Static)Full Shutdown Mode 0.5 μA max SCLK on or off (20 nA typ)Power Dissipation4Normal Mode (Operational) 13.5 mW max AV DD = 5 V, f SCLK = 20 MHz6 mW max AV DD = 3 V, f SCLK = 20 MHzAuto Shutdown Mode (Static) 2.5 μW max AV DD = 5 V1.5 μW max AV DD = 3 VFull Shutdown Mode 2.5 μW max AV DD = 5 V1.5 μW max AV DD = 3 V1 Temperature ranges as follows: B version: −40°C to +85°C.2 See Terminology section.3 Sample tested @ 25°C to ensure compliance.4 See Power vs. Throughput Rate section.Rev. B | Page 4 of 28AD7908/AD7918/AD7928Rev. B | Page 5 of 28AD7918 SPECIFICATIONSAV DD = V DRIVE = 2.7 V to 5.25 V , REF IN = 2.5 V , f SCLK = 20 MHz, T A = T MIN to T MAX , unless otherwise noted. Table 2.Parameter B Version 1 Unit Test Conditions/Comments DYNAMIC PERFORMANCE f IN = 50 kHz sine wave, f SCLK = 20 MHz Signal-to-(Noise + Distortion) (SINAD)2 61 dB minSignal-to-Noise Ratio (SNR)261 dB minTotal Harmonic Distortion (THD)2−72 dB max Peak Harmonic or Spurious Noise (SFDR)2−74 dB maxIntermodulation Distortion (IMD)2fa = 40.1 kHz, fb = 41.5 kHz Second-Order Terms −90 dB typ Third-Order Terms −90 dB typ Aperture Delay 10 ns typ Aperture Jitter 50 ps typ Channel-to-Channel Isolation 2 −85 dB typ f IN = 400 kHz Full Power Bandwidth 8.2 MHz typ @ 3 dB 1.6 MHz typ @ 0.1 dB DC ACCURACY 2 Resolution 10 Bits Integral Nonlinearity ±0.5 LSB max Differential Nonlinearity ±0.5 LSB max Guaranteed no missed codes to 10 bits 0 V to REF IN Input Range Straight binary output coding Offset Error ±2 LSB max Offset Error Match ±0.2 LSB max Gain Error ±0.5 LSB max Gain Error Match ±0.2 LSB max 0 V to 2 × REF IN Input Range −REF IN to +REF IN biased about REF IN with twoscomplement output codingPositive Gain Error ±0.5 LSB max Positive Gain Error Match ±0.2 LSB max Zero Code Error ±2 LSB max Zero Code Error Match ±0.2 LSB max Negative Gain Error ±0.5 LSB max Negative Gain Error Match ±0.2 LSB max ANALOG INPUT Input Voltage Ranges 0 to REF IN V RANGE bit set to 1 0 to 2 × REF IN V RANGE bit set to 0, AV DD /V DRIVE = 4.75 V to 5.25 V DC Leakage Current ±1 μA max Input Capacitance 20 pF typ REFERENCE INPUT REF IN Input Voltage 2.5 V ±1% specified performance DC Leakage Current ±1 μA max REF IN Input Impedance 36 kΩ typ f SAMPLE = 1 MSPS LOGIC INPUTS Input High Voltage, V INH 0.7 × V DRIVE V min Input Low Voltage, V INL 0.3 × V DRIVE V max Input Current, I IN ±1 μA max Typically 10 nA, V IN = 0 V or V DRIVE Input Capacitance, C IN 3 10 pF maxAD7908/AD7918/AD7928Rev. B | Page 6 of 28Parameter B Version 1 Unit Test Conditions/Comments LOGIC OUTPUTS Output High Voltage, V OH V DRIVE − 0.2 V min I SOURCE = 200 μA, AV DD = 2.7 V to 5.25 V Output Low Voltage, V OL 0.4 V max I SINK = 200 μA Floating-State Leakage Current ±1 μA max Floating-State Output Capacitance 3 10 pF max Output Coding Straight (natural) binary Coding bit set to 1 Twos complement Coding bit set to 0 CONVERSION RATE Conversion Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time 300 ns max Sine wave input 300 ns max Full-scale step input Throughput Rate 1 MSPS max See Serial Interface section POWER REQUIREMENTS AV DD 2.7/5.25 V min/max V DRIVE 2.7/5.25 V min/max I DD 4 Digital inputs = 0 V or V DRIVENormal Mode (Static) 600 μA typ AV DD = 2.7 V to 5.25 V, SCLK on or off Normal Mode (Operational) 2.7 mA max AV DD = 4.75 V to 5.25 V, f SCLK = 20 MHz 2 mA max AV DD = 2.7 V to 3.6 V, f SCLK = 20 MHz Using Auto Shutdown Mode 960 μA typ f SAMPLE = 250 kSPS 0.5 μA max (Static) Full Shutdown Mode 0.5 μA max SCLK on or off (20 nA typ)Power Dissipation 4Normal Mode (Operational) 13.5 mW max AV DD = 5 V, f SCLK = 20 MHz 6 mW max AV DD = 3 V, f SCLK = 20 MHz Auto Shutdown Mode (Static) 2.5 μW max AV DD = 5 V 1.5 μW max AV DD = 3 V Full Shutdown Mode 2.5 μW max AV DD = 5 V 1.5 μW max AV DD = 3 V1 Temperature ranges as follows: B version: –40°C to +85°C. 2See Terminology section. 3Sample tested @ 25°C to ensure compliance. 4See Power vs. Throughput Rate section.AD7908/AD7918/AD7928AD7928 SPECIFICATIONSA VDD = V DRIVE = 2.7 V to 5.25 V, REF IN = 2.5 V, f SCLK = 20 MHz, T A = T MIN to T MAX, unless otherwise noted.Table 3.Parameter B Version1Unit Test Conditions/CommentsDYNAMIC PERFORMANCE f IN = 50 kHz sine wave, f SCLK = 20 MHzSignal-to-(Noise + Distortion) (SINAD)270 dB min @ 5 V69 dB min @ 3 V typically 70 dBSignal-to-Noise Ratio (SNR)270 dB minTotal Harmonic Distortion (THD)2−77 dB max @ 5 V typically −84 dB−73 dB max @ 3 V typically −77 dBPeak Harmonic or Spurious Noise −78 dB max @ 5 V typically −86 dB(SFDR)2−76 dB max @ 3 V typically −80 dBIntermodulation Distortion (IMD)2fa = 40.1 kHz, fb = 41.5 kHzSecond-Order Terms −90 dB typThird-Order Terms −90 dB typAperture Delay 10 ns typAperture Jitter 50 ps typChannel-to-Channel Isolation2−85 dB typ f IN = 400 kHzFull Power Bandwidth 8.2 MHz typ @ 3 dB1.6 MHz typ @ 0.1 dBDC ACCURACY2Resolution 12 BitsIntegral Nonlinearity ±1 LSB maxDifferential Nonlinearity −0.9/+1.5 LSB max Guaranteed no missed codes to 12 bits0 V to REF IN Input Range Straight binary output codingOffset Error ±8 LSB max Typically ±0.5 LSBOffset Error Match ±0.5 LSB maxGain Error ±1.5 LSB maxGain Error Match ±0.5 LSB max0 V to 2 × REF IN Input Range −REF IN to +REF IN biased about REF IN with twoscomplement output coding Positive Gain Error ±1.5 LSB maxPositive Gain Error Match ±0.5 LSB maxZero Code Error ±8 LSB max Typically ±0.8 LSBZero Code Error Match ±0.5 LSB maxNegative Gain Error ±1 LSB maxNegative Gain Error Match ±0.5 LSB maxANALOG INPUTInput Voltage Ranges 0 to REF IN V RANGE bit set to 10 to 2 × REF IN V RANGE bit set to 0, AV DD/V DRIVE = 4.75 V to 5.25 VDC Leakage Current ±1 μA maxInput Capacitance 20 pF typREFERENCE INPUTREF IN Input Voltage 2.5 V ±1% specified performanceDC Leakage Current ±1 μA maxREF IN Input Impedance 36 kΩ typ f SAMPLE = 1 MSPSLOGIC INPUTSInput High Voltage, V INH0.7 × V DRIVE V minInput Low Voltage, V INL0.3 × V DRIVE V maxInput Current, I IN±1 μA max Typically 10 nA, V IN = 0 V or V DRIVEInput Capacitance, C IN310 pF maxRev. B | Page 7 of 28AD7908/AD7918/AD7928Parameter B Version1Unit Test Conditions/Comments LOGIC OUTPUTSOutput High Voltage, V OH V DRIVE − 0.2 V min I SOURCE = 200 μA, AV DD = 2.7 V to 5.25 V Output Low Voltage, V OL0.4 V max I SINK = 200 μAFloating-State Leakage Current ±1 μA maxFloating-State Output Capacitance310 pF maxOutput Coding Straight (natural) binary Coding bit set to 1Twos complement Coding bit set to 0 CONVERSION RATEConversion Time 800 ns max 16 SCLK cycles with SCLK at 20 MHz Track-and-Hold Acquisition Time 300 ns max Sine wave input300 ns max Full-scale step inputThroughput Rate 1 MSPS max See Serial Interface section POWER REQUIREMENTSAV DD 2.7/5.25 V min/maxV DRIVE 2.7/5.25 V min/maxI DD4Digital inputs = 0 V or V DRIVENormal Mode (Static) 600 μA typ AV DD = 2.7 V to 5.25 V, SCLK on or off Normal Mode (Operational) 2.7 mA max AV DD = 4.75 V to 5.25 V, f SCLK = 20 MHz2 mA max AV DD = 2.7 V to 3.6 V, f SCLK = 20 MHzUsing Auto Shutdown Mode 960 μA typ f SAMPLE = 250 kSPS0.5 μA max (Static)Full Shutdown Mode 0.5 μA max SCLK on or off (20 nA typ)Power Dissipation4Normal Mode (Operational) 13.5 mW max AV DD = 5 V, f SCLK = 20 MHz6 mW max AV DD = 3 V, f SCLK = 20 MHzAuto Shutdown Mode (Static) 2.5 μW max AV DD = 5 V1.5 μW max AV DD = 3 VFull Shutdown Mode 2.5 μW max AV DD = 5 V1.5 μW max AV DD = 3 V1 Temperature ranges as follows: B Version: −40°C to +85°C.2 See Terminology section.3 Sample tested @ 25°C to ensure compliance.4 See Power vs. Throughput Rate section.Rev. B | Page 8 of 28AD7908/AD7918/AD7928Rev. B | Page 9 of 28TIMING SPECIFICATIONSAV DD = 2.7 V to 5.25 V , V DRIVE ≤ AV DD , REF IN = 2.5 V , T A = T MIN to T MAX , unless otherwise noted.11Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of AV DD ) and timed from a voltage level of 1.6 V. See Figure 2. The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V. 2Mark/space ratio for the SCLK input is 40/60 to 60/40. 3Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × V DRIVE . 4t 8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.TO OUTPUTPIN1.6V03089-002Figure 2. Load Circuit for Digital Output Timing SpecificationsAD7908/AD7918/AD7928Rev. B | Page 10 of 28ABSOLUTE MAXIMUM RATINGST A = 25°C, unless otherwise noted. Table 5.Parameter Rating AV DD to AGND −0.3 V to +7 VV DRIVE to AGND −0.3 V to AV DD + 0.3 VAnalog Input Voltage to AGND −0.3 V to AV DD + 0.3 VDigital Input Voltage to AGND −0.3 V to +7 VDigital Output Voltage to AGND −0.3 V to AV DD + 0.3 VREF IN to AGND −0.3 V to AV DD + 0.3 VInput Current to Any Pin ExceptSupplies 1±10 mA Operating Temperature Range Commercial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TSSOP Package, Power Dissipation 450 mW θJA Thermal Impedance 143°C/W (TSSOP) θJC Thermal Impedance 45°C/W (TSSOP) Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°CESD 2kV1Transient currents of up to 100 mA do not cause SCR latch-up.Stresses above those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. This is a stressrating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.ESD CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.PIN CONFIGURATION AND FUNCTION DESCRIPTIONSSCLK DIN CS AGND AGND AV DD AV DD DRIVE REF IN V IN 7V IN 6IN 0IN 1IN 2IN 3IN 4IN 503089-003Figure 3. Pin ConfigurationTERMINOLOGYIntegral NonlinearityThis is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a position 1 LSB below the first code transition, and full scale, a position 1 LSB above the last code transition.Differential NonlinearityThis is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.Offset ErrorThis is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, that is, AGND + 1 LSB.Offset Error MatchThis is the difference in offset error between any two channels. Gain ErrorThis is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (that is, REF IN – 1 LSB) after the offset error has been adjusted out.Gain Error MatchThis is the difference in gain error between any two channels. Zero Code ErrorThis applies when using the twos complement output coding option, in particular to the 2 × REF IN input range with −REF IN to +REF IN biased about the REF IN point. It is the deviation of the midscale transition (all 0s to all 1s) from the ideal V IN voltage, that is, REF IN − 1 LSB.Zero Code Error MatchThis is the difference in zero code error between any two channels.Positive Gain ErrorThis applies when using the twos complement output coding option, in particular to the 2 × REF IN input range with −REF IN to +REF IN biased about the REF IN point. It is the deviation of the last code transition (011. . .110) to (011 . . . 111) from the ideal (that is, +REF IN − 1 LSB) after the zero code error has been adjusted out.Positive Gain Error MatchThis is the difference in positive gain error between any two channels.Negative Gain ErrorThis applies when using the twos complement output coding option, in particular to the 2 × REF IN input range with −REF IN to +REF IN biased about the REF IN point. It is the deviation of the first code transition (100 . . . 000) to (100 . . . 001) from the ideal (that is, −REF IN + 1 LSB) after the zero code error has been adjusted out. Negative Gain Error MatchThis is the difference in negative gain error between any two channels.Channel-to-Channel IsolationChannel-to-channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a full-scale 400 kHz sine wave signal to all seven nonselected input channels and determining how much that signal is attenuated in the selected channel with a 50 kHz signal. The figure is given worst case across all eight channels for the AD7908/AD7918/ AD7928.Power Supply Rejection (PSR)Variations in power supply affect the full-scale transition, but not the converter’s linearity. Power supply rejection is the maximum change in full-scale transition point due to a change in power-supply voltage from the nominal value (see the Performance Curves section).Track-and-Hold Acquisition TimeThe track-and-hold amplifier returns to track mode at the end of conversion. Track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1 LSB, after the end of conversion. Signal-to-(Noise + Distortion) RatioThis is the measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (f S/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given bySignal-to-(Noise + Distortion) = (6.02N + 1.76)dBThus for a 12-bit converter, this is 74 dB; for a 10-bit converter, this is 62 dB; and for an 8-bit converter, this is 50 dB.Total Harmonic DistortionTotal harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7908/AD7918/AD7928, it is defined as:()12625242322log20VVVVVVdBTHD++++=where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics.TYPICAL PERFORMANCE CHARACTERISTICSPERFORMANCE CURVESFigure 4 shows a typical FFT plot for the AD7928 at 1 MSPS sample rate and 50 kHz input frequency. Figure 5 shows the signal-to-(noise + distortion) ratio performance vs. inputfrequency for various supply voltages while sampling at 1 MSPS with an SCLK of 20 MHz.Figure 6 shows the power supply rejection ratio vs. supply ripple frequency for the AD7928 when no decoupling is used. The power supply rejection ratio is defined as the ratio of the power in the ADC output at full-scale frequency f, to the power of a 200 mV p-p sine wave applied to the ADC AV DD supply of frequency f SPSRR (dB) = 10 log(Pf /Pfs )Pf is equal to the power at frequency f in ADC output; Pf S is equal to the power at frequency f S coupled onto the ADC AV DD supply. Here a 200 mV p-p sine wave is coupled onto the AV DD supply.050100150200250300350400450500S N R (d B )FREQUENCY (kHz)–10–30–50–70–90–1104096 POINT FFT AV DD = 5Vf SAMPLE = 1MSPS f IN = 50kHzSINAD = 71.147dB THD = –87.229dB SFDR = –90.744dB03089-004Figure 4. AD7928 Dynamic Performance at 1 MSPS7570656055S I N A D (d B )INPUT FREQUENCY (kHz)AV = V = 5.25V 03089-005Figure 5. AD7928 SINAD vs. Analog Input Frequency forVarious Supply Voltages at 1 MSPSFigure 7 shows a graph of total harmonic distortion vs. analog input frequency for various supply voltages, and Figure 8 shows a graph of total harmonic distortion vs. analog input frequency for various source impedances. See the Analog Input section. Figure 9 and Figure 10 show typical INL and DNL plots for the AD7928.P S R R (d B )SUPPLY RIPPLE FREQUENCY (kHz)–40–60–80–90–20–50–700–10–3003089-006Figure 6. AD7928 PSRR vs. Supply Ripple Frequency–50–65–75–85–90–60–70–80–55T H D (d B )INPUT FREQUENCY (kHz)03089-007Figure 7. AD7928 THD vs. Analog Input Frequency forVarious Supply Voltages at 1 MSPS。

半导体传感器AD7686BRMZ中文规格书

Data SheetAD7688 CHAIN MODE, NO BUSY INDICATORThis mode can be used to daisy-chain multiple AD7688s on a3-wire serial interface. This feature is useful for reducingcomponent count and wiring connections, for example, inisolated multiconverter applications or for systems with alimited interfacing capacity. Data readback is analogous to clocking a shift register.A connection diagram example using two AD7688s is shown in Figure 42 and the corresponding timing is given in Figure 43.When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion, selects the chainmode, and disables the BUSY indicator. In this mode, CNV isheld high during the conversion phase and the subsequent data readback. When the conversion is complete, the MSB is output onto SDO and the AD7688 enters the acquisition phase and powers down. The remaining data bits stored in the internal shift register are then clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 × N clocks are required to readback the N ADCs. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate and, consequently more AD7688s in the chain, provided the digital host has an acceptable hold time. The maximum conversion rate may be reduced due to the total readback time. For instance, with a 3 ns digital host set-up time and 3 V interface, up to four AD7688s running at a conversion rate of 360 kSPS can be daisy-chained on a 3-wire port.02973-041Figure 42. Chain Mode, No BUSY Indicator Connection DiagramSDO ASDI A = 0t 02973-042Figure 43. Chain Mode, No BUSY Indicator Serial Interface TimingRev. B | Page 21 of 28AD7688Data Sheet CHAIN MODE WITH BUSY INDICATORThis mode can also be used to daisy-chain multiple AD7688s on a 3-wire serial interface while providing a BUSY indicator. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverterapplications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register.A connection diagram example using three AD7688s is shown in Figure 44 and the corresponding timing is given in Figure 45. When SDI and CNV are low, SDO is driven low. With SCK high, a rising edge on CNV initiates a conversion, selects the chain mode, and enables the BUSY indicator feature. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When all ADCs in the chain have completed their conversions, the nearend ADC (ADC C in Figure 44) SDO is driven high. This transition on SDO can be used as a BUSY indicator to trigger the data readback controlled by the digital host. The AD7688 then enters the acquisition phase and powers down. The data bits stored in the internal shift register are then clocked out, MSB first, by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 × N + 1 clocks are required to readback the N ADCs. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate and consequently more AD7688s in the chain, provided the digital host has an acceptable hold time. For instance, with a 3 ns digital host setup time and 3 V interface, up to four AD7688s running at a conversion rate of 360 kSPS can be daisy-chained to a single 3-wire port.02973-043Figure 44. Chain Mode with BUSY Indicator Connection DiagramSDO ASDO B t 02973-044Figure 45. Chain Mode with BUSY Indicator Serial Interface TimingRev. B | Page 22 of 28。

半导体传感器AD7190BRUZ中文规格书

ADuM1400/ADuM1401/ADuM1402Data Sheet Rev. L | Page 22 of 31PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONSV DD1*GND 1V IA V IB V DD2GND 2*V OA V OB V IC V OC V ID V OD NC V E2*GND 1GND 2*NC = NO CONNECT03786-005*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND 1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND 2 IS RECOMMENDED.Figure 5. ADuM1400 Pin Configuration Table 16. ADuM1400 Pin Function DescriptionsPin No.Mnemonic Description 1V DD1 Supply Voltage for Isolator Side 1. 2GND 1Ground 1. Ground reference for Isolator Side 1. 3V IA Logic Input A. 4V IB Logic Input B. 5V IC Logic Input C. 6V ID Logic Input D. 7NC No Connect. 8GND 1 Ground 1. Ground reference for Isolator Side 1. 9GND 2 Ground 2. Ground reference for Isolator Side 2. 10V E2 Output Enable 2. Active high logic input. V OA , V OB , V OC , and V OD outputs are enabled when V E2 is high or disconnected. V OA , V OB , V OC , and V OD outputs are disabled when V E2 is low. In noisy environments, connecting V E2 to an external logic high or low is recommended. 11V OD Logic Output D. 12V OC Logic Output C. 13V OB Logic Output B. 14V OA Logic Output A. 15GND 2Ground 2. Ground reference for Isolator Side 2. 16 V DD2 Supply Voltage for Isolator Side 2.Data SheetADuM1400/ADuM1401/ADuM1402 Rev. L | Page 23 of 31V DD1*GND 1V IA V IB V DD2GND 2*V OA V OB V IC V OC V OD V ID V E1V E2*GND 1GND 2*03786-006*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND 1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND 2 IS RECOMMENDED.Figure 6. ADuM1401 Pin Configuration Table 17. ADuM1401 Pin Function Descriptions Pin No.Mnemonic Description 1V DD1 Supply Voltage for Isolator Side 1. 2GND 1Ground 1. Ground reference for Isolator Side 1. 3V IA Logic Input A. 4V IB Logic Input B. 5V IC Logic Input C. 6V OD Logic Output D. 7V E1 Output Enable 1. Active high logic input. V OD output is enabled when V E1 is high or disconnected. V OD is disabled when V E1 is low. In noisy environments, connecting V E1 to an external logic high or low is recommended. 8GND 1 Ground 1. Ground reference for Isolator Side 1. 9GND 2 Ground 2. Ground reference for Isolator Side 2. 10V E2 Output Enable 2. Active high logic input. V OA , V OB , and V OC outputs are enabled when V E2 is high or disconnected. V OA , V OB , and V OC outputs are disabled when V E2 is low. In noisy environments, connecting V E2 to an external logic high or low is recommended. 11V ID Logic Input D. 12V OC Logic Output C. 13V OB Logic Output B. 14V OA Logic Output A. 15GND 2Ground 2. Ground reference for Isolator Side 2. 16 V DD2 Supply Voltage for Isolator Side 2.。

AD7799中文资料

AIN3-/P2 AIN1+ AIN1AIN2+ AIN2REFIN+
REFINPSW GND AVDD DVDD DOUT/RDY
DIN
描述串行时钟输入。这是数据传输和 ADC 的串行时钟输入。该时钟的施密特触发输入，使界面适合光电隔离的应用。片选输入。对 AD7799 的操作在 CS 低电平时有效，模拟输入/数字输出。另外该引脚还可以作为一般用途上的输出参照位同上模拟输入。模拟输入。模拟输入模拟输入同相参考输入。外部参考电压可应用在这两脚之间，参考值是 2.5V，但对于不同的应用可以在 0.1V---AVDD 之间反向参考输入。参考值在 GND 到 AVDD-0.1V 之间
0.3 V −0.3 V to DVDD +
AIN/数字输入电流
0.3 V 10 mA
操作温度范围
−40°C to +85°C
保存温度范围
−65°C to +150°
最高结温
C 150°C
TSSOP θJA Thermal Impedance 128°C/W
θJC Thermal Impedance 14°C/W
500 Hz
11.33 9.44 3.132 1.773 1.107 0.5
0.413 0.374
AD7799在2.5V参考电源下其典型分辨率（BIT）与增益和输出更新速率之间的关
系
更新速率Gain=1 Gain=2 Gain=3 Gain=4 Gain=5 Gain=6 Gain=7 Gain=8
·内设自校准电路;
·带有 SPI 数据接口，可以方便地与 DPS 或者 MCU 连接;
·50 H z 和 06Hz 同步陷波，消除 05Hz 和 06Hz 电源干扰;

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3-Channel, Low Noise, Low Power,16-/24-Bit, Σ-Δ ADC with On-Chip In-AmpAD7798/AD7799 Rev. AInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, M A 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved.FEATURESRMS noise:27 nV at 4.17 Hz (AD7799)65 nV at 16.7 Hz (AD7799)40 nV at 4.17 Hz (AD7798)85 nV at 16.7 Hz (AD7798)Current: 380 μA typicalPower-down: 1 μA maximumLow noise, programmable gain, instrumentation amp Update rate: 4.17 Hz to 470 Hz3 differential inputsInternal clock oscillatorSimultaneous 50 Hz/60 Hz rejectionReference detectLow-side power switchProgrammable digital outputsBurnout currentsPower supply: 2.7 V to 5.25 V–40°C to +105°C temperature rangeIndependent interface power supply16-lead TSSOP packageINTERFACE3-wire serialSPI®, QSPI™, MICROWIRE™, and DSP compatible Schmitt trigger on SCLKAPPLICATIONSWeigh scalesPressure measurementStrain gauge transducersGas analysisIndustrial process controlInstrumentationPortable instrumentationBlood analysisSmart transmittersLiquid/gas chromotography6-digit DVMFUNCTIONAL BLOCK DIAGRAMAIN2(+)AIN2(–)AIN3(+)/P1AIN1(+)AIN1(–)AIN3(–)/P2PSW4856-1Figure 1.GENERAL DESCRIPTIONThe AD7798/AD7799 are low power, low noise, complete analog front ends for high precision measurement applications. The AD7798/AD7799 contains a low noise, 16-/24-bit ∑-ΔADC with three differential analog inputs. The on-chip, low noise instrumentation amplifier means that signals of small amplitude can be interfaced directly to the ADC. With a gain setting of 64, the rms noise is 27 nV for the AD7799 and 40 nV for the AD7798 when the update rate equals 4.17 Hz.On-chip features include a low-side power switch, reference detect, programmable digital output pins, burnout currents,and an internal clock oscillator. The output data rate from the part is software-programmable and can be varied from 4.17 Hz to 470 Hz.The part operates with a power supply from 2.7 V to 5.25 V. The AD7798 consumes a current of 300 μA typical, whereas the AD7799 consumes 380 μA typical. Both devices are housed in a 16-lead TSSOP package.AD7798/AD7799Rev. A | Page 2 of 28TABLE OF CONTENTSFeatures..............................................................................................1 Interface.............................................................................................1 Applications.......................................................................................1 Functional Block Diagram..............................................................1 General Description.........................................................................1 Revision History...............................................................................2 Specifications.....................................................................................3 Timing Characteristics.....................................................................6 Absolute Maximum Ratings............................................................8 ESD Caution..................................................................................8 Pin Configuration and Function Descriptions.............................9 Output Noise and Resolution Specifications..............................10 AD7798........................................................................................10 AD7799........................................................................................11 Typical Performance Characteristics...........................................12 On-Chip Registers..........................................................................13 Communication Register..........................................................13 Status Register.............................................................................14 Mode Register.............................................................................14 Configuration Register..............................................................16 Data Register...............................................................................17 ID Register...................................................................................17 IO Register...................................................................................17 Offset Register............................................................................17 Full-Scale Register......................................................................17 ADC Circuit Information..............................................................18 Overview.....................................................................................18 Digital Interface..........................................................................19 Circuit Description.........................................................................22 Analog Input Channel...............................................................22 Instrumentation Amplifier........................................................22 Bipolar/Unipolar Configuration..............................................22 Data Output Coding..................................................................23 Burnout Currents.......................................................................23 Reference.....................................................................................23 Reference Detect.........................................................................23 Reset.............................................................................................23 AV DD Monitor.............................................................................24 Calibration...................................................................................24 Grounding and Layout..............................................................25 Applications Information..............................................................26 Weigh Scales................................................................................26 Outline Dimensions.......................................................................27 Ordering Guide.. (27)REVISION HISTORY3/07—Rev. 0 to Rev. AUpdated Format..................................................................Universal Changes to Specifications................................................................3 Changes to Table 5 and Table 6.....................................................10 Changes to Table 7 and Table 8.....................................................11 Changes to Table 14........................................................................15 Changes to Ordering Guide..........................................................27 1/05—Revision 0: Initial VersionAD7798/AD7799SPECIFICATIONSAV DD = 2.7 V to 5.25 V; DV DD = 2.7 V to 5.25 V; GND = 0 V; REFIN(+) = AV DD; REFIN(−) = 0 V. All specifications T MIN to T MAX, unless otherwise noted.Table 1.Parameter AD7798B/AD7799B1Unit Test Conditions/CommentsADC CHANNELOutput Update Rate 4.17 − 470 Hz nomNo Missing Codes224 Bits min AD7799: f ADC < 242 Hz16 Bits min AD7798Resolution See Table 5 to Table 8Output Noise and Update Rates See Table 5 to Table 8Integral Nonlinearity ±15 ppm of FSR maxOffset Error3±1 μV typOffset Error Drift vs. Temperature4±10 nV/°C typFull-Scale Error3, 5±10 μV typGain Drift vs. Temperature4±1 ppm/°C typPower Supply Rejection 100 dB min AIN = 1 V/gain, gain ≥ 4ANALOG INPUTSDifferential Input Voltage Ranges ±V REF/gain V nom V REF = REFIN(+) – REFIN(–), gain = 1 to 128 Absolute AIN Voltage Limits2Unbuffered Mode GND − 30 mV V min Gain = 1 or 2AV DD + 30 mV V maxBuffered Mode GND + 100 mV V min Gain = 1 or 2AV DD – 100 mV V maxIn-Amp Active GND + 300 mV V min Gain = 4 to 128AV DD − 1.1 V maxCommon-Mode Voltage, V CM0.5 V min V CM = (AIN(+) + AIN(−))/2, gain = 4 to 128Analog Input CurrentBuffered Mode or In-Amp ActiveAverage Input Current2±1 nA max Gain = 1 or 2, update rate < 100 Hz±250 pA max Gain = 4 to 128, update rate < 100 Hz±1 nA max AIN3(+)/AIN3(−), update rate < 100 Hz Average Input Current Drift ±2 pA/°C typUnbuffered Mode Gain = 1 or 2Average Input Current ±400 nA/V typ Input current varies with input voltageAverage Input Current Drift ±50 pA/V/°C typNormal Mode Rejection2@ 50 Hz, 60 Hz 65 dB min 80 dB typ, 50 ± 1 Hz, 60 ± 1 Hz (FS[3:0] = 1010)6 @ 50 Hz 80 dB min 90 dB typ, 50 ± 1 Hz (FS[3:0] = 1001)6@ 60 Hz 90 dB min 100 dB typ, 60 ± 1 Hz (FS[3:0] = 1000)6Common-Mode Rejection@ DC 100 dB min AIN = 1 V/gain, gain ≥ 4@ 50 Hz, 60 Hz2100 dB min 50 ± 1 Hz, 60 ± 1 Hz (FS[3:0] = 1010)6@ 50 Hz, 60 Hz2100 dB min 50 ± 1 Hz (FS[3:0] = 10016), 60 ± 1 Hz(FS[3:0] = 10006)Rev. A | Page 3 of 28AD7798/AD7799Rev. A | Page 4 of 28AD7798/AD7799Rev. A | Page 5 of 28ParameterAD7798B/AD7799B 1Unit Test Conditions/Comments SYSTEM CALIBRATION 2Full-Scale Calibration Limit1.05 × FSV maxFS = Full-scale analog input. When V REF = AV DD , the differential input must be limited to (0.9 × V REF /gain) if the in-amp is active.Zero-Scale Calibration Limit −1.05 × FS V min Input Span 0.8 × FS V min 2.1 × FS V max POWER REQUIREMENTS 7 Power Supply Voltage AV DD – GND 2.7/5.25 V min/max DV DD – GND 2.7/5.25 V min/max Power Supply Currents I DD Current 140 μA max Unbuffered mode, 110 μA typ @ AV DD = 3 V,125 μA typ @ AV DD = 5 V180 μA max Buffered mode, gain = 1 or 2, 130 μA typ @ AV DD = 3 V,165 μA typ @ AV DD = 5 V400 μA max AD7798: gain = 4 to 128, 300 μA typ @ AV DD = 3 V,350 μA typ @ AV DD = 5 V500 μA max AD7799: gain = 4 to 128, 380 μA typ @ AV DD = 3 V,440 μA typ @ AV DD = 5 VI DD (Power-Down Mode) 1 μA max1Temperature range is –40°C to +105°C. At the 19.6 Hz and 39.2 Hz update rates, the INL, power supply rejection (PSR), common-mode rejection (CMR), and normal mode rejection (NMR) do not meet the data sheet specification if the voltage on the AIN(+) or AIN(−) pins exceeds AV DD − 1.6 V typically. When this voltage isexceeded, the INL, for example, is reduced to 18 ppm of FS typically and the PSR is reduced to 69 dB typically. Therefore, for guaranteed performance at these update rates, the absolute voltage on the analog input pins needs to be below AV DD − 1.6 V. 2Specification is not production tested, but is supported by characterization data at initial product release. 3Following a calibration, this error is in the order of the noise for the programmed gain and update rate selected. 4Recalibration at any temperature removes these errors. 5Full-scale error applies to both positive and negative full-scale and applies at the factory calibration conditions (AV DD = 4 V, gain = 1, T A = 25°C). 6FS[3:0] are the four bits used in the mode register to select the output word rate. 7Digital inputs equal to DV DD or GND.AD7798/AD7799Rev. A | Page 6 of 28TIMING CHARACTERISTICSAV DD = 2.7 V to 5.25 V , DV DD = 2.7 V to 5.25 V , GND = 0 V , Input Logic 0 = 0 V , Input Logic 1 = DV DD , unless otherwise noted.1 Sample tested during initial release to ensure compliance. All input signals are specified with t R = t F = 5 ns (10% to 90% of DV DD ) and timed from a voltage level of 1.6 V. 2See Figure 3 and Figure 4. 3These times are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the V OL or V OH limits. 4SCLK active edge is the falling edge of SCLK. 5These times are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured time is thenextrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 6 RDY returns high after a read of the ADC. In single-conversion mode and continuous-conversion mode, data can be reread, if required, while RDY is high, but care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once.DD = 5V,DD = 3V)DD = 5V,DD = 3V)1.6VTO OUTPUTPIN04856-002Figure 2. Load Circuit for Timing CharacterizationAD7798/AD7799Rev. A | Page 7 of 28048CS (I)I = INPUT, O = OUTPUTFigure 3. Read Cycle Timing Diagram04856I = INPUT, O = OUTPUTCS (I)SCLK (I)DIN (I)Figure 4. Write Cycle Timing DiagramAD7798/AD7799Rev. A | Page 8 of 28ABSOLUTE MAXIMUM RATINGST A = 25°C, unless otherwise noted. Table 3.Parameter RatingAV DD to GND −0.3 V to +7 V DV DD to GND−0.3 V to +7 VAnalog Input Voltage to GND −0.3 V to AV DD + 0.3 V Reference Input Voltage to GND −0.3 V to AV DD + 0.3 V Digital Input Voltage to GND −0.3 V to DV DD + 0.3 V Digital Output Voltage to GND −0.3 V to DV DD + 0.3 V AIN/Digital Input Current10 mAOperating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C TSSOPθJA Thermal Impedance 128°C/W θJC Thermal Impedance 14°C/W Lead Temperature, SolderingVapor Phase (60 sec) 215°C Infrared (15 sec)220°CStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.ESD CAUTIONAD7798/AD7799Rev. A | Page 9 of 28PIN CONFIGURATION AND FUNCTION DESCRIPTIONSCSAIN3(+)/P1AIN3(–)/P2AIN2(+)AIN1(–)AIN1(+)SCLK DOUT/RDY DV DD AV DD REFIN(–)AIN2(–)REFIN(+)PSW GND DIN 04856-005Figure 5. Pin ConfigurationAD7798/AD7799Rev. A | Page 10 of 28OUTPUT NOISE AND RESOLUTION SPECIFICATIONSAD7798Table 5 shows the AD7798 output rms noise for some update rates and gain settings. The numbers given are for the bipolar input range with a 2.5 V reference. These numbers are typical and are generated with a differential input voltage of 0 V . Table 6 shows the effective resolution, and the output peak-to-peak resolution is shown in parentheses. It is important to note thatthe effective resolution is calculated using the rms noise, whereas the peak-to-peak resolution is based on the peak-to-peak noise. The peak-to-peak resolution represents the resolution for which there is no code flicker. These numbers are typical and are rounded to the nearest LSB.Table 5. Output RMS Noise (μV) vs. Gain and Output Update Rate for the AD7798 Using a 2.5 V ReferenceUpdate Rate Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 4.17 Hz 0.64 0.6 0.29 0.22 0.1 0.065 0.039 0.041 8.33 Hz 1.04 0.96 0.38 0.26 0.13 0.078 0.057 0.055 16.7 Hz 1.55 1.45 0.54 0.36 0.18 0.11 0.087 0.086 33.2 Hz 2.3 2.13 0.74 0.5 0.23 0.17 0.124 0.118 62 Hz 2.95 2.85 0.92 0.58 0.29 0.2 0.153 0.144 123 Hz 4.89 4.74 1.49 1 0.48 0.32 0.265 0.283 242 Hz 11.76 9.5 4.02 1.96 0.88 0.45 0.379 0.397 470 Hz11.339.443.071.790.990.630.5680.593Table 6. Typical Resolution (Bits) vs. Gain and Output Update Rate for the AD7798 Using a 2.5 V ReferenceUpdate Rate Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 4.17 Hz 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 8.33 Hz 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16.7 Hz 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 33.2 Hz 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 62 Hz 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 123 Hz 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (14.5) 242 Hz 16 (16) 16 (15.5) 16 (15.5) 16 (15.5) 16 (16) 16 (16) 16 (15) 16 (14) 470 Hz16 (16)16 (15.5)16 (16)16 (16)16 (15.5)16 (15.5)16 (14.5)15.5 (13.5)AD7799Table 7 shows the AD7799 output rms noise for some update rates and gain settings. The numbers given are for the bipolar input range with a 2.5 V reference. These numbers are typical and are generated with a differential input voltage of 0 V. Table 8 shows the effective resolution, and the output peak-to-peak resolution is given in parentheses. Note that the effective resolution is calculated using the rms noise, whereas the peak-to-peak resolution is based on peak-to-peak noise. The peak-to-peak resolution represents the resolution for which there is no code flicker. These numbers are typical and are rounded to the nearest LSB.Table 7. Output RMS Noise (μV) vs. Gain and Output Update Rate for the AD7799 Using a 2.5 V ReferenceUpdate Rate Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 4.17 Hz 0.64 0.6 0.185 0.097 0.075 0.035 0.027 0.0278.33 Hz 1.04 0.96 0.269 0.165 0.108 0.048 0.037 0.04016.7 Hz 1.55 1.45 0.433 0.258 0.176 0.085 0.065 0.06533.2 Hz 2.3 2.13 0.647 0.364 0.24 0.118 0.097 0.09462 Hz 2.95 2.85 0.952 0.586 0.361 0.178 0.133 0.134123 Hz 4.89 4.74 1.356 0.785 0.521 0.265 0.192 0.192242 Hz 11.76 9.5 3.797 2.054 1.027 0.476 0.326 0.308470 Hz 11.33 9.44 3.132 1.773 1.107 0.5 0.413 0.374Table 8. Typical Resolution (Bits) vs. Gain and Output Update Rate for the AD7799 Using a 2.5 V ReferenceUpdate Rate Gain of 1 Gain of 2 Gain of 4 Gain of 8 Gain of 16 Gain of 32 Gain of 64 Gain of 128 4.17 Hz 23 (20.5) 22 (19.5) 22.5 (20) 22.5 (20) 22 (19.5) 22 (19.5) 21.5 (19) 20.5 (18) 8.33 Hz 22 (19.5) 21.5 (19) 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 21 (18.5) 20 (17.5) 16.7 Hz 21.5 (19) 20.5 (18) 21.5 (19) 21 (18.5) 21 (18.5) 21 (18.5) 20 (17.5) 19 (16.5) 33.3 Hz 21 (18.5) 20 (17.5) 21 (18.5) 20.5 (18) 20.5 (18) 20.5 (18) 19.5 (17) 18.5 (16)62 Hz 20.5 (18) 19.5 (17) 20.5 (18) 20 (17.5) 19.5 (17) 19.5 (17) 19 (16.5) 18 (15.5) 123 Hz 20 (17.5) 19 (16.5) 20 (17.5) 19.5 (17) 19 (16.5) 19 (16.5) 18.5 (16) 17.5 (15) 242 Hz 18.5 (16) 18 (15.5) 18.5 (16) 18 (15.5) 18 (15.5) 18.5 (16) 18 (15.5) 17 (14.5) 470 Hz 18.5 (16) 18 (15.5) 18.5 (16) 18.5 (16) 18 (15.5) 18.5 (16) 17.5 (15) 16.5 (14)TYPICAL PERFORMANCE CHARACTERISTICS8388640838863083886208388610838860083885908388580020040060080099904856-006SAMPLESC OD EFigure 6. AD7799 Noise (V REF = AV DD /2, Gain = 64, Update Rate = 4.17 Hz)838858183885908388600838861083886208388630838863504856-007CODEO C C U R R E N C EFigure 7. AD7799 Noise Distribution Histogram (V REF = AV DD /2,Gain = 64, Update Rate = 4.17 Hz)83886808388660838864083886208388600838858083885608388540020040060080099904856-008SAMPLESC OD EFigure 8. AD7799 Noise (V REF = AV DD /2, Gain = 64, Update Rate = 16.7 Hz)838854983885608388580838860083886208388640838866904856-009CODEO C C U R R E N C EFigure 9. AD7799 Noise Distribution Histogram (V REF = AV DD /2,Gain = 64, Update Rate = 16.7 Hz)00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.004856-010REFERENCE VOLTAGE (V)R M S N O I S E (μV )Figure 10. RMS Noise vs. Reference Voltage (Gain = 1)ON-CHIP REGISTERSThe ADC is controlled and configured via a number of on-chip registers, which are described on the following pages. In the following descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise stated.COMMUNICATION REGISTERRS2, RS1, RS0 = 0, 0, 0The communication register is an 8-bit, write-only register. All communication to the part must start with a write operation to the communication register. The data written to the communication register determines whether the next operation is a read or write operation, and to which register this operation takes place. After the read or write operation is complete, the interface returns to its default state, where it expects a write operation to the communication register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high returns the ADC to this default state by resetting the entire part. Table 9 outlines the bit designations for the communication register. CR0 through CR7 indicate the bit location, with CR denoting that the bits are in the communication register. CR7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit.Table 10. Register SelectionRS2 RS1 RS0 Register Register Size0 0 0 Communication register during a write operation 8 bits0 0 0 Status register during a read operation 8 bits0 0 1 Mode register 16 bits0 1 0 Configuration register 16 bits0 1 1 Data register 16 bits (AD7798)/24 bits (AD7799)1 0 0 ID register 8 bits1 0 1 IO register 8 bits1 1 0 Offset register 16 bits (AD7798)/24 bits (AD7799)1 1 1 Full-scale register 16 bits (AD7798)/24 bits (AD7799)STATUS REGISTERRS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80 (AD7798)/0x88 (AD7799)The status register is an 8-bit, read-only register. To access the status register, the user must write to the communication register, select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 11 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, with SR denoting that the bits are in the status register. SR7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of the bit.MODE REGISTERRS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x000AThe mode register is a 16-bit register from which data can be read or to which data can be written. This register is used to select the operating mode, update rate, and low-side power switch. Table 12 outlines the bit designations for the mode register. MR0 through MR15 indicate the bit locations, with MR denoting that the bits are in the mode register. MR15 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. A write to the mode register resets the modulator and filter and sets the RDY bit.MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8MD2(0) MD1(0) MD0(0) PSW(0) 0(0) 0(0) 0(0) 0(0)R7 R6 R5 R4 R3 R2 R1 R0 0(0) 0(0) 0(0) 0(0) FS3(1) FS2(0) FS1(1) FS0(0)Table 12. Mode Register Bit DesignationsBit Location Bit Name DescriptionMR15 to MR13 MD2 to MD0 Mode Select Bits. These bits select the operational mode of the AD7798/AD7799 (see Table 13).MR12 PSW Power Switch Control Bit. Set by user to close the power switch PSW to GND. The power switch cansink up to 30 mA. Cleared by user to open the power switch. When the ADC is placed in power-downmode, the power switch is opened.MR11 to MR4 0 These bits must be programmed with a Logic 0 for correct operation.MR3 to MR0 FS3 to FS0 Filter Update Rate Select Bits (see Table 14).Table 14. Update Rates AvailableFS3 FS2 FS1 FS0 f ADC (Hz) t SETTLE (ms) Rejection @ 50 Hz/60 Hz 0 0 0 0 Reserved0 0 0 1 470 40 0 1 0 242 80 0 1 1 123 160 1 0 0 62 320 1 0 1 50 400 1 1 0 39 480 1 1 1 33.2 601 0 0 0 19.6 101 90 dB (60 Hz only)1 0 0 1 16.7 120 80 dB (50 Hz only)1 0 1 0 16.7 120 65 dB1 0 1 1 12.5 160 66 dB1 1 0 0 10 200 69 dB1 1 0 1 8.33 240 70 dB1 1 1 0 6.25 320 72 dB1 1 1 1 4.17 480 74 dBCONFIGURATION REGISTERRS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x0710The configuration register is a 16-bit register from which data can be read or to which data can be written. This register is used to configure the ADC for unipolar or bipolar mode, to enable or disable the buffer, to enable or disable the burnout currents, to select the gain, and to select the analog input channel. Table 15 outlines the bit designations for the filter register. CON0 through CON15 indicate the bit locations, with CON denoting that the bits are in the configuration register. CON15 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of the bit.DATA REGISTERRS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x0000(00)The conversion result from the ADC is stored in the data register. This is a read-only register. Upon completion of a read operation from this register, the RDY bit and DOUT/RDY pin are set.ID REGISTERRS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0xX8 (AD7798)/0xX9 (AD7799)The identification number for the AD7798/AD7799 is stored in the ID register. This is a read-only register.IO REGISTERRS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00The IO register is an 8-bit register from which data can be read or to which data can be written. This register is used to select the function of the AIN3(+)/AIN3(−) pins. Table 16 outlines the bit designations for the IO register. IO0 through IO7 indicate the bit locations, with IO denoting that the bits are in the IO register. IO7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit.IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO00(0) IOEN(0) IO2DAT(0) IO1DAT(0) 0(0) 0(0) 0(0) 0(0)Table 16. IO Register Bit DesignationsBit Location Bit Name DescriptionIO7 0 This bit must be programmed with a Logic 0 for correct operation.IO6 IOEN Configures the pins AIN3(+)/P1 and AIN3(−)/P2 as analog input pins or digital output pins. Whenthis bit is set, the pins are configured as Digital Output Pins P1 and P2. When this bit is cleared,these pins are configured as analog input pins AIN3(+) and AIN3(−).IO5, IO4 IO2DAT, IO1DAT P1/P2 Data. When IOEN is set, the data for the Digital Output Pins P1 and P2 is written to Bit IO1DATand Bit IO2DAT.IO3 to IO0 0 These bits must be programmed with a Logic 0 for correct operation.OFFSET REGISTERRS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x8000(AD7798)/0x800000 (AD7799)Each analog input channel has a dedicated offset register that holds the offset calibration coefficient for the channel. This register is16 bits wide on the AD7798 and 24 bits wide on the AD7799, and its power-on/reset value is 8000(00) hex. The offset register is used in conjunction with its associated full-scale register to form a register pair. The power-on/reset value is automatically overwritten if an internal or system zero-scale calibration is initiated by the user. The offset register is a read/write register. However, the AD7798/AD7799 must be in idle mode or power-down mode when writing to the offset register.FULL-SCALE REGISTERRS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXX (AD7798)/0x5XXX00 (AD7799)The full-scale register is a 16-bit register on the AD7798 and a 24-bit register on the AD7799. The full-scale register holds the full-scale calibration coefficient for the ADC. The AD7798/AD7799 has three full-scale registers, with each channel having a dedicated full-scale register. The full-scale registers are read/write registers. However, when writing to the full-scale registers, users must place the ADC in power-down mode or idle mode. Upon power-on, these registers are configured with factory-calibrated, full-scale calibration coefficients, with the calibration performed at gain = 128, the default gain setting. The default value is automatically overwritten if an internal or system full-scale calibration is initiated by the user, or the full-scale register is written to.。