AT27LV020A-90VC中文资料
AT90SC144144CT中文资料
Features Array General•High-performance, Low-power secure AVR® RISC Architecture•137 Powerful Instructions (Most Executed in a Single Clock Cycle)•Low Power Idle and Power-down Modes•Bond Pad Locations Conforming to ISO 7816-2•ESD Protection to ± 6000V•Operating Ranges: 2.7V to 5.5V•Compliant with GSM, 3GPP and EMV 2000 Specifications; PC Industry Compatible •Available in Wafers, Modules, and Industry-standard PackagesMemory•144K Bytes of FLASH Program Memory•144K Bytes of EEPROM, Including 128 OTP Bytes and 384-byte Bit-addressable Area –1 to 128-byte Program / Erase–1.25 ms Program / 1.25 ms Erase–Typically More than 500,000 Write/Erase Cycles at a Temperature of 25o C–10 Years Data Retention–EEPROM Erase Only Mode–Write EEPROM With or Without Autoerase•8K Bytes of RAM•32K Bytes of ROM Dedicated to Atmel’s Crypto-libraryPeripherals•Two I/O Ports–Configurable to Support Communication Protocols, Including ISO7816-3 and2-wire protocols•ISO7816 Controller–Up to 625 kbps at 5 MHz–Compliant with T=0 and T=1 Protocols•Serial Peripheral Interface (SPI) Contoller (up to 12 MHz)•Programmable Internal Oscillator–Up to 10 MHz on FLASH–Up to 40 MHz for Cryptographic Accelerator•Two 16-bit Timers•Random Number Generator (RNG)•2-level, 8-vector Interrupt Controller•32-bit Cryptographic Accelerator for Public Key Operations Including –RSA, DSA, ECC, Diffie-Hellman•Hardware DES and Triple DES (DPA Resistant)•Checksum Accelerator•CRC 16 and 32 Engine (Compliant with ISO/IEC 3309)Security•Dedicated Hardware for Protection Against SPA/DPA Attacks•Advanced Protection Against Physical Attack, Including Active Shield •Environmental Protection Systems•Voltage Monitor•Frequency Monitor•Light Protection•Temperature Monitor•Secure Memory Management/Access Protection (Supervisor Mode)Development Tools•Voyager Emulation Platform (ATV4 Standard) to Support Software Development•IAR Embedded Workbench® V3.20c Debugger or Atmel’s AVR Studio® Version 4.07 or Above•Software Libraries and Application NotesCertification•EAL4+•VISA•CAST•FIPSDescriptionThe AT90SC144144CT is a low-power, high-performance, 8/16-bit microcontroller with ROM program memory, EEPROM data memory, based on the secureAVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90SC144144CT achieves throughputs close to 1 MIPS per MHz. Its Harvard architecture includes 32 general-purpose working registers directly connected to the ALU, allowing two independent registers to be accessed in one single instruction executed in one clock cycle.The ability to map the EEPROM in the code space allows parts of the program memory to be reprogrammed in-system. This technology combined with the versatile 8/16-bit CPU on a monolithic chip provides a highly flexible and cost-effective solution to many smart card applications. The AT90SC144144CT benefits of advanced EEPROM functions (XP Mode), but can also be configured to offer compatibility with previous product generations (e.g. AT90SC25672R or AT90SC19236R). The cryptographic accelerator, running with the secureAVR core, featured in the AT90SC144144CT series is the new AdvX‰. It is based on a 32-bit multiplier-accumulator architecture which is designed to perform fast encryption and authen-tication functions. This enables fast computation and low-power operation. The controlling firmware is located either in the dedicated ROM memory (Atmel’s cryptolibrary supports standard finite field arithmetic functions including RSA, DSA, DH and ECC) or in the ROM program memory (customer specific).Additional security features include power and frequency protection logic, logical scrambling on program data and addresses, Power Analysis countermeasures and memory accesses controlled by a supervisor mode.Figure 1 shows the AT90SC144144CT block diagram.Figure 1.Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.Atmel CorporationAtmel Operations2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 487-2600Regional HeadquartersEuropeAtmel SarlRoute des Arsenaux 41Case Postale 80CH-1705 Fribourg SwitzerlandTel: (41) 26-426-5555Fax: (41) 26-426-5500AsiaRoom 1219Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong KongTel: (852) 2721-9778Fax: (852) 2722-1369Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Memory2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314Microcontrollers2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314La Chantrerie BP 7060244306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18Fax: (33) 2-40-18-19-60ASIC/ASSP/Smart CardsZone Industrielle13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00Fax: (33) 4-42-53-60-011150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300Fax: 1(719) 540-1759Scottish Enterprise Technology Park Maxwell BuildingEast Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000Fax: (44) 1355-242-743RF/AutomotiveTheresienstrasse 2Postfach 353574025 Heilbronn, Germany Tel: (49) 71-31-67-0Fax: (49) 71-31-67-23401150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300Fax: 1(719) 540-1759Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF DatacomAvenue de Rochepleine BP 12338521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00Fax: (33) 4-76-58-34-80Literature Requests/literatureATMEL ®, AVR ® and AVRstudio ® are registered trademarks of Atmel; secureAVR ™ and AdvX ™ are trademarks of Atmel.EWAVR ® is a registered trademark of IAR Systems AB. Other terms and product names may be the trademark of others.Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.Atmel CorporationAtmel Operations2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 487-2600Regional HeadquartersEuropeAtmel SarlRoute des Arsenaux 41Case Postale 80CH-1705 Fribourg SwitzerlandTel: (41) 26-426-5555Fax: (41) 26-426-5500AsiaRoom 1219Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong KongTel: (852) 2721-9778Fax: (852) 2722-1369Japan9F, Tonetsu Shinkawa Bldg.1-24-8 ShinkawaChuo-ku, Tokyo 104-0033JapanTel: (81) 3-3523-3551Fax: (81) 3-3523-7581Memory2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314Microcontrollers2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311Fax: 1(408) 436-4314La Chantrerie BP 7060244306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18Fax: (33) 2-40-18-19-60ASIC/ASSP/Smart CardsZone Industrielle13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00Fax: (33) 4-42-53-60-011150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300Fax: 1(719) 540-1759Scottish Enterprise Technology Park Maxwell BuildingEast Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000Fax: (44) 1355-242-743RF/AutomotiveTheresienstrasse 2Postfach 353574025 Heilbronn, Germany Tel: (49) 71-31-67-0Fax: (49) 71-31-67-23401150 East Cheyenne Mtn. Blvd.Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300Fax: 1(719) 540-1759Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF DatacomAvenue de Rochepleine BP 12338521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00Fax: (33) 4-76-58-34-80Literature Requests/literature。
EN29LV160B-70TP资料
0.FEATURES• 3.0V, single power supply operation- Minimizes system level power requirements• High performance- Access times as fast as 70 ns• Low power consumption (typical values at 5 MHz)- 9 mA typical active read current- 20 mA typical program/erase current- 1 µA typical standby current (standard access time to active mode)• Flexible Sector Architecture:- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, andthirty-one 64 Kbyte sectors (byte mode) - One 8 Kword, two 4 Kword, one 16 Kword and thirty-one 32 Kword sectors (word mode) - Supports full chip erase- Individual sector erase supported - Sector protection:Hardware locking of sectors to preventprogram or erase operations within individual sectorsAdditionally, temporary Sector GroupUnprotect allows code changes in previously locked sectors.• High performance program/erase speed- Byte program time: 8µs typical - Sector erase time: 500ms typical - Chip erase time: 17.5s typical• JEDEC Standard program and erase commands• JEDEC standard DATA polling and toggle bits feature• Single Sector and Chip Erase • Sector Unprotect Mode• Embedded Erase and Program Algorithms • Erase Suspend / Resume modes:Read and program another Sector during Erase Suspend Mode• 0.23 µm triple-metal double-poly triple-well CMOS Flash Technology • Low Vcc write inhibit < 2.5V• >100K program/erase endurance cycle• Package Options - 48-pin TSOP (Type 1) - 48 ball 6mm x 8mm FBGA • Commercial Temperature RangeGENERAL DESCRIPTIONThe EN29LV160 is a 16-Megabit, electrically erasable, read/write non-volatile flash memory, organized as 2,097,152 bytes or 1,048,576 words. Any byte can be programmed typically in 8µs. The EN29LV160 features 3.0V voltage read and write operation, with access times as fast as 70ns to eliminate the need for WAIT states in high-performance microprocessor systems.The EN29LV160 has separate Output Enable (OE ), Chip Enable (CE ), and Write Enable (WE) controls, which eliminate bus contention issues. This device is designed to allow either single Sector or full chip erase operation, where each Sector can be individually protected againstprogram/erase operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K program/erase cycles on each Sector.EN29LV160 ******PRELIMINARY DRAFT******16 Megabit (2048K x 8-bit / 1024K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-onlyCONNECTION DIAGRAMSA6 A5 A4A1A3 A2 FBGATop View, Balls Facing DownA13A9 A3 RY/BY#WE# A7 B6 B5 B4B1B3 B2 A12A8 A4NCRESET# A17 C6C5C4C1C3C2A14A10 A2A18NCA6 D6 D5 D4D1D3 D2 A15A11 A1NCA19A5 E6E5E4E1E3E2A16DQ7A0DQ2DQ5DQ0F6F5F4F3F2BYTE#DQ14CE#DQ10DQ12DQ8G6G5G4G3G2DQ15/A-1DQ13OE#DQ11Vcc DQ9H6H5H3H2VssDQ6VssDQ4DQ1F1G1H4H1DQ312 3 4 5 6 78 91011 12 1314 15 16 17 18 19202122 2324 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25Standard TSOPA15A14A13A12A11A10A9A8A19NC WE#RESET#NCNC RY/BY#A18A17A7A6A5A4A3A2A1A16 BYTE# VssDQ15/A-1DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 Vcc DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# Vss CE# A0TABLE 1. PIN DESCRIPTION FIGURE 1. LOGIC DIAGRAM Pin Name FunctionA0-A19 20AddressesDQ0-DQ14 15 Data Inputs/OutputsDQ15 / A-1 DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode)CE# ChipEnable OE# OutputEnable RESET# Hardware Reset PinRY/BY# Ready/BusyOutput WE# WriteEnableVcc Supply Voltage(2.7-3.6V)Vss Ground NC Not Connected to anythingBYTE# Byte/WordModeEN29LV160A0 – A19WECEOERY/BY ResetByteTable 2. Sector Address Tables (EN29LV160T)Address Range (in hexadecimal)Sector A19 A18 A17 A16 A15 A14A13A12Sector Size(Kbytes/ Kwords)Byte mode (x8) Word Mode(x16) SA0 0 0 0 0 0 X X X 62/32 000000–00FFFF 00000–07FFF SA1 0 0 0 0 1 X X X 64/32 010000–01FFFF 08000–0FFFF SA2 0 0 0 1 0 X X X 64/32 020000–02FFFF 10000–17FFF SA3 0 0 0 1 1 X X X 64/32 030000–03FFFF 18000–1FFFF SA4 0 0 1 0 0 X X X 64/32 040000–04FFFF 20000–27FFF SA5 0 0 1 0 1 X X X 64/32 050000–05FFFF 28000–2FFFF SA6 0 0 1 1 0 X X X 64/32 060000–06FFFF 30000–37FFF SA7 0 0 1 1 1 X X X 64/32 070000–07FFFF 38000–3FFFF SA8 0 1 0 0 0 X X X 64/32 080000–08FFFF 40000–47FFF SA9 0 1 0 0 1 X X X 64/32 090000–09FFFF 48000–4FFFF SA10 0 1 0 1 0 X X X 64/32 0A0000–0AFFFF 50000–57FFF SA11 0 1 0 1 1 X X X 64/32 0B0000–0BFFFF 58000–5FFFF SA12 0 1 1 0 0 X X X 64/32 0C0000–0CFFFF 60000–67FFF SA13 0 1 1 0 1 X X X 64/32 0D0000–0DFFFF 68000–6FFFF SA14 0 1 1 1 0 X X X 64/32 0E0000–0EFFFF 70000–77FFF SA15 0 1 1 1 1 X X X 64/32 0F0000–0FFFFF 78000–7FFFF SA16 1 0 0 0 0 X X X 64/32 100000–10FFFF 80000–87FFF SA17 1 0 0 0 1 X X X 64/32 110000–11FFFF 88000–8FFFF SA18 1 0 0 1 0 X X X 64/32 120000–12FFFF 90000–97FFF SA19 1 0 0 1 1 X X X 64/32 130000–13FFFF 98000–9FFFF SA20 1 0 1 0 0 X X X 64/32 140000–14FFFF A0000–A7FFF SA21 1 0 1 0 1 X X X 64/32 150000–15FFFF A8000–AFFFF SA22 1 0 1 1 0 X X X 64/32 160000–16FFFF B0000–B7FFF SA23 1 0 1 1 1 X X X 64/32 170000–17FFFF B8000–BFFFF SA24 1 1 0 0 0 X X X 64/32 180000–18FFFF C0000–C7FFF SA25 1 1 0 0 1 X X X 64/32 190000–19FFFF C8000–CFFFF SA26 1 1 0 1 0 X X X 64/32 1A0000–1AFFFF D0000–D7FFF SA27 1 1 0 1 1 X X X 64/32 1B0000–1BFFFF D8000–DFFFF SA28 1 1 1 0 0 X X X 64/32 1C0000–1CFFFF E0000–E7FFF SA29 1 1 1 0 1 X X X 64/32 1D0000–1DFFFF E8000–EFFFF SA30 1 1 1 1 0 X X X 64/32 1E0000–1EFFFF F0000–F7FFF SA31 1 1 1 1 1 0 X X 32/16 1F0000–1F7FFF F8000–FBFFF SA32 1 1 1 1 1 1 0 0 8/4 1F8000–1F9FFF FC000–FCFFF SA33 1 1 1 1 1 1 0 1 8/41FA000–1FBFFF FD000–FDFFFSA34 1 1 1 1 1 1 1 X16/8 1FC000–1FFFFF FE000–FFFFFTable 3. Sector Address Tables (EN29LV160B)Address Range (in hexadecimal) Sector A19 A18 A17 A16 A15 A14A13A12Sector Size (Kbytes/ Kwords)Byte mode (x8)Word Mode(x16) SA0 0 0 0 0 0 0 0 X 16/8 000000–003FFF 00000–01FFF SA1 0 0 0 0 0 0 1 0 8/4 004000–005FFF 02000–02FFF SA2 0 0 0 0 0 0 1 18/4006000–007FFF 03000–03FFFSA3 0 0 0 0 0 1 X X 32/16 008000–00FFFF 04000–07FFF SA4 0 0 0 0 1 X X X 64/32 010000–01FFFF 08000–0FFFF SA5 0 0 0 1 0 X X X 64/32 020000–02FFFF 10000–17FFF SA6 0 0 0 1 1 X X X 64/32 030000–03FFFF 18000–1FFFF SA7 0 0 1 0 0 X X X 64/32 040000–04FFFF 20000–27FFF SA8 0 0 1 0 1 X X X 64/32 050000–05FFFF 28000–2FFFF SA9 0 0 1 1 0 X X X 64/32 060000–06FFFF 30000–37FFF SA10 0 0 1 1 1 X X X 64/32 070000–07FFFF 38000–3FFFF SA11 0 1 0 0 0 X X X 64/32 080000–08FFFF 40000–47FFF SA12 0 1 0 0 1 X X X 64/32 090000–09FFFF 48000–4FFFF SA13 0 1 0 1 0 X X X 64/32 0A0000–0AFFFF 50000–57FFF SA14 0 1 0 1 1 X X X 64/32 0B0000–0BFFFF58000–5FFFFSA15 0 1 1 0 0 X X X 64/32 0C0000–0CFFFF 60000–67FFF SA16 0 1 1 0 1 X X X 64/32 0D0000–0DFFFF 68000–6FFFF SA17 0 1 1 1 0 X X X 64/32 0E0000–0EFFFF 70000–77FFF SA18 0 1 1 1 1 X X X 64/32 0F0000–0FFFFF 78000–7FFFF SA19 1 0 0 0 0 X X X 64/32 100000–10FFFF 80000–87FFF SA20 1 0 0 0 1 X X X 64/32 110000–11FFFF 88000–8FFFF SA21 1 0 0 1 0 X X X 64/32 120000–12FFFF 90000–97FFF SA22 1 0 0 1 1 X X X 64/32 130000–13FFFF 98000–9FFFF SA23 1 0 1 0 0 X X X 64/32 140000–14FFFF A0000–A7FFF SA24 1 0 1 0 1 X X X 64/32 150000–15FFFF A8000–AFFFF SA25 1 0 1 1 0 X X X 64/32 160000–16FFFF B0000–B7FFF SA26 1 0 1 1 1 X X X 64/32 170000–17FFFF B8000–BFFFF SA27 1 1 0 0 0 X X X 64/32 180000–18FFFF C0000–C7FFF SA28 1 1 0 0 1 X X X 64/32 190000–19FFFF C8000–CFFFF SA29 1 1 0 1 0 X X X 64/32 1A0000–1AFFFF D0000–D7FFF SA30 1 1 0 1 1 X X X 64/32 1B0000–1BFFFF D8000–DFFFF SA31 1 1 1 0 0 X X X 64/32 1C0000–1CFFFF E0000–E7FFF SA32 1 1 1 0 1 X X X 64/32 1D0000–1DFFFF E8000–EFFFF SA33 1 1 1 1 0 X X X 64/32 1E0000–1EFFFF F0000–F7FFF SA34 1 1 1 1 1 X X X 64/321F0000–1FFFFF F8000–FFFFFPRODUCT SELECTOR GUIDEProduct Number EN29LV160Regulated Voltage Range: Vcc=3.0 – 3.6 VSpeed OptionFull Voltage Range: Vcc=2.7 – 3.6 V-70 -90Max Access Time, ns (t acc ) 70 90Max CE# Access, ns (t ce ) 70 90Max OE# Access, ns (t oe ) 30 35BLOCK DIAGRAMWECE OEState ControlCommand RegisterErase Voltage GeneratorInput/Output BuffersProgram Voltage GeneratorChip Enable Output EnableLogicData LatchY-Decoder X-DecoderY-GatingCell MatrixTimerVcc DetectorA0-A19Vcc VssDQ0-DQ15 (A-1)Address LatchBlock Protect SwitchesSTBSTBRY/BYTABLE 3. OPERATING MODES16M FLASH USER MODE TABLEDQ8-DQ15Operation CE# OE# WE# Reset# A0-A19 DQ0-DQ7 Byte# = V IH Byte#= V IL Read L L H H A IN D OUT D OUT High-Z Write L H L H A IN D IN D IN High-Z CMOS Standby V cc ± 0.3V X X V cc ± 0.3V X High-Z High-Z High-Z TTL Standby H X X H X High-Z High-Z High-Z Output Disable L H H H X High-Z High-Z High-Z Hardware Reset X X X L X High-Z High-Z High-Z TemporarySector Unprotect X X X V IDA IN D IN D IN XNotes:L=logic low= V IL , H=Logic High= V IH , V ID =11 ± 0.5V, X=Don’t Care (either L or H, but not floating!), D IN =Data In, D OUT =Data Out, A IN =Address InTABLE 4. DEVICE IDENTIFICTION (Autoselect Codes)16M FLASH MANUFACTURER/DEVICE ID TABLENote:1. A8=H is recommended for Manufacturing ID check. If a manufacturing ID is read with A8=L, the chip will output a configuration code 7Fh2. A9 = VID is for HV A9 Autoselect mode only. A9 must be ≤ Vcc (CMOS logic level) for Command Autoselect Mode.Description Mode A19 to A12A11 toA10A92A8A7A6A5 to A2A1 A0 DQ8to DQ15 DQ7 to DQ0 Manufacturer ID:EonL L H X X V IDH1X L X L L X 1CH Word L L H22h C4H Device ID (top bootblock) Byte L L H X X V ID X X L X L H X C4H Word L L H22h49H Device ID(bottom bootblock)Byte L L HX X V IDXXLXLHX 49H X01h(Protected)Sector ProtectionVerification L L H SA X V IDX X L X H LX00h(Unprotected)OE CE WEUSER MODE DEFINITIONSWord / Byte ConfigurationThe signal set on the BYTE# Pin controls whether the device data I/O pins DQ15-DQ0 operate in the byte or word configuration. When the Byte# Pin is set at logic ‘1’, then the device is in word configuration, DQ15-DQ0 are active and are controlled by CE# and OE#.On the other hand, if the Byte# Pin is set at logic ‘0’, then the device is in byte configuration, and only data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.Standby ModeThe EN29LV160 has a CMOS-compatible standby mode, which reduces the current to < 1µA (typical). It is placed in CMOS-compatible standby when the CE pin is at V CC± 0.5. RESET# and BYTE# pin must also be at CMOS input levels. The device also has a TTL-compatible standby mode, which reduces the maximum V CC current to < 1mA. It is placed in TTL-compatible standby when the pin is at V IH. When in standby modes, the outputs are in a high-impedance state independent of the OE input.Read ModeThe device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm.After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more additional information.The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” additional details.Output Disable ModeWhen the CE or OE pin is at a logic high level (V IH), the output from the EN29LV160 is disabled. The output pins are placed in a high impedance state.Auto Select Identification ModeThe autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ15–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.When using programming equipment, the autoselect mode requires V ID (10.5 V to 11.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are don’t-care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15–DQ0.To access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require V ID. See “Command Definitions” for details on using the autoselect mode.Write ModeProgramming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. The Command Definitions in Table 5 show the address and data requirements for the byte program command sequence.When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. See “Write Operation Status” for information on these status bits.Any commands written to the device during the Embedded Program Algorithm are ignored.Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to “1”, or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”.Sector Protection/UnprotectionThe hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors.There are two methods to enabling this hardware protection circuitry. The first one requires only that the RESET# pin be at V ID and then standard microprocessor timings can be used to enable or disable this feature. See Flowchart 7a and 7b for the algorithm and Figure 12 for the timings.When doing Sector Unprotect, all the other sectors should be protected first.The second method is meant for programming equipment. This method requires V ID be applied to both OE# and A9 pin and non-standard microprocessor timings are used. This method is described in a separate document called EN29LV160 Supplement, which can be obtained by contacting a representative of Eon Silicon Solution, Inc.Temporary Sector UnprotectThis feature allows temporary unprotection of previously protectedsector groups to change data while in-system. The Sector Unprotectmode is activated by setting the RESET# pin to V ID. During this mode,formerly protected sectors can be programmed or erased by simplyselecting the sector addresses. Once is removed from the RESET#pin, all the previously protected sectors are protected again. Seeaccompanying figure and timing diagrams for more details.COMMON FLASH MEMORYINTERFACE(CFI)The common flash interface (CFI) specification outlines device and host systems software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support canStartReset#=V ID(note 1)Perform Erase or ProgramOperationsReset#=V IHTemporary SectorUnprotect Completed (note 2)Notes:1. All protected sectors unprotected.2. Previously protected sectors protected again.then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendirs can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 5-8. In word mode, the upper address bits (A7–MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command.The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode and the system can read CFI data at the addresses given in Tables 5–8. The system must write the reset command to return the device to the autoselect mode.Table 5. CFI Query Identification StringAdresses (Word Mode)Adresses(Byte Mode) Data Description10h 11h 12h 20h22h24h0051h0052h0059hQuery Unique ASCII string “QRY”13h 14h 26h28h0002h0000hPrimary OEM Command Set15h 16h 2Ah2Ch0040h0000hAddress for Primary Extended Table17h 18h 2Eh30h0000h0000hAlternate OEM Command set (00h = none exists)19h 1Ah 32h34h0000h0000hAddress for Alternate OEM Extended Table (00h = none exists Table 6. System Interface StringAddresses (Word Mode)Addresses(Byte Mode) Data Description1Bh 36h 0027hVccMin(write/erase)D7-D4: volt, D3 –D0: 100 millivolt1Ch 38h 0036h Vcc Max (write/erase)D7-D4: volt, D3 –D0: 100 millivolt1Dh 3Ah 0000h Vpp Min. voltage (00h = no Vpp pin present)1Eh 3Ch 0000h Vpp Max. voltage (00h = no Vpp pin present)1Fh 3Eh 0004hTypical timeout per single byte/word write 2^N µs20h 40h 0000hTypical timeout for Min, size buffer write 2^N µs (00h = notsupported)21h 42h 000Ah Typical timeout per individual block erase 2^N ms22h 44h 0000h Typical timeout for full chip erase 2^N ms (00h = not supported) 23h 46h 0005h Max. timeout for byte/word write 2^N times typical24h 48h 0000h Max. timeout for buffer write 2^N times typical25h 4Ah 0004h Max. timeout per individual block erase 2^N times typical26h 4Ch 0000h Max timeout for full chip erase 2^N times typical (00h = notsupported)Table 7. Device Geometry DefinitionAddresses (Word mode)Addresses(Byte Mode) Data Description27h 4Eh 0015h Device Size = 2^N byte28h 29h 50h 52h 0002h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 54h 56h 0000h 0000h Max. number of byte in multi-byte write = 2^N (00h = not supported)2Ch 58h 0004h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 5Ah 5Ch 5Eh 60h 0000h 0000h 0040h 0000h Erase Block Region 1 Information(refer to the CFI specification of CFI publication 100)31h 32h 33h 34h 62h 64h 66h 68h 0001h 0000h 0020h 0000h Erase Block Region 2 Information35h 36h 37h 38h 6Ah 6Ch 6Eh 70h 0000h 0000h 0080h 0000h Erase Block Region 3 Information39h 3Ah 3Bh 3Ch72h 74h 76h 78h001Eh 0000h 0000h 0001hErase Block Region 4 InformationTable 8. Primary Vendor-specific Extended QueryAdresses (Word Mode)Addresses (Byte Mode)Data Description 40h 41h 42h 80h 82h 84h 0050h0052h 0049hQuery-unique ASCII string “PRI” 43h 86h 0031h Major version number, ASCII 44h88h0030h Minor version number, ASCII45h 8Ah 0000hAddress Sensitive Unlock0 = Required, 1 = Not Required 46h 8Ch 0002hErase Suspend0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 8Eh 0001hSector Protect0 = Not Supported, X = Number of sectors in per group 48h 90h 0001hSector Temporary Unprotect00 = Not Supported, 01 = Supported 49h 92h 0004h Sector Protect/Unprotect scheme01 = 29F040 mode, 02 = 29F016 mode,03 = 29F400 mode, 04 = 29LV800A mode 4Ah 94h 0000hSimultaneous Operation00 = Not Supported, 01 = Supported 4Bh 96h 0000hBurst Mode Type00 = Not Supported, 01 = Supported 4Ch 98h 0000hPage Mode Type00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word PageHardware Data protectionThe command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the Command Definitions table. Additionally, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by false system level signals during Vcc power up and power down transitions, or from system noise.Low V CC Write InhibitWhen Vcc is less than V LKO, the device does not accept any write cycles. This protects data during Vcc power up and power down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until Vcc is greater than V LKO. The system must provide the proper signals to the control pins to prevent unintentional writes when Vcc is greater than V LKO. Write Pulse “Glitch” protectionNoise pulses of less than 5 ns (typical) on OE, CE or W E do not initiate a write cycle.Logical InhibitWrite cycles are inhibited by holding any one of OE = VIL, CE = VIH, or W E = VIH. To initiate a write cycle, CE and W E must be a logical zero while OE is a logical one. If CE, W E, and OE are all logical zero (not recommended usage), it will be considered a read.Power-up Write InhibitDuring power-up, the device automatically resets to READ mode and locks out write cycles. Even with CE = V IL, W E = V IL and OE = V IH, the device will not accept commands on the rising edge of W E.COMMAND DEFINITIONSThe operations of the EN29LV160 are selected by one or more commands written into the command register to perform Read/Reset Memory, Read ID, Read Sector Protection, Program, Sector Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data sequences written at specific addresses via the command register. The sequences for the specified operation are defined in the Command Definitions table (Table 5). Incorrect addresses, incorrect data values or improper sequences will reset the device to Read Mode.Table 9. EN29LV160 Command DefinitionsBus Cycles1stWrite Cycle 2ndWrite Cycle 3rdWrite Cycle4thWrite Cycle5thWrite Cycle6thWrite Cycle Command SequenceC y c l e sAdd DataAdd DataAdd DataAdd DataAdd DataAdd DataRead 1 RA RDReset 1 xxx F0Word555 2AA555000/1007F/1CManufacturerID Byte 4AAA AA55555AAA90000/2007F/1CWord 555 2AA555 x0122C4 Device ID Top Boot Byte 4 AAA AA55555 AAA 90x02 C4Word 555 2AA555 x01 2249Device ID Bottom Boot Byte 4AAA AA55555AAA 90x02 49XX00Word5552AA555(SA)X02XX0100A u t o s e l e c tSector Protect Verify Byte4AAA AA55555AAA90(SA)X0401Word 555 2AA555ProgramByte 4 AAA AA55555 AAAA0 PA PDWord555 2AA555Unlock BypassByte3 AAA AA55555 AAA 20Unlock Bypass Program 2 XXX A0 PA PD Unlock Bypass Reset2 XXX 90 XXX 00 Word555 2AA555 5552AA 555Chip EraseByte 6 AAA AA55555 AAA 80 AAA AA 555 55 AAA 10Word555 2AA555 5552AASector EraseByte6 AAA AA55555 AAA 80 AAA AA 555 55 SA 30Erase Suspend 1 xxx B0 Erase Resume1 xxx 30Address and Data values indicated in hexRA = Read Address: address of the memory location to be read. This is a read cycle. RD = Read Data: data read from location RA during Read operation. This is a read cycle. PA = Program Address: address of the memory location to be programmed. X = Don’t-Care PD = Program Data: data to be programmed at location PASA = Sector Address: address of the Sector to be erased or verified. Address bits A19-A12 uniquely select any Sector.Reading Array DataThe device is automatically set to reading array data after power up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm.Following an Erase Suspend command, Erase Suspend mode is entered. The system can read array data using the standard read timings, with the only difference in that if it reads at an address within erase suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception.The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See next section for details on Reset.Reset CommandWriting the reset command to the device resets the device to reading array data. Address bits are don’t-care for this command.The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete.The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend).If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend).Autoselect Command SequenceThe autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This is an alternative to the method that requires V ID on address bit A9 and is intended for PROM programmers.Two unlock cycles followed by the autoselect command initiate the autoselect command sequence. Autoselect mode is then entered and the system may read at addresses shown in Table 4 any number of times, without needing another command sequence.The system must write the reset command to exit the autoselect mode and return to reading array data. Word / Byte Programming CommandThe device may be programmed by byte or by word, depending on the state of the Byte# Pin. Programming the EN29LV160 is performed by using a four bus-cycle operation (two unlock write cycles followed by the Program Setup command and Program Data Write cycle). When the program command is executed, no additional CPU controls or timings are necessary. An internal timer terminates the program operation automatically. Address is latched on the falling edge of CE or W E, whichever is last; data is latched on the rising edge of CE or W E, whichever is first. Programming status may be checked by sampling data on DQ7 (DATA polling) or on DQ6 (toggle bit). ). When the program operation is successfully completed, the device returns to read mode and the user can read the data programmed to the device at that address. Note that data can not be programmed from a 0 to a 1. Only an erase operation can change a data from 0 to 1. When programming time limit is exceeded, DQ5 will produce a logical “1” and a Reset command can return the device to Read mode.Unlock BypassTo speed up programming operation, the Unlock Bypass Command may be used. Once this feature is activated, the shorter two cycle Unlock Bypass Program command can be used instead of the normal four cycle Program Command to program the device. This mode is exited after issuing the Unlock Bypass Reset Command. The device powers up with this feature disabled.。
AT27C020中文资料
The AT27C020 is available in a choice of industry standard JEDEC-approved one-time programmable (OTP) plastic PDIP, PLCC, and TSOP packages. All devices feature two-line control (CE, OE) to give designers the flexibility to pre-vent bus contention.With 256K byte storage capability, the AT27C020 allows firmware to be stored reliably and to be accessed by the system without the delays of mass storage media. Atmel’s 27C020 have additional features to ensure high quality and efficient production use. The Rapid™Program-ming Algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 100 µs/byte. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry standard programming equipment to select the proper programming algorithms and voltages.System ConsiderationsSwitching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these tran-sients may exceed data sheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency, low inherent inductance, ceramic capacitor should be uti-lized for each device. This capacitor should be connected between the V CC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again connected between the V CC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array.Block DiagramAbsolute Maximum Ratings*T emperature Under Bias.......................-55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to abso-lute maximum rating conditions for extended periods may affect device reliability.Note:1.Minimum voltage is -0.6V DC which mayundershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is V CC + 0.75V DC which may overshoot to +7.0V for pulses of less than 20 ns.Storage T emperature............................-65°C to +150°C Voltage on Any Pin withRespect to Ground...............................-2.0V to +7.0V (1)Voltage on A9 withRespect to Ground ............................-2.0V to +14.0V (1)V PP Supply Voltage withRespect to Ground.............................-2.0V to +14.0V (1)Operating ModesNotes:1.X can be V IL or V IH.2.Refer to Programming Characteristics.3.V H = 12.0 ± 0.5V .4.T wo identifier bytes may be selected. All Ai inputs are held low (V IL ), except A9 which is set to V H and A0 which is toggledlow (V IL ) to select the Manufacturer’s Identification byte and high (V IH ) to select the Device Code byte.Mode/Pin CE OE PGM Ai V PP Outputs ReadV IL V IL X (1)Ai X D OUT Output Disable X V IH X X X HighZ Standby V IH X X X X High Z Rapid Program (2)V IL V IH V IL Ai V PP D IN PGM Verify V IL V IL V IH Ai V PP D OUT PGM InhibitV IH X X X V PP High Z Product Identification (4)V ILV ILXA9 = V H (3)A0 = V IH or V IL A1 - A17 = V ILXIdentification CodeAC Characteristics for Read OperationNote:1.2, 3, 4, 5. See AC Waveforms for Read Operation diagram.Symbol ParameterAT27C020Units -55-70-90-12-15Condition Min Max MinMax MinMax MinMax MinMax t ACC (3)Address to Output Delay CE =OE = V IL 557090120150ns t CE (2)CE to Output Delay OE = V IL 557090120150ns t OE (2)(3)OE to Output Delay CE = V IL2030353540ns t DF(4)(5)OE or CE High to Output Float,whichever occurred first 1820203040nst OH Output Holdfrom Address,CE or OE,whichever occurred first77000nsDC and AC Operating Conditions for Read OperationAT27C020-55-70-90-12-15Operating T emperature (Case)Com.0°C - 70°C 0°C - 70°C 0°C - 70°C 0°C - 70°C 0°C - 70°C Ind.-40°C - 85C -40°C - 85C -40°C - 85C -40°C - 85C -40°C - 85C V CC Power Supply5V ± 10%5V ± 10%5V ± 10%5V ± 10%5V ± 10%DC and Operating Characteristics for Read OperationNotes:1.V CC must be applied simultaneously or before V PP , and removed simultaneously or after V PP .2.V PP may be connected directly to V CC except during programming. The supply current would then be the sum of I CC and I PP .Symbol Parameter ConditionMinMax Units I LI Input Load Current V IN = 0V to V CC (Com., Ind.)±1.0µA I LO Output Leakage Current V OUT = 0V to V CC (Com., Ind.)±5.0µA I PP (2)V PP (1) Read/Standby Current V PP = V CC±10µA I SB V CC (1) Standby Current I SB1 (CMOS), CE = V CC ± 0.3V 100µA I SB2 (TTL), CE = 2.0 to V CC + 0.5V 1.0mA I CC V CC Active Current f = 5 MHz, I OUT = 0 mA, CE = V IL25mA V IL Input Low Voltage -0.60.8V V IH Input High Voltage 2.0V CC + 0.5V V OL Output Low Voltage I OL = 2.1 mA 0.4V V OH Output High VoltageI OH = -400 µA2.4VAC Waveforms for Read Operation (1)Notes: 1.Timing measurement references are 0.8V and 2.0V . Input AC drive levels are 0.45V and 2.4V , unless otherwise specified.2.OE may be delayed up to t CE - t OE after the falling edge of CE without impact on t CE.3.ACC - t OE after the address is valid without impact on t ACC .4.This parameter is only sampled and is not 100% tested.5.Output float is defined as the point when data is no longer driven.Input Test Waveforms and Measurement LevelsFor -55 devices only:t R , t FFor -70,-90,-12,-15 devices only:t R , t F < 20 ns (10% to 90%)Pin Capacitancef = 1 MHz, T = 25°C (1)Note:1.T ypical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.TypMax Units Conditions C IN 48pF V IN = 0V C OUT812pFV OUT = 0VOutput Test Load (1)Note: 1.CL = 100 pF including jig capacitance except -55 devices where CL = 30 pF.Programming Waveforms (1)Notes: 1.The Input Timing reference is 0.8V for V IL and 2.0V for V IH.2.t OE and t DFP are characteristics of the device but must be accommodated by the programmer.3.When programming the A T27C020, a 0.1 µF capacitor is required across V PP and ground to suppress voltage transients.DC Programming CharacteristicsT A = 25 ± 5°C, V CC = 6.5 ± 0.25V, V PP = 13.0 ± 0.25VSymbol Parameter Test ConditionsLimitsUnits Min MaxI LI Input Load Current V IN = V IL, V IH±10µA V IL Input Low Level-0.60.8V V IH Input High Level 2.0VCC+ 1.0V V OL Output Low Voltage I OL = 2.1 mA0.4V V OH Output High Voltage I OH = -400 µA 2.4V I CC2V CC Supply Current (Program and Verify)40mA I PP2V PP Supply Current CE = PGM = V IL20mA V ID A9 Product Identification Voltage11.512.5VAC Programming CharacteristicsT A = 25 ± 5°C, V CC = 6.5 ± 0.25V,V PP = 13.0 ± 0.25VNotes:1.V CC must be applied simultaneously or before V PP and removed simultaneously or after V PP .2.This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven— see timing diagram.3.Program Pulse width tolerance is 100 µs ± 5%.Symbol ParameterTest Condition (1)LimitsUnits Min Max t AS Address Setup Time Input Rise and Fall Times:(10% to 90%) 20 ns.Input Pulse Levels:0.45V to 2.4V Input Timing Reference Level:0.8V to 2.0V Output Timing Reference Level:0.8V to 2.0V2µs t CES CE Setup Time 2µs t OES OE Setup Time 2µs t DS Data Setup Time 2µs t AH Address Hold Time 0µs t DH Data Hold Time2µst DFP OE High to Output Float Delay (2)0130ns t VPS V PP Setup Time 2µs t VCS V CC Set up Time2µs t PW PGM Program Pulse Width (3)95105µs t OE Data Valid from OE150ns t PRTV PP Pulse Rise Time During Programming50nsAtmel’s 27C020 Integrated Product Identification CodePinsCodes A0O7O6O5O4O3O2O1O0Hex DataManufacturer 0000111101E Device T ype111186Rapid Programming AlgorithmA 100 µs PGM pulse width is used to program. The address is set to the first location. V CC is raised to 6.5V and V PP is raised to 13.0V. Each address is first programmed with one 100 µs PGM pulse without verification. Then a verification / reprogramming loop is executed for each address. In the event a byte fails to pass verification, up to 10 successive 100 µs pulses are applied with a verification after each pulse. If the byte fails to verify after 10 pulses have been applied, the part is considered failed. After the byte verifies properly, the next address is selected until all have been checked. V PP is then lowered to 5.0V and V CC to 5.0V. All bytes are read again and compared with the origi-nal data to determine if the device passes or fails.Ordering Informationt ACC (ns)I CC (mA)Ordering Code Package Operation Range Active Standby55250.1A T27C020-55JCA T27C020-55PCA T27C020-55TC 32J32P632TCommercial(0°C to 70°C)250.1A T27C020-55JIA T27C020-55PIA T27C020-55TI 32J32P632TIndustrial(-40°C to 85°C)70250.1A T27C020-70JCA T27C020-70PCA T27C020-70TC 32J32P632TCommercial(0°C to 70°C)250.1A T27C020-70JIA T27C020-70PIAT27C020-70TI 32J32P632TIndustrial(-40°C to 85°C)90250.1A T27C020-90JCA T27C020-90PCA T27C020-90TC 32J32P632TCommercial(0°C to 70°C)250.1A T27C020-90JIA T27C020-90PIAT27C020-90TI 32J32P632TIndustrial(-40°C to 85°C)120250.1A T27C020-12JCA T27C020-12PCA T27C020-12TC 32J32P632TCommercial(0°C to 70°C)250.1A T27C020-12JIA T27C020-12PIA T27C020-12TI 32J32P632TIndustrial(-40°C to 85°C)150250.1A T27C020-15JCA T27C020-15PCA T27C020-15TC 32J32P632TCommercial(0°C to 70°C)250.1A T27C020-15JIA T27C020-15PIA T27C020-15TI 32J32P632TIndustrial(-40°C to 85°C)Package Type32J32-Lead,Plastic J-Leaded Chip Carrier (PLCC)32P632-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 32T32-Lead, Plastic Thin Small Outline Package (TSOP)。
MR2920中文资料
Input voltage autosensingProvision for Standby mode operation Partial Resonance Power Supply IC Module MR29001. The circuit diagrams and parts tables provided for reference purposes in this document are for the use of persons with basic circuit design knowledge to aid in understanding the product.As such they do not constitute a guarantee of output, temperature, or other characteristics, or characteristics or safety as determined by the relevant authorities.2. The products noted in this document are semiconductor components for use in general electronic equipment and for general industrial use. Consideration has been given to ensure safety and reliability as appropriate for the importance of the systems used by the customer. Please contact Shindengen's sales section if any points are unclear.3. Fail-safe design and safety requirements must be considered in applications in which particularly high levels of reliability and safety are required (eg nuclear power control, aerospace, traffic equipment, medical equipment used in life-support, combustion control equipment, various types of safety equipment).Please contact our sales department if anything is unclear.4. Shindengen takes no responsibility for losses or damage incurred, or infringements of patents or other rights, as a result of the use of the circuit diagrams and parts tables provided for reference purposes in this document.5. The circuit diagrams and parts tables provided for reference purposes in this document do not guarantee or authorize execution of intellectual property rights, or any other rights, of Shindengen or third parties.6. Systems using Shindengen products noted in this document and which are strategic materials as defined in the Foreign Exchange and Foreign Trade Control Law or the Export and Trade Control Law require export permission under the relevant legislation prior to export.Inquiries: Functional Devices Division, Device Sales Department, Device Sales SectionPh 03-5951-8131Fax 03-5951-8089Thank you July 1st, 19951. Outline1.1 Introduction (4)Characteristics (4)1.2Applications (4)1.31.4 Absolute Maximum Ratings (4)and Reference Output Capacities1.5 Equivalent Circuit and Dimensions (4)2. Block Diagram2.1 Block Diagram (5)2.2 Pin Function Description (5)3. Operation Description3.1 Start-up Circuit (6)3.2 On-trigger Circuit (7)3.3 Partial Resonance (7)3.4 Standby Mode Control (8)3.5 Output Voltage Control (9)3.6 Soft Drive Circuit (9)3.7 Circuit for Load Shorts (10)3.8 Collector Pin (pin 7) (10)3.9 Thermal Shut-down Circuit (TSD) (10)3.10 Over-voltage Protection Circuit (OVP) (10)3.11 Malfunction Prevention Circuit (11)(patent applied for)3.12 Over-current Protection Circuit (11)4. Standard Circuit (12)5. Design Procedures5.1 Design Flow Chart (13)5.2 Main Transformer Design Procedure (13)5.3 Main Transformer Design Examples (15)5.4 Selection of Constants for (18)Peripheral Components6. Cooling Design6.1 Junction Temperature and Power Losses (19)6.2 Junction Temperature (19)and Thermal Resistance6.3 Cautions for Cooling Design (19)The values presented in this document are based on tentative specifications as of June 29th, 2001, and may change in futureThe MR2900 Series IC modules are designed for both 200V and autosensing input with a burst-mode switching function at micro-loads. These modules are of the partial resonance type, and are comprised of a switching device optimized for both 200V and autosensing power supply input, and a control IC. They are designed to provide the following power supply characteristics.1.2 Characteristics1. An ultra high-speed IGBT with 900V resistance ensures high efficiency and low noise at partial resonance.2. An ultra high-speed IGBT with 900V resistance simplifies design for autosensing power supply input.3. Very low power consumption at micro-loads (in burst mode).4. Onboard start-up circuit eliminates the need for start-up resistors.5. Soft drive circuit achieves low noise levels.6. Excess current protection function (ton limit, primary current limit).7. Excess voltage protection and thermal shut-down function.8. Power supply circuits may be constructed with a minimum of external components. 9. The use of a full mold package provides benefits in insulation design.1.3 ApplicationsTVs, displays, printers, VTR, DVD, STB, air-conditioners, refrigerators, and other electrical appliances, and office equipment.1.4 Absolute Maximum Ratings and Reference Output CapacitiesAbsolute maximum ratingsMaximum output capacity P o ［W ］Peak input voltagePeak input currentInput voltage rangeModelV in ［V ］I in ［A ］90V to 276VAC180V to 276VACMR2920 7 100 150MR2940 90010 150 225Maximum output capacity and input voltage range differ with design conditions.1.5 Equivalent Circuit and DimensionsCollector GNDV ccEmitter/OCL F/BZ/C V in 4.5±0.54.2±0.5 4.25.0±0.2+0.27.6±0.52.7±0.20.7±0.22.2 Pin Function DescriptionPin numberAbbreviationDescription1Z/CTrigger input pinZero detection voltage: 0.35VStandby: Up to 4.5V in standby mode.2 F/B Feedback signal input pint on(min) to t on(max): 1.5V to 4.5V/0μs to 25μs Standby: Oscillation stopped at up to 0.8V. Standby: Oscillation started at 1.8V or higher.3 GND GND pin4 V cc IC power supply pinOscillation start voltage: V cc ≧14V Oscillation stop voltage: V cc ≦8.5V Excess voltage latching voltage:V cc =20V 5 V in Start pinCurrent supplied V in →V cc at start-up Start-up circuit OFF:V cc ≧14V Start-up circuit ON: V cc ≦7.6V6Emitter /OCL Main switching device emitter and current detection pin Excess current detection threshold:0.6VExcess current detection threshold at standby: 50mV7 Collecter Main switching device collector pinCollector Emitter/OCLV cc Z/C F/B V in GNDshort, oscillation is stopped when the voltage at the V cc pin reaches 8.5V, and when this voltage drops to 7.6V the start-up circuit operates again and the voltage at the V cc pin then begins rising. See Fig.3.2.Incorporation of the functions described above improve efficiency, particularly during standby, and reduces the number of start-up resistors required, thus reducing the overall number of components.The MR2000 Series employs current-critical operation to detect energy bursts at the secondary side of the main transformer and switch on the main switching device.Energy discharge timing is detected at the negative edge of the control coil voltage waveform (0.2V in the diagram at right), and the main switching device switched on for current-critical operation.The on-trigger detection voltage (0.2V) incorporates a 50mV hystersis to increase noise resistance.3.3 Partial ResonanceIn current-critical switching power supplies (RCC), damping begins at the resonance frequency (determined by the primary inductance L P of the main transformer and the resonating condenser C) when the secondary current in the circuit formed by connecting the resonating condenser between the collector and GND of the main switching device reaches 0A.The discharge current of the resonating condenser flows through the primary coil and returns energy to the input. Adjustment of the CR time constant applied to the Z/C pin (see diagram at right) allows the main switching device to be turned on at the trough of the damping voltage waveform, thus permitting a reduction in turn-on losses.In a circuit using partial resonance, the energy stored in the resonating condenser during the OFF period of the main switching device is returned to the input, thus permitting a reduction in turn-on losses. This allows the connection of a large-capacity condenser between the collector and GND of the main switching device, and thus permits a reduction in noise.The use of partial resonance is effective in permitting a simple circuit configuration with improved efficiency andnoise reduction.3.4 Standby Mode Control (patent applied for)The MR2000 Series is able to switch between two methodsof output voltage control - normal operation and the standbymode, in a single power supply.The standby mode supported by this IC employs the burst method for intermittent operation under light loads to reduce oscillation frequency and switching losses, and is effective in reducing the standby input voltage undermicro-loads.A unique characteristic of this IC is the use of the burstmode for intermittent operation without stopping IC control, and thus minimizing output ripple. The Z/C pin is clamped to a voltage of 4.5V (typical) or less by an external signal to allow selection of standby modecontrol. The standby mode is cleared (ie restored to thenormal mode) by clearing the clamp voltage on the Z/C pin, and applying a voltage of 4.5V (typical) or higher.In normal operation the ON range of the main switching device is controlled in a linear manner in relation to voltage variation at the F/B pin, while in standby mode operation the Emitter/OCL pin current detection threshold value isswitched from 0.6V for the normal mode to 0.05V for thestandby mode.The collector current is fixed at a peak value by the currentdetection threshold value, and the burst mode is selected.Burst mode control is such that oscillation occurs when the voltage at the F/B pin is 1.8V (typical) or higher, and isstopped when this voltage is 0.8V (typical) or lower.As output voltage control in the standby mode fixes thedrain current peak value for each oscillation cycle, the dutyratio of the oscillating and non-oscillating intervals is varied to ensure a constant voltage.3.5 Output Voltage Control (normal operation)The MR2000 Series controls output voltage with the ON range proportional to the voltage at the F/B pin.When the voltage at the F/B pin is 1.5V the ON range is 0µs, and is controlled in a linear manner so that when the voltage is 4.5V the ON range is 25µs. A current of 200µA=IF/B (typical) flows at the F/B pin, and the impedance of the photocoupler transistor connected externally between the F/B pin and GND is varied with the control signal from the secondary output detection circuit, thus controlling the ON range of the main switching device to produce a constant voltage.The maximum ON range is adjusted by setting the maximum value for the voltage at the F/B pin using a resistor connected externally between the F/B pin and GND.3.6 Soft Drive Circuit (patent applied for)The MR2000 Series supplies the main switching device gate drive voltage from two separate drive circuits.A voltage exceeding the threshold value for the main switching device is supplied from the first drive circuit at the leading edge of the drive voltage waveform to switch on the main switching device with the optimum timing.The drive voltage is then supplied gradually by the second drive circuit (see Fig.3.9).Supply of drive voltage in this manner reduces drive losses, as well as reducing noise due to gate charge current and discharge current when the resonating condenser is switched on.3.7 Circuit for Load ShortsThe MR2000 Series is designed so that when droop occurs under excessive load, output voltage drops, and control coil voltage drops in proportion.When the control coil voltage falls below 4.5V (typical) the standby mode is selected and the Emitter/OCL pin threshold voltage changes from 0.6V to 0.05V, thus limiting the collector current to approximately 1/10th of its previous value.This design permits a reduction in the stress on the MR2000 Series IC in the case of a load short, and control of the short-circuit current in the secondary diode and load circuit.3.8 Collector Pin (pin 7)The collector pin on the main switching device.The transformer is designed, and the resonating condenser adjusted, to ensure that V CE(max) is less than 900V.Depending upon input conditions, the collector pin may be subjected to reverse bias for a period during partial resonance.This IC employs an ultra high-speed IGBT in the main switching device. This device differs from MOSFET devices in that it has no body diode structure, thus requiring connection of an external high-speed diode between the Collector and Emitter/OCL pins.3.9 Thermal Shut-down Circuit (TSD)The MR2000 Series incorporates a thermal shut-down circuit.The onboard IC is latched at 150°C (typical) and oscillation is then stopped.Unlatch is achieved by momentarily dropping the voltage at the V cc pin to V UL (unlatch voltage) or lower.3.10 Over-voltage Protection Circuit (OVP)The MR2000 Series incorporates an over-voltage protection circuit (OVP).Latching occurs when the control coil voltage exceeds 20V (typical), and secondary output over-voltage protection then operates indirectly.Unlatch is achieved in the same manner as for the overheat protection circuit.3.11 Malfunction Prevention Circuit (patent applied for)The use of current-critical operation in the MR2000 Series ensures that the main transformer does not become saturated provided the droop setting is optimized.On the other hand, at start-up, and in the case of a load short, the output voltage is very much less than the set voltage.As the control coil voltage is proportional to the output voltage it also reaches an extremely small value, and the on-trigger timing may be incorrectly detected due to the ringing voltage while the device is OFF and switched on before the current-critical point.To counter this problem, the MR2000 Seriesincorporates a circuit to prevent on-trigger malfunction at start-up, and in the case of a load short. This function disables the on-trigger for a period of 2.7μs (typical) after the main switching device in the IC is switched OFF (on-dead time). This prevents incorrect detection due to the ringing voltage while the device is OFF.This design permits detection of the point at which the transformer secondary current is 0A at start-up, and in the case of a load short. The main switching device is then switched on at this point, allowing abnormal oscillation to be controlled.3.12 Over-current Protection CircuitA current detection resistor is connected between theEmitter/OCL pin and GND to detect current betweenthe emitter of the main switching device and the emitter current detection pin.During stable operation the main switching devicecurrent is limited by pulse-by-pulse operation with the0.6V threshold value.The leading edge clamp function preventsmalfunctioning and thus prevents incorrect detection atturn-on.During standby, the 50mV threshold value is selected and the oscillation noise from the transformer due to burst oscillation is reduced.V O NGND5.2 Main Transformer Design ProcedureThis design procedure provides an example of an electrical design procedure.Ensure that design of insulation materials, insulation configuration, and structure are in accordance with the necessary safety standards as determined by the relevant authorities.5.2.1 Standard Design ConditionsAbbreviation Unit ReferencevalueMinimum input voltage V AC(min) V ― Rated output voltage V o V ― Rated output current I o A ― Maximum output current I o(max) A ― Efficiencyη0.80～0.85Minimum oscillation frequency f (min) kHz 25k ～50kHz Duty ratio D 0.50～0.70 Control coil voltageV NC V 15～17V Effective cross-sectional area of transformer core A e mm 2― Magnetic flux density variation ΔB mT 250～320mTCoil current densityα A/mm 24～6A/mm 2Note that the above values are for reference only, and should be adjusted to suit load conditions.ReexaminationgReview transformer core size and oscillation frequency and redesign if I g is 1mm or greater.V FNC is the control coil voltage rectification diode forward voltage.The reference value for determining the control coil voltage V NC(min) is 15V to 17V.If the V NC(min) value is too small, start-up characteristics may deteriorate and start-up may become difficult. If the V NC(min) value is too large, the over-voltage latch stop voltage V OP is able to be reached easily. Check the V NC(min) voltage in an actual circuit during the design process to determine its optimum value.A NC C5.3 Main Transformer Design Examples5.3.1 Initial SetupInput voltage AC90～276V V O1：DC135V, 0.45A Efficiency 85% V O2：DC35V,0.40ARated output V O3：DC16V,0.40ATotal output 81.2W Oscillationfrequency at droop 29.6kHzDroop output110.36W (rated output x 1.36) Duty ratioT ON /T=0.655P on(max) is s or less. L °C isq μs.q andS1S2S35.4 Selection of Constants for Peripheral ComponentsT j(max) for the MR Series is 150°C.As operation of the MR Series is accompanied by an increase in temperature associated with power losses, it is necessary to consider the type of heat sink to be used. While a design which ensures that T j(max) is not exceeded is of absolute importance, the overheat protection function (T SD =150°C (typical)) must be also considered in any design. The extent to which T j is derated in a design is therefore extremely important in improving reliability.The majority of power losses during operation of the MR Series are associated with the internal MOSFET.If the majority of power losses are considered as ON losses, they may be expressed by the following equation.P D =V DS ×I DThe temperature increase (ΔT j ) due to power losses (P D ) is expressed as,ΔT j +T a ≦T j(max)and if T SD =150°C (typical) and T SD(min)=120°C are assumed, P D is limited so that the following equation is satisfied.ΔT j +T a ≦T SD(min)T j may be calculated as follows using the thermal resistance θja .T j =( P D ×θja ) +T aθja is the thermal resistance in the vicinity of the junction, and is expressed as follows.θja =θjc +θcf +θfaThermal shutdown (TSD) is a protective function which stops and latches operation at 150°C in the event of abnormal heating of the MR1520. Circuit design therefore requires a cooling design in which temperature has been sufficiently derated. Shindengen recommends that cooling design be such that case temperature does not exceed 100°C.6.1 Junction Temperature and Power Losses 6.2 Junction Temperature and Thermal Resistance Abbreviation UnitThermal resistance between junction and vicinity. θja ℃/WThermal resistance between junction and case. θjc ℃/WThermal resistance between case and fins(contact thermal resistance).θcf ℃/W Thermal resistance between case and fins(contact thermal resistance).θfa ℃/W 6.3 Cautions for Cooling Design。
国家及地区代码-V1.1
地区代码 004 184 200 007 006 001 009 131 005 212 008 003 013 012 010 014 213 018 017 020 031 030 016 033 022 202 023 029 025 027 015 024 214 026 019 021 036 215 044 039 043 173 093 047 045 041 035 011 042 216 046 204 037 217 049 050 071 052 051 053 054 002 055 060 056 218 059
南苏丹
South Sudan
249
169 NT
中立区
Neutral Zone
229
170 NU
纽埃
Niue
230
171 NZ
纽西兰
New Zealand
133
172 OM
阿曼
Oman
138
173 PA
巴拿马
Panama
141
174 PE
秘鲁
Peru
144
175 PF
法属玻里尼西亚
French Polynesia
地区简称 AD AE AF AG AI AL AM AN AO AQ AR AS AT AU AW AZ BA BB BD BE BF BG BH BI BJ BL BM BN BO BR BS BT BV BW BY BZ CA CC CD CF CG CH CI CI CK CL CM CN CO CQ CR CU CV CX CY CZ DE DJ DK DM DO DZ EC EE EG EH ER
Norfolk Island
227
EN29LV640L-90TIP资料
FEATURES• Single power supply operation- Full voltage range: 2.7 to 3.6 volts for read, erase and program operations• Low power cons umption (typical values at 5 MHz)- 9 mA typical active read current- 20 mA typical program/erase current- Less than 1 μA current in standby or automatic sleep mode.• JEDEC standards compatible- Pinout and software compatible with single-power supply Flash standard• Manufactured on 0.18μm process technology• Flexible Sector Architecture:- One hundred and twenty-eight 32K-Word /64K-byte sectors.• Minimum 100K program/erase endurance cycles.• High performance for program and erase - Word program time: 8µs typical - Sector Erase time: 500ms typical - Chip Erase time: 64s typical • Package Options - 48-pin TSOP - 48-ball FBGASoftware features: • Sector Group Protection- Provide locking of sectors to prevent program or erase operations within individual sectors - Additionally, temporary Sector GroupUnprotect allows code changes in previously protected sectors. • Standard DATA# polling and toggle bits feature• Unlock Bypass Program command supported • Sector Erase Suspend / Resume modes: Read and program another Sector during Sector Erase Suspend Mode• Support JEDEC Common Flash Interface (CFI).Hardware features:• Pin compatible to lower density, easy replacement for code expansion. • RESET# hardware reset pin- Hardware method to reset the device to read mode. • WP#/ACC input pin- Write Protect (WP#) function allowsprotection of first or last 32K-word sector, regardless of previous sector protect status - Acceleration (ACC) function provides accelerated program timesGENERAL DESCRIPTIONThe EN29LV640H/L / EN29LV640U is a 64-Megabit ( 4Mx16 ), electrically erasable, read/write non-volatile flash memory. Any word can be programmed typically in 8µs. This device is entirely command set compatible with the JEDEC single-power-supply Flash standard.The EN29LV640H/L / EN29LV640U is designed to allow either single Sector or full Chip erase operation, where each Sector Group can be protected against program/erase operations or temporarily unprotected to erase or program. The device can sustain a minimum of 100K program/erase cycles on each Sector.EN29LV640 64 Megabit (4M x 16-bit ) CMOS 3.0 Volt-only, Uniform Sector Flash MemoryPRODUCT SELECTOR GUIDEProduct Number EN29LV640H/LEN29LV640USpeed OptionFull Voltage Range: V CC =2.7 – 3.6 V90 90 Max Access Time (ns) 90 90 Max CE# Access Time (ns) 90 90 Max OE# Access Time (ns) 3535BLOCK DIAGRAMWE# CE# OE#State ControlCommand RegisterErase Voltage GeneratorInput/Output BuffersProgram Voltage GeneratorChip Enable Output EnableLogicData LatchY-Decoder X-Decoder Y-GatingCell MatrixTimerV CC DetectorA21-A0V CC V SS DQ15-DQ0Address LatchSector Protect SwitchesSTBSTBWP#/ ACC RY/BY#RESET#CONNECTION DIAGRAMSTABLE 1. PIN DESCRIPTIONLOGIC DIAGRAMDQ15 – DQ0A21 – A0WE#CE#RY/BY#OE#RESET#WP# / ACCPin Name Function A21-A0 22 Address inputs DQ15-DQ0 16 Data Inputs/Outputs CE# Chip Enable Input OE# Output Enable Input WE#Write Enable InputWP#/ACC Write Protect / Acceleration Pin RY/BY# Ready/Busy status output RESET# Hardware Reset Input Pin V cc Supply Voltage (2.7-3.6V) V ss GroundNCNot Connected to anythingORDERING INFORMATIONEN29LV640 H ─90 T C PPACKAGING CONTENT(Blank) = ConventionalP = Pb FreeTEMPERATURE RANGEI = Industrial (-40°C to +85°C)C = Commercial (0°C to +70°C)PACKAGET = 48-pin TSOPB = 48-Ball Fine Pitch Ball Grid Array (FBGA)0.80mm pitchSPEED OPTIONSee Product Selector Guide and Valid CombinationsSECTOR for WRITE PROTECT (WP#/ACC=0)H=highestaddresssectorprotectedL=lowestaddresssectorprotectedBASE PART NUMBEREN29LV640 / EN29LV640U64 Megabit(4M x 16-Bit) Uniform Sector Flash3V Read, Erase and ProgramPRODUCT SELECTOR GUIDEValid Combinations VccEN29LV640H–90 EN29LV640L–90 TI, TCBI,BCV cc = 2.7V-3.6VTable 2. Sector (Group) Address Tables Sector GroupProtect/UnprotectSector Address Range for Sector EraseSector Group A21-A17 Sector A21A20A19A18A17A16A15Address Range(hexadecimal) SA0 0 0 0 0 0 0 0 000000–007FFFSA1 0 0 0 0 0 0 1 008000–00FFFFSA2 0 0 0 0 0 1 0 010000–017FFFSG0 00000SA3 0 0 0 0 0 1 1 018000–01FFFFSA4 0 0 0 0 1 0 0 020000–027FFFSA5 0 0 0 0 1 0 1 028000–02FFFFSA6 0 0 0 0 1 1 0 030000–037FFF SG100001SA7 0 0 0 0 1 1 1 038000–03FFFFSA8 0 0 0 1 0 0 0 040000–047FFFSA9 0 0 0 1 0 0 1 048000–04FFFFSA10 0 0 0 1 0 1 0 050000–057FFF SG200010SA11 0 0 0 1 0 1 1 058000–05FFFFSA12 0 0 0 1 1 0 0 060000–067FFFSA13 0 0 0 1 1 0 1 068000–06FFFFSA14 0 0 0 1 1 1 0 070000–077FFF SG300011SA15 0 0 0 1 1 1 1 078000–07FFFFSA16 0 0 1 0 0 0 0 080000–087FFFSA17 0 0 1 0 0 0 1 088000–08FFFFSA18 0 0 1 0 0 1 0 090000–097FFF SG4 00100SA19 0 0 1 0 0 1 1 098000–09FFFFSA20 0 0 1 0 1 0 0 0A0000–0A7FFFSA21 0 0 1 0 1 0 1 0A8000–0AFFFFSA22 0 0 1 0 1 1 0 0B0000–0B7FFF SG5 00101SA23 0 0 1 0 1 1 1 0B8000–0BFFFFSA24 0 0 1 1 0 0 0 0C0000–0C7FFFSA25 0 0 1 1 0 0 1 0C8000–0CFFFFSA26 0 0 1 1 0 1 0 0D0000–0D7FFF SG6 00110SA27 0 0 1 1 0 1 1 0D8000–0DFFFFSA28 0 0 1 1 1 0 0 0E0000–0E7FFFSA29 0 0 1 1 1 0 1 0E8000–0EFFFFSA30 0 0 1 1 1 1 0 0F0000–0F7FFF SG700111SA31 0 0 1 1 1 1 1 0F8000–0FFFFFSector Group A21-A17 Sector A21 A20A19A18A17A16A15Address Range(hexadecimal) SA32 0 1 0 0 0 0 0 100000–107FFFSA33 0 1 0 0 0 0 1 108000–10FFFFSA34 0 1 0 0 0 1 0 110000–117FFFSG8 01000SA35 0 1 0 0 0 1 1 118000–11FFFFSA36 0 1 0 0 1 0 0 120000–127FFFSA37 0 1 0 0 1 0 1 128000–12FFFFSA38 0 1 0 0 1 1 0 130000–137FFF SG9 01001SA39 0 1 0 0 1 1 1 138000–13FFFFSA40 0 1 0 1 0 0 0 140000–147FFFSA41 0 1 0 1 0 0 1 148000–14FFFFSA42 0 1 0 1 0 1 0 150000–157FFF SG10 01010SA43 0 1 0 1 0 1 1 158000–15FFFFSA44 0 1 0 1 1 0 0 160000–167FFFSA45 0 1 0 1 1 0 1 168000–16FFFFSA46 0 1 0 1 1 1 0 170000–177FFF SG11 01011SA47 0 1 0 1 1 1 1 178000–17FFFFSA48 0 1 1 0 0 0 0 180000–187FFFSA49 0 1 1 0 0 0 1 188000–18FFFFSA50 0 1 1 0 0 1 0 190000–197FFF SG12 01100SA51 0 1 1 0 0 1 1 198000–19FFFFSA52 0 1 1 0 1 0 0 1A0000–1A7FFFSA53 0 1 1 0 1 0 1 1A8000–1AFFFFSA54 0 1 1 0 1 1 0 1B0000–1B7FFF SG13 01101SA55 0 1 1 0 1 1 1 1B8000–1BFFFFSA56 0 1 1 1 0 0 0 1C0000–1C7FFFSA57 0 1 1 1 0 0 1 1C8000–1CFFFFSA58 0 1 1 1 0 1 0 1D0000–1D7FFF SG14 01110SA59 0 1 1 1 0 1 1 1D8000–1DFFFFSA60 0 1 1 1 1 0 0 1E0000–1E7FFFSA61 0 1 1 1 1 0 1 1E8000–1EFFFFSA62 0 1 1 1 1 1 0 1F0000–1F7FFF SG15 01111SA63 0 1 1 1 1 1 1 1F8000–1FFFFFSector Group A21-A17 Sector A21A20A19A18A17A16A15Address Range(hexadecimal) SA64 1 0 0 0 0 0 0 200000–207FFFSA65 1 0 0 0 0 0 1 208000–20FFFFSA66 1 0 0 0 0 1 0 210000–217FFFSG16 10000SA67 1 0 0 0 0 1 1 218000–21FFFFSA68 1 0 0 0 1 0 0 220000–227FFFSA69 1 0 0 0 1 0 1 228000–22FFFFSA70 1 0 0 0 1 1 0 230000–237FFF SG1710001SA71 1 0 0 0 1 1 1 238000–23FFFFSA72 1 0 0 1 0 0 0 240000–247FFFSA73 1 0 0 1 0 0 1 248000–24FFFFSA74 1 0 0 1 0 1 0 250000–257FFF SG1810010SA75 1 0 0 1 0 1 1 258000–25FFFFSA76 1 0 0 1 1 0 0 260000–267FFFSA77 1 0 0 1 1 0 1 268000–26FFFFSA78 1 0 0 1 1 1 0 270000–277FFF SG1910011SA79 1 0 0 1 1 1 1 278000–27FFFFSA80 1 0 1 0 0 0 0 280000–287FFFSA81 1 0 1 0 0 0 1 288000–28FFFFSA82 1 0 1 0 0 1 0 290000–297FFF SG2010100SA83 1 0 1 0 0 1 1 298000–29FFFFSA84 1 0 1 0 1 0 0 2A0000–2A7FFFSA85 1 0 1 0 1 0 1 2A8000–2AFFFFSA86 1 0 1 0 1 1 0 2B0000–2B7FFF SG2110101SA87 1 0 1 0 1 1 1 2B8000–2BFFFFSA88 1 0 1 1 0 0 0 2C0000–2C7FFFSA89 1 0 1 1 0 0 1 2C8000–2CFFFFSA90 1 0 1 1 0 1 0 2D0000–2D7FFF SG2210110SA91 1 0 1 1 0 1 1 2D8000–2DFFFFSA92 1 0 1 1 1 0 0 2E0000–2E7FFFSA93 1 0 1 1 1 0 1 2E8000–2EFFFFSA94 1 0 1 1 1 1 0 2F0000–2F7FFF SG2310111SA95 1 0 1 1 1 1 1 2F8000–2FFFFFSector Group A21-A17 Sector A21A20A19A18A17A16A15Address Range(hexadecimal) SA96 1 1 0 0 0 0 0 300000–307FFFSA97 1 1 0 0 0 0 1 308000–30FFFFSA98 1 1 0 0 0 1 0 310000–317FFFSG24 11000SA99 1 1 0 0 0 1 1 318000–31FFFFSA100 1 1 0 0 1 0 0 320000–327FFFSA101 1 1 0 0 1 0 1 328000–32FFFFSA102 1 1 0 0 1 1 0 330000–337FFF SG25 11001SA103 1 1 0 0 1 1 1 338000–33FFFFSA104 1 1 0 1 0 0 0 340000–347FFFSA105 1 1 0 1 0 0 1 348000–34FFFFSA106 1 1 0 1 0 1 0 350000–357FFF SG26 11010SA107 1 1 0 1 0 1 1 358000–35FFFFSA108 1 1 0 1 1 0 0 360000–367FFFSA109 1 1 0 1 1 0 1 368000–36FFFFSA110 1 1 0 1 1 1 0 370000–377FFF SG27 11011SA111 1 1 0 1 1 1 1 378000–37FFFFSA112 1 1 1 0 0 0 0 380000–387FFFSA113 1 1 1 0 0 0 1 388000–38FFFFSA114 1 1 1 0 0 1 0 390000–397FFF SG28 11100SA115 1 1 1 0 0 1 1 398000–39FFFFSA116 1 1 1 0 1 0 0 3A0000–3A7FFFSA117 1 1 1 0 1 0 1 3A8000–3AFFFFSA118 1 1 1 0 1 1 0 3B0000–3B7FFF SG29 11101SA119 1 1 1 0 1 1 1 3B8000–3BFFFFSA120 1 1 1 1 0 0 0 3C0000–3C7FFFSA121 1 1 1 1 0 0 1 3C8000–3CFFFFSA122 1 1 1 1 0 1 0 3D0000–3D7FFF SG30 11110SA123 1 1 1 1 0 1 1 3D8000–3DFFFFSA124 1 1 1 1 1 0 0 3E0000–3E7FFFSA125 1 1 1 1 1 0 1 3E8000–3EFFFFSA126 1 1 1 1 1 1 0 3F0000–3F7FFF SG31 11111SA127 1 1 1 1 1 1 1 3F8000–3FFFFF Note: The sizes of all sectors are 32K-word.USER MODE DEFINITIONSTABLE 3. BUS OPERATIONSOperation CE#OE#WE#RESET#WP#/ACC A21-A0DQ15-DQ0 Read LLHHL/HA IN D OUTWrite LHLH(Note1)A IN(Note 3)AcceleratedProgramL H L H V HH A IN(Note 3)CMOS Standby V cc±0.3V X X V cc±0.3VH XHigh-ZTTL Standby H X X H L / H X High-Z Output Disable L H H H L / H X High-Z Hardware Reset X X X L L / H X High-ZSector Group Protect (Note 2) L H L V ID HSA,A6=L,A1=H,A0=L(Note 3)Sector GroupUnprotect (Note 2) L H L V ID HSA,A6=H,A1=H,A0=L(Note 3)TemporarySector GroupUnprotectX X X V ID H A IN(Note 3)L=logic low= V IL, H=Logic High= V IH, V ID= V HH = 11 ± 0.5V = 10.5 ─ 11.5V, X=Don’t Care (eitherL or H, but not floating!), SA=Sector Addresses (A21-A15), D IN=Data In, D OUT=Data Out,A IN=Address InNotes:1. If the system asserts V IL on the WP# / ACC pin, the device disables program and erasefunctions in the first or last sector independent of whether those sectors were protected orunprotected; if the system asserts V IH on the WP# /ACC pin, the device reverts to whether thefirst or last sector was previously protected or unprotected. If WP# / ACC = V HH, all sectors willbe unprotected.2. Please refer to “Sector Group Protection & Unprotection”, Flowchart 6a and Flowchart 6b.3. D IN or D OUT as required by command sequence, data polling, or sector protect algorithm.Read ModeThe device is automatically set to reading array data after device power-up or hardware reset. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithmAfter the device accepts an Sector Erase Suspend command, the device enters the Sector Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing aprogramming operation in the Sector Erase Suspend mode, the system may once again read array data with the same exception. See “Sector Erase Suspend/Resume Commands” for more additional information.The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high or while in the autoselect mode. See the “Reset Command” for additional details.Output Disable ModeWhen the OE# pin is at a logic high level (V IH), the output from the device is disabled. The output pins are placed in a high impedance state.Standby ModeThe device has a CMOS-compatible standby mode, which reduces the c urrent to < 1µA (typical). It is placed in CMOS-compatible standby when the CE# pin is at V CC± 0.5. RESET# and BYTE# pin must also be at CMOS input levels. The device also has a TTL-compatible standby mode, which reduces the maximum V CC c urrent to < 1mA. It is placed in TTL-compatible standby when the CE# pin is at V IH. When in standby modes, the outputs are in a high-impedance state independent of the OE# input.Automatic Sleep ModeThe device has an automatic sleep mode, which minimizes power consumption. The devices will enter this mode automatically when the states of address bus remain stable for t acc + 30ns. ICC4 in the DC Characteristics table shows the current specification. With standard access times, the device will output new data when addresses change.Writing Command SequencesTo write a command or command sequence to program data to the device or erase data, the system has to drive WE# and CE# to V IL, and OE# to V IH.The device has an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four.The system can also read the autoselect codes by entering the autoselect mode, which need the autoselect command sequence to be written. Please refer to the “Command Definitions” for all the available commands.Autoselect Identification ModeThe autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ15–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register.When using programming equipment, the autoselect mode requires V ID(10.5 V to 11.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when verifying sector group protection, the sector group address must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The “Command Definitions” table shows the remaining address bits that are don’t-care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15–DQ0. To access the autoselect codes in-system; the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require V ID. See“Command Definitions” for details on using the autoselect mode. Note that a Reset command is required to return to read mode when the device is in the autoselect mode.TABLE 4. Autoselect Codes (Using High Voltage, V ID )L=logic low= V IL , H=Logic High= V IH , V ID =11 ± 0.5V, X=Don’t Care (either L or H, but not floating!), SA=Sector AddressesNote:1. A8=H is recommended for Manufacturing ID check. If a manufacturing ID is read with A8=L, the chip will output a configuration code 7Fh.2. A9 = V ID is for HV A9 Autoselect mode only. A9 must be ≤ Vcc (CMOS logic level) for Command AutoselectMode.RESET#: Hardware ResetWhen RESET# is driven low for t RP , all output pins are tristates. All commands written in the internal state machine are reset to reading array data.Please refer to timing diagram for RESET# pin in “AC Characteristics”.Sector Group Protection & UnprotectionThe hardware sector group protection feature disables both program and erase operations in any sector group. The hardware chip unprotection feature re-enables both program and erase operations in previously protected sector group. A sector group consists of four adjacent sectors that would be protected at the same time. Please see Table 2 which show the organization of sector groups.There are two methods to enable this hardware protection circuitry. The first one requires only that the RESET# pin be at V ID and then standard microprocessor timings can be used to enable or disable this feature. See Flowchart 6a and 6b for the algorithm and Figure 11 for the timings.When doing Sector Group Unprotect, all the unprotected sector groups must be protected prior to any unprotect write cycle.The second method is for programming equipment. This method requires V ID to be applied to both OE# and A9 pins and non-standard microprocessor timings are used. This method is described in a separate document, the Datasheet Supplement of EN29LV640H/L ; EN29LV640U, which can be obtained by contacting a representative of Eon Silicon Solution, Inc.Description CE# OE# WE# A21toA15 A14 to A10A92A8A7A6A5 to A2A1 A0 DQ15 to DQ0H1XX1Ch Manufacturer ID: Eon L L H X X V IDLX L XL LXX7FhAutoselect Device ID L L H X X V IDX X L X L H 227Eh Sector Protection VerificationL L H SA X V IDX X L X H LXX01h(Protected)XX00h(Unprotected)Write Protect / Accelerated Program (WP# / ACC)The Write Protect function provides a hardware method to protect the first or last sector against erase and program without using V ID.When WP# is Low, the device protects the first or last sector regardless of whether these sectors were previously protected or unprotected using the method described in “Sector Group Protection & Unprotection”, Program and Erase operations in these sectors are ignored.When WP# is High, the device reverts to the previous protection status of the first or last sector. Program and Erase operations can now modify the data in those sectors unless the sector is protected using Sector Group Protection.Note that the WP# pin must not be left floating or unconnected.When WP#/ACC is raised to V HH the memory automatically enters the Unlock Bypass mode(please refer to “Command Definitions”), temporarily unprotects every protected sectors, and reduces the time required for program operation. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. When WP#/ACC returns to V IH or V IL, normal operation resumes. The transitions from V IH or V IL to V HH and from V HH to V IH or V IL must be slower than t V HH, see Figure 5. Note that the WP#/ACC pin must not be left floating or unconnected. In addition, WP#/ACC pin mustnot be at V HH for operations other than accelerated programming. It could cause the device to be damaged.Never raise this pin to V HH from any mode except Read mode, otherwise the memory may be left in an indeterminate state.A 0.1µF capacitor should be connected between the WP#/ACC pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Unlock Bypass Program.Temporary Sector Group UnprotectThis feature allows temporary unprotection of previously protected sector groups to change data while in-system. The Temporary Sector Group Unprotect mode is activated by setting the RESET# pin to V I D. During this mode, formerly protected sector groups can be programmed or erased by simply selecting the sector group addresses. Once V I D is removed from the RESET# pin, all the previously protected sector groups are protected again. See accompanying flowchart and timing diagrams in Figure 10 for more details.StartReset#=V ID(note 1) Perform Erase or ProgramOperationsRESET#=V IH Temporary Sector Group Unprotect Completed (note 2)Notes:1. All protected sector groups are unprotected. (If WP#/ACC=V IL, the first or last sector will remain protected.)2. Previously protected sector groups are protected again.COMMON FLASH INTERFACE (CFI)The common flash interface (CFI) specification outlines device and host systems software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility.This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data.The system can read CFI information at the addresses given in Tables 5-8.The upper address bits (A7–MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command.The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode and the system can read CFI data at the addresses given in Tables 5–8. The system must write the reset command to return the device to the autoselect mode.Table 5. CFI Query Identification StringAddresses Data Description10h 11h 12h 0051h0052h0059hQuery Unique ASCII string “QRY”13h 14h 0002h0000hPrimary OEM Command Set15h 16h 0040h0000hAddress for Primary Extended Table17h 18h 0000h0000hAlternate OEM Command set (00h = none exists)19h 1Ah 0000h0000hAddress for Alternate OEM Extended Table (00h = none exists)Table 6. System Interface StringAddresses Data Description1Bh 0027h Vcc Min (write/erase)DQ7-DQ4: volt, DQ3 –DQ0: 100 millivolt1Ch 0036h Vcc Max (write/erase)DQ7-DQ4: volt, DQ3 –DQ0: 100 millivolt1Dh 0000h Vpp Min. voltage (00h = no Vpp pin present)1Eh 0000h Vpp Max. voltage (00h = no Vpp pin present)1Fh 0003h Typical timeout per single byte/word write 2NμS20h 0000h Typical timeout for Min, size buffer write 2NμS (00h = not supported) 21h 000Ah Typical timeout per individual block erase 2N ms22h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)23h 0005h Max. timeout for byte/word write 2N times typical24h 0000h Max. timeout for buffer write 2N times typical25h 0002h Max. timeout per individual block erase 2N times typical26h 0000h Max timeout for full chip erase 2N times typical (00h = not supported)Table 7. Device Geometry DefinitionAddresses Data Description27h 0017h Device Size = 2Nbytes 28h 29h 0001h0000h Flash Device Interface description (refer to CFI publication 100)2Ah 2Bh 0000h 0000h Max. number of byte in multi-byte write = 2N (00h = not supported) 2Ch 0001h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 007Fh 0000h 0000h 0001h Erase Block Region 1 Information (refer to the CFI specification of CFI publication 100) 31h 32h 33h 34h 0000h 0000h0000h 0000h Erase Block Region 2 Information35h 36h 37h 38h 0000h 0000h0000h 0000h Erase Block Region 3 Information39h 3Ah 3Bh 3Ch 0000h 0000h0000h 0000hErase Block Region 4 InformationTable 8. Primary Vendor-specific Extended QueryAddresses Data Description40h 41h 42h 0050h 0052h 0049h Query-unique ASCII string “PRI” 43h 0031h Major version number, ASCII 44h 0033h Minor version number, ASCII45h 0004hAddress Sensitive Unlock0 = Required, 1 = Not Required 46h 0002hErase Suspend0 = Not Supported, 1 = To Read Only, 2 = To Read & Write 47h 0004hSector Protect0 = Not Supported, X = Number of sectors in per group 48h 0001hSector Temporary Unprotect00 = Not Supported, 01 = Supported 49h 0004h Sector Protect/Unprotect scheme01 = 29F040 mode, 02 = 29F016 mode,03 = 29F400 mode, 04 = 29LV800A mode 4Ah 0000hSimultaneous Operation00 = Not Supported, 01 = Supported 4Bh 0000hBurst Mode Type00 = Not Supported, 01 = Supported 4Ch 0000hPage Mode Type00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page 4Dh 00A5hMinimum WP#/ACC (Acceleration) Supply Voltage00 = Not Supported, DQ7-DQ4 : Volts, DQ3-DQ0 : 100mV 4Eh 00B5hMaximum WP#/ACC (Acceleration) Supply Voltage00 = Not Supported, DQ7-DQ4 : Volts, DQ3-DQ0 : 100mV4Fh 00XXh 00h = Uniform Sector DevicesHardware Data protectionThe command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes as seen in the Command Definitions table. Additionally, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by false system level signals during Vcc power up and power down transitions, or from system noise.Low V CC Write InhibitWhen V CC is less than V LKO, the device does not accept any write cycles. This protects data during V CC power up and power down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until V CC is greater than V LKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than V LKO.Write Pulse “Glitch” protectionNoise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.Logical InhibitWrite cycles are inhibited by holding any one of OE# = V IL, CE# = V IH, or WE# = V IH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE# are all logical zero (not recommended usage), it will be considered a read.Power-up Write InhibitDuring power-up, the device automatically resets to READ mode and locks out write cycles. Even with CE# = V IL, WE#= V IL and OE# = V IH, the device will not accept commands on the rising edge of WE#.COMMAND DEFINITIONSThe operations of the device are selected by one or more commands written into the commandregister. Commands are made up of data sequences written at specific addresses via the command register. The sequences for the specified operation are defined in the Command Definitions table (Table 9). Incorrect addresses, incorrect data values or improper sequences will reset the device to Read Mode.Table 9. EN29LV640H/L / EN29LV640U Command DefinitionsBus Cycles (Note 1-2)1stCycle 2ndCycle3rdCycle4thCycle5thCycle6thCycleCommand Sequence C y c l e sAddr DataAddr DataAddr DataAddr DataAddr DataAddr DataRead (Note 3)1RA RD Reset 1xxx F0 Manufacturer ID 4555 AA 2AA 55 55590000 1007F 1CDevice ID 4555 AA 2AA 55 55590 X01 227E A u t o s e l e c tSector Protect Verify (Note 4)4555 AA 2AA 55 55590(SA)X02XX00 XX01Program 4555 AA 2AA 55 555A0 PA PD Unlock Bypass 3555 AA 2AA 55 55520 Unlock Bypass Program2XXX A0 PA PD Unlock Bypass Reset 2XXX90XXX00Chip Erase 6555 AA 2AA 55 55580 555 AA 2AA 55 55510Sector Erase 6555 AA 2AA 55 55580 555 AA 2AA 55 SA 30 Sector Erase Suspend 1BA B0 Sector Erase Resume 1BA 30 CFI Query 15598Address and Data values indicated are in hex. Unless specified, all bus cycles are write cycles RA = Read Address: address of the memory location to be read. This is a read cycle. RD = Read Data: data read from location RA during Read operation. This is a read cycle. PA = Program Address: address of the memory location to be programmed. X = Don’t-Care PD = Program Data: data to be programmed at location PASA = Sector Address: address of the Sector to be erased or verified (in Autoselect mode).Address bits A21-A15 uniquely select any Sector.Notes:1. Data bits DQ15-DQ8 are don’t care in command sequences, except for RD and PD.2. Unless otherwise noted, address bits A21-A15 are don’t cares.3. No unlock or command cycles required when device is in read mode.4. The data is 00h for an unprotected sector group and 01h for a protected sector group.。
VL900说明书
感谢您选用沃陆变频器！同时，你将享受到我们为您提供的全面、真诚的服务！VL900简易型变频器是高品质、多功能变频器。
该系列变频器能够在多种场合满足您的需求。
本手册为用户提供安装调试、参数设定、操作使用、故障诊断及日常维护的有关注意事项，在安装、使用前请仔细阅读，正确操作。
本手册随变频器一起提供，并请妥善保管，以备以后查阅和维护使用。
目录一,安全使用…………………………………1-2页二,产品简介…………………………………3-6页三,安装配线…………………………………7-17页四,运行操作说明……………………………18-22页五功能参数表………………………………23-41页六,详细功能说明……………………………42-100页七,故障诊断及异常处理……………………101-105页八,保养和维护………………………………106-107页I♦变频器的存放、安装应避开强振动、强腐蚀、高粉尘、高温、高湿的环境。
♦应定期检查变频器输入输出接线是否正确及设备其它电线是否老化。
♦电机绝缘强度要在安装、运行前进行检查。
♦电机经常低速运转工作时，要对电机采取额外冷却措施。
有频繁起动场合和能量回馈时，要采用制动电阻或制动单元，防频繁过压或过流。
12♦ 不要在变频器输出端连接可变电阻器和电容以试图提高功率因数。
不要在变频器输出与电机之间安装断路器，如果必须安装，则要保证断路器仅在变频器输出电流为零时动作。
♦ VL900型变频器的防护等级为IP20。
♦变频器使用1～3个月后，建议对内部器件和散热器进行清洁处理。
如长时间不用，应间隔一定时间（建议一个月）给变频器通电一次。
阅读提示：危险！会引起人身伤亡和财产损失的不正确操作与安装，不正确的使用产品！警告！会引起人身伤害和财产损失的不正确操作与 安装，不正确的使用产品！注意！会影响变频器性能的不正确操作3二：产品简介2.1型号及铭牌产品型号意义为（以三相2.2KW 带内置制动单元的变频器为例）：A-不带制动 B-带制动系列代号：G ：通用型；P ：水泵型功率等级：0022：2.2KW电压等级 ：S ：单相/三相220V品系列代码图2－1VL900型系列变频器的铭牌如图2-2所示（以三相输入、2.2KW 变频器为例）。
Vigor2920 系
Vigor2920 系列雙WAN安全防護路由器快速安裝手冊版本: 1.0韌體版本: V3.3.3.1日期: 19/07/2010因手冊更新無法及時通知用戶，請隨時連上居易網站，取得最新的手冊內容。
版權資訊版權聲明© 2010版權所有，翻印必究。
此出版物所包含資訊受版權保護。
未經版權所有人書面許可，不得對其進行拷貝、傳播、轉錄、摘錄、儲存到檢索系統或轉譯成其他語言。
交貨以及其他詳細資料的範圍若有變化，恕不預先通知。
商標本手冊內容使用以下商標:z Microsoft為微軟公司註冊商標z Windows視窗系列，包括Windows 95, 98, Me, NT, 2000, XP 以及其Explorer均屬微軟公司商標z Apple以及Mac OS均屬蘋果電腦公司的註冊商標z其他產品則為各自生產廠商之註冊商標安全說明和保障安全說明z在設置前請先閱讀安裝說明。
z由於路由器是複雜的電子產品，請勿自行拆除或是維修本產品。
z請勿自行打開或修復路由器。
z請勿把路由器置於潮濕的環境中，例如浴室。
z請將本產品放置在足以遮風避雨之處，適合溫度在攝氏5度到40度之間。
z請勿將本產品暴露在陽光或是其他熱源下，否則外殼以及零件可能遭到破壞。
z請勿將LAN網線置於戶外，以防電擊危險。
z請將本產品放置在小孩無法觸及之處。
z若您想棄置本產品時，請遵守當地的保護環境的法律法規。
保固自使用者購買日起二年內為保固期限，請將您的購買收據保存二年，因為它可以證明您的購買日期。
當本產品發生故障乃導因於製作及(或)零件上的錯誤，只要使用者在保固期間內出示購買證明，居易科技將採取可使產品恢復正常之修理或更換有瑕疵的產品(或零件)，且不收取任何費用。
居易科技可自行決定使用全新的或是同等價值且功能相當的再製產品。
下列狀況不在本產品的保固範圍內：(1)若產品遭修改、錯誤(不當)使用、不可抗力之外力損害，或不正常的使用，而發生的故障；(2) 隨附軟體或是其他供應商提供的授權軟體；(3) 未嚴重影響產品堪用性的瑕疵。
AT90CAN128中文资料
特点•高性能，低功耗的A VR ® 8位微控制器•先进的RISC结构- 133 - 最强大的单时钟周期指令执行- 32个8位通用工作寄存器+外设控制寄存器- 全静态工作- 高达16 MIPS的吞吐量为16兆赫- 片2周期乘法器•非挥发性程序和数据存储器- 在系统内32K/64K/128K字节可重编程闪存（A T90CAN32/64/128）•耐久性：10,000写入/擦除周期- 可选启动代码段与独立锁定位•可选启动大小：1K字节，2K字节，4K字节或8K 字节•在系统编程的片上引导程序（CAN总线，UART 的，...）•真正的了解，同时，写操作- 1K/2K/4K字节的EEPROM（耐力：100,000写入/擦除周期）（A T90CAN32/64/128）- 2K/4K/4K字节内部SRAM（AT90CAN32/64/128）- 高达64K字节可选外部存储空间- 编程软件安全锁•JTAG接口（IEEE标准。
1149.1兼容）接口- 边界扫描功能根据JTAG标准- 编程闪存（硬件的ISP）的EEPROM，熔丝位和锁定- 广泛的片上调试支持•CAN控制器的电流及2.0B - 的ISO 16845认证（1）- 15个具有独立完整的邮件对象标识标签和面具- 发送，接收，自动回复和帧缓冲区接收模式- 1Mbits / s的8 MHz的最大传输速率- 冲压时，公车及听力模式（间谍或自动波特）•外设特点- 可编程看门狗定时器，带有片上振荡器- 8位同步Timer/Counter-0•10位预分频器•外部事件计数器•输出比较或8位PWM输出- 8位异步Timer/Counter-2•10位预分频器•外部事件计数器•输出比较或8位PWM输出•32kHz振荡器实时时钟运行- 双通道16位同步Timer/Counters-1＆3 •10位预分频器•输入捕获噪声抵消•外部事件计数器•3输出比较或16位PWM输出•输出比较调制- 8通道，10位SAR ADC•8个单端通道•7个差分通道•2个差分通道，再加上1倍，10倍，或200x中可编程增益- 片内模拟比较器- 字节为导向的两线串行接口- 双可编程串行的USART- 主/从SPI串行接口•编程闪存（硬件的ISP）•特殊的处理器特点- 上电复位和可编程欠压检测- 内部RC振荡器校准- 8个外部中断源- 5睡眠模式：空闲，ADC噪声降低，电力保存，掉电和待机- 软件可选的时钟频率- 全球拉禁用•I / O和软件包- 53可编程I / O口线- 64引脚TQFP和64引脚QFN封装•工作电压：2.7 - 5.5V的•工作温度：工业（-40 °C至+85℃）•最大工作频率：在2.7V 8兆赫，16兆赫在4.5V 注：1。
BS62LV1600FI55中文资料
BS62LV1600FI55中⽂资料Very Low Power CMOS SRAM 2M X 8 bitBS62LV1600Pb-Free and Green package materials are compliant to RoHSn FEATURESWide V CC operation voltage : 2.4V ~ 5.5V Very low power consumption : V CC = 3.0V Operation current : 46mA (Max.) a t 55ns 2mA (Max.) at 1MHz Standby current : 1.5uA (Typ.) at 25 O C V CC = 5.0V Operation current : 115mA (Max.) a t 55ns 10mA (Max.) a t 1MHz Standby current : 6.0uA (Typ.) at 25O C ? High speed access time : -55 55ns (Max.) at V CC :3.0~5.5V -70 70ns (Max.) at V CC : 2.7~5.5V ? Automatic power down when chip is deselected ? Easy expansion with CE1, CE2 and OE options ? Three state outputs and TTL compatible ? Fully static operation ? Data retention supply voltage as low as 1.5V n DESCRIPTIONThe BS62LV1600 is a high performance, very low power CMOS Static Random Access Memory organized as 2048K by 8 bits and operates form a wide range of 2.4V to 5.5V supply voltage.Advanced CMOS technology and circuit techniques provide both high speed and low power features with typical CMOS standby current of 1.5uA at 3.0V/25O C and maximum access time of 55ns at 3.0V/85O C.Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state output drivers.The BS62LV1600 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV1600 is available in JEDEC standard 44-pin TSOP II and 48-ball BGA package.n POWER CONSUMPTIONPOWER DISSIPATIONSTANDBY(I CCSB1, Max)Operating(I CC , Max)V CC =5.0V V CC =3.0V PRODUCT FAMILYOPERATING TEMPERATUREV CC =5.0V V CC =3.0V1MHz10MHzf Max. 1MHz10MHzf Max.PKG TYPEBS62LV1600EC TSOP II-44 BS62LV1600FC Commercial +0O C to +70O C 50uA 8.0uA 9mA 48mA 113mA 1.5mA 19mA 45mABGA-48-0912 BS62LV1600EITSOP II-44 BS62LV1600FIIndustrial -40O C to +85O C100uA 16uA 10mA 50mA 115mA 2mA 20mA 46mABGA-48-0912n PIN CONFIGURATIONSn BLOCK DIAGRAMBrilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.G H F E D C B A 1 2 3 4 5 6 A9 A11 A10 A19A12 A14 A13 A15 WE NC NC NC DQ7 A17 A16 A7 VSS VCC DQ2 DQ1 DQ6 DQ5 NC A5 OE A3 A0 A6 A4 A1A2CE2 NC NC NCCE1 DQ4 NC 48-ball BGA top view NC NC DQ0 VSS VCC DQ3 NC A18 A20 A8n TRUTH TABLEn ABSOLUTE MAXIMUM RATINGS (1)SYMBOL PARAMETER RATING UNITSV TERM Terminal Voltage withRespect to GND-0.5(2) to 7.0 VT BIAS Temperature UnderBias-40 to +125 O CT STG Storage Temperature -60 to +150 O CP T Power Dissipation 1.0 WI OUT DC Output Current 20 mA1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.2. –2.0V in case of AC pulse width less than 30 ns. n OPERATING RANGERANGAMBIENTTEMPERATUREV CC Commercial 0O C to + 70O C 2.4V ~ 5.5VIndustrial -40O C to + 85O C 2.4V ~ 5.5Vn CAPACITANCE (1) (T A = 25O C, f = 1.0MHz) SYMBOL PAMAMETER CONDITIONS MAX. UNITS C INInputCapacitanceV IN = 0V 10 pFC IOInput/OutputCapacitanceV I/O = 0V 12 pF1. This parameter is guaranteed and not 100% tested.n DC ELECTRICAL CHARACTERISTICS (T A =-40O C to +85OC)1. Typical characteristics are at T A =25O C and not 100% tested.2. Undershoot: -1.0V in case of pulse width less than 20 ns.3. Overshoot: V CC +1.0V in case of pulse width less than 20 ns.4. F MAX =1/t RC.5. I CC(MAX.) is 45mA/113mA at V CC =3.0V/5.0V and T A =70O C.6. I CCSB1(MAX.) is 8.0uA/50uA at V CC =3.0V/5.0V and T A =70O C.n DATA RETENTION CHARACTERISTICS (T A = -40O C to +85OC)1. V CC =1.5V, T A =25O C and not 100% tested.2. t RC = Read Cycle Time.3. I CCRD(Max.) is4.0uA at T A =70O C.n LOW V CC DATA RETENTION WAVEFORM (1) (CE1 Controlled)Data Retention Mode V CCt CDRV CC t RV IHV IHCE1≧V CC - 0.2V V DR ≧1.5V CE1V CCn LOW V CC DATA RETENTION WAVEFORM (2) (CE2 Controlled)n AC TEST CONDITIONS (Test Load and Input/Output Reference)Input Pulse Levels Vcc / 0V Input Rise and Fall Times 1V/ns Input and Output Timing Reference Level 0.5Vcc t CLZ , t OLZ , t CHZ , t OHZ , t WHZ C L = 5pF+1TTL Output LoadOthersC L = 30pF+1TTL1. Including jig and scope capacitance.n KEY TO SWITCHING WAVEFORMSn AC ELECTRICAL CHARACTERISTICS (T A = -40O C to +85OC)READ CYCLECE2 Data Retention Mode V CC t CDR V CC t R V ILV IL V CCV DR ≧1.5V CE2≦0.2V 1 TTL ALL INPUT PULSES→← 90%V CC GND Rise Time : 1V/ns Fall Time : 1V/ns90%→← 10%10%n SWITCHING WAVEFORMS (READ CYCLE)READ CYCLE 1 (1,2,4)READ CYCLE 2 (1,3,4)READ CYCLE 3 (1, 4)NOTES:1. WE is high in read Cycle.2. Device is continuously selected when CE1 = V IL and CE2= V IH .3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.4. OE = V IL .5. Transition is measured ± 500mV from steady state with C L = 5pF. The parameter is guaranteed but not 100% tested. t RC t OHt AA D OUT ADDRESS t OHD OUTCE2 CE1D OUTCE2 CE1 OE ADDRESSn AC ELECTRICAL CHARACTERISTICS (T A = -40OC to +85OC)WRITE CYCLEn SWITCHING WAVEFORMS (WRITE CYCLE)WRITE CYCLE 1 (1)t WCt WR1(3)t CW(11)t CW(11)t WP(2)t AWt OHZ(4,10)t AS t WR2(3)t DHt DWD IND OUTWECE2CE1OEADDRESS(5)(5)WRITE CYCLE 2 (1,6)NOTES:1. WE must be high during address transitions.2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write.3. t WR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write cycle.4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state.6. OE is continuously low (OE = V IL ).7. D OUT is the same phase of write data of this write cycle. 8. D OUT is the read data of next address.9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. T ransition is measured ± 500mV from steady state with C L = 5pF. The parameter is guaranteed but not 100% tested. 11. t CW is measured from the later of CE1 going low or CE2 going high to the end of write.D IND OUTWE CE2 CE1ADDRESSn ORDERING INFORMATIONBSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments.n PACKAGE DIMENSIONSTSOP II-44n PACKAGE DIMENSIONS (continued)3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.N EDNOTES:4812.09.0E1D1e3.755.250.75 48 mini-BGA (9mm x 12mm)n Revision HistoryRevision No. History Draft Date Remark2.2 Add Icc1 characteristic parameter Jan. 13, 2006Improve Iccsb1 spec.I-grade from 220uA to 100uA at 5.0V20uA to 16uA at 3.0VC-grade from 110uA to 50uA at 5.0V10uA to 8.0uA at 3.0V2.3 Change I-grade operation temperature range May. 25, 2006 - from –25O C to –40O C。
多功能编程器极品版说明书
多功能编程器极品版CZ多功能编程器极品版，基于LZ-A编程器的升级版本，不需要51适配器的多功能编程器,写51系列芯片的操作变得更简单、更直接、更稳定。
操作省时省力。
适合烧写各类常用的存储器、51、PIC等系列单片机的编程，同时还适合BIOS玩家烧写各种常见的BIOS芯片。
接插件特色：3个非常养眼的万能ZIF40IC座、漂亮的彩色跳线帽，非常醒目。
东西好不好，只需要看看就知道了。
零件的特色：DC-DC升压部分采用了高成本的线绕电感，VPP编程电压更稳定。
没有采用色环或豆状电感，不会出现豆状电感在写27系列容易烧的问题。
所有的电阻均为高精度金属膜电阻。
集成的IC：全部为德州、摩托罗拉、菲利浦等大厂的集成电路，所有的IC都配有集成电路插座。
布局的特色：VPP高压源电路、三极管功率控制电路都集中在电源VCC附近，抗干扰能力更好。
以往的经验告诉我们，VCC、VPP和开关三极管的距离越近，抗干扰的能力就越强。
电源的设计：USB取电、设有外接电源专用接口，双电源接口之见可以自动切换，支持外部其他标准5V电源的接入，省时省力。
产品的工艺：焊接采用一如既往的波峰焊接工工艺。
PCB电路板：PCB电路板由专业大厂制作，PCB全部采用精致的覆铜设计，绝非裸线板。
产品的定位：高成本精心打造多功能编程器中的高级精品,不求市场占有率，一心给同志们打造多功能编程器中的“劳斯莱斯”。
CZ多功能编程器主机的外观多功能BIOS编程器支持的芯片程器可以支持最新Intel810、815、845主板上使用的N82802AB、SST49LF002、SST49LF004等3.3V电压的芯片，也就是说，目前几乎所有主板上的BIOS芯片，多功能BIOS编程器都可以支持，真正是一款性价比较高的编程器。
多功能编程器程序的跳线设置在多功能编程器上，共有三组跳线，用来设置不同类型的芯片，共具体说明如下：第一组跳线：PCB上的标号为J1和J2用来设置2732、2716、2816、I28F001、AT29C256几个特殊芯片。
L6599_中文资料
L6599高压谐振控制器特征50%占空比，谐振半桥变频控制 高精度振荡器高至500kHz 的工作频率 序号编码器件编码封 装包 装L6599D SO-16N 管装 L6599DTR SO-16N 卷带 L6599NDIP16管装两级过流保护：变频和停机闭锁 与PFC 控制器的接口 自锁禁止输入 轻载脉冲工作模式上电/断电顺序或欠压保护输入 单调输出电压上升为非线性软启动整合了一个能够承受600V 以上电压的高压浮动结构和一个同步驱动式高压横向双扩散金属氧化物半导体(LDMOS)器件，节省了一个外部快速恢复自举二极管用低电压下拉方式为两个栅驱动器提供一个输出电流0.3A 和灌入电流0.8A的典型峰值电流处理能力。
DIP-16，SO-16N 两种封装特征液晶电视和等离子电视的电源 台式电脑和初级服务器 电信设备开关电源 交直流适配器的开关电源框图目录1 驱动描述 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 引脚设置 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52.1 引脚排列 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52.2 引脚功能说明 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 典型系统框图 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 电气数据 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74.1 极限参数. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74.2 热相关数据. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 电气参数. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 典型的电气性能. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 应用资料. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157.1 振荡器. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167.2 工作在空载或非常轻的负载状态. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187.3 软启动. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217.4 电流检测，过流保护和过载保护 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237.5 闭锁关机. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267.6 LINE检测功能. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277.7 自举部分 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287.8 应用实例. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 封装外形尺寸 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 修订记录 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 驱动描述L6599是一个用于谐振半桥拓扑电路的精确的双端控制器。
施耐德A9系列介绍
7
iC65H 系列断路器
产品标准 IEC60898-1/GB10963.1 产品认证 CCC CE 产品极数 1,2,3,4 脱扣曲线 B/C/D 分断能力 10000A 额定电流 1~63A 防护等级 IP40(正面） IP20(端子）
Schneider Electric - Power Business - Final Distribution – A9 China internal sales argument
30mA(G)
A9V50240 A9V50263
100mA
A9V63240 A9V63263 A9V63340 A9V63363 A9V63440 A9V63463
100mA-S
A9V73263 A9V73363 A9VV83263 A9V83340 A9V83363 A9V83440 A9V83463
Vigi iC65(ELM)
30mA A9V52225 A9V52240 A9V52263 A9V52325 A9V52340 A9V52363 A9V52425 A9V52440 A9V52463
100mA A9V62263 A9V62363 A9V62463
100mA-S
300mA
300mA-S
Schneider Electric - Power Business - Final Distribution – A9 China internal sales argument
17
iINT 隔离开关
产品标准 GB14048.3 产品认证 CCC CE 产品极数 1,2,3,4 额定电流32~125A NO/NF指示附件 外形尺寸与M9 INT125一致
chinaoffersoverviewacti全新终端配电系统保护功能控制功能安装系统acti9保护类断路器隔离开关rcdspdvigiic65vigiidpniidic65idpnic60lmaispdiintacti9信号控制类ict接触器itl脉冲继电器器reflexic60集成控制断路器ara自动重合附件rca远程控制附件acti9安装接线类电缆分配器端子盖保护齿绝缘端子multiclipic65n系列断路器产品标准iec608981gb109631产品认证cccce产品极数1234脱扣曲线分断能力6000a额定电流163a防护等级ip40正面ip20端子ic65h系列断路器产品标准iec608981gb109631产品认证cccce产品极数1234脱扣曲线分断能力10000a额定电流163a防护等级ip40正面ip20端子ic65l系列断路器产品标准iec609472gb140482产品认证cccce产品极数1234脱扣曲线分断能力15ka额定电流163a防护等级ip40正面ip20端子idpnk2系列断路器产品标准iec608981gb109631产品认证cccce产品极数分断能力6000a额定电流1063a防护等级ip40正面ip20端子vigiic65rcd附件产品标准gb1691722产品认证cccce产品极数234产品类型eleelm保护类型ac额定电流254063a防护等级ip40正面ip20端子vigiic65rcd附件30ma30mag100ma100mas300ma300mas40aa9v5364063aa9v5366340aa9v53240a9v50240a9v63240a9v83240a9v9324063aa9v53263a9v50263a9v63263a9v73263a9v83263a9v9326340aa9v53340a9v63340a9v83340a9v9334063aa9v53363a9v63363a9v73363a9v83363a9v9336340aa9v53440a9v63440a9v83440a9v9344063aa9v53463a9v63463a9v73463a9v83463a9v9346330ma30mag100ma100mas300ma300mas40aa9v5764063aa9v5766340aa9v5724063aa9v5726340aa9v5734063a
Am29LV160DB-90SE中文资料
July 2003The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-inally developed the specification, these products will be offered to customers of both AMD and Fujitsu.Continuity of SpecificationsThere is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate,and changes will be noted in a revision summary.Continuity of Ordering Part NumbersAMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document.For More InformationPlease contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.Am29L V160DData SheetPublication Number 22358 Revision B Amendment +3 Issue Date November 10, 2000This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 22358Rev: B Amendment/+3 Issue Date: November 10, 2000Am29LV160D16 Megabit (2 M x 8-Bit/1 M x 16-Bit)CMOS 3.0 Volt-only Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICSs Single power supply operation—Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications —Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with highperformance 3.3 volt microprocessorss Manufactured on 0.23 µm process technology —Fully compatible with 0.32 µm Am29LV160B device s High performance—Access times as fast as 70 nss Ultra low power consumption (typical values at 5MHz)—200 nA Automatic Sleep mode current—200 nA standby mode current—9 mA read current—20 mA program/erase currents Flexible sector architecture—One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-one 64 Kbyte sectors (byte mode)—One 8 Kword, two 4 Kword, one 16 Kword, and thirty-one 32 Kword sectors (word mode)—Supports full chip erase—Sector Protection features:A hardware method of locking a sector to preventany program or erase operations within that sectorSectors can be locked in-system or viaprogramming equipmentTemporary Sector Unprotect feature allows codechanges in previously locked sectorss Unlock Bypass Program Command—Reduces overall programming time when issuing multiple program command sequencess Top or bottom boot block configurations available s Embedded Algorithms—Embedded Erase algorithm automatically preprograms and erases the entire chip or anycombination of designated sectors—Embedded Program algorithm automatically writes and verifies data at specified addresses s Minimum 1,000,000 write cycle guarantee per sectors20-year data retention at 125°C—Reliable operation for the life of the systems Package option—48-ball FBGA—48-pin TSOP—44-pin SOs CFI (Common Flash Interface) compliant —Provides device-specific information to the system, allowing host software to easilyreconfigure for different Flash devicess Compatibility with JEDEC standards—Pinout and software compatible with single-power supply Flash—Superior inadvertent write protections Data# Polling and toggle bits—Provides a software method of detecting program or erase operation completions Ready/Busy# pin (RY/BY#)—Provides a hardware method of detecting program or erase cycle completion (not availableon 44-pin SO)s Erase Suspend/Erase Resume—Suspends an erase operation to read data from, or program data to, a sector that is not beingerased, then resumes the erase operations Hardware reset pin (RESET#)—Hardware method to reset the device to reading array dataGENERAL DESCRIPTIONThe Am29LV160D is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system with the standard system 3.0 volt V CC supply. A 12.0 V V PP or 5.0 V CC are not required for write or erase operations. The device can a l s o b e p r o g r a m m e d i n s t a n d a r d EPROM programmers.The device offers access times of 70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.The Am29LV160D is entirely command set compatible with the JEDEC single-power-supply Flash stan-dard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that auto-matically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facili-tates faster programming times by requiring only two write cycles to program data instead of four.Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automati-cally preprograms the array (if it is not already pro-grammed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.Hardware data protection measures include a low V CC detector that automatically inhibits write opera-tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via pro-gramming equipment.The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved.The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective-ness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tun-neling. The data is programmed using hot electron injection.2Am29LV160DTABLE OF CONTENTSProduct Selector Guide . . . . . . . . . . . . . . . . . . . . .4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .7 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . .8 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .9 Table 1. Am29LV160D Device Bus Operations (9)Word/Byte Configuration (9)Requirements for Reading Array Data (9)Writing Commands/Command Sequences (10)Program and Erase Operation Status (10)Standby Mode (10)Automatic Sleep Mode (10)RESET#: Hardware Reset Pin (11)Output Disable Mode (11)Table 2. Sector Address Tables (Am29LV160DT) (12)Table 3. Sector Address Tables (Am29LV160DB) (13)Autoselect Mode (14)Table 4. Am29LV160D Autoselect Codes (High Voltage Method) ..14 Sector Protection/Unprotection (14)Temporary Sector Unprotect (15)Figure 1. Temporary Sector Unprotect Operation (15)Figure 2. In-System Sector Protect/Unprotect Algorithms (16)Common Flash Memory Interface (CFI) . . . . . . .17 Table 5. CFI Query Identification String (17)Table 6. System Interface String (18)Table 7. Device Geometry Definition (18)Hardware Data Protection (19)Table 8. Primary Vendor-Specific Extended Query (19)Low V CC Write Inhibit (19)Write Pulse “Glitch” Protection (19)Logical Inhibit (19)Power-Up Write Inhibit (19)Command Definitions . . . . . . . . . . . . . . . . . . . . . .20 Reading Array Data (20)Reset Command (20)Autoselect Command Sequence (20)Word/Byte Program Command Sequence (20)Unlock Bypass Command Sequence (21)Figure 3. Program Operation (21)Chip Erase Command Sequence (21)Sector Erase Command Sequence (22)Erase Suspend/Erase Resume Commands (22)Figure 4. Erase Operation (23)Command Definitions (24)Table 9. Am29LV160D Command Definitions (24)Write Operation Status . . . . . . . . . . . . . . . . . . . . .25 DQ7: Data# Polling (25)Figure 5. Data# Polling Algorithm (25)RY/BY#: Ready/Busy# (26)DQ6: Toggle Bit I (26)DQ2: Toggle Bit II (26)Reading Toggle Bits DQ6/DQ2 (26)Figure 6. Toggle Bit Algorithm (27)DQ3: Sector Erase Timer (28)Table 10. Write Operation Status (28)Absolute Maximum Ratings . . . . . . . . . . . . . . . . 29 Figure 7. Maximum Negative Overshoot Waveform (29)Figure 8. Maximum Positive Overshoot Waveform (29)Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 29 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 9. I CC1 Current vs. Time (Showing Active andAutomatic Sleep Currents) (31)Figure 10. Typical I CC1 vs. Frequency (31)Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 11. Test Setup (32)Table 11. Test Specifications (32)Figure 12. Input Waveforms and Measurement Levels (32)AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33 Read Operations (33)Figure 13. Read Operations Timings (33)Hardware Reset (RESET#) (34)Figure 14. RESET# Timings (34)Word/Byte Configuration (BYTE#) (35)Figure 15. BYTE# Timings for Read Operations (35)Figure 16. BYTE# Timings for Write Operations (35)Erase/Program Operations (36)Figure 17. Program Operation Timings (37)Figure 18. Chip/Sector Erase Operation Timings (38)Figure 19. Data# Polling Timings (During Embedded Algorithms). 39 Figure 20. Toggle Bit Timings (During Embedded Algorithms) (39)Figure 21. DQ2 vs. DQ6 for Erase andErase Suspend Operations (40)Figure 22. Temporary Sector Unprotect/Timing Diagram (40)Figure 23. Sector Protect/Unprotect Timing Diagram (41)Figure 24. Alternate CE# Controlled Write Operation Timings (43)Erase and Programming Performance . . . . . . . 44 Latchup Characteristics. . . . . . . . . . . . . . . . . . . . 44 TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 44 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 45 TS 048—48-Pin Standard TSOP (45)TSR048—48-Pin Reverse TSOP (46)FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA)8x9mm (47)SO 044—44-Pin Small Outline Package (48)Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 49 Revision A (January 1999) (49)Revision A+1 (April 19, 1999) (49)Revision B (November 23, 1999) (49)Revision B+1 (February 22, 2000) (49)Revision B+2 (November 7, 2000) (49)Revision B+3 (November 10, 2000) (49)Am29LV160D34Am29LV160DPRODUCT SELECTOR GUIDENote: See “AC Characteristics” for full specifications.BLOCK DIAGRAMFamily Part Number Am29LV160DSpeed OptionVoltage Range: V CC = 2.7–3.6 V-70-90-120Max access time, ns (t ACC )7090120Max CE# access time, ns (t CE )7090120Max OE# access time, ns (t OE )303550Input/Output BuffersX-DecoderY-Decoder Chip Enable Output EnableLogicErase Voltage GeneratorPGM Voltage GeneratorTimerV CC DetectorState Control Command RegisterV CC V SS WE#BYTE#CE#OE#STBSTBDQ0–DQ15 (A-1)Sector SwitchesRY/BY#RESET#Data LatchY-GatingCell MatrixA d d r e s s L a t c hA0–A19CONNECTION DIAGRAMSAm29LV160D5CONNECTION DIAGRAMSSpecial Handling InstructionsSpecial handling is required for Flash Memory products in FBGA packages.Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.6Am29LV160DPIN CONFIGURATIONA0–A19=20 addressesDQ0–DQ14=15 data inputs/outputsDQ15/A-1=DQ15 (data input/output, word mode),A-1 (LSB address input, byte mode) BYTE#=Selects 8-bit or 16-bit modeCE#=Chip enableOE#= Output enableWE#=Write enableRESET#=Hardware reset pinRY/BY#= Ready/Busy output(N/A SO 044)V CC= 3.0 volt-only single power supply(see Product Selector Guide for speedoptions and voltage supply tolerances) V SS=Device groundNC=Pin not connected internally LOGIC SYMBOL2016 or 8DQ0–DQ15(A-1)A0–A19CE#OE#WE#RESET#BYTE#RY/BY#(N/A SO 044)Am29LV160D78Am29LV160DORDERING INFORMATION Standard ProductsAMD standard products are available in several packages and operating ranges. The order number (Valid Combi-nation) is formed by a combination of the elements below.Valid CombinationsValid Combinations list configurations planned to be sup-ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.Am29LV160DT-70ECTEMPERATURE RANGE C =Commercial (0°C to +70°C)I = Industrial (–40°C to +85°C)E =Extended (–55°C to +125°C)PACKAGE TYPE E =48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)F =48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048)S =44-Pin Small Outline Package (SO 044)WC =48-ball Fine-Pitch Ball Grid Array (FBGA)0.80 mm pitch, 8 x 9 mm package (FBC048)SPEED OPTIONSee Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sectorDEVICE NUMBER/DESCRIPTIONAm29LV160D16 Megabit (2M x 8-Bit/1M x 16-Bit) CMOS Flash Memory 3.0 Volt-only Read, Program, and EraseValid Combinations For TSOP and SO Packages Am29LV160DT -70,Am29LV160DB-70EC, EI, EE, FC, FI, FE,SC, SI, SEAm29LV160DT -90,Am29LV160DB-90Am29LV160DT -120,Am29LV160DB-120Valid Combinations for FBGA Packages Order NumberPackage Marking Am29LV160DT -70,Am29LV160DB-70WCC,WCI,WCEL160DT70V ,L160DB70VC, I, EAm29LV160DT -90,Am29LV160DB-90L160DT90V ,L160DB90VAm29LV160DT -120,Am29LV160DB-120L160DT12V ,L160DB12VDEVICE BUS OPERATIONSThis section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register it-self does not occupy any addressable memory loca-tion. The register is composed of latches that store the commands, along with the address and data informa-tion needed to execute the command. The contents of the register serve as inputs to the internal state ma-chine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.Table 1.Am29LV160D Device Bus OperationsLegend:L = Logic Low = V IL, H = Logic High = V IH, V ID = 12.0 ± 0.5 V, X = Don’t Care, A IN = Address In, D IN = Data In, D OUT = Data Out Notes:1.Addresses are A19:A0 in word mode (BYTE# = V IH), A19:A-1 in byte mode (BYTE# = V IL).2.The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “SectorProtection/Unprotection” section.Word/Byte ConfigurationThe BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configura-tion. If the BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ15–DQ0 are active and con-trolled by CE# and OE#.If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are ac-tive and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. Requirements for Reading Array DataTo read array data from the outputs, the system must drive the CE# and OE# pins to V IL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should re-main at V IH. The BYTE# pin determines whether the de-vice outputs array data in words or bytes.The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the mem-ory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that as-sert valid addresses on the device address inputs pro-duce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered.See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifica-tions and to Figure 13 for the timing diagram. I CC1 in the DC Characteristics table represents the active cur-rent specification for reading array data.Operation CE#OE#WE#RESET#Addresses(Note 1)DQ0–DQ7DQ8–DQ15BYTE#= V IHBYTE#= V ILRead L L H H A IN D OUT D OUT DQ8–DQ14 = High-Z,DQ15 = A-1 Write L H L H A IN D IN D INStandby V CC±0.3 VX XV CC±0.3 VX High-Z High-Z High-ZOutput Disable L H H H X High-Z High-Z High-Z Reset X X X L X High-Z High-Z High-ZSector Protect (Note 2)L H L V ID Sector Address,A6 = L, A1 = H,A0 = LD IN X XSector Unprotect (Note 2)L H L V ID Sector Address,A6 = H, A1 = H,A0 = LD IN X XTemporary SectorUnprotectX X X V ID A IN D IN D IN High-ZAm29LV160D9Writing Commands/Command Sequences To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to V IH.For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more information.The device features an Unlock Bypass mode to facili-tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word/Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences.An erase operation can erase one sector, multiple sec-tors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. The “Command Definitions”section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect Command Sequence” sections for more information.I CC2 in the DC Characteristics table represents the ac-tive current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations.Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and I CC read specifications apply. Refer to “Write Operation Status” for more information, and to “AC Characteris-tics” for timing diagrams.Standby ModeWhen the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde-pendent of the OE# input.The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at V IH, but not within V CC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data.If the device is deselected during erasure or program-ming, the device draws active current until the operation is completed.In the DC Characteristics table, I CC3 and I CC4 repre-sents the standby current specification.Automatic Sleep ModeThe automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I CC4 in the DC Characteristics table represents the automatic sleep mode current specification.RESET#: Hardware Reset PinThe RESET# pin provides a hardware method of reset-ting the device to reading array data. When the system drives the RESET# pin to V IL for at least a period of t RP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state ma-chine to reading array data. The operation that was in-terrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity.Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS±0.3 V, the device draws CMOS standby current (I CC4). If RESET# is held at V IL but not within V SS±0.3 V, the standby current will be greater.The RESET# pin may be tied to the system reset cir-cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm-ware from the Flash memory.If RESET# is asserted during a program or erase op-eration, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not ex-ecuting (RY/BY# pin is “1”), the reset operation is completed within a time of t READY (not during Embed-ded Algorithms). The system can read data t RH after the RESET# pin returns to V IH.Refer to the AC Characteristics tables for RESET# pa-rameters and to Figure 14 for the timing diagram. Output Disable ModeWhen the OE# input is at V IH, output from the device is disabled. The output pins are placed in the high imped-ance state.Table 2.Sector Address Tables (Am29LV160DT)Note:Address range is A19:A-1 in byte mode and A19:A0 in word mode. See “Word/Byte Configuration” section.Sector A19A18A17A16A15A14A13A12Sector Size (Kbytes/Kwords)Address Range (in hexadecimal)Byte Mode (x8)Word Mode (x16)SA000000X X X 64/32000000–00FFFF 00000–07FFF SA100001X X X 64/32010000–01FFFF 08000–0FFFF SA200010X X X 64/32020000–02FFFF 10000–17FFF SA300011X X X 64/32030000–03FFFF 18000–1FFFF SA400100X X X 64/32040000–04FFFF 20000–27FFF SA500101X X X 64/32050000–05FFFF 28000–2FFFF SA600110X X X 64/32060000–06FFFF 30000–37FFF SA700111X X X 64/32070000–07FFFF 38000–3FFFF SA801000X X X 64/32080000–08FFFF 40000–47FFF SA901001X X X 64/32090000–09FFFF 48000–4FFFF SA1001010X X X 64/320A0000–0AFFFF 50000–57FFF SA1101011X X X 64/320B0000–0BFFFF 58000–5FFFF SA1201100X X X 64/320C0000–0CFFFF 60000–67FFF SA1301101X X X 64/320D0000–0DFFFF 68000–6FFFF SA1401110X X X 64/320E0000–0EFFFF 70000–77FFF SA1501111X X X 64/320F0000–0FFFFF 78000–7FFFF SA1610000X X X 64/32100000–10FFFF 80000–87FFF SA1710001X X X 64/32110000–11FFFF 88000–8FFFF SA1810010X X X 64/32120000–12FFFF 90000–97FFF SA1910011X X X 64/32130000–13FFFF 98000–9FFFF SA2010100X X X 64/32140000–14FFFF A0000–A7FFF SA2110101X X X 64/32150000–15FFFF A8000–AFFFF SA2210110X X X 64/32160000–16FFFF B0000–B7FFF SA2310111X X X 64/32170000–17FFFF B8000–BFFFF SA2411000X X X 64/32180000–18FFFF C0000–C7FFF SA2511001X X X 64/32190000–19FFFF C8000–CFFFF SA2611010X X X 64/321A0000–1AFFFF D0000–D7FFF SA2711011X X X 64/321B0000–1BFFFF D8000–DFFFF SA2811100X X X 64/321C0000–1CFFFF E0000–E7FFF SA2911101X X X 64/321D0000–1DFFFF E8000–EFFFF SA3011110X X X 64/321E0000–1EFFFF F0000–F7FFF SA31111110X X 32/161F0000–1F7FFF F8000–FBFFF SA32111111008/41F8000–1F9FFF FC000–FCFFF SA33111111018/41FA000–1FBFFF FD000–FDFFF SA341111111X16/81FC000–1FFFFFFE000–FFFFFTable 3.Sector Address Tables (Am29LV160DB)Note:Address range is A19:A-1 in byte mode and A19:A0 in word mode. See the “Word/Byte Configuration” section.Sector A19A18A17A16A15A14A13A12Sector Size (Kbytes/Kwords)Address Range (in hexadecimal)Byte Mode (x8)Word Mode (x16)SA00000000X 16/8000000–003FFF 00000–01FFF SA1000000108/4004000–005FFF 02000–02FFF SA2000000118/4006000–007FFF 03000–03FFF SA3000001X X 32/16008000–00FFFF 04000–07FFF SA400001X X X 64/32010000–01FFFF 08000–0FFFF SA500010X X X 64/32020000–02FFFF 10000–17FFF SA600011X X X 64/32030000–03FFFF 18000–1FFFF SA700100X X X 64/32040000–04FFFF 20000–27FFF SA800101X X X 64/32050000–05FFFF 28000–2FFFF SA900110X X X 64/32060000–06FFFF 30000–37FFF SA1000111X X X 64/32070000–07FFFF 38000–3FFFF SA1101000X X X 64/32080000–08FFFF 40000–47FFF SA1201001X X X 64/32090000–09FFFF 48000–4FFFF SA1301010X X X 64/320A0000–0AFFFF 50000–57FFF SA1401011X X X 64/320B0000–0BFFFF 58000–5FFFF SA1501100X X X 64/320C0000–0CFFFF 60000–67FFF SA1601101X X X 64/320D0000–0DFFFF 68000–6FFFF SA1701110X X X 64/320E0000–0EFFFF 70000–77FFF SA1801111X X X 64/320F0000–0FFFFF 78000–7FFFF SA1910000X X X 64/32100000–10FFFF 80000–87FFF SA2010001X X X 64/32110000–11FFFF 88000–8FFFF SA2110010X X X 64/32120000–12FFFF 90000–97FFF SA2210011X X X 64/32130000–13FFFF 98000–9FFFF SA2310100X X X 64/32140000–14FFFF A0000–A7FFF SA2410101X X X 64/32150000–15FFFF A8000–AFFFF SA2510110X X X 64/32160000–16FFFF B0000–B7FFF SA2610111X X X 64/32170000–17FFFF B8000–BFFFF SA2711000X X X 64/32180000–18FFFF C0000–C7FFF SA2811001X X X 64/32190000–19FFFF C8000–CFFFF SA2911010X X X 64/321A0000–1AFFFF D0000–D7FFF SA3011011X X X 64/321B0000–1BFFFF D8000–DFFFF SA3111100X X X 64/321C0000–1CFFFF E0000–E7FFF SA3211101X X X 64/321D0000–1DFFFF E8000–EFFFF SA3311110X X X 64/321E0000–1EFFFF F0000–F7FFF SA3411111XXX64/321F0000–1FFFFFF8000–FFFFF。
s29al016d90tfi020的规格书
规格书是产品开发过程中非常重要的文件，它包含了产品的详细规格和技术要求，对于产品的设计、生产和检验都有着重要的指导作用。
s29al016d90tfi020是一款存储器芯片，具有较高的性能和可靠性，本规格书将详细介绍其技术指标、功能特点、电气特性、工作条件、引脚排列等内容。
一、技术指标s29al016d90tfi020的主要技术指标包括存储容量、工作电压、工作温度、数据接口、速度等方面。
具体包括：1. 存储容量：XXGB2. 工作电压：XV3. 工作温度：-40℃~85℃4. 数据接口：XXX5. 速度：XXX二、功能特点s29al016d90tfi020具有以下功能特点：1. 高速读写：具有快速的数据读写速度，可以满足高性能应用的需求。
2. 高可靠性：采用优质材料和先进工艺制造，具有较高的可靠性和稳定性。
3. 低功耗：工作时的功耗较低，适合在功耗敏感的设备中使用。
4. 兼容性：具有良好的兼容性，可与多种主控芯片配合使用。
三、电气特性s29al016d90tfi020的电气特性包括输入电压、输出电流、引脚电压等方面的参数。
具体包括：1. 输入电压范围：XV~XV2. 输出电流：XmA3. 引脚电压：Vcc、Vss等引脚的电压参数。
四、工作条件s29al016d90tfi020在不同的工作条件下，具有不同的性能表现和可靠性。
工作条件包括工作温度、工作湿度、储存温度等参数。
具体包括：1. 工作温度范围：-40℃~85℃2. 工作湿度范围：X~X3. 储存温度范围：-40℃~125℃五、引脚排列s29al016d90tfi020的引脚排列图和引脚功能表，具体包括每个引脚的编号、名称和功能描述。
引脚排列图清晰显示了各个引脚的位置和布局。
总结规格书是产品开发过程中必不可少的文档，它对产品的设计、生产和检验都具有重要的指导作用。
s29al016d90tfi020作为一款存储器芯片，具有较高的性能和可靠性，本规格书详细介绍了其技术指标、功能特点、电气特性、工作条件、引脚排列等内容，为产品的设计和应用提供了重要的参考信息。
ATV900_变频器
产品目录10-2015变频器ATV 御程系列ATV900Digi-Cat ，轻便的PC 用USB 密钥请联系您当地的服务代表获取您自己的Digi-Cat如何将6000页的产品目录装到您的口袋里？施耐德电气通过一个轻便的PC 用USB 密钥或平板电脑应用，为您提供全套的工业自动化产品目录e-Library ，平板电脑APP>携带方便 >持续更新 >环境友好>轻松分享>打开App Store ，搜索e-Library >或者扫描二维码如果您使用的是iPad®：>打开Google Play Store TM ，搜索eLibrary >或者扫描二维码如果您使用的是Android 平板电脑：目录●一般介绍 (2)IP 21, IP 54 或 IP 55变频器选型指导 (4)IP 23 或 IP 54变频驱动系统选型指引 (6)●ATV御程系列 ATV900变频器介绍 (8)●ATV御程系列 ATV900变频驱动系统介绍 (16)ATV御程ATV900变频器●200...240 V 50/60 Hz电源，IP 21/UL 1型 .. (18)●380...480 V 50/60 Hz电源 .. (19)○IP 21/UL 1类，集成C2或C3类EMC滤波器 (19)○IP 55，集成C2或C3类EMC滤波器 (21)○IP 55，带有Vario负荷开关和集成C2或C3类EMC滤波器 (22)●380...440 V 50/60 Hz电源 . (20)○IP 21，落地安装式，带有集成C3类EMC滤波器 (20)○IP 54，落地安装式，带有集成C3类EMC滤波器 (23)●更换备件 (23)●图形显示终端 (24)●附件 (25)●网页服务器 (26)●DTM库和SoMove调试软件 (27)选件●变频器/选件组合 (28)●编码器模块和I/O扩展模块 (32)●通信总线和网络 (34)●制动单元和制动电阻 (40)●无源滤波器 (44)●EMC滤波器 (48)●dv/dt滤波器 (50)●正弦滤波器 (52)●共模滤波器 (54)电机起动器●200...240 V 50/60 Hz电源 . (56)●380...415 V 50/60 Hz电源 (57)●440 V 50/60 Hz电源 (59)ATV御程系列ATV900系统变频●高性能变频驱动系统 (62)●带能量反馈系统变频 (66)●选件 (70)尺寸●变频器 (74)●选件 (78)服务●为您的变频器提供遍及全球的服务 (82)ATV 御程提供您应该享受的效率电机控制应用性能O pe r at ion a l I n t e l li g en c e 面板画面ATV 御程是施耐德电气提供的新的全系列变频器，涵盖大部分工业应用场合，包括2个系列：>ATV600：着力于流体管理和处理以及节能的变频器>ATV900：以出众的电机控制和连接能力，着力于使生产率最大幅度提升的变频器根据客户要求，可按IP 21、IP 23、IP 54和IP 55防护等级提供挂墙安装式变频器、内置式机柜和落地安装式解决方案。
Fadal VMC 4020 配件手册说明书
Fadal VMC 4020 Parts Manual PartsManualVMC OPTIONSHYDROSWEEP (2)PALLET CHANGER (5)15K AIR/OIL SPINDLE (12)VH5C ROTARY TABLE (13)VH65 ROTARY TABLE (16)TR65 ROTARY TABLE (19)DUAL VH65 ASSEMBLY (25)ROTARY ACCESSORIES (27)32 MP PENDANT ASSY (28)HYDRAULIC BRAKE (29)REMOTE MPG (30)SERVO COOLANT (31)FLOPPY / ZIP DRIVES (32)300/400 ROTARY TABLE BOX (33)fULL ENCLOSURE SHEETMETAL (36)CHAIN HOIST SHEETMETAL 3020 (38)CHAIN HOIST SHEETMETAL 4020S (39)CHAIN HOIST SHEETMETAL 4525 (40)CHAIN HOIST SHEETMETAL 6535 (41)50 TAPER SPINDLE (42)500 TAPER SPINDLE B.O.M. (43)Fadal VMC 4020 Parts ManualThis reference covers the following Fadal products:VMC Options Parts ManualCorporate Office.............................voice (818) 407-1400....................fax (818) 407-0020 Service / Parts...............................voice (818) 727-2100....................fax (818) 407-1004 Programming Support....................voice (818) 727-2100....................fax (818) 407-0061*****************20701 Plummer Street, Chatsworth, California 91311 USAThe content of this manual has been reviewed for accuracy and is applicable to current Fadal hardware and software products as described herein. Differences may exist and we cannot guarantee that they are completely covered in this document. The information in this document is reviewed regularly and any necessary changes will be incorporated in the next revision. We welcome any suggestions for improvement.Material is subject to change without notice.This manual is for the exclusive use of Fadal Customers and Distributors. The reproduction, transmission or use of this document or its contents is not permitted without the expressed written permission of Fadal Machining Centers. All rights, including rights created by patent grant or registration of a utility, model or design, are reserved.© Copyright 2002 Fadal Machining Centers.HYDROSWEEPPART #PART #PART # 1STM-0672 (VMC 2216,3016)6HYS-002413PLM-0124 STM-0666 (VMC 4020)7STM-0680 (VMC 2216,3016)14HYS-0006 STM-0213/0444 (VMC 6030)STM-0204(VMC-4020)15VLV-0022 STM-0461/0460 (VMC 8030)STM-0207 (VMC 6030,8030)16PLM-0132 2STM-02998STM-0417 (VMC6030)17PLM-0128 3STM-0222 (VMC 2216,3016)STM-0418 (VMC 8030)18PLM-0129 STM-0200 (VMC 4020,6030,8030)9HYS-002519HDW-0544 4STM-0212 (VMC 2216,3016,4020)10CVR-0056 (2216/3016)STM-0208 (VMC 6030)CVR-0042 (4020)STM-0209 (VMC 8030)CVR-0049 (6030/8030)5STM-0458 (VMC 8030)11PLM-0131STM-0459 (ALL OTHERS)12PLM-0125PALLET CHANGERPART#PART#PART#PART#1STM-01939HDW-030417HDW-047225HDW-0238** 2STM-019410HDW-030118HDW-047226HDW-0472 3STM-019511HDW-023919PLC-001127PLC-0027** 4HDW-011912BRG-004620HDW-047228PLM-0034** 5HDW-057013HDW-023821HDW-047729PLC-0017** 6HDW-029514PLC-007022910046**30HYD-0005** 7PLC-002015PLC-0009*23HYD-0001**31HDW-0295** 8PLC-001016HDW-061724PLM-0039**32HDW-028933PLC-0080 *PLC-0009 THREADED HOLES AL TERNATE UNTHREADED HOLES PLC-0039 ** ASSEMBLY PART # PLC-0005PALLET CHANGERPART#PART#PART#PART# 1STM-027212BRG-004124HDW-057536PLC-0019 2PLC-007313HDW-054825HDW-004837ELE-0146 3HDW-023514PLC-007426PUL-003538HDW-0333 4BRG-004115HDW-023427BRG-004439HDW-0313 BRG-004216HDW-047028HDW-004940HDW-0313 5PLC-0072*17PLC-001329PLC-001541HDW-0444 6HYD-002318BRG-004330CYL-001042HDW-0571 7PLC-001819HDW-050531PLC-002543HDW-0269 8HDW-047220PLC-002832ELE-078644HYD-0004 9PLC-000821HDW-028033PLC-001645HYD-0003 10HDW-030422HDW-069534HDW-023711BRG-004223HDW-034835HDW-0236* COMPLETE HYDRAWLIC PALLET ARM HOUSING ASSY PLC-0002PALLET CHANGERPART#PART#PART#PART# 1PLC-006716PLC-002331HDW-031446HDW-0476 2PLC-004217HDW-039332HDW-029447HDW-0791 3HDW-098818PLC-002233HDW-031448WIR-0112 4HDW-028019PLC-002134PLC-001249WIR-0113 5HDW-047820HDW-032935HDW-033350WIR-0549 6HDW-021821HDW-032936HDW-077951WIR-0405 7STM-066922BRG-004537HDW-03048PLC-005823HDW-048938PLC-0041/409ELE-038624STM-037939HDW-055910PLC-007625HDW-033340PLC-007711PLC-007526HDW-028041HDW-065512HDW-030327HDW-044442PLC-007713HDW-074928PLC-002443HDW-005014HDW-027529HDW-047944HDW-045115HDW-057130HDW-005045HDW-0543PALLET CHANGERPART #PART # 1STM-06625ELE-0939 2STM-06616HDW-0589 3PLC-00687HDW-04434A,B,C ,D,E ELE-0939PALLET CHANGERPART #PART # 1STM-06606HDW-0647 2CNT-01517HDW-0437 3STM-06588HDW-0299 4STM-06599HDW-0443 5HDW-0442* MIRROR LIGHT CURTAIN ASY: PLC-0068PALLET CHANGERPART #PART #PART #PART # 1STM-019111CYL-001821HYD-000531PLM-0056 2STM-018912PLC-001422STM-079132PLM-0081 3PLC-006013VLV-003823HYD-000533PLM-0081 4PLC-007214PMP-000924PLM-000134PCB-0005 5DOR-001815PLM-004225PMP-001235PCB-0019 6STM-028616PLM-015126HYD-000236HYD-0006 7ELE-011217PLM-008827HYD-001237HYD-0007 8ELE-011118PLM-000328STM-079138HYD-0004 9ELE-011019PLM-005729VLV-003039HYD-0003 10STM-040520PLM-005430PLM-007640CYL-0009 * REED SWITCH SENSOR CYL-001115K AIR/OIL SPIDLEPART #PART #PART #PART # 1PLM-0034LUB-0049PLM-0028PLM-0036 2SPN-0053REG-0030ELE-0901REG-0033 3PLM-0034LUB-0091LUB-0099PLM-0024 4PLM-0034PLM-0028ELE-0874PLM-0038 PMP-0024LUB-0051ELE-0873VLV-0054LUB-0100LUB-0036LUB-0094PLM-0048LUB-0098LUB-0090PCB-01575LUB-0097PLM-0034PLM-0165VH5C ROTARY TABLEPART#PART#PART# 1ROT-00896BRG-005011HDW-0162 2HDW-02467BRG-005112ROT-0299 3ROT-00908ROT-029613HDW-0422 4ROT-00129BRG-01115BRG-004910ROT-0191VH5C ROTARY TABLEPART #PART #PART #1ROT-02977BRG-011113HDW-070420VLV-00262HDW-04098ROT-027314HDW-015321PLM-00403HDW-04229HDW-075215STM-019922MTR-0003 OR MTR-0012 4ROT-015210ROT-007516LBL-017923HDW-03785PLM-003411HDW-024817WIR-017724STM-04336ROT-029512HDW-016218HDW-018825LBL-0178VH5C ROTARY TABLEPART#PART#PART#PART#1ROT-00699ROT-007017ROT-007125HDW-01682STM-019710BRG-005318BRG-000326ROT-00743HDW-017411BRG-005219ROT-007227HDW-01714ROT-006712BRG-005320BRG-005528HDW-0247 OR HDW-0992 5HDW-016513HDW-017521BRG-005629ROT-00736HDW-015214BRG-005422BRG-005730HDW-03067ROT-006815BRG-004823HDW-01518HDW-016616HDW-016024ROT-0077VH65 ROTARY TABLEPART #PART #PART #1HDW-02688ROT-005015HDW-016222LBL-01762HDW-02229HDW-023016MTR-000323WIR-0080(9FT), 0081(6FT), 0217(7.5) 3HDW-062010HDW-022617PLM-002324PLM-00464ROT-003711HDW-017918ELE-003725HDW-01775ROT-004312HDW-016219ELE-00656BRG-002413HDW-021220HDW-03657ROT-028014ROT-004021STM-0274VH65 ROTARY TABLEPART#PART#PART#PART# 1ROT-00464HDW-02247ROT-003910ROT-0044 ROT-00475BRG-00248HDW-023011STM-0044 2BRG-00376HDW-01629HDW-0179BRG-00383ROT-0000VH65 ROTARY TABLEPART#PART#PART#PART# 1ROT-00365ROT-00349BRG-003512ROT-0035 2HDW-05026HDW-0172BRG-003613HDW-0426 3HDW-01767ROT-003310HDW-022314HDW-06154HDW-01678HDW-030311HDW-0164TR65 ROTARY TABLEPART#PART#PART#PART#1HDW-02688ROT-028015ROT-005022STM-05072ROT-02879HDW-022616HDW-023023MTR-00033ROT-003710ROT-028117HDW-072724WIR-0080(9FT), 0081(6FT), 0217(7.5FT) 4ROT-004411BRG-001518HDW-016125HDW-03475ROT-030212ROT-030119ROT-028226BRG-00166BRG-001713HDW-016320STM-05067BRG-002414ROT-023021HDW-0366TR65 ROTARY TABLEPART#PART#PART#PART# 1HDW-01545BRG-00458ROT-000012BRG-0024 2ROT-00846ROT-00859BRG-022413HDW-0226 3BRG-00617BRG-003810STM-004414HDW-01614BRG-0062BRG-003711ROT-004515ROT-0283TR65 ROTARY TABLEPART#PART#PART#PART# 1ROT-00364ROT-00347BRG-004210HDW-0173 2HDW-01765ROT-00338BRG-004111ROT-0035 3HDW-01676HDW-01729HDW-0225TR65 ROTARY TABLEPART #1ROT-02916ROT-003411HDW-022516SCL-0023 2HDW-02657HDW-016712ROT-003517SCL-0087 3HDW-02248ROT-003313ROT-028518SCL-0016 4ROT-00369HDW-017214ROT-028619HDW-02225HDW-017610BRG-0036 OR 003715SCL-002220SCL-0018TR65 ROTARY TABLEPART #PART #PART #PART # 1HDW-02247HDW-016113ROT-003319ROT-0058 2BRG-0038 OR BRG-00378ROT-028814HDW-017220BRG-0040 3ROT-00379ROT-003615BRG-0036 OR BRG-003521BRG-0039 4ROT-004310HDW-017616HDW-022522HDW-0173 5BRG-002411HDW-016717HDW-016423ROT-00836HDW-022612ROT-003418ROT-003524HDW-0491TR65 ROTARY TABLEPART #PART #PART #PART # 1STM-05085HDW-03679HDW-018113ROT-0280 2ROT-03256STM-050910ROT-005014BRG-0024 3PLM-00447MTR-012511HDW-023015ROT-00334WIR-0080(9FT), 0081(6FT), 0217(7.5FT)8ROT-028412HDW-0226DUAL VH65 ASSEMBLYPART #PART #PART #PART #1ROT-01888ROT-031415ROT-015022ROT-0329 (RH)2HDW-02229ROT-008216ROT-0311ROT-0394 (LH)3ROT-008210ROT-031217PUL-004123MTR-01254ROT-031311HDW-016218PUL-003224STM-05085HDW-029512ROT-009219BEL-002525WIR-0080(9FT), 0081(6FT), 0217(7.5FT) 6HDW-049713ROT-031520STM-0519714HDW-023121HDW-0593DUAL VH65 ASSYPART#PART#PART#PART# HDW-06457518-34RP7132-1834HDW-0381 ROT-0056HDW-0228HDW-0415ROT-0334 HDW-0322ROT-0054HDW-0050ROT-0334 ROT-0336ROT-0330HDW-0557HDW-0646 BRG-0020HDW-0616ROT-0057ROT-0335ROT-0055ROT-00536918-56325HDW-0229ROTARY ACCESSORIESPART #PART #PART #1ROT-01535HDW-05789HDW-02272HDW-04966STM-031510ROT-00143ROT-00517ROT-001711HDW-04724ROT-0026(VH65), 0028(VH5C)8ROT-001612WIR-0080(9FT), 0081(6FT), 0217(7.5)HYDRAULIC BRAKEPART#PART#PART#PART# 1STM-01296PLM-011511REG-000416PLM-0022 2HYD-00107PLM-004412REG-001717HYD-0008 3HYD-00128PLM-003313HYD-00134PLM-00569PLM-002314HDW-03925HYD-000910PLM-003615PLM-0034* HYDRAULIC OIL FOR BRAKE SYSTEM IS MOBIL DTE LIGHTREMOTE MPGPART#PART#PART#PART# 1PCB-001210CTR-000919ELE-006728HDW-0847 2STM-012811BRG-007720ELE-007829PCB-00193ELE-008312CTR-007721ELE-011230ELE-0070SERVO COOLANTSERVO COOLANTSERVO COOLANTPART #PART #PART #PART # 1CNT-018815HDW-069629PLM-010442HDW-05932CNT-019016CNT-015530PLM-001443BRG-01173PUL-004917CNT-015231HDW-025344HDW-03464PUL-004818CNT-016132PLM-0020/ 014445HDW-0279519CNT-016033HDW-032546HDW-05896MTR-005520CNT-015734WIR-053347LBL-0044/ 0180/ 02467CNT-018921CNT-015635ELE-072248HDW-06718BEL-002822BRG-011836HDW-030249STM-07599CNT-015323HDW-075737HDW-059450HDW-034810HDW-080024HDW-069738HDW-111451ELE-006611BRG-012025CNT-015439WIR-051752HDW-068712BRG-011626PLM-018940AMP-001353WIR-004813BRG-011927PLM-009241STM-0674 (3016/4020)54HDW-030214HDW-075828VLV-0017STM-0675 (6030/8030)55PLM-0089FLOPPY/ZIP DRIVESPART #PART #PART #PART # 1CTR-00785HDW-06499WIR-0659(STD), WIR-0658(ZIP)13WIR-0657 2HDW-08556HDW-045310ELE-0168(STD), WIR-0967(ZIP)14PCB-0156 3CTR-00797HDW-050811WIR-0660(STD), WIR-0656(ZIP)15STM-04704HDW-0594812ELE-0966300/400 ROTARY TABLE BOXPART#PART#PART#PART# 1ROT-036023PUL-004645HDW-101167ROT-00492ROT-034724PUL-004746HDW-048468ROT-00473BRG-013525ROT-034647HDW-034769HDW-0298 4ROT-036426HDW-093948HDW-047370HDW-0955 5ROT-34827ROT-036149HDW-004971HDW-1006 6ROT-036128BRG-0137,013850HDW-033372HDW-0657 7ROT-034929ROT-035051HDW-029673SCL-00418ROT-013630ROT-035752HDW-049474SCL-00819ROT-035231ROT-035553HDW-068275SCL-0083 10ROT-035632HDW-094554HDW-079976ROT-0397 11ROT-039533ROT-037055HDW-030377ROT-0402 12SCL-004034PUL-005656HDW-093378HDW-0475 13HDW-099635BEL-003157HDW-070379HDW-0461 14ROT-035136HDW-100558HDW-093880STM-0920 15HDW-094037STM-072359HDW-093681LBL-0286 16ROT-035838STM-072260HDW-093782SUP-0032 17ROT-035339HDW-003061HDW-093583LBL-0012 18ROT-035440HDW-094162HDW-100684HDW-0349 19HDW-100441HDW-099763HDW-099820SCL-004042HDW-022264HDW-100721ROT-036943HDW-088665ROT-004622MTR-013944HDW-048166ROT-0048V300 Cable:WIR:-0663 CBL ASY; CYL 10’ PWR A/B SLANTWIR:-0664 CBL ASY; CYL 10’ LGIC A/B SLANTWIR:-0665 CBL ASY; CYL 15’ PWR A/B SLANTWIR:-0666 CBL ASY; CYL 15’ LGIC A/B SLANTFULL ENCLOSURE SHEETMETALPART#1STM-04492STM-04503STM-04514STM-04525STM-04536STM-04547STM-04558STM-0456CHAIN HOIST SHEETMETAL 3020PART #PART # 1STM-09597STM-0967 2STM-09618STM-0968 3STM-09629DOR-0066 4STM-096410HDW-1068 5STM-096511HDW-1069 6STM-096612STM-1022CHAIN HOIST SHEETMETAL 4020SPART #PART #1STM-09598STM-09682STM-09609DOR-00633STM-096310HDW-10684STM-096411HDW-10695STM-096512STM-10936STM-096613*STM-10947STM-0967* FOR STANDARD TOOL CHANGER ONLYCHAIN HOIST SHEETMETAL 4525PART #PART # 1STM-09597STM-0967 2STM-09618STM-0968 3STM-09629DOR-0067 4STM-096410HDW-1068 5STM-096511HDW-1069 6STM-096612STM-1092。
IC datasheet pdf-AM26LV32,pdf(Low-voltage high-speed quadruple differential line receiver)
−0.8−0.6−0.4−0.20.20.40.60.811.2 1.4 1.6 1.822.22.4−1V IC − Common-Mode Input Voltage − VNotRecommendedIncreased Receiver Input SensitivityFigure 8. V IC Versus V ID Receiver Sensitivity LevelsAM26LV32C, LOWĆVOLTAGE HIGHĆSPEED QUADRUPLE DIFFERENTIALAM26LV32C, LOWĆVOLTAGE HIGHĆSPEED QUADRUPLE DIFFERENTIALPACKAGING INFORMATIONOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)AM26LV32CD ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV32CDE4ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV32CDG4ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV32CDR ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV32CDRE4ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV32CDRG4ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIM AM26LV32CNSLE OBSOLETE SO NS16TBD Call TI Call TIAM26LV32CNSR ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV32CNSRE4ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV32CNSRG4ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV32ID ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV32IDE4ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV32IDG4ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV32IDR ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV32IDRE4ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV32IDRG4ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV32INS ACTIVE SO NS1650Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV32INSE4ACTIVE SO NS1650Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV32INSG4ACTIVE SO NS1650Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV32INSR ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV32INSRE4ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV32INSRG4ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan-The planned eco-friendly classification:Pb-Free(RoHS),Pb-Free(RoHS Exempt),or Green(RoHS&no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free(RoHS Exempt):This component has a RoHS exemption for either1)lead-based flip-chip solder bumps used between the die and package,or2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free(RoHS compatible)as defined above.Green(RoHS&no Sb/Br):TI defines"Green"to mean Pb-Free(RoHS compatible),and free of Bromine(Br)and Antimony(Sb)based flame retardants(Br or Sb do not exceed0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.TAPE AND REEL INFORMATION*All dimensions are nominal Device Package Type Package DrawingPinsSPQ Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant AM26LV32CDR SOICD 162500330.016.4 6.510.3 2.18.016.0Q1AM26LV32CDR SOICD 162500330.016.4 6.510.3 2.18.016.0Q1AM26LV32CNSR SONS 162000330.016.48.210.5 2.512.016.0Q1AM26LV32IDR SOICD 162500330.016.4 6.510.3 2.18.016.0Q1AM26LV32INSR SO NS 162000330.016.48.210.5 2.512.016.0Q1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) AM26LV32CDR SOIC D162500333.2345.928.6 AM26LV32CDR SOIC D162500346.0346.033.0 AM26LV32CNSR SO NS162000346.0346.033.0 AM26LV32IDR SOIC D162500333.2345.928.6 AM26LV32INSR SO NS162000346.0346.033.0IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by government requirements,testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design.Customers are responsible for their products and applications using TI components.To minimize the risks associated with customer products and applications,customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license,either express or implied,is granted under any TI patent right,copyright,mask work right, or other TI intellectual property right relating to any combination,machine,or process in which TI products or services are rmation published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement e of such information may require a license from a third party under the patents or other intellectual property of the third party,or a license from TI under the patents or other intellectual property of TI.Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties,conditions,limitations,and notices.Reproduction of this information with alteration is an unfair and deceptive business practice.TI is not responsible or liable for such altered rmation of third parties may be subject to additional restrictions.Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice.TI is not responsible or liable for any such statements.TI products are not authorized for use in safety-critical applications(such as life support)where a failure of the TI product would reasonably be expected to cause severe personal injury or death,unless officers of the parties have executed an agreement specifically governing such use.Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications,and acknowledge and agree that they are solely responsible for all legal,regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications,notwithstanding any applications-related information or support that may be provided by TI.Further,Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications.TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or"enhanced plastic."Only products designated by TI as military-grade meet military specifications.Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk,and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS16949requirements.Buyers acknowledge and agree that,if they use any non-designated products in automotive applications,TI will not be responsible for any failure to meet such requirements.Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAmplifiers Audio /audioData Converters Automotive /automotiveDLP®Products Communications and /communicationsTelecomDSP Computers and /computersPeripheralsClocks and Timers /clocks Consumer Electronics /consumer-appsInterface Energy /energyLogic Industrial /industrialPower Mgmt Medical /medicalMicrocontrollers Security /securityRFID Space,Avionics&/space-avionics-defenseDefenseRF/IF and ZigBee®Solutions /lprf Video and Imaging /videoWireless /wireless-appsMailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2010,Texas Instruments Incorporated。
MX29LV160CTMC-70资料
MX29LV160C T/B16M-BIT [2Mx8/1Mx16] CMOS SINGLE VOLTAGE3V ONLY FLASH MEMORY•Ready/Busy# pin (RY/BY#)- Provides a hardware method of detecting program or erase operation completion.•Sector protection- Hardware method to disable any combination of sectors from program or erase operations- Temporary sector unprotect allows code changes in previously locked sectors.•CFI (Common Flash Interface) compliant- Flash device parameters stored on the device and provide the host system to access•100,000 minimum erase/program cycles•Latch-up protected to 100mA from -1V to VCC+1V •Boot Sector Architecture - T = Top Boot Sector - B = Bottom Boot Sector•Low VCC write inhibit is equal to or less than 1.4V •Package type:- 44-pin SOP - 48-pin TSOP - 48-ball CSP- All Pb-free devices are RoHS Compliant •Compatibility with JEDEC standard- Pinout and software compatible with single-power supply Flash•10 years data retentionFEATURES•Extended single - supply voltage range 2.7V to 3.6V •2,097,152 x 8/1,048,576 x 16 switchable •Single power supply operation- 3.0V only operation for read, erase and program operation•Fully compatible with MX29LV160B device •Fast access time: 55R/70/90ns •Low power consumption- 30mA maximum active current - 0.2uA typical standby current •Command register architecture- Byte/word Programming (9us/11us typical)- Sector Erase (Sector structure 16K-Bytex1,8K-Bytex2, 32K-Bytex1, and 64K-Byte x31)•Auto Erase (chip & sector) and Auto Program- Automatically erase any combination of sectors with Erase Suspend capability.- Automatically program and verify data at specified address•Erase Suspend/Erase Resume- Suspends sector erase operation to read data from,or program data to, any sector that is not being erased,then resumes the erase.•Status Reply- Data# Polling & Toggle bit for detection of program and erase operation completion.GENERAL DESCRIPTIONThe MX29L V160C T/B is a 16-mega bit Flash memory organized as 2M bytes of 8 bits or 1M words of 16 bits.MXIC's Flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. The MX29LV160C T/B is packaged in 44-pin SOP , 48-pin TSOP and 48-ball CSP . It is designed to be reprogrammed and erased in system or in standard EPROM programmers.The standard MX29LV160C T/B offers access time as fast as 55ns, allowing operation of high-speed micropro-cessors without wait states. To eliminate bus conten-tion, the MX29LV160C T/B has separate chip enable (CE#) and output enable (OE#) controls.MXIC's Flash memories augment EPROM functionality with in-circuit electrical erasure and programming. The MX29LV160C T/B uses a command register to manage this functionality. The command register allows for 100%TTL level control inputs and fixed power supply levels during erase and programming, while maintaining maxi-mum EPROM compatibility.MXIC Flash technology reliably stores memory contents even after 100,000 erase and program cycles. The MXIC cell is designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cy-cling. The MX29LV160C T/B uses a 2.7V~3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms.The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up pro-tection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V.MX29LV160C T/BPIN CONFIGURATIONSPIN DESCRIPTIONSYMBOL PIN NAME A0~A19Address Input Q0~Q14Data Input/OutputQ15/A-1Q15(Word mode)/LSB addr(Byte mode)CE#Chip Enable Input WE#Write Enable Input BYTE#Word/Byte Selection input RESET#Hardware Reset Pin/Sector Protect UnlockOE#Output Enable Input RY/BY#Ready/Busy OutputVCC Power Supply Pin (2.7V~3.6V)GNDGround Pin48 TSOP (Standard Type) (12mm x 20mm)44 SOP(500 mil)A B C D E F GH6A13A12A14A15A16BYTE#Q15/A-1GND 5A9A8A10A11Q7Q14Q13Q64WE#RESET#NCA19Q5Q12VCC Q43RY/BY#NC A18NC Q2Q10Q11Q32A7A17A6A5Q0Q8Q9Q11A3A4A2A1A0CE#OE#GND48-Ball CSP 6mm x 8mm (Ball Pitch=0.8mm) Top View, Balls Facing Down234567891011121314151617181920212244434241403938373635343332313029282726252423RESET#A18A17A7A6A5A4A3A2A1A0CE#GND OE#Q0Q8Q1Q9Q2Q10Q3Q11WE#A19A8A9A10A11A12A13A14A15A16BYTE#GND Q15/A-1Q7Q14Q6Q13Q5Q12Q4VCCM X 29L V 160C T /BA15A14A13A12A11A10A9A8A19NC WE#RESET#NC NC RY/BY#A18A17A7A6A5A4A3A2A1123456789101112131415161718192021222324A16BYTE#GND Q15/A-1Q7Q14Q6Q13Q5Q12Q4VCC Q11Q3Q10Q2Q9Q1Q8Q0OE#GND CE#A0484746454443424140393837363534333231302928272625MX29LV160C T/BMX29LV160C T/BBLOCK STRUCTURETable 1: MX29LV160CT SECTOR ARCHITECTURESector Sector Size Address range Sector Address Byte Mode Word Mode Byte Mode(x8) Word Mode(x16)A19A18A17A16A15A14A13A12 SA064Kbytes32Kwords000000-00FFFF00000-07FFF00000X X X SA164Kbytes32Kwords010000-01FFFF08000-0FFFF00001X X X SA264Kbytes32Kwords020000-02FFFF10000-17FFF00010X X X SA364Kbytes32Kwords030000-03FFFF18000-1FFFF00011X X X SA464Kbytes32Kwords040000-04FFFF20000-27FFF00100X X X SA564Kbytes32Kwords050000-05FFFF28000-2FFFF00101X X X SA664Kbytes32Kwords060000-06FFFF30000-37FFF00110X X X SA764Kbytes32Kwords070000-07FFFF38000-3FFFF00111X X X SA864Kbytes32Kwords080000-08FFFF40000-47FFF01000X X X SA964Kbytes32Kwords090000-09FFFF48000-4FFFF01001X X X SA1064Kbytes32Kwords0A0000-0AFFFF50000-57FFF01010X X X SA1164Kbytes32Kwords0B0000-0BFFFF58000-5FFFF01011X X X SA1264Kbytes32Kwords0C0000-0CFFFF60000-67FFF01100X X X SA1364Kbytes32Kwords0D0000-0DFFFF68000-6FFFF01101X X X SA1464Kbytes32Kwords0E0000-0EFFFF70000-77FFF01110X X X SA1564Kbytes32Kwords0F0000-0FFFFF78000-7FFFF01111X X X SA1664Kbytes32Kwords100000-10FFFF80000-87FFF10000X X X SA1764Kbytes32Kwords110000-11FFFF88000-8FFFF10001X X X SA1864Kbytes32Kwords120000-12FFFF90000-97FFF10010X X X SA1964Kbytes32Kwords130000-13FFFF98000-9FFFF10011X X X SA2064Kbytes32Kwords140000-14FFFF A0000-A7FFF10100X X X SA2164Kbytes32Kwords150000-15FFFF A8000-AFFFF10101X X X SA2264Kbytes32Kwords160000-16FFFF B0000-B7FFF10110X X X SA2364Kbytes32Kwords170000-17FFFF B8000-BFFFF10111X X X SA2464Kbytes32Kwords180000-18FFFF C0000-C7FFF11000X X X SA2564Kbytes32Kwords190000-19FFFF C8000-CFFFF11001X X X SA2664Kbytes32Kwords1A0000-1AFFFF D0000-D7FFF11010X X X SA2764Kbytes32Kwords1B0000-1BFFFF D8000-DFFFF11011X X X SA2864Kbytes32Kwords1C0000-1CFFFF E0000-E7FFF11100X X X SA2964Kbytes32Kwords1D0000-1DFFFF E8000-EFFFF11101X X X SA3064Kbytes32Kwords1E0000-1EFFFF F0000-F7FFF11110X X X SA3132Kbytes16Kwords1F0000-1F7FFF F8000-FBFFF111110X X SA328Kbytes4Kwords1F8000-1F9FFF FC000-FCFFF11111100 SA338Kbytes4Kwords1FA000-1FBFFF FD000-FDFFF11111101 SA3416Kbytes8Kwords1FC000-1FFFFF FE000-FFFFF1111111XNote: Byte mode: address range A19:A-1, word mode:address range A19:A0.MX29LV160C T/BTable 2: MX29LV160CB SECTOR ARCHITECTURESector Sector Size Address range Sector Address Byte Mode Word Mode Byte Mode (x8)Word Mode (x16)A19A18A17A16A15A14A13A12 SA016Kbytes8Kwords000000-003FFF00000-01FFF0000000X SA18Kbytes4Kwords004000-005FFF02000-02FFF00000010 SA28Kbytes4Kwords006000-007FFF03000-03FFF00000011 SA332Kbytes16Kwords008000-00FFFF04000-07FFF000001X X SA464Kbytes32Kwords010000-01FFFF08000-0FFFF00001X X X SA564Kbytes32Kwords020000-02FFFF10000-17FFF00010X X X SA664Kbytes32Kwords030000-03FFFF18000-1FFFF00011X X X SA764Kbytes32Kwords040000-04FFFF20000-27FFF00100X X X SA864Kbytes32Kwords050000-05FFFF28000-2FFFF00101X X X SA964Kbytes32Kwords060000-06FFFF30000-37FFF00110X X X SA1064Kbytes32Kwords070000-07FFFF38000-3FFFF00111X X X SA1164Kbytes32Kwords080000-08FFFF40000-47FFF01000X X X SA1264Kbytes32Kwords090000-09FFFF48000-4FFFF01001X X X SA1364Kbytes32Kwords0A0000-0AFFFF50000-57FFF01010X X X SA1464Kbytes32Kwords0B0000-0BFFFF58000-5FFFF01011X X X SA1564Kbytes32Kwords0C0000-0CFFFF60000-67FFF01100X X X SA1664Kbytes32Kwords0D0000-0DFFFF68000-6FFFF01101X X X SA1764Kbytes32Kwords0E0000-0EFFFF70000-77FFF01110X X X SA1864Kbytes32Kwords0F0000-0FFFFF78000-7FFFF01111X X X SA1964Kbytes32Kwords100000-10FFFF80000-87FFF10000X X X SA2064Kbytes32Kwords110000-11FFFF88000-8FFFF10001X X X SA2164Kbytes32Kwords120000-12FFFF90000-97FFF10010X X X SA2264Kbytes32Kwords130000-13FFFF98000-9FFFF10011X X X SA2364Kbytes32Kwords140000-14FFFF A0000-A7FFF10100X X X SA2464Kbytes32Kwords150000-15FFFF A8000-AFFFF10101X X X SA2564Kbytes32Kwords160000-16FFFF B0000-B7FFF10110X X X SA2664Kbytes32Kwords170000-17FFFF B8000-BFFFF10111X X X SA2764Kbytes32Kwords180000-18FFFF C0000-C7FFF11000X X X SA2864Kbytes32Kwords190000-19FFFF C8000-CFFFF11001X X X SA2964Kbytes32Kwords1A0000-1AFFFF D0000-D7FFF11010X X X SA3064Kbytes32Kwords1B0000-1BFFFF D8000-DFFFF11011X X X SA3164Kbytes32Kwords1C0000-1CFFFF E0000-E7FFF11100X X X SA3264Kbytes32Kwords1D0000-1DFFFF E8000-EFFFF11101X X X SA3364Kbytes32Kwords1E0000-1EFFFF F0000-FFFFF11110X X X SA3464Kbytes32Kwords1F0000-1FFFFF F8000-FFFFF11111X X XNote: Byte mode:address range A19:A-1, word mode:address range A19:A0.MX29LV160C T/BBLOCK DIAGRAMCONTROL INPUT LOGICPROGRAM/ERASE HIGH VOLTAGEWRITE STATE MACHINE (WSM)STATE REGISTERFLASH ARRAYX-DECODERADDRESS LATCHAND BUFFERY -PASS GATEY -DECODERARRAY SOURCE HVCOMMAND DATADECODERCOMMAND DATA LATCHI/O BUFFERPGM DATA HVPROGRAM DATA LATCHSENSE AMPLIFIERQ0-Q15/A-1A0-A19CE#OE#WE#RESET#MX29LV160C T/BAUTOMATIC PROGRAMMINGThe MX29L V160C T/B is byte/word programmable using the Automatic Programming algorithm. The Automatic Programming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. The typical chip programming time at room temperature of the MX29LV160C T/B is less than 18 sec (byte)/12 sec (word).AUTOMATIC PROGRAMMING ALGORITHMMXIC's Automatic Programming algorithm requires the user to only write program set-up commands (including 2 unlock write cycle and A0H) and a program command (program data and address). The device automatically times the programming pulse width, provides the pro-gram verification, and counts the number of sequences.A status bit similar to Data# Polling and a status bit toggling between consecutive read cycles, provide feed-back to the user as to the status of the programming operation. Refer to write operation status, table 7, for more information on these status bits.AUTOMATIC CHIP ERASEThe entire chip is bulk erased using 10 ms erase pulses according to MXIC's Automatic Chip Erase algorithm. T ypical erasure at room temperature is accomplished in less than 25 second. The Automatic Erase algorithm automatically programs the entire array prior to electrical erase. The timing and verification of electrical erase are controlled internally within the device.AUTOMATIC SECTOR ERASEThe MX29L V160C T/B is sector(s) erasable using MXIC's Auto Sector Erase algorithm. The Automatic Sector Erase algorithm automatically programs the specified sector(s) prior to electrical erase. The timing and verifi-cation of electrical erase are controlled internally within the device. An erase operation can erase one sector, multiple sectors, or the entire device.AUTOMATIC ERASE ALGORITHMMXIC's Automatic Erase algorithm requires the user to write commands to the command register using stan-dard microprocessor write timings. The device will auto-matically pre-program and verify the entire array. Then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. A status bit toggling between consecutive read cycles provides feedback to the user as to the sta-tus of the erasing operation.Register contents serve as inputs to an internal state-machine which controls the erase and programming cir-cuitry. During write cycles, the command register inter-nally latches address and data needed for the program-ming and erase operations. During a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of WE# or CE#, whichever happens first.MXIC's Flash technology combines years of EPROM experience to produce the highest levels of quality, reli-ability, and cost effectiveness. The MX29LV160C T/B electrically erases all bits simultaneously using Fowler-Nordheim tunneling. The bytes are programmed by us-ing the EPROM programming mechanism of hot electron injection.During a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. During a Sector Erase cycle, the command register will only respond to Erase Suspend command. After Erase Suspend is completed, the device stays in read mode. After the state machine has completed its task, it will allow the command regis-ter to respond to its full command set.AUTOMATIC SELECTThe automatic select mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on Q7~Q0. This mode is mainly adapted for programming equipment on the de-vice to be programmed with its programming algorithm. When programming by high voltage method, automatic select mode requires VID (11.5V to 12.5V) on address pin A9. Other address pin A6, A1 and A0 as referring to T able 3. In addition, to access the automatic select codes in-system, the host can issue the automatic select com-mand through the command register without requiring VID, as shown in table 5.To verify whether or not sector being protected, the sec-tor address must appear on the appropriate highest orderMX29LV160C T/BA19A11A9A8A6A5A1A0Description Mode CE#OE#WE#RESET# || | |Q15~Q0A12A10A7A2Read Silicon ID LLHHXXVID XL XLLC2HManufacture Code Device ID Word L L H H X X VID X L X L H 22C4H (Top Boot Block)Byte L L H H X X VID X L X L H XXC4H Device IDWordL L H H X X VID X L X L H 2249H (Bottom Boot Block)ByteL L H H X X VID X L X L H XX49H XX01HSector Protection LLHHSAXVIDXLXHL(protected)VerificationXX00H(unprotected)TABLE 3. MX29LV160C T/B AUTO SELECT MODE BUS OPERATION (A9=VID)NOTE: SA=Sector Address, X=Don't Care, L=Logic Low, H=Logic Highaddress bit (see T able 1 and T able 2). The rest of address bits, as shown in T able 3, are don't care. Once all neces-sary bits have been set as required, the programming equipment may read the corresponding identifier code on Q7~Q0.MX29LV160C T/BQUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODEMX29L V160C T/B is capable of operating in the CFI mode. This mode all the host system to determine the manu-facturer of the device such as operating parameters and configuration. T wo commands are required in CFI mode. Query command of CFI mode is placed first, then the Reset command exits CFI mode. These are described in T able 4.The single cycle Query command is valid only when the device is in the Read mode, including Erase Suspend, Standby mode, and Automatic Select mode; however, it is ignored otherwise.The Reset command exits from the CFI mode to the Read mode, or Erase Suspend mode, or Automatic Se-lect mode. The command is valid only when the device is in the CFI mode.Table 4-1. CFI mode: Identification Data Values(All values in these tables are in hexadecimal)Description Address Address Data(Byte Mode)(Word Mode) Query-unique ASCII string "QRY"201000512211005224120059 Primary vendor command set and control interface ID code2613000228140000 Address for primary algorithm extended query table2A1500402C160000 Alternate vendor command set and control interface ID code (none)2E17000030180000 Address for secondary algorithm extended query table (none)32190000341A0000 Table 4-2. CFI Mode: System Interface Data Values(All values in these tables are in hexadecimal)Description Address Address Data(Byte Mode)(Word Mode) VCC supply, minimum (2.7V)361B0027 VCC supply, maximum (3.6V)381C0036 VPP supply, minimum (none)3A1D0000 VPP supply, maximum (none)3C1E0000 Typical timeout for single word/byte write (2N us)3E1F0004 Typical timeout for Minimum size buffer write (2N us) (not supported)40200000 Typical timeout for individual sector erase (2N ms)4221000A Typical timeout for full chip erase (2N ms)44220000 Maximum timeout for single word/byte write times (2N X Typ)46230005 Maximum timeout for buffer write times (2N X Typ)48240000 Maximum timeout for individual sector erase times (2N X Typ)4A250004 Maximum timeout for full chip erase times (not supported)4C260000MX29LV160C T/B Table 4-3. CFI Mode: Device Geometry Data Values(All values in these tables are in hexadecimal)Description Address Address Data(Byte Mode)(Word Mode) Device size (2N bytes)4E270015 Flash device interface code (x8/x16 async.)5028000252290000 Maximum number of bytes in multi-byte write (not supported)542A0000562B0000 Number of erase sector regions582C0004 Erase sector region 1 information (refer to the CFI publication 100)5A2D00005C2E00005E2F004060300000 Erase sector region 2 information62310001643200006633002068340000 Erase sector region 3 information6A3500006C3600006E37008070380000 Erase sector region 4 information7239001E743A0000763B0000783C0001 Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values(All values in these tables are in hexadecimal)Description Address Address Data(Byte Mode)(Word Mode) Query-unique ASCII string "PRI"804000508241005284420049 Major version number, ASCII86430031 Minor version number, ASCII88440030 Address sensitive unlock (0=required, 1= not required)8A450000 Erase suspend (2= to read and write)8C460002 Sector protect (N= # of sectors/group)8E470001 Temporary sector unprotect (1=supported)90480001 Sector protect/chip unprotect scheme92490004 Simultaneous R/W operation (0=not supported)944A0000 Burst mode type (0=not supported)964B0000 Page mode type (0=not supported)984C0000MX29LV160C T/Bin the improper sequence will reset the device to the read mode. Table 5 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in progress.COMMAND DEFINITIONSDevice operations are selected by writing specific ad-dress and data sequences into the command register.Writing incorrect address and data values or writing them First Bus Second Bus Third Bus Fourth Bus Fifth Bus Sixth Bus CommandBusCycleCycleCycleCycleCycle CycleCycle AddrData Addr Data Addr Data Addr DataAddrData Addr DataReset 1XXXH F0H Read1RARDRead Silicon IDWord 4555H AAH 2AAH 55H 555H 90H ADI DDI Byte4AAAH AAH 555H 55H AAAH 90H ADI DDI Sector Protect Word4555H AAH 2AAH55H555H90H (SA)XX00H Verifyx02HXX01H Byte4AAAH AAH 555H55HAAAH90H (SA)00H x04H01H Program Word 4555H AAH 2AAH 55H 555H A0H PA PD Byte4AAAH AAH 555H 55H AAAH A0H PAPDChip Erase Word 6555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H Byte6AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H AAAH 10H Sector Erase Word 6555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H Byte6AAAH AAH 555H 55HAAAH80H AAAH AAH555H 55HSA30HSector Erase Suspend 1XXXH B0H Sector Erase Resume 1XXXH 30H CFI QueryWord 155H 98ByteAAHTABLE 5. MX29L V160C T/B COMMAND DEFINITIONSNote:1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A19=do not care. (Refer to table 3)DDI = Data of Device identifier : C2H for manufacture code, C4H/49H (x8) and 22C4H/2249H (x16) for device code. X = X can be VIL or VIHRA=Address of memory location to be read. RD=Data to be read at location RA.2.PA = Address of memory location to be programmed. PD = Data to be programmed at location PA. SA = Address of the sector to be erased.3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or 555H to Address A10~A-1 in byte mode.Address bit A11~A19=X=Don't care for all address commands except for Program Address (P A) and Sector Address (SA). Write Sequence may be initiated with A11~A19 in either state.4. For Sector Protect Verify operation: If read out data is 01H, it means the sector has been protected. If read out data is 00H,it means the sector is still not being protected.5. Any number of CFI data read cycles are permitted.MX29LV160C T/BTABLE 6. MX29L V160C T/B BUS OPERATIONADDRESS Q8~Q15 DESCRIPTION CE#OE#WE#RE- A19A11A9A8A6A5A1A0Q0~Q7BYTE BYTESET#A12A10A7A2=VIH=VIL Read L L H H AIN Dout Dout Q8~Q14=High ZQ15=A-1 Write L H L H AIN DIN(3)DINReset X X X L X High Z High Z High Z Temporary sector unlock X X X VID AIN DIN DIN High Z Output Disable L H H H X High Z High Z High Z Standby Vcc±X X Vcc±X High Z High Z High Z0.3V0.3VSector Protect L H L VID SA X X X L X H L DIN X XChip Unprotect L H L VID X X X X H X H L DIN X X Sector Protection Verify L L H H SA X VID X L X H L CODE(5)X XNOTES:1.Manufacturer and device codes may also be accessed via a command register write sequence. Refer to T able 4.2. VID is the high voltage, 11.5V to 12.5V.3.Refer to T able 5 for valid Data-In during a write operation.4.X can be VIL or VIH.5.Code=00H/XX00H means unprotected.Code=01H/XX01H means protected.6.A19~A12=Sector address for sector protect.7.The sector protect and chip unprotect functions may also be implemented via programming equipment.MX29LV160C T/BREQUIREMENTS FOR READING ARRAY DATAT o read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should re-main at VIH.The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory con-tent occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. WRITE COMMANDS/COMMAND SEQUENCESTo program data to the device or erase sectors of memory, the system must drive WE# and CE# to VIL, and OE# to VIH.An erase operation can erase one sector, multiple sec-tors, or the entire device. T able 1 and T able 2 indicate the address space that each sector occupies. A "sector ad-dress" consists of the address bits required to uniquely select a sector. The Writing specific address and data commands or sequences into the command register ini-tiates device operations. Table 5 defines the valid regis-ter command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. Section has de-tails on erasing a sector or the entire chip, or suspend-ing/resuming the erase operation.After the system writes the "read silicon-ID" and "sector protect verify" command sequence, the device enters the "read silicon-ID" and "sector protect verify" mode. The system can then read "read silicon-ID" and "sector protect verify" codes from the internal register (which is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this mode. Refer to the "read silicon-ID" and "sector protect verify" Mode and "read silicon-ID" and "sector protect verify" Command Se-quence section for more information.ICC2 in the DC Characteristics table represents the ac-tive current specification for the write mode. The "AC Characteristics" section contains timing specification table and timing diagrams for write operations. STANDBY MODEWhen using both pins of CE# and RESET#, the device enter CMOS Standby with both pins held at Vcc ± 0.3V. If CE# and RESET# are held at VIH, but not within the range of VCC ± 0.3V, the device will still be in the standby mode, but the standby current will be larger. During Auto Algorithm operation, Vcc active current (ICC2) is required even CE# = "H" until the operation is completed. The device can be read with standard access time (tCE) from either of these standby modes, before it is ready to read data.OUTPUT DISABLEWith the OE# input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins to be in a high impedance state.RESET# OPERATIONThe RESET# pin provides a hardware method of reset-ting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write com-mands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be re-initiated once the device is ready to accept another com-mand sequence, to ensure data integrity.Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3V, the standby current will be greater.The RESET# pin may be tied to system reset circuitry.A system reset would that also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.If RESET# is asserted during a program or erase opera-tion, the RY/BY# pin remains a "0" (busy) until the inter-MX29LV160C T/Bnal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset op-eration is complete. If RESET# is asserted when a pro-gram or erase operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# pa-rameters and to Figure 22 for the timing diagram.READ/RESET COMMANDThe read or reset operation is initiated by writing the read/ reset command sequence into the command register. Microprocessor read cycles retrieve array data. The de-vice remains enabled for reads until the command regis-ter contents are altered.If program-fail or erase-fail happen, the write of F0H will reset the device to abort the operation. A valid com-mand must then be written to place the device in the desired state.SILICON-ID READ COMMANDFlash memories are intended for use in applications where the local CPU alters memory contents. As such, manu-facturer and device codes must be accessible while the device resides in the target system. PROM program-mers typically access signature codes by raising A9 to a high voltage (VID). However, multiplexing high voltage onto address lines is not generally desired system de-sign practice.The MX29LV160C T/B contains a Silicon-ID-Read op-eration to supple traditional PROM programming meth-odology. The operation is initiated by writing the read silicon ID command sequence into the command regis-ter. Following the command write, a read cycle with A1=VIL, A0=VIL retrieves the manufacturer code of C2H/ 00C2H. A read cycle with A1=VIL, A0=VIH returns the device code of C4H/22C4H for MX29L V160CT, 49H/2249H for MX29L V160CB.The system must write the reset command to exit the "Silicon-ID Read Command" code.AUTOMATIC CHIP ERASE COMMANDSChip erase is a six-bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command 80H. T wo more "unlock" write cycles are then followed by the chip erase command 10H. The device does not require the system to entirely pre-program prior to executing the Automatic Chip Erase. Upon executing the Automatic Chip Erase, the device will automatically program and verify the entire memory for an all-zero data pattern. When the device is auto-matically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. The erase and verify operations are completed when the data on Q7 is "1" at which time the device returns to the Read mode. The system is not required to provide any control or timing during these operations.When using the Automatic Chip Erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required).If the Erase operation was unsuccessful, the data on Q5 is "1" (see Table 8), indicating the erase operation ex-ceed internal timing limit.The automatic erase begins on the rising edge of the last WE# or CE# pulse, whichever happens first in the com-mand sequence and terminates when either the data on Q7 is "1" at which time the device returns to the Read mode or the data on Q6 stops toggling for two consecu-tive read cycles at which time the device returns to the Read mode.。
- 1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
- 2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
- 3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。
Features•Fast Read Access Time - 90 ns•Dual Voltage Range OperationLow Voltage Power Supply Range, 3.0V to 3.6Vor Standard 5V ± 10% Supply Range•Compatible with JEDEC Standard AT27C020•Low Power CMOS Operation20 µA max. (less than 1 µA typical) Standby for V CC = 3.6V29 mW max. Active at 5 MHz for V CC = 3.6V•JEDEC Standard Packages32-Lead PLCC32-Lead TSOP (8 X 20 mm)32-Lead VSOP (8 x 14 mm)•High Reliability CMOS Technology2,000V ESD Protection200 mA Latchup Immunity•Rapid™Programming Algorithm - 100 µs/byte (typical)•Two-Line Control•CMOS and TTL Compatible Inputs and OutputsJEDEC Standard for LVTTL•Integrated Product Identification Code•Commercial and Industrial Temperature RangesDescriptionThe AT27LV020A is a high performance, low power, low voltage 2,097,152 bit one-time programmable read only memory (OTP EPROM) organized as 256K by 8 bits. It requires only one supply in the range of 3.0 to 3.6V in normal read mode operation, making it ideal for fast, portable systems using battery power.Pin ConfigurationsPin Name FunctionA0 - A17AddressesO0 - O7OutputsCE Chip EnableOE Output EnablePGM Program StrobePLCC, T op View TSOP, VSOP T op ViewType 1Atmel's innovative design techniques provide fast speeds that rival 5V parts while keeping the low power consump-tion of a 3V supply. At V CC = 3.0V, any byte can be accessed in less than 90 ns. With a typical power dissipa-tion of only 18 mW at 5 MHz and V CC = 3.3V, the AT27LV020A consumes less than one fifth the power of a standard 5V EPROM. Standby mode supply current is typi-cally less than 1 µA at 3.3V.The AT27LV020A is available in industry standard JEDEC approved one-time programmable (OTP) plastic PLCC, TSOP and VSOP packages. All devices feature two-line bus contention.The AT27LV020A operating with V CC at 3.0V produces TTL level outputs that are compatible with standard TTL logic devices operating at V CC = 5.0V. The device is also capable of standard 5-volt operation making it ideally suited for dual supply range systems or card products that are pluggable in both 3-volt and 5-volt hosts.Atmel's AT27LV020A has additional features to ensure high quality and efficient production use. The Rapid™Pro-gramming Algorithm reduces the time required to program the part and guarantees reliable programming. Program-ming time is typically only 100 µs/byte. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry standard programming equipment to select the proper pro-gramming algorithms and voltages. The AT27LV020A pro-grams exactly the same way as a standard 5V AT27C020 and uses the same programming equipment.System ConsiderationsSwitching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these tran-sients may exceed data sheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency, low inherent inductance, ceramic capacitor should be uti-lized for each device. This capacitor should be connected between the V CC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again connected between the V CC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array.AT27LV020ABlock Diagram Absolute Maximum Ratings**NOTICE: Stresses beyond those listed under “Absolute Maxi-mum Ratings” may cause permanent damage to the device.This is a stress rating only and functional operation of the deviceat these or any other conditions beyond those indicated in theoperational sections of this specification is not implied. Expo-sure to absolute maximum rating conditions for extended peri-ods may affect device reliability.Note: 1.Minimum voltage is -0.6V dc which may undershootto -2.0V for pulses of less than 20 ns.Maximum out-put pin voltage is V CC + 0.75V dc which may beexceeded if certain precautions are observed (con-sult application notes) and which may overshoot to+7.0 volts for pulses of less than 20 ns. Operating ModesIL IH2.Read, output disable, and standby modes require,3.0V ≤ V CC≤ 3.6V, or4.5V ≤ V CC≤5.5V.3.Refer to Programming Characteristics. Programmingmodes require V CC = 6.5V.4.V H = 12.0 ± 0.5V.held low (V IL), except A9 which is set to VH and A0which is toggled low (V IL) to select the Manufacturer’sIdentification byte and high (V IH) to select the DeviceCode byte.T emperature Under Bias..................................-40°C to +85°C Storage T emperature.....................................-65°C to +125°C Voltage on Any Pin withRespect to Ground........................................-2.0V to +7.0V (1) Voltage on A9 withRespect to Ground .....................................-2.0V to +14.0V (1) V PP Supply Voltage withRespect to Ground......................................-2.0V to +14.0V (1)Mode \ Pin CE OE PGM Ai V PP V CC Outputs Read (2)V IL V IL X (1)Ai X V CC(2)D OUT Output Disable (2)X V IH X X X V CC(2)High Z Standby (2)V IH X X X X V CC(2)High Z Rapid Program (3)V IL V IH V IL Ai V PP V CC(3)D IN PGM Verify (3)V IL V IL V IH Ai V PP V CC(3)D OUT PGM Inhibit (3)V IH X X X V PP V CC(3)High ZProduct Identification (3, 5)V IL V IL XA9 = V H(4)A0 = V IH or V ILA1 - A17 = V ILX V CC(3)Identification Code元器件交易网DC and AC Operating Conditions for Read OperationDC and Operating Characteristics for Read OperationAT27L V020A-90-12-15Operating T emperature (Case)Com.0°C - 70°C 0°C - 70°C 0°C - 70°C Ind.-40°C - 85°C -40°C - 85°C -40°C - 85°C V CC Power Supply3.0V to 3.6V 3.0V to 3.6V 3.0V to 3.6V 5V ± 10%5V ± 10%5V ± 10%Symbol Parameter Condition MinMax Units V CC = 3.0V to 3.6VI LI Input Load Current V IN = 0V to V CC ±1µA I LO Output Leakage Current V OUT = 0V to V CC ±5µA I PP1 (2)Read/Standby Current V PP = V CC10µA I SBV CC (1) Standby CurrentI SB1 (CMOS), CE = V CC ± 0.3V 20µA I SB2 (TTL),CE = 2.0 to V CC + 0.5V100µA I CC V CC Active Current f = 5 MHz, I OUT = 0 mA,CE = V IL8mA V IL Input Low Voltage -0.60.8V V IH Input High Voltage 2.0V CC + 0 .5V V OL Output Low Voltage I OL = 2.0 mA 0.4V V OH Output High Voltage I OH = -2.0 mA 2.4V V CC = 4.5V to 5.5VI LI Input Load Current V IN = 0V to V CC ±1µA I LO Output Leakage Current V OUT = 0V to V CC ±5µA I PP1 (2)Read/Standby Current V PP = V CC10µA I SB V CC (1) Standby Current I SB1 (CMOS), CE = V CC ± 0.3V 100µA I SB2 (TTL), CE = 2.0 to V CC + 0.5V 1mA I CC V CC Active Current f = 5 MHz, I OUT = 0 mA,CE = V IL25mA V IL Input Low Voltage -0.60.8V V IH Input High Voltage 2.0V CC + 0.5V V OL Output Low Voltage I OL = 2.1 mA 0.4V V OHOutput High VoltageI OH = -400 µA2.4V元器件交易网AT27LV020A AC Characteristics for Read Operation (V CC = 3.0V to 3.6V and 4.5V to 5.5V)AC Waveforms for Read Operation (1)Notes: 1.Timing measurement references are 0.8V and 2.0V.Input AC drive levels are 0.45V and 2.4V, unless oth-erwise specififed.2.CE - t OE after the fallingedge of CE without impact on t CE.3.ACC - t OE after the addressis valid without impact on t ACC.4.This parameter is only sampled and is not 100%tested.5.Output float is defined as the point when data is nolonger driven.AT27L V020A-90-12-15Symbol Parameter Condition Min Max Min Max Min Max Units t ACC(3)Address to Output Delay CE = OE = V IL90120150ns t CE(2)CE to Output Delay OE = V IL90120150ns t OE (2, 3)OE to Output Delay CE = V IL505060ns t DF (4, 5)OE or CE High to Output Float,whichever occurred first404050nst OH Output Hold from Address, CE or OE,whichever occurred first000ns元器件交易网Input Test Waveform and Measurement LeveltR, tF < 20 ns (1% to 90%)Output Test LoadNote:CL = 1 pF including jig clearance.Pin Capacitance (f = 1 MHz, T = 25°C)(1)Note:1.T ypical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.TypMax Units Conditions C IN 48pF V IN = 0V C OUT 812pFV OUT = 0V元器件交易网AT27LV020AProgramming Waveforms (1)Notes:1.The Input Timing Reference is 0.8V for V IL and2.0V for V IH .2.t OE and t DFP are characteristics of the device but must be accomodated by the programmer.3.When programming the A T27L V020A a 0.1 µF capacitor is required across V PP and ground to suppress spurious voltagetransients.DC Programming CharacteristicsT A = 25 ± 5°C, V CC = 6.5 ± 0.25V , V PP = 13.0 ± 0.25VSymbol Parameter Test Conditions Limits UnitsMinMax I LI Input Load Current V IN = V IL , V IH±10µAV IL Input Low Level -0.60.8V V IH Input High Level 2.0V CC + 0.5V V OL Output Low Voltage I OL = 2.1 mA 0.4V V OH Output High VoltageI OH = -400 µA 2.4V I CC2V CC Supply Current (Program and Verify)40mA I PP2V PP Supply CurrentCE = PGM = V IL20mA V IDA9 Product Identification Voltage11.512.5V元器件交易网AC Programming CharacteristicsT A = 25 ± 5°C, V CC = 6.5 ± 0.25V, V PP = 13.0 ± 0.25V*AC Conditions of Test:Input Rise and Fall Times (10% to 90%).............20 nsInput Pulse Levels..................................0.45V to 2.4VInput Timing Reference Level..................0.8V to 2.0VOutput Timing Reference Level...............0.8V to 2.0V Notes: 1.V CC must be applied simultaneously or before V PP and removed simultaneously or after V PP.2.This parameter is only sampled and is not 100%tested. Output Float is defined as the point wheredata is no longer driven —see timing diagram.3.Program Pulse width tolerance is 100 µsec ± 5%. Atmel's 27L V020A IntegratedProduct Identification Code(1)Note: 1.The A T27L V020A has the same Product Identification Code as the A T27C020. Both are programming com-patible.Rapid Programming AlgorithmA 100 µs PGM pulse width is used to program. The address is set to the first location. V CC is raised to 6.5V and V PP is raised to 13.0V. Each address is first programmed with one 100 µs PGM pulse without verification. Then a verification/reprogramming loop is executed for each address. In the event a byte fails to pass verification, up to 10 successive 100 µs pulses are applied with a verification after each pulse. If the byte fails to verify after 10 pulses have been applied, the part is considered failed. After the byte verifies properly, the next address is selected until all have been checked. V PP is then lowered to 5.0V and V CC to 5.0V. All bytes are read again and compared with the original data to determine if the device passes or fails.Symbol Parameter TestConditions*(1)LimitsUnitsMin Maxt AS Address Setup Time2µs t CES CE Setup Time2µs t OES OE Setup Time2µs t DS Data Setup Time2µs t AH Address Hold Time0µs t DH Data Hold Time2µst DFP OE High to OutputFloat Delay0130nst VPS V PP Setup Time2µs t VCS V CC Setup Time2µs t PW PGM Program Pulse Width95105µs t OE Data Valid from OE150nst PRT V PP Pulse Rise TimeDuring Programming50nsCodesPins HexData A0O7O6O5O4O3O2O1O0Manufacturer0000111101E Device T ype11000011086元器件交易网AT27LV020A Ordering Informationt ACC (ns)I CC (mA)V CC = 3.6VOrdering Code Package Operation Range Active Standby9080.02A T27LV020A-90JC32J CommercialA T27LV020A-90TC32T(0°C to 70°C)A T27LV020A-90VC32V80.02A T27LV020A-90JI32J IndustrialA T27LV020A-90TI32T(-40°C to 85°C)A T27LV020A-90VI32V12080.02A T27LV020A-12JC32J CommercialA T27LV020A-12TC32T(0°C to 70°C)A T27LV020A-12VC32V80.02A T27LV020A-12JI32J IndustrialA T27LV020A-12TI32T(-40°C to 85°C)A T27LV020A-12VI32V15080.02A T27LV020A-15JC32J CommercialA T27LV020A-15TC32T(0°C to 70°C)A T27LV020A-15VC32V80.02A T27LV020A-15JI32J IndustrialA T27LV020A-15TI32T(-40°C to 85°C)A T27LV020A-15VI32VPackage Type32J32 Lead, Plastic J-Leaded Chip Carrier (PLCC)32T32 Lead, Plastic Thin Small Outline Package (TSOP) 8 x 20 mm32V32 Lead, Plastic Thin Small Outline Package (VSOP) 8 x 14 mm元器件交易网。