HI-3583PQT-10资料

(Note: All 3 VDD pins must be connected to the same 3.3V supply)
64 - Pin Plastic 9mm x 9mm Chip-Scale Package
52 - D/R1 51 - RIN2B 50 - RIN2A 49 - RIN1B 48 - RIN1A 47 - VDD 46 - N/C 45 - TEST 44 - MR 43 - TXCLK 42 - CLK 41 - RSR 40 - N/C
GENERAL DESCRIPTION
The HI-3582/HI-3583 from Holt Integrated Circuits are silicon gate CMOS devices for interfacing a 16-bit parallel data bus directly to the ARINC 429 serial bus. The HI-3582/HI-3583 design offers many enhancements to the industry standard HI-8282 architecture. The device provides two receivers each with label recognition, 32 by 32 FIFO, and analog line receiver. Up to 16 labels may be programmed for each receiver. The independent transmitter has a 32 X 32 FIFO and a built-in line driver. The status of all three FIFOs can be monitored using the external status pins, or by polling the HI-3582/HI-3583 status register. Other new features include a programmable option of data or parity in the 32nd bit, and the ability to unscramble the 32 bit word. Also, versions are available with different values of input resistance and output resistance to allow users to more easily add external lightning protection circuitry. The 16-bit parallel data bus exchanges the 32-bit ARINC data word in two steps when either loading the transmitter or interrogating the receivers. The databus and all control signals are CMOS and TTL compatible. The HI-3582/HI-3583 apply the ARINC protocol to the receivers and transmitter. Timing is based on a 1 Megahertz clock. Although the line driver shares a common substrate with the receivers, the design of the physical isolation does not allow parasitic crosstalk, and thereby achieves the same isolation as common hybrid layouts.
PIN CONFIGURATIONS (Top View)
(See page 14 for additional pin configuration)
See Note below
64 - N/C 63 - RIN2B 62 - RIN2A 61 - RIN1B 60 - RIN1A 59 - N/C 58 - VDD 57 - VDD 56 - VDD 55 - N/C 54 - TEST 53 - MR 52 - TXCLK 51 - CLK 50 - RSR 49 - N/C
FUNCTION
POWER INPUT INPUT INPUT INPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT INPUT INPUT I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O POWER I/O I/O I/O I/O I/O I/O INPUT INPUT OUTPUT OUTPUT OUTPUT POWER OUTPUT OUTPUT POWER INPUT INPUT INPUT INPUT OUTPUT INPUT INPUT
HI-3582PQI HI-3582PQT & HI-3583PQI HI-3583PQT
39 - N/C 38 - CWSTR 37 - ENTX 36 - V+ 35 - TXBOUT 34 - TXAOUT 33 - V32 - FFT 31 - HFT 30 - TX/R 29 - PL2 28 - PL1 27 - BD00
FEATURES
! ! ! ! ! ! ! ! ! ! ! ! ! ! ARINC specification 429 compatible 3.3V logic supply operation Dual receiver and transmitter interface Analog line driver and receivers connect directly to ARINC bus Programmable label recognition On-chip 16 label memory for each receiver 32 x 32 FIFOs each receiver and transmitter Independent data rate selection for Transmitter and each receiver Status register Data scramble control 32nd transmit bit can be data or parity Self test mode Low power Industrial & full military temperature ranges
01/06
元器件交易网
HI-3582, HI-3583
PIN DESCRIPTIONS
SIGNAL
VDD RIN1A RIN1B RIN2A RIN2B D/R1 FF1 HF1 D/R2 FF2 HF2 SEL EN1 EN2 BD15 BD14 BD13 BD12 BD11 BD10 BD09 BD08 BD07 BD06 GND BD05 BD04 BD03 BD02 BD01 BD00 PL1 PL2 TX/R HFT FFT VTXAOUT TXBOUT V+ ENTX CWSTR RSR CLK TX CLK MR TEST
DESCRIPTION
+3.3V power supply pin ARINC receiver 1 positive input ARINC receiver 1 negative input ARINC receiver 2 positive input ARINC receiver 2 negative input Receiver 1 data ready flag FIFO full Receiver 1 FIFO Half full, Receiver 1 Receiver 2 data ready flag FIFO full Receiver 2 FIFO Half full, Receiver 2 Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2) Data Bus control, enables receiver 1 data to outputs Data Bus control, enables receiver 2 data to outputs if EN1 is high Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus 0V Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Latch enable for byte 1 entered from data bus to transmitter FIFO. Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow PL1. Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high after transmission and FIFO empty. Transmitter FIFO Half Full Transmitter FIFO Full -9.5V to -10.5V Line driver output - A side Line driver output - B side +9.5V to +10.5V Enable Transmission Clock for control word register Read Status Register if SEL=0, read Control Register if SEL=1 Master Clock input Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80. Master Reset, active low Disable Transmitter output if high (pull-down)
FF1 - 1 HF1 - 2 D/R2 - 3 FF2 - 4 HF2 - 5 SEL - 6 EN1 - 7 EN2 - 8 BD15 - 9 BD14 - 10 BD13 - 11 BD12 - 12 BD11 - 13
N/C - 17 BD10 - 18 BD09 - 19 BD08 - 20 BD07 - 21 BD06 - 22 GND - 23 N/C - 24 N/C - 25 N/C - 26 N/C - 27 BD05 - 28 BD04 - 29 BD03 - 30 BD02 - 31 N/C - 32
元器件交易网
HI-3582, HI-3583
JanuaryERMINAL IC
APPLICATIONS
! Avionics data communication ! Serial to parallel conversion ! Parallel to serial conversion
48 - CWSTR 47 - ENTX 46 - N/C 45 - V+ 44 - TXBOUT 43 - TXAOUT 42 - V41 - N/C 40 - FFT 39 - HFT 38 - TX/R 37 - PL2 36 - PL1 35 - BD00 34 - BD01 33 - N/C
N/C - 1 D/R1 - 2 FF1 - 3 HF1 - 4 D/R2 - 5 FF2 - 6 HF2 - 7 SEL - 8 EN1 - 9 EN2 - 10 N/C - 11 BD15 - 12 BD14 - 13 BD13 - 14 BD12 - 15 BD11 - 16
HI-3582PCI HI-3582PCT & HI-3583PCI HI-3583PCT
52 - Pin Plastic Quad Flat Pack (PQFP)
(DS3582 Rev. F)
HOLT INTEGRATED CIRCUITS
BD10 - 14 BD09 - 15 BD08 - 16 BD07 - 17 BD06 - 18 N/C - 19 GND - 20 N/C - 21 BD05 - 22 BD04 - 23 BD03 - 24 BD02 - 25 BD01 - 26