Pacemaker-1.1-Clusters_from_Scratch-zh-CN
病态窦房结综合征中西医结合诊疗研究进展
病态窦房结综合征中西医结合诊疗研究进展2.辽宁中医药大学附属医院，辽宁沈阳）摘要：病态窦房结综合征（SSS）是因窦房结起搏或传导异常导致功能障碍，诱发多种心律失常的一种综合征。
对于本病的发病机制研究得到的结论尚未统一，仍需要进一步研究。
现代医学认为除心脏起搏器植入治疗外西药治疗本病不良反应极多。
近年来随着中医药事业的快速发展，中西医结合治疗本病成为热门话题。
对于本病，中西医研究百花齐放，相互结合，本文对SSS的研究现状及发病机制和治疗进行总结和论述。
关键词：病窦；发病机制；基因通路；综述；心脏起搏Research progress in the diagnosis and treatment of sick sinus syndrome by combining traditional Chinese and western medicine.YANGMeng 1 , HOU Ping 2(1.Liaoning University of TCM, Shenyang, Liaoning, China;2.The Affiliated Hospital of Liaoning University of TCM, Shenyang, Liaoning, China)Abstract: Sick sinus syndrome (SSS) is a syndrome that causesdysfunction due to abnormal pacing or conduction of the sinus node and induces various arrhythmias. The conclusions of the study on the pathogenesis of this disease have not been unified, and further research is still needed. Modern medicine believes that in addition to cardiac pacemaker implantation, there are many adverse reactions in the treatment of this disease with western medicine. In recent years, with the rapid development of traditional Chinese medicine, the treatment of this disease by combining traditional Chinese and western medicine has become a hot topic. For this disease, the research of traditional Chinese and western medicine is in full bloom andcombined with each other. This paper summarizes and discusses the research status, pathogenesis and treatment of SSS.Key words:sick sinus; Pathogenesis; Gene pathway; overview; cardiacpacing病态窦房结综合征(sick sinus syndrome , SSS)是由窦房结及其周围组织器质性病变导致窦房结冲动形成及传导障碍，进而产生多种心律失常的临床综合征，多伴有心、脑、肾等器官供血不足表现，严重者可导致晕厥、猝死，是临床常见的心血管疑难病症。
MAPMAKER操作方式
Mapmaker 一般的运行程序（适用于较少的区域作图）1.photo xxx.raw2.Prepare date(可简写pd）xx.txt3.seq all4.Group5.Centimargan function kosambi(可简写cent kos)6.Error detection on7.Sequence {1 2 3 4 5 6 7}(连锁群）pare 连锁群的最佳顺序（一般情况下第一个最好）9.Sequence 最优序列（不加括号）10.Map 作图11.List loci 显示名maker中基因型的数目特点12.Lod table 查看marker间的距离和lod值13.Suggest sabset 实现自动分组14.用compare 对各个subset来实现自动分组15.Try 未能放进去的marker16.键入sabset顺序，用map查看markers间完整图。
Mapmaker全基因组作图Dealing with larger data setPhoto 文件名或pd 文件名1.unite cM2.Centimogan function kosambi3.Print name on4.Triple error detectionrmationess criteria 4.06.Make chromose chrom1.......chrom127.Seq 标记8.Anchor chrom1Repeat 7-89.Seq 标记10.Anchor chrom1211.Seq all12.Two paint13.Seq all14.Assign15.List down16.Seq unassigned17.List status18.Links19.Seq 标记20.Attach chrom1Repeat 19-2021.Seq chrom122.Three point23.Order24.Seq order 125.Ripple26.Frame work27.Seq assigned28.placeLander ES, Green P, Abrahamson J, Barlow A, Daly MJ, Lincoln SE, Newburg L: MAPMAKER: an interactive computer package for constructing primary genetic linkage maps of experimental and natural populations. Genomics 1987, 1:174-181做基因定位的都应该熟悉Mapmaker软件。
pacemaker编译
pacemaker编译编译 Pacemaker 是一个涉及到高可用性集群管理的软件项目。
下面我将从多个角度对 Pacemaker 编译进行全面回答。
首先，编译 Pacemaker 需要一些前提条件和依赖项。
你需要确保你的系统上已经安装了以下软件包或库：1. C 编译器（如 GCC）和 C++ 编译器（如 g++）。
2. GNU Make 工具。
3. Autotools 工具链（包括 Autoconf、Automake 和Libtool）。
4. 必要的开发库和头文件，例如 GLib、DBus、Corosync、OpenAIS 等。
5. 一些额外的工具，如 pkg-config、libtoolize 等。
一旦你的系统满足了这些依赖项，你可以按照以下步骤编译Pacemaker：1. 下载 Pacemaker 的源代码。
你可以从官方网站或源代码仓库获取最新的稳定版本或开发版本。
2. 解压源代码包，并进入源代码目录。
3. 运行 Autotools 工具链生成配置脚本。
你可以运行以下命令：./autogen.sh.这将根据你的系统环境生成正确的配置脚本。
4. 运行配置脚本来检查系统环境并生成 Makefile。
你可以运行以下命令：./configure.这将根据你的系统环境和配置选项生成 Makefile。
5. 运行 Make 命令来编译 Pacemaker。
你可以运行以下命令：make.这将根据 Makefile 中的规则编译源代码。
6. （可选）运行 Make 命令来进行测试。
你可以运行以下命令： make check.这将运行一系列测试用例来验证编译结果的正确性。
7. （可选）运行 Make 命令来安装 Pacemaker。
你可以运行以下命令：make install.这将把编译好的二进制文件和相关文件安装到系统中。
以上是编译 Pacemaker 的基本步骤。
需要注意的是，具体的编译过程可能会因系统环境和版本而有所差异，你可能需要根据实际情况进行调整。
CompactPCI+a+Specification标准
P r o p e r t y o f M o t o r o l a F orI nternalUseO nl y-Ext ernalD is tr ibutionPr ohibi te d PICMG 2.0 R3.0 CompactPCI® Specification October 1, 1999P r o p e r t y o f M o t o r o l aF o r I n t e r n a l U s e O n l y - E x t e r n a l D i s t r i b u t i o n P r o h i b i t e dP r o p e r t y o f M o t o r o l aF orI nternalUseO nl y-Ext ernalD is tr ibutionPr ohibi te dRelease Note for PICMG 2.0 Revision 3.0 CompactPCI ® Specification October 1, 1999P r o p e r t y o f M o t o r o l aF orI nternalUseO nl y-Ext ernalD is tr ibutionPr ohibi te d Purpose This Release Note records some issues raised in the course of developing and balloting PICMG 2.0 Revision 3.0, the CompactPCI core specification. 1. System Management Bus pin assignments . This specification reserves pins on J1/P1 of all slots and J2/P2 of the System Slot for definition as I 2C System Management Busses by PICMG 2.9, CompactPCI System Management Specification. These signals have been tentatively assigned by the PICMG 2.9 as indicated in Section 3.2.7.7 and in Tables 13 through 16 with their notes. The IPMB_SDA pin is an I2C data bus connecting all slots in a backplane. The IPMB_SCL pin is the clock associated with that data line, and the IPMB_PWR pin is a power pin for the IPMB node. The data and clock pins providing System Slot access to platform devices from J2/P2 were designated ICMB_SDA and ICMB_SCL in the draft specification reviewed and adopted by the Executive Membership on October 1, 1999. These signal names are misleading, implying the use of an RS-485 UART bus as specified in the Intel IPMI documents. These signals are designated SMB_SDA and SMB_SCL in the released document. A second System Management power pin, designated ICMB_PWR in the executive draft, was also reserved on J2/P2 of the System Slot. As of the approval of PICMG 2.0 Revision 3.0, the PICMG 2.9 subcommittee is in doubt as to whether this pin will actually be used for power, and is considering assigning a different function to this reserved pin. The released specification accord designates this pin as SMB_RSV. 2. System Slot Hot Swap Signals . This specification designates Pin J1/P1 D15 as a short BD_SEL# (Board Select) signal in agreement with PICMG 2.1, CompactPCI Hot Swap Specification, but only on peripheral slots. The pin is shown as a ground on System Slots. Implementers of CompactPCI boards and systems should anticipate that this signal may also be designated as BD_SEL# on System Slots in PICMG 2.13, CompactPCI Redundant System Slot Specification. J1/P1 Pin B4 is designated as the HEALTHY# signal on System and Peripheral Slots in this specification. ###P r o p e r t y o f M o t o r o l a F orI nternalUseO nl y-Ext ernalD is tr ibutionPr ohibi te d PICMG 2.0 R3.0CompactPCI® SpecificationOctober 1, 1999P r o p e r t y o f M o t o r o l aF orI nternalUseO nl y-Ext ernalD is tr ibutionPr ohibi te d PICMG 2.0 R3.0 10/1/99ii ©Copyright 1995, 1996, 1997, 1998, 1999 PCI Industrial Computers Manufacturers Group (PICMG).The attention of adopters is directed to the possibility that compliance with or adoption of PICMG ® specifications may require use of an invention covered by patent rights.PICMG ® shall not be responsible for identifying patents for which a license may be required by any PICMG ® specification, or for conducting legal inquiries into the legal validity or scope of those patents that are brought to its attention. PICMG ® specifications are prospective and advisory only. Prospective users are responsible for protecting themselves against liability for infringement of patents.NOTICE:The information contained in this document is subject to change without notice. The material in this document details a PICMG ® specification in accordance with the license and notices set forth on this page. This document does not represent a commitment to implement any portion of this specification in any company's products.WHILE THE INFORMATION IN THIS PUBLICATION IS BELIEVED TO BE ACCURATE, PICMG ® MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO ANY WARRANTY OF TITLE OR OWNERSHIP, IMPLIED WARRANTY OF MERCHANTABILITY OR WARRANTY OF FITNESS FOR PARTICULAR PURPOSE OR USE.In no event shall PICMG ® be liable for errors contained herein or for indirect, incidental,special, consequential, reliance or cover damages, including loss of profits, revenue, data or use, incurred by any user or any third pliance with this specification does not absolve manufacturers of CompactPCI equipment, from the requirements of safety and regulatory agencies (UL, CSA, FCC,IEC, etc.).PICMG ®, CompactPCI ®, and the PICMG ® and CompactPCI ® logos are registered trademarks of the PCI Industrial Computers Manufacturers Group.All other brand or product names may be trademarks or registered trademarks of their respective holders.P r o p e r t y o f M o t o r o l aF orI nternalUseO nl y-Ext ernalD is tr ibutionPr ohibi te d CompactPCI ® Core Specification PICMG 2.0 R3.0 10/1/99iii Contents1OVERVIEW.........................................................................................................................................91.1C OMPACT PCI O BJECTIVES ................................................................................................................91.2B ACKGROUND AND T ERMINOLOGY ....................................................................................................91.3D ESIRED A UDIENCE ...........................................................................................................................91.4C OMPACT PCI F EATURES .................................................................................................................101.5A PPLICABLE D OCUMENTS ................................................................................................................101.6A DMINISTRATION .............................................................................................................................111.7N AME A ND L OGO U SAGE .................................................................................................................112FEATURE SET..................................................................................................................................132.1F ORM F ACTOR .................................................................................................................................132.2C ONNECTOR .....................................................................................................................................152.3M ODULARITY ...................................................................................................................................162.4H OT S WAP C APABILITY ....................................................................................................................163ELECTRICAL REQUIREMENTS..................................................................................................173.1B OARD D ESIGN R ULES .....................................................................................................................173.1.1Decoupling Requirements......................................................................................................173.1.2CompactPCI Signal Additions...............................................................................................183.1.3CompactPCI Stub Termination..............................................................................................183.1.4Peripheral Board Signal Stub Length ...................................................................................183.1.5Characteristic Impedance......................................................................................................193.1.6System Slot Board Signal Stub Length ..................................................................................193.1.7Peripheral Board PCI Clock Signal Length..........................................................................193.1.8Pull-Up Location...................................................................................................................193.1.9Board Connector Shield Requirements.................................................................................203.2B ACKPLANE D ESIGN R ULES .............................................................................................................213.2.1Characteristic Impedance......................................................................................................213.2.2Eight-Slot Backplane Termination........................................................................................213.2.3Signaling Environment..........................................................................................................223.2.4IDSEL Assignment.................................................................................................................223.2.5REQ#/GNT# Assignment.......................................................................................................233.2.6PCI Interrupt Binding............................................................................................................243.2.7CompactPCI Signal Additions...............................................................................................253.2.8Power Distribution................................................................................................................283.2.9Power Decoupling.................................................................................................................293.2.10Healthy (Healthy#)................................................................................................................303.333 MH Z PCI C LOCK D ISTRIBUTION .................................................................................................303.3.1Backplane Clock Routing Design Rules................................................................................313.3.2System Slot Board Clock Routing Design Rules....................................................................313.464-B IT D ESIGN R ULES ......................................................................................................................313.566 MH Z E LECTRICAL R EQUIREMENTS .............................................................................................333.5.166 MHz Board Design Rules.................................................................................................333.5.266 MHz System Board Design Rules.....................................................................................343.5.366MHz Backplane Design Rules...........................................................................................343.5.466MHz PCI Clock Distribution.............................................................................................343.5.566 MHz System Slot Board Clock Routing Design Rules (35)3.5.666 MHz Hot Swap (35)3.6S YSTEM AND B OARD G ROUNDING (36)3.6.1Board Front Panel Grounding Requirements (36)3.6.2Backplane Grounding Requirements (36)3.7C OMPACT PCI B UFFER M ODELS (36)P r o p e r t y o f M o t o r o l aF orI nternalUseO nl y-Ext ernalD is tr ibutionPr ohibi te d PICMG 2.0 R3.0 10/1/99iv 4MECHANICAL REQUIREMENTS................................................................................................374.1B OARD R EQUIREMENTS ...................................................................................................................374.1.13U Boards..............................................................................................................................374.1.26U Boards..............................................................................................................................374.1.3Rear-panel I/O Boards..........................................................................................................374.1.4ESD Discharge Strip.............................................................................................................384.1.5ESD Clip................................................................................................................................384.1.6Cross Sectional View.............................................................................................................394.1.7Component Outline and Warpage.........................................................................................394.1.8Solder Side Cover..................................................................................................................394.1.9Front Panels..........................................................................................................................484.1.10System Slot Identification......................................................................................................494.2R EAR -P ANEL I/O B OARD R EQUIREMENTS .......................................................................................524.2.1Mechanicals...........................................................................................................................524.2.2Power.....................................................................................................................................524.2.3Rear Panel Keying.................................................................................................................534.3B ACKPLANE R EQUIREMENTS ...........................................................................................................534.3.1Connector Orientation...........................................................................................................534.3.2Slot Spacing...........................................................................................................................534.3.3Slot Designation....................................................................................................................544.3.4Bus Segments.........................................................................................................................544.3.5Backplane Dimensions..........................................................................................................545CONNECTOR IMPLEMENTATION.............................................................................................585.1O VERVIEW .......................................................................................................................................585.1.1Location.................................................................................................................................585.1.2Housing Types.......................................................................................................................595.1.3Connector Tail Lengths.........................................................................................................595.1.4Backplane / Board Population Options.................................................................................595.2J1 (32-B IT PCI S IGNALS ).................................................................................................................595.3J2 C ONNECTOR ................................................................................................................................605.3.1Peripheral Slot 64-Bit PCI....................................................................................................605.3.2Peripheral Slot Rear-Panel I/O.............................................................................................605.3.3System Slot 64-bit PCI...........................................................................................................605.3.4System Slot Rear-Panel I/O...................................................................................................605.4B USSED R ESERVED P INS ..................................................................................................................605.5N ON -B USSED R ESERVED P INS .........................................................................................................605.6P OWER P INS .....................................................................................................................................605.75V/3.3V PCI K EYING ......................................................................................................................615.8P IN A SSIGNMENTS PACTPCI BUFFER MODELS...............................................................................................69B.CONNECTOR IMPLEMENTATION.............................................................................................73B.1G ENERAL .........................................................................................................................................73B.2C ONNECTORS ...................................................................................................................................73B.3A LIGNMENT .....................................................................................................................................73B.3.1Front Plug-In Board Alignment............................................................................................73B.3.2Rear Panel I/O Board Alignment..........................................................................................74B.3.3Backward Compatibility for Rear Panel I/O Boards. (74)P r o p e r t y o f M o t o r o l aF orI nternalUseO nl y-Ext ernalD is tr ibutionPr ohibi te d CompactPCI ® Core Specification PICMG 2.0 R3.0 10/1/99v TablesT ABLE 1. C ODING K EY C OLOR A SSIGNMENTS ..............................................................................................15T ABLE 2. B OARD D ECOUPLING R EQUIREMENTS ...........................................................................................17T ABLE 3. S TUB T ERMINATION R ESISTOR ......................................................................................................18T ABLE 4. B OARD C HARACTERISTICS .............................................................................................................19T ABLE 5. P ULL -UP R ESISTOR V ALUES ...........................................................................................................20T ABLE 6. B ACKPLANE C HARACTERISTICS .....................................................................................................21T ABLE 7. S YSTEM TO L OGICAL S LOT S IGNAL A SSIGNMENTS ........................................................................23T ABLE 8. S YSTEM TO L OGICAL S LOT I NTERRUPT A SSIGNMENTS ..................................................................24T ABLE 9. P HYSICAL S LOT A DDRESSES ..........................................................................................................27T ABLE 10. P OWER S PECIFICATIONS ...............................................................................................................28T ABLE 11. B ACKPLANE D ECOUPLING R ECOMMENDATIONS ..........................................................................30T ABLE 12. C ODING K EY C OLOR A SSIGNMENTS AND P ART N UMBERS ...........................................................61T ABLE 13. C OMPACT PCI P ERIPHERAL S LOT 64-B IT C ONNECTOR P IN A SSIGNMENTS ...................................62T ABLE 14 C OMPACT PCI P ERIPHERAL S LOT R EAR -P ANEL I/O C ONNECTOR P IN A SSIGNMENTS ....................63T ABLE 15. C OMPACT PCI S YSTEM S LOT 64-BIT C ONNECTOR P IN A SSIGNMENT .............................................64T ABLE 16. C OMPACT PCI S YSTEM S LOT R EAR -P ANEL I/O C ONNECTOR P IN A SSIGNMENTS ..........................65T ABLE 17. R EVISION H ISTORY . (67)P r o p e r t y o f M o t o r o l a F o r I n t e r n a l U s e O n l y - E x t e r n a l D i s t r i b u t i o n P r o h i b i t e d PICMG 2.0 R3.0 10/1/99vi This page is left intentionally blank.P r o p e r t y o f M o t o r o l aF orI nternalUseO nl y-Ext ernalD is tr ibutionPr ohibi te d CompactPCI ® Core Specification PICMG 2.0 R3.0 10/1/99vii IllustrationsF IGURE 1. 3U 64-B IT C OMPACT PCI F ORM F ACTOR ......................................................................................13F IGURE 2. 3U C OMPACT PCI B ACKPLANE E XAMPLE .....................................................................................14F IGURE 3. PCI S IGNAL T ERMINATION ...........................................................................................................22F IGURE 4. L OCAL 64 B IT I NITIALIZATION ......................................................................................................33F IGURE 5. ESD C LIP L OCATION ....................................................................................................................39F IGURE 6. 3U B OARD ....................................................................................................................................40F IGURE 7. 6U B OARD ....................................................................................................................................41F IGURE 8. F RONT S IDE B OARD ESD D IMENSIONS .........................................................................................42F IGURE 9. 3U R EAR -P ANEL I/O B OARD D IMENSIONS ...................................................................................43F IGURE 10. 6U R EAR P ANEL I/O B OARD D IMENSIONS ..................................................................................44F IGURE 11. R EAR P ANEL I/O ESD D IMENSIONS ...........................................................................................45F IGURE 12. C ROSS S ECTIONAL B OARD , C ONNECTOR , B ACKPLANE AND F RONT P ANEL V IEW ......................46F IGURE 13. C OMPONENT O UTLINE ................................................................................................................47F IGURE 15. C OMPACT PCI C OMPATIBILITY G LYPHS ......................................................................................48F IGURE 16. C OMPACT PCI L OGO ...................................................................................................................48F IGURE 17. 3U EMC F RONT P ANEL ..............................................................................................................50F IGURE 18. 6U EMC F RONT P ANEL ..............................................................................................................51F IGURE 19. 3U B ACKPLANE E XAMPLE - F RONT V IEW ..................................................................................53F IGURE 20. 3U B ACKPLANE D IMENSIONS .....................................................................................................56F IGURE 21. 6U B ACKPLANE D IMENSIONS .....................................................................................................57F IGURE 22. 3U C ONNECTOR I MPLEMENTATION ............................................................................................58F IGURE 23. 6U C ONNECTOR I MPLEMENTATION ............................................................................................58F IGURE 24. 5V S TRONG PCI M ODEL ............................................................................................................69F IGURE 25. 5V W EAK PCI M ODEL ...............................................................................................................70F IGURE 26. 3.3V S TRONG PCI M ODEL .........................................................................................................70F IGURE 27. 3.3V W EAK PCI M ODEL (71)P r o p e r t y o f M o t o r o l aF orI nternalUseO nl y-Ext ernalD is tr ibutionPr ohibi te d PICMG 2.0 R3.0 10/1/99viii This page is left intentionally blank.P r o p e r t y o f M o t o r o l aF orI nternalUseO nl y-Ext ernalD is tr ibutionPr ohibi te d 1. Overview CompactPCI ® Core Specification PICMG 2.0 R3.0 10/1/99Page 9 of 741 Overview 1.1 CompactPCI Objectives CompactPCI is an adaptation of the Peripheral Component Interconnect (PCI)Specification 2.1 or later for industrial and/or embedded applications requiring a more robust mechanical form factor than desktop PCI. CompactPCI uses industry standard mechanical components and high performance connector technologies to provide an optimized system intended for rugged applications. CompactPCI provides a system that is electrically compatible with the PCI Specification, allowing low cost PCI components to be utilized in a mechanical form factor suited for rugged pactPCI is an open specification supported by the PICMG (PCI Industrial Co m-puter Manufacturers Group), which is a consortium of companies involved in utiliz-ing PCI for embedded applications. PICMG controls this specification.1.2 Background and Terminology Eurocard - A series of mechanical board form factor sizes for rack-based systems as used in VME, Multibus II, and other applications defined by the Institute of Electri-cal and Electronics Engineers (IEEE) and International Electrotechnical Committee (IEC).ISA - Industry Standard Architecture. A specification by which Personal Com puters (PCs) add boards.PCI - Peripheral Component Interconnect. A specification for defining a common in-terconnect between logic components. Typically used for interconnecting high-speed,PC-compatible chipset components. The PCI specification is issued through the PCI Special Interest Group (PCI SIG).This specification utilizes several key words, which are defined below:may : A key word indicating flexibility of choice with no implied preference.shall : A key word indicating a mandatory requirement. Designers shall im-plement such mandatory requirements to ensure interchangeability and to claim conformance with the specification.should: A key word indicating flexibility of choice with a strongly preferred implementation.1.3 Desired AudienceCompactPCI exists to provide a standard form factor for those applications requiring the high performance of PCI as well as the small size and ruggedness of a rack mount system. CompactPCI provides a mechanism for OEM and end users to di-rectly apply PCI components and technology to a new mechanical form factor while。
Pacemaker
PacemakerA pacemaker is a small device that helps control your heart rate by:• Speeding up the heart rate when it is too slow• Slowing down the heart rate when it is too fast• Helping the heart beat regular if it is irregularA pacemaker isplaced in the chestduring surgery. Wirescalled leads are putinto the heart muscle.The device with thebattery is placedunder your skin,below your shoulder.An adult familymember or friendneeds to come withyou to take you homeafter your surgery. Itis not safe for you todrive or leave alone.Have an adult staywith you at home forthe first day after yoursurgery.Arrive on time for your appointment. The surgery will take 1-2 hours. To Prepare• Talk to your doctor if you take blood thinners or have diabetes.• Do not eat or drink anything, including water, after midnight before your surgery.• Ask your doctor if you should take your medicines the morning of your surgery. If so, take with sips of water only.心臟起搏器心臟起搏器是幫助您控制心率的一個小裝置﹕• 心率太慢時，它加快心率 • 心率太快時，它使之慢下來 • 如果心率不齊，它則有助於心率規則心臟起搏器是 由手術置入胸部的。
斑马技术公司DS8108数字扫描仪产品参考指南说明书
OpenStack专业术语和用途说明大全
OpenStack专业术语和用途说明大全∙AMQP- 全称Advanced Message Queuing Protocol，是一个国际标准的消息中间件，是一个wire-level protocol。
Mirantis OpenStack和Fuel都是用RabbitMQ作为AMQP兼容的消息接口；∙Astute - Fuel使用它来部署OpenStack环境。
Nailgun服务创建一个JSON文件，里面包含了节点和对应的角色讯息，然后将这个文件啊烦恼公道RabbitMQ队列。
Astue工作进程收到讯息后在Cobbler里部署到每个节点；∙Availability Zone - Availability Zone是一种Host Aggregate的名字；∙Bonding - NIC Bonding也叫NIC Aggregation，将多个物理网路连接组合在一起，既可以提供容错也可以增加速率。
Mirantis OpenStack通过OVS来实现NIC Bonding；∙Ceilometer - Ceilometer会聚合部署在OpenStack环境里所有服务的使用情况和性能数据。
相关数据收集起来之后可以用作很多参考用途。
Fuel可以在CentOS或Ubuntu安装Ceilometer。
注意，Ceilometer会收集大量的数据，所以，会产生对Database的大量写入。
缺省情况下收集100个Resource大概每小时会有16K的数据量。
使用它需要MongoDB；∙Ceph - 这是Open Source的存储平台，提供统一Object、Block和File Storage；∙Cinder - 它是OpenStack的Block Storage项目的代号。
它是Nova项目的初始构成部分，不过现在已经独立出来了。
Cinder可以部署到OpenStack Storage Node（通常叫做Cinder Node）或者也可以与Controller Node共享。
Pacemaker入门手册_Clusters_from_Scratch
用来突出系统输入，其中包括 shell 命令、文件名以及路径。
还可用来突出按键以及组合键。
例如：要看到文件您当前工作目录中文件my_next_bestselling_novel的内容，请在 shell 提示符后输入cat my_next_bestselling_novel命令并按Enter键执行该命令。
以上内容包括一个文件名，一个 shell 命令以及一个按键，它们都以固定粗体形式出现，且全部与上下文有所区别。
组合键可通过使用连字符连接组合键的每个部分来与按键区别。
例如：按Enter执行该命令。
按Ctrl+Alt+F2切换到第一个虚拟终端。
Ctrl+Alt+F1返回您的 X-Windows 会话。
第一段突出的是要按的特定按键。
第二段突出了两个按键组合（每个组合都要同时按）。
下。
如果讨论的是源码、等级名称、方法、功能、变量名称以及在段落中提到的返回的数值，那么都会以上述形式固定粗体。
例如：出现，即固定粗体与文件相关的等级包括用于文件系统的filesystem、用于文件的file以及用于目录的dir。
每个等级都有其自身相关的权限。
比例粗体这是指在系统中遇到的文字或者短语，其中包括应用程序名称、对话框文本、标记的按钮、复选框以及单选按钮标签、菜单标题以及子菜单标题。
例如：「按钮」标签中点击鼠标首选项。
在「按钮」在主菜单条中选择「系统」「鼠标」启动鼠标首选项「系统」→「首选项」→「鼠标」关闭切换到主鼠标按钮从左向右（让鼠标适合左手使用）。
「惯用左手鼠标」复选框并点击关闭「应用程序」→「附件」→「字符映要在gedit文件中插入一个特殊字符，请在主菜单中选择「应用程序」「查找」，在「搜索」「搜索」→「查找」「搜索」字段输入字符名称射表」射表」。
下一步在字符映射表字符映射表菜单条中选择「搜索」「字符表」中突出出来。
双击这个突出的字符将其放入并点击下一个按钮。
您输入的字符会在「字符表」「编「要复制的文本」字段，然后点击复制按钮。
Pacemaker 集群管理解决方案
基于Pacemaker的开发
高可用集群管理页面
高可用集群架构设计
Pacemaker快速部署
准备阶段(所有节点)
• 设置主机名，hosts文件或DNS • ssh key互信 • 时间同步 • 防火墙和SELinux • 共享存储(NFS/Ceph/DRBD)及目录
软件安装 # yum install -y pacemaker corosync pcs psmisc policycoreutils-python fence-agents-all
配置节点的pcs守护程序 # systemctl start pcsd # systemctl enable pcsd
Pacemaker快速部署(续)
集群用户设置及授权 # echo password | passwd --stdin hacluster # pcs cluster auth node1 node2 -u hacluster -p password
• 负载均衡集群
Load balance cluster， LBC 功能：利用一个集群中的多台单机完成许多并行的工作 场景：互联网、电子商务
• 高性能集群
High performance cluster，HPC 功能：利用集群中的多台机器共同完成同一任务弥补单机 性能的不足 场景：天气预报、环境监控等数据量大，计算复杂的环境
• STONITHd：集群 Fencing进程,隔离用途
主要支持模式
Active/Active模式
这种模式下集群中的节点通常部署了相同的软件并具有相同的 参数配置，同时各服务在这些节点上并行运行 故障节点上的访问请求或自动转到另外一个正常运行节点上， 或通过负载均衡器在剩余的正常运行的节点上进行负载均衡。
postgresql9.1.4+pacemker实现Master-Slave
基于Pacemaker实现postgreSQL9.1.4的主从备份本文主要介绍使用Pacemaker、heartbeat实现postgresql9.1.4的基于Streaming Replication的hot standby。
其中postgresql9.1的resource agent (RA)的下载地址为：https:///t-matsuo/resource-agents/blob/pgsql-rep-master/heartbeat/pgsql。
本文的pacemaker配置都是基于该RA的。
场景：两台机器ip分别为192.168.4.105和192.168.4.104，主机名分别为：h105和h104，其中h105为master主机。
1 P ostgreSQL的主机配置和从机配置1)在两台机器上安装postgresql9.1.4,pacemaker,heartbeat，其中pacemaker的安装方法参考文档《pacemaker的安装步骤.doc》；master主机：2)初始化数据库，本文假设数据目录在～/data，postgresql安装目录为～/pginstall;3)修改配置文件postgresql.conf,添加如下内容：listen_addresses='*'wal_level=hot_standbymax_wal_senders=2wal_keep_segments=32archive_mode=onarchive_command='cp %p ~/data/archive/%f'hot_standby=on4)修改配置文件pg_hba.conf,添加如下内容：host replication repl 192.168.4.104/32 trusthost all all 192.168.4.104/32 trust5)在data目录下创建archive目录：mkdir ~/data/archive；6)手动启动postgresql：~/pginstall/bin/pg_ctl start -D ~/data -l ~/data/postgresql.log7)登录postgres数据库，创建repl超级用户，该用户用来进行流复制；～/pginstall/bin/psql postgres postgres -p 5432 -c “create user repl superuser password 'repl';”8)对数据库做一次基础备份：～/pginstall/bin/psql postgres postgres -p 5432 -c “select pg_start_backup('base');”9)打包当前数据目录，然后复制到h104机器上：tar -xvf ~/data.tar ~/datascp ~/data.tar 192.168.4.104:~/10)结束当前的基础备份，并关闭当前的postgresql：～/pginstall/bin/psql postgres postgres -p 5432 -c “select pg_stop_backup();”~/pginstall/bin/pg_ctl stop -D ~/data -l ~/data/postgresql.log注意：对当前数据库做基础备份这几步是必须要做的。
Pacemaker的安装步骤
Pacemaker的安装【注】1.操作系统版本：Asianux Server 3 (Quartet SP2) （64位）2.内核版本：2.6.18-128.7AXS31.下载pacemaker从/pacemaker/stable-1.0/archive/tip.tar.bz2上下载pacemaker的文档版本。
2.解压下载后的文档，tar -xvf Pacemaker-1-0-9af47ddebcad.tar.bz2进入Pacemaker-1-0-9af47ddebcad文件夹 cd Pacemaker-1-0-9af47ddebcad3.执行 ./ConfigureMe configure，出现如下错误：checking hb_config.h usability... nochecking hb_config.h presence... nochecking for hb_config.h... nochecking glue_config.h usability... nochecking glue_config.h presence... nochecking for glue_config.h... nochecking agent_config.h usability... nochecking agent_config.h presence... nochecking for agent_config.h... noconfigure: error: Core development headers were not found该错误产生的原因是没有安装resource-agent。
1）下载resource-agent，地址为：https:///ClusterLabs/resource-agents/tarball/v3.9.2tar -xvf ClusterLabs-resource-agents-v3.9.2-0-ge261943.tar.gzcd ClusterLabs-resource-agents-b735277执行./autogen.sh，报告如下错误：configure.ac:9: error: Autoconfversion 2.63 or higher is required该问题是autoconf本版太低。
pacemaker 标签 2
pacemaker 标签一、DRBD概述DRBD(DistributedReplicatedBlockDevice)是Linux平台上的分散式储存系统。
由内核模组、用户空间工具组成，通常用于高可用性（highavailability,HA）集群。
其实现方式是通过网络在服务器之间的对块设备（硬盘，分区，逻辑卷等）进行镜像。
你可以把它看作是一种网络RAID..[原创] DRDB实现mariadb高可用HA DRBD corosync pacemaker | 博主：jinlinger------本文大纲简介DRBD资源属性原理安装DRDBDRDB实现高可用============一、简介DRBD是一种块设备，可以被用于高可用(HA)之中。
它类似于一个网络RAID-1功能。
当你将数据写入本地文件系统时，数据还将会被发送到网络中另一台主机上。
以相同的形式记录在一个文件系统中。
本地(主节?..[原创] CentOS 6.5 Corosync+Pacemaker crm实现DRBD高可用过程及DRBD详解crm HA DRBD Corosync pacemaker pssh | 博主：wei0164DRBD(DistributedReplicatedBlockDevice)分布式复制块设备，它是Linux平台上的分散式储存系统，通常用于高可用性（highavailability,HA）集群中。
DRBD类似磁盘阵列的RAID1（镜像），只不过RAID1是在同一台电脑内，而DRBD是透过网络。
DRBDResource：DRBD所具有的几种属性：resource..说明：这是1个小项目就两台DELL的服务器，和一台IPSAN存储（DELLMD3200i）。
原来是4台小服务器，而且服务器台湾高山茶 太老了，经常有问题，这回相当于一次ftp 的迁移，以前用的是proftp，这次换成了vsftp。
数据量有2.5T。
拓扑很简单：系统：CENTOS6.4（64bit）高可用软件：corosync+pacemaker..[原创] 基于corosync+pacemaker 实现web的高可用web corosync pacemaker crmsh | 博主：jinlinger温馨提示：前一篇博文己经介绍过了corosync+pacemaker基本用法，这篇将重点介绍基于corosync+pacemaker的web高可用---本文大纲资源分配及拓扑图实现过程测试==================一、水草玛瑙 资源分配及拓扑图1、资源分配系统主机名角色ip地址关系Centos6.5x86_数据库+NF..一、Corosync简介和pacemaker简介1、CorosyncCorosync是OpenAIS发展到Wilson版本后衍生出来的开放性集群引擎工程。
pacemaker编译
pacemaker编译1. 什么是PacemakerPacemaker是一个开源的高可用性集群资源管理软件，它可以用于管理集群中的各种资源，如虚拟IP地址、文件系统、数据库等。
Pacemaker可以自动检测和处理节点故障，保证集群中的资源始终可用。
Pacemaker采用了分布式架构，每个节点都运行一个Pacemaker的实例，通过互相通信来协调资源的管理。
它提供了一套灵活的规则和策略，可以根据集群的需求来配置资源的启动、停止、迁移等操作。
2. Pacemaker的编译过程Pacemaker的编译过程相对复杂，需要一些准备工作和依赖项。
下面是一个基本的编译过程的步骤：2.1 准备工作在编译Pacemaker之前，我们需要确保系统已经安装了一些必要的软件和依赖项。
这些软件和依赖项包括：•开发工具链，如gcc、make等•自动构建工具，如autotools、autoconf等•必要的库文件，如GLib、DBus等我们可以使用系统自带的包管理工具来安装这些软件和依赖项。
以Ubuntu为例，可以使用以下命令来安装：sudo apt-get install build-essential autoconf automake libtool libglib2.0-dev libdbus-1-dev2.2 下载源代码Pacemaker的源代码可以从官方的Git仓库中获取。
我们可以使用以下命令来克隆官方仓库：git clone2.3 配置和编译在克隆完源代码之后，我们需要进行一些配置和编译的准备工作。
首先，我们需要进入源代码目录：cd pacemaker然后，我们可以使用以下命令来生成配置脚本：autoreconf -i接下来，我们可以使用以下命令来配置编译选项：./configure --prefix=/usr/local/pacemaker这里我们将Pacemaker安装到/usr/local/pacemaker目录下，你也可以根据需要更改安装路径。
corosync+pacemaker安装配置实验
Corosync安装测试一、实验要求1、corosync + pacemaker集群安装测试二、架构拓扑网络要求：所有服务器位于同一VLan机器无特殊要求。
三、系统环境1、操作系统：CentOS 6.62、相关软件：corosync、pacemaker、pcs3、网络要求：/etc/hosts文件添加双方主机名列表。
四、地址规划名称角色IP地址虚拟IP地址CentOS-66A 主服务器192.168.10.11 192.168.10.15 CentOS-66B 从服务器192.168.10.12 192.168.10.15五、安装软件1、安装支持软件#在编译安装之前，必须安装内核开发包，以及支持库[shell]# yum -y install gcc gcc-c++ kernel-devel openssl openssl-devel[shell]# yum -y install automake autoconf pkgconfig nss nss-devel[shell]# yum -y install libqb libqb-devel libtool libtool-ltdl-devel[shell]# yum -y install glib2 glib2-devel libuuid libuuid-devel[shell]# yum -y install libxml2 libxml2-devel libxslt libxslt-devel[shell]# yum -y install bzip2 bzip2-devel dbus dbus-devel[shell]# yum -y install pam pam-devel libesmtp libesmtp-devel[shell]# yum -y install fence-agents resource-agents docbook-style-xsl[shell]# yum -y install cluster-glue cluster-glue-libs cluster-glue-libs-devel [shell]# yum -y install gnutls gnutls-devel python python-devel python-lxml2.1、创建所需的用户和组#在编译安装之前，创建软件所需的用户(hacluster)和组(haclient)[shell]# groupadd -g 201 haclient[shell]# useradd -g haclient -u 201 -s /sbin/nologin -M hacluster[shell]# passwd hacluster ## 设置群集管理用户的密码2.2、编译安装corosync、pacemaker、pcs软件，使用默认路径安装。
pacemaker配置一个三节点主备集群并配置vip资源
pacemaker配置一个三节点主备集群并配置vip资源展开全文接着上一章来讲，/minxihou/article/details/72862715 本章中会讲述一些集群简单配置命令，法定人数概念，配置一个VIP服务并且如何防止资源在节点恢复后移动。
接着搭建继续来写在搭建完pacemaker之后如果不在里面配置任何服务其实这个东西是完全没有什么用的。
那么我们从最简单的一个配置来说起，那就是配置VIP。
我们通过配置一个VIP，下连三台服务器来对这个IP提供服务，这个在网站的基础架构中是非常重要的。
在网站中为了解决单点故障一般在一个公网ip中下连至少有两台http服务器来防止单点故障。
这样做的好处显而易见就是为了保障服务的可用性。
那么设置VIP就是其中要做的第一步。
架构图如下：这里依旧沿用了我们上篇文章中搭建好的pacemaker服务集群。
这里我打算将这三个节点都启用，两个节点作为standby一个节点作为active，当active节点发生单点故障时，剩下两个节点则会接管该服务保证服务不受中断。
Part1.浏览现有集群配置当pacemaker启动的时候，他会自动记录节点的数量和详细信息，以及基层软件和Pacemaker的版本。
最初始配置文件的模样：[root@node-1 ~]# crmcrm(live)# configurecrm(live)configure# shownode 1: node-1node 2: node-2node 3: node-3property cib-bootstrap-options: have-watchdog=false dc-version=1.1.15-11.el7_3.4-e174ec8 cluster-infrastructure=c orosync cluster-name=my_cluste如果想看xml格式，可以添加xml选项来看到原始的配置文件。
基于Pacemaker和Corosync搭建HA集群
基于Pacemaker和Corosync搭建HA集群2010-07-17 01:04:21标签：heartbeat3corosync休闲pacemaker职场原创作品，允许转载，转载时请务必以超链接形式标明文章原始出处、作者信息和本声明。
否则将追究法律责任。
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asram首先鄙视一下/wiki/Main_Page网站，我从上面下载：∙Heartbeat 3.0.3: Heartbeat-3-0-STABLE-3.0.3.tar.bz2∙Cluster Glue 1.0.5: glue-1.0.5.tar.bz2∙Resource Agents 1.0.3: agents-1.0.3.tar.bz2就从来没成功过。
环境：2台服务器：主机名系统IPwww RHEL 5.1 192.168.1.13web CentOS5.5 192.168.1.1 4一、安装HA集群软件先安装EPELRHEL/CentOS 5.3 for i386:#su -c 'rpm -Uvh /pub/epel/5/i386/epel-release-5-3.noarch.rpm' 安装Cluster Labs repository :#wget -O /etc/yum.repos.d/pacemaker.repo /rpm/epel-5/clusterlabs.repo查看包含的软件仓库：#yum repolist查看pacemaker软件信息：#yum info pacemaker安装corosync、pacemaker和heartbeat#yum install -y corosync pacemaker heartbeatRedHat请修改yum的配置文件二、准备工作配置主机名:#uname -n#dnsdomainname#vi /etc/sysconfig/network NETWORKING=yesHOSTNAME=test1GATEWAY=192.168.1.2应用主机名：#source /etc/sysconfig/network#hostname $HOSTNAME配置主机信任关系:#ssh-keygen -t dsa -f ~/.ssh/id_dsa -N “”#cp .ssh/id_dsa.pub .ssh/authorized_keys#scp -r .ssh test2:三、配置Corosync#vi /etc/corosync/corosync.confinterface {ringnumber: 0# The following values need to be set based on your environment bindnetaddr: 192.168.1.0 #内部网段mcastaddr: 226.94.1.1 #组播地址mcastport: 4000 #组播端口}#vi /etc/corosync/server.d/pcmkservice {# Load the Pacemaker Cluster Resource Managerver: 0name: pacemaker}将配置同步到另外一台服务器# for i in /etc/corosync/corosync.conf /etc/corosync/service.d/pcmk;do scp $i www:$i ; done启动Corosync:#/etc/init.d/corosync start检查日志判断Corosync启动和初始化成员节点# grep -e "corosync.*network interface" -e "Successfully read main configurationfile" /var/log/messages#grep TOTEM /var/log/messages检查是否有错误：# grep ERROR: /var/log/messages | grep -v unpack_resources 检查pacemaker启动情况：grep pcmk_startup /var/log/messages启动另外一节点Corosync：#ssh test2 -- /etc/init.d/corosync start通过crm查询2个节点状态：crm status四、修改crm配置和添加资源#crm_verify –L由于stonith未配置造成的错误日志我们先进制该功能#crm configure property stonith-enabled=false查询目前cib状态#crm configure show为集群添加资源：软件自带的脚本在/usr/lib/ocf/resource.d/下[root@www ~]# ls /usr/lib/ocf/resource.d/ heartbeat pacemaker也可以通过命令来查看除此之外还有基于LSB的脚本和/etc/init.d/下的脚本一致添加虚拟IP#crmcrm(live)# configurecrm(live)configure# primitive ClusterIP ocf:heartbeat:IPaddr2 \ params ip=192.168.1.20 cidr_netmask=32 op monitor interval=10s crm(live)configure#verifycrm(live)configure#commitcrm(live)configure#show在另外一个节点www上查看状态：将apache添加到资源里，这里我们分别使用基于LSB格式的脚本和OCF格式LSB：[root@www ~]# crmccrm(live)# configurecrm(live)configure# primitive website lsb:httpd op monitor interval=20s crm(live)configure#commit服务已经起来了OCF：由于默认apache脚本是基于apache2的，所以有可能需要修改一下，删除线表示修改过的#: ${OCF_FUNCTIONS_DIR=${OCF_ROOT}/resource.d/heartbeat}. ${OCF_FUNCTIONS_DIR}/usr/lib/ocf/resource.d/heartbeat/.ocf-shellfuncsHA_VARRUNDIR=${HA_VARRUN}############################################################# ############ Configuration options - usually you don't need to change these############################################################## ###########IBMHTTPD=/opt/IBMHTTPServer/bin/httpdHTTPDLIST="/sbin/httpd /usr/sbin/httpd /usr/sbin/apache /sbin/httpd /usr/sbin/httpd /usr/sbin/apache $IBMHTTPD"MPM=/usr/share/apache/find_mpmif[ -x $MPM ]thenHTTPDLIST="$HTTPDLIST `$MPM 2>/dev/null`"fi# default options for http clients# NB: We _always_ test a local resource, so it should be# safe to connect from the local interface.WGETOPTS="-O- -q -L --no-proxy --bind-address=127.0.0.1" CURLOPTS="-o - -Ss -L --interface lo"LOCALHOST="http://localhost"HTTPDOPTS="-DSTATUS"DEFAULT_IBMCONFIG=/opt/IBMHTTPServer/conf/httpd.conf DEFAULT_NORMCONFIG="/etc/httpd/conf/httpd.conf"服务已经起来了。
Pacemaker详解
Pacemaker详解⼀、前⾔ 云计算与集群系统密不可分，作为分布式计算和集群计算的集⼤成者，云计算的基础设施必须通过集群进⾏管理控制，⽽作为拥有⼤量资源与节点的集群，必须具备⼀个强⼤的集群资源管理器（Cluster system Manager, CSM)来调度和管理集群资源。
对于任何集群⽽⾔，集群资源管理器是整个集群能够正常运转的⼤脑和灵魂，任何集群资源管理器的缺失和故障都会导致集群陷⼈瘫痪混乱的状态。
Openstack的众多组件服务既可以集成到单个节点上运⾏，也可以在集群中分布式运⾏。
但是，要实现承载业务系统的⾼可⽤集群， Openstack服务必须部署到⾼可⽤集群上，并在实现 Openstack服务⽆单点故障的同时，实现故障的⾃动转移和⾃我愈合，⽽这些功能是 Openstack的多数服务本⾝所不具备的。
因此，在⽣产环境中部署 OpenStack⾼可⽤集群时，必须引⼈第三⽅集群资源管理软件，专门负责 Openstack集群资源的⾼可⽤监控调度与管理。
集群资源管理软件种类众多，并有商业软件与开源软件之分。
在传统业务系统的⾼可⽤架构中，商业集群管理软件的使⽤⾮常普遍，如 IBM的集群系统管理器、 PowerHA SystemMirror（也称为 HACMP)以及针对 DB2的 purescale数据库集群软件；再如orcale的 Solaris Cluster系列集群管理软件，以及 oracle数据库的 ASM和 RAC集群管理软件等商业⾼可⽤集群软件都在市场上占有很⼤的⽐例。
此外，随着开源社区的发展和开源⽣态系统的扩⼤，很多商业集群软件也正在朝着开源的⽅向发展，如 IBM开源的 xCAT集软件⽽在 Linux 开源领域， Pacemaker/Corosync、 HAproxy/Keepalived等组合集群资泖管理软件也有着极为⼴泛的应⽤。
⼆、 Pacemaker概述1、Pacemaker介绍： Pacemaker是 Linux环境中使⽤最为⼴泛的开源集群资源管理器， Pacemaker利⽤集群基础架构(Corosync或者 Heartbeat)提供的消息和集群成员管理功能，实现节点和资源级别的故障检测和资源恢复，从⽽最⼤程度保证集群服务的⾼可⽤。
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在Fedora上面创建主/主和主备集群
Andrew Beekhof
从头开始搭建集群
Pacemaker 1.1 从头开始搭建集群 在Fedora上面创建主/主和主备集群 版 3
作者 译者 Andrew Beekhof Raoul 言 1. 文档约定 ..................................................................... 1.1. 排版约定 .............................................................. 1.2. 抬升式引用约定 ......................................................... 1.3. 备注及警告 ............................................................ 2. We Need Feedback! ............................................................ 1. Read-Me-First 1.1. 本文范围 .................................................................... 1.2. 什么是Pacemaker? ............................................................ 1.3. Pacemaker 架构 .............................................................. 1.3.1. 内部组件 ............................................................. 1.4. Pacemaker 集群的种类 ........................................................ 2. 安装 2.1. 安装操作系统 ................................................................ 2.2. 集群软件安装 ............................................................... 2.2.1. 安全提示 ............................................................ 2.2.2. 安装集群软件 ......................................................... 2.3. 写在开始之前 ............................................................... 2.4. 安装 ....................................................................... 2.4.1. 设定网络 ............................................................ 2.4.2. 配置SSH ............................................................. 2.4.3. 简化节点名称 ......................................................... 2.4.4. 配置 Corosync ....................................................... 2.4.5. 传送配置文件 ......................................................... ix ix ix x xi xi 1 1 1 2 4 5 7 7 10 10 11 15 15 15 16 16 17 19
本文档的主要目的是提供一站式指南，教您如何使用Pacemaker创建一个主/备模式的集群并把它转换到 主/主模式。 示例集群会使用以下软件: 1. Fedora 13 as the host operating system 2. Corosync作为通信层和提供关系管理服务 3. Pacemaker来实现资源管理 4. DRBD 作为一个经济的共享存储方案 5. GFS2 作为集群文件系统（主/主模式中） 6. crm shell 来显示并修改配置文件 虽然给出了图形化安装Fedora的过程，并且有很多截图，但是本文的主要是靠命令来操作，包括为什么 要运行这个命令和这些操作产生的结果。(译者注:本文中基本是crm shell来操作的，这里应该是老版 本文档的遗留)
3. 检验集群的安装 21 3.1. 检验Corosync的安装 ......................................................... 21 3.2. 检查Pacemaker的安装 ........................................................ 21 4. 使用Pacemaker工具 25 5. 创建一个主/备集群 5.1. 浏览现有配置 ............................................................... 5.2. 添加一个资源 ............................................................... 5.3. 做一次失效备援 ............................................................. 5.3.1. 法定人数和双节点集群 ................................................. 5.3.2. 防止资源在节点恢复后移动 ............................................. 6. Apache 6.1. 6.2. 6.3. 6.4. 6.5. 6.6. 6.7. 6.8. - 添加更多的服务 安装Apache ................................................................. 准备工作 ................................................................... 开启 Apache status URL .................................................... 更新配置文件 ............................................................... 确保资源在同一个节点运行 ................................................... 控制资源的启动停止顺序 ..................................................... 指定优先的 Location ........................................................ 在集群中手工地移动资源 ..................................................... 6.8.1. 把控制权交还给集群 ................................................... 27 27 28 30 30 31 35 35 37 37 37 38 39 40 41 42 43 43 44 44 iii
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