FLIP-FLOP CIRCUIT
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申请人：HITACHI SEISAKUSHO KK,NIPPON DENSHIN DENWA KOSHA
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摘要：PURPOSE:To execute at a high speed an operation of an FF circuit for constituting an NTL circuit by connecting in parallel two or more resistance elements provided on the post-stage and other gate circuits, to a TR for constituting an emitter follower for forming a feedback signal of the gate circuit of the post- stage. CONSTITUTION:A wiring lf of a feedback loop to NOR gates G2, G3 of the pre- stage is connected to one of emitter followers EF41, EF42 of an NOR gate G4 of the post-stage. In this state, when wired OR of outputs of emitter followers EF11-EF31 of gates G1-G3 has been te R33 in the emitter follower EF31 which is not used is connected to said wiring lf. Therefore, in an output node of the emitter follower EF41 of the gate G4, a resistance R43 and R33 are connected in parallel to power supply voltage VTT. As a result, a current flowing to the EF41 increases, its driving capacity is raised, a delay of a signal of the feedback loop is reduced, and an operating speed of the whole FF circuit is increased.
专利内容由知识产权出版社提供
专利名称：FLIP-FLOP CIRCUIT 发明人：USAMI MITSUO,ISHII SHIYUUICHI,MITANI
TSUNEO,HORIGUCHI KATSUJI,HIRATA MICHIHIRO 申请号：J P 24 728583 申请日：19831230 公开号：J P S6014 4 017A 公开日：19850730
更多信息请下载全文后查看
摘要：PURPOSE:To execute at a high speed an operation of an FF circuit for constituting an NTL circuit by connecting in parallel two or more resistance elements provided on the post-stage and other gate circuits, to a TR for constituting an emitter follower for forming a feedback signal of the gate circuit of the post- stage. CONSTITUTION:A wiring lf of a feedback loop to NOR gates G2, G3 of the pre- stage is connected to one of emitter followers EF41, EF42 of an NOR gate G4 of the post-stage. In this state, when wired OR of outputs of emitter followers EF11-EF31 of gates G1-G3 has been te R33 in the emitter follower EF31 which is not used is connected to said wiring lf. Therefore, in an output node of the emitter follower EF41 of the gate G4, a resistance R43 and R33 are connected in parallel to power supply voltage VTT. As a result, a current flowing to the EF41 increases, its driving capacity is raised, a delay of a signal of the feedback loop is reduced, and an operating speed of the whole FF circuit is increased.
专利内容由知识产权出版社提供
专利名称：FLIP-FLOP CIRCUIT 发明人：USAMI MITSUO,ISHII SHIYUUICHI,MITANI
TSUNEO,HORIGUCHI KATSUJI,HIRATA MICHIHIRO 申请号：J P 24 728583 申请日：19831230 公开号：J P S6014 4 017A 公开日：19850730