Generating test patterns used in testing semicondu
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专利名称：Generating test patterns used in testing
semiconductor integrated circuit
发明人：Masahiro Ishida,Takahiro Yamaguchi
申请号：US11239414
申请日：20050928
公开号：US07225377B2
公开日：
20070529
专利内容由知识产权出版社提供
专利附图：
摘要：Selected test pattern sequences to be used in transient power supply current testing to detect path delay faults in an IC are easily and rapidly generated. A stored fault list of path delay faults is prepared. A train of transition signal values is calculated
by simulation of transitions occurring in the IC when a test pattern sequence is applied to the IC, and respective path delay fault in the stored fault list is determined whether it is a detectable fault that is capable of being detected by the transient power supply current testing by using the transition signal values. Those detectable faults that exist in the stored fault list are deleted from the stored fault list and those test pattern sequences that are used to detect the detectable faults existing in the stored fault list are registered in a test pattern sequence list as the selected test pattern sequence.
申请人：Masahiro Ishida,Takahiro Yamaguchi
地址：Tokyo JP,Tokyo JP
国籍：JP,JP
代理机构：Gallagher & Lathrop
代理人：David N. Lathrop, Esq.
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