AD8619ARUZ-REEL中文资料

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AD8692ARMZ-REEL中文资料

Short-Circuit Current Closed-Loop Output Impedance POWER SUPPLY Power-Supply Rejection Ratio
Supply Current/Amplifier
DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin Total Harmonic Distortion + Noise
Applications for this amplifier include PA controls, laser diode control loops, portable and loop-powered instrumentation, audio amplification for portable devices, and ASIC input and output amplifiers.
REVISION HISTORY 10/04—Revision 0: Initial Version
Typical Performance Characteristics ..............................................6 Outline Dimensions ....................................................................... 11
Conditions
VCM = −0.3 V to +1.6 V VCM = −0.1 V to +1.6 V; −40°C < TA < +125°C

AD9860资料

REV.0aInformation furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/ Fax: 781/326-8703© Analog Devices, Inc., 2002AD9860/AD9862*Mixed-Signal Front-End (MxFE ™) Processorfor Broadband Communications*Protected by U.S.Patent No. 5,969,657; other patents pending.MxFE is a trademark of Analog Devices, Inc.GENERAL DESCRIPTIONThe AD9860 and AD9862 (AD9860/AD9862) are versatile integrated mixed-signal front-ends (MxFE) that are optimized for broadband communication markets. The AD9860/AD9862are cost effective, mixed signal solutions for wireless or wireline standards based or proprietary broadband modem systems where dynamic performance, power dissipation, cost, and size are all critical attributes. The AD9860 has 10-bit ADCs and 12-bit DACs;the AD9862 has 12-bit ADCs and 14-bit DACs.The AD9860/AD9862 receive path (Rx) consists of two channels that each include a high performance, 10-/12-bit, 64 MSPS analog-to-digital converter (ADC), input buffer, Programmable Gain Amplifier (RxPGA), digital Hilbert filter, and decimation filter. The Rx can be used to receive real, diversity, or I/Q data at baseband or low IF. The input buffers provide a constant input impedance for both channels to ease impedance matching with external com-ponents (e.g., SAW filter). The RxPGA provides a 20dB gainrange for both channels. The output data bus can be multi-plexed to accommodate a variety of interface types.The AD9860/AD9862 transmit path (Tx) consists of two chan-nels that contain high performance, 12-/14-bit, 128 MSPS digital-to-analog converters (DAC), programmable gain amplifiers (TxPGA), interpolation filters, a Hilbert filter, and digital mixers for complex or real signal frequency modulation. The Tx latch and demultiplexer circuitry can process real or I/Q data. Interpo-lation rates of 2ϫ and 4ϫ are available to ease requirements on an external reconstruction filter. For single channel systems, the digital Hilbert filter can be used with an external quadrature modulator to create an image rejection architecture. The two 12-/14-bit, high performance DACs produce an output signal that can be scaled over a 20 dB range by the TxPGA.A programmable delay-locked loop (DLL) clock multiplier and integrated timing circuits enable the use of a single external reference clock or an external crystal to generate clocking for all internal blocks and also provides two external clock outputs.Additional features include a programmable sigma-delta output,four auxiliary ADC inputs and three auxiliary DAC outputs.Device programmability is facilitated by a serial port interface (SPI) combined with a register bank. The AD9860/AD9862 is available in a space saving 128-lead LQFP.FUNCTIONAL BLOCK DIAGRAMTx DA T A [0:13]SIGDEL T A T A FEATURESMixed-Signal Front-End Processor with Dual Converter Receive and Dual Converter Transmit Signal Paths Receive Signal Path Includes:Two 10-/12-Bit, 64 MSPS Sampling A/D Converters with Internal or External Independent References,Input Buffers, Programmable Gain Amplifiers,Low-Pass Decimation Filters, and a Digital Hilbert Filter Transmit Signal Path Includes:Two 12-/14-Bit, 128 MSPS D/A Converters with Programmable Full-Scale Output Current, Channel Independent Fine Gain and Offset Control, Digital Hilbert and Interpolation Filters, and Digitally Tunable Real or Complex Up-ConvertersDelay-Locked Loop Clock Multiplier and Integrated Timing Generation Circuitry Allow for Single Crystal or Clock OperationProgrammable Output Clocks, Serial Programmable Interface, Programmable Sigma-Delta, Three Auxiliary DAC Outputs and Two Auxiliary ADCs with Dual Multiplexed InputsAPPLICATIONSBroadband Wireless SystemsFixed Wireless, WLAN, MMDS, LMDS Broadband Wireline SystemsCable Modems, VDSL, PowerPlug Digital CommunicationsSet-Top Boxes, Data ModemsAD9860/AD9862–SPECIFICATIONS(V A = 3.3 V ؎ 5%, V D = 3.3 V ؎ 10%, f DAC = 128 MHz, f ADC = 64 MHzNormal Timing Mode, 2؋ DLL Setting, R SET = 4 k⍀, 50 ⍀ DAC Load,–2–REV. 0AD9860/AD9862–3–Test AD9860/AD9862Rx PARAMETERS (continued)Temp Level Min Typ Max Unit DC ACCURACYDifferential Nonlinearity25ºC III±0.3/±0.4LSB Integral Nonlinearity25ºC III±1.2/±5LSB Offset Error25ºC III±0.1%FSR Gain Error25ºC III±0.2%FSR Aperture Delay25ºC III 2.0ns Aperture Uncertainty (Jitter)25ºC III 1.2ps rms Input Referred Noise25ºC III 250µV Reference Voltage ErrorREFT-REFB Error (1 V)25ºC I±1±4mV AD9860 DYNAMIC PERFORMANCE (A IN = –0.5 dBFS, f = 5 MHz)Signal-to-Noise Ratio25∞C I59.0 60.66dBc Signal-to-Noise and Distortion Ratio25∞C I56.0 58.0dBc Total Harmonic Distortion25∞C I–76.5–70.5dBc Spurious Free Dynamic Range25∞C I70.3 81.0dBc AD9862 DYNAMIC PERFORMANCE (A IN = –0.5 dBFS, f = 5 MHz)Signal-to-Noise Ratio25∞C I62.6 64.2dBc Signal-to-Noise and Distortion Ratio25∞C I62.5 64.14dBc Total Harmonic Distortion25∞C I–79.22–73.2dBc Spurious Free Dynamic Range25∞C I77.09 85.13dBc CHANNEL-TO-CHANNEL ISOLATIONTx-to-Rx (A OUT = 0 dBFS, f OUT = 7 MHz)25ºC III >90dB Rx Channel Crosstalk (f1 = 6 MHz, f2 = 9 MHz)25ºC III >80dB PARAMETERSCMOS LOGIC INPUTSLogic “1” Voltage, V IH25ºC II DRVDD – 0.7V Logic “0” Voltage, V IL25ºC II0.4V Logic “1” Current25ºC II12µA Logic “0” Current25ºC II12µA Input Capacitance25ºC III 3pF CMOS LOGIC OUTPUTS (1 mA Load)Logic “1” Voltage, V OH25ºC II DRVDD – 0.6V Logic “0” Voltage, V OL25ºC II0.4V POWER SUPPLYAnalog Supply CurrentsTx (Both Channels, 20 mA FS Output)25ºC I 7076mA Tx Powered Down25ºC I 2.5 5.0mA Rx (Both Channels, Input Buffer Enabled)25ºC I 275307mA Rx (Both Channels, Input Buffer Disabled)25ºC III 245mA Rx (32 MSPS, Low Power Mode, Buffer Disabled)25ºC III 155mA Rx (16 MSPS, Low Power Mode, Buffer Disabled)25ºC III 80mA Rx Path Powered Down25ºC I 5.0 6.0mA DLL25ºC III 12mA Digital Supply CurrentAD9860 Both Rx and Tx Path (All Channels Enabled)2ϫ Interpolation, f DAC = f ADC = 64 MSPS25ºC I 92112mA AD9862 Both Rx and Tx Path (All Channels Enabled)2ϫ Interpolation, f DAC = f ADC = 64 MSPS25ºC I 104124mA Tx Path (f DAC = 128 MSPS)Processing Blocks Disabled25ºC III 45mA 4ϫ Interpolation25ºC III 90mA 4ϫ Interpolation, Coarse Modulation25ºC III 110mA 4ϫ Interpolation, Fine Modulation25ºC III 110mA 4ϫ Interpolation, Coarse and Fine Modulation25ºC III 130mAREV. 0REV. 0–4–AD9860/AD9862Test AD9860/AD9862(20 pF Load)Temp Level Min Typ MaxUnit Minimum Reset Pulsewidth Low (t RL )NA NA 5Clock Cycles Digital Output Rise/Fall Time 25ºC III 2.84ns DLL Output Clock25ºC III 32128MHz DLL Output Duty Cycle25ºC III 50%Tx –/Rx –Interface (See Figures 11 and 12)TxSYNC/TxIQ Setup Time (t Tx1, t Tx3)25ºC III 3ns TxSYNC/TxIQ Hold Time (t Tx2, t Tx4)25ºC III 3ns RxSYNC/RxIQ/IF to Valid Time(t Rx1, t Rx3)25ºC III 5.2ns RxSYNC/RxIQ/IF Hold Time (t Rx2, t Rx4)25ºC III 0.2ns Serial Control Bus (See Figures 1 and 2)Maximum SCLK Frequency (f SCLK )Full III 16MHz Minimum Clock Pulsewidth High (t HI )Full III 30ns Minimum Clock Pulsewidth Low (t LOW )Full III 30ns Maximum Clock Rise/Fall TimeFull III 1ms Minimum Data/SEN Setup Time (t S )Full III 25ns Minimum SEN/Data Hold Time (t H )Full III 0ns Minimum Data/SCLK Setup Time (t DS )Full III 25ns Minimum Data Hold Time (t DH )Full III 0ns Output Data Valid/SCLK Time (t DV )Full III 30ns AUXILARY ADC Conversion Rate 25ºC III 1.25MHz Input Range 25ºC III 3V Resolution 25ºC III 10Bits AUXILARY DAC Settling Time 25ºC III 8m s Output Range 25ºC III 3V Resolution25ºC III 8Bits ADC TIMINGLatency (All Digital Processing Blocks Disabled)25ºC III 7Cycles DAC TimingLatency (All Digital Processing Blocks Disabled)25ºC III 3Cycles Latency (2ϫ Interpolation Enabled)25ºC III 30Cycles Latency (4ϫ Interpolation Enabled)25ºC III 72Cycles Additional Latency (Hilbert Filter Enabled)25ºC III 36Cycles Additional Latency (Coarse Modulation Enabled)25ºC III 5Cycles Additional Latency (Fine Modulation Enabled)25ºC III 8Cycles Output Settling Time (TST) (to 0.1%)25ºCIII35nsSpecifications subject to change without notice.TIMING CHARACTERISTICSTest AD9860/AD9862PARAMETERS (continued)TempLevelMinTyp MaxUnitPOWER SUPPLY (continued)Rx Path (f ADC = 64 MSPS)Processing Blocks Disabled 25ºCIII 9mA Decimation Filter Enabled 25ºC III 15mA Hilbert Filter Enabled25ºC III 16mA Hilbert and Decimation Filter Enabled25ºC III 18.5mANOTES 1% f DATA refers to the input data rate of the digital block.2Interpolation filter stop band is defined by image suppression of 50 dB or greater.Specifications subject to change without notice.REV. 0AD9860/AD9862–5–CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9860/AD9862 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions arerecommended to avoid performance degradation or loss of functionality.ABSOLUTE MAXIMUM RATINGS 1Power Supply (V AS , V DS ) . . . . . . . . . . . . . . . . . . . . . . . . .3.9 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . .5 mA Digital Inputs . . . . . . . . . . . . . . . .–0.3 V to DRVDD + 0.3 V Analog Inputs . . . . . . . . . . . . . .–0.3 V to AVDD (IQ) + 0.3 V Operating Temperature 2 . . . . . . . . . . . . . . . . .–40؇C to +70؇C Maximum Junction Temperature . . . . . . . . . . . . . . . . .150؇C Storage Temperature . . . . . . . . . . . . . . . . . . .–65؇C to +150؇C Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . .300؇CNOTES 1Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.2The AD9860/AD9862 have been characterized to operate over the industrial temperature range (–40؇C to +85؇C) when operated in Half Duplex Mode.EXPLANATION OF TEST LEVELSI.Devices are 100% production tested at 25ºC and guaranteed by design and characterization testing for the extended industrial temperature range (–40ºC to +70ºC).II.Parameter is guaranteed by design and/or characterization testing.III.Parameter is a typical value only.NA.Test level definition is not applicable.THERMAL CHARACTERISTICS Thermal Resistance128-Lead LQFP ␪JA = 29ºC/WORDERING GUIDEModel Temperature Range Package DescriptionPackage Option AD9860BST –40∞C to +70∞C *128-Lead Low Profile Plastic Quad Flatpack (LQFP) ST-128B AD9862BST –40∞C to +70∞C *128-Lead Low Profile Plastic Quad Flatpack (LQFP) ST-128BAD9860PCB Evaluation Board with AD9860AD9862PCBEvaluation Board with AD9862*The AD9860/AD9862 have been characterized to operate over the industrial temperature range (–40؇C to +85؇C) when operated in Half Duplex Mode.REV. 0–6–AD9860/AD9862PIN CONFIGURATIONAGND AVDD DVDD DGND DGND DVDD Tx11/13 (MSB)Tx10/12T x 9/1T x 8/1T x 7/T x 6/T x 5/T x 4/T x 3/T x 2/T x 1/T x 0/N C /T x N C /T x AUX_ADC_A1AGND AVDD AVDD SIGDEL T AUX_DAC_A AUX_DAC_B AUX_DAC_CAGNDDLL_Lock AGND NC AVDD OSC1OSC2AGND CLKSEL AVDD AGND AVDD REFIO FSADJ AVDD AGND IOUT–A IOUT+A AGND AGND IOUT+B IOUT–B T x S Y N D G N D V D S C L S D S D I S E D G N D V D D G N D V D M O D E /T x B L A N R E S E T C L K O U T A G N DA V D DA V D DA G N DV I N +BV I N –BA G N DA G N DV R E FA G N DA G N DV I N –AV I N +AA G N DA V D DA V D DA G N DR E F B _AR E F T _AA G N DA V D DA V D DA U X _A D C _B 2A U X _A D C _B 1A U X _A D C _R E FA U X _A D C _A 2NC = NO CONNECTAD9860/AD9862–7–Pin No.Mnemonic FunctionClock Pins10DLL_Lock DLL Lock Indicator Pin11, 16AGND DLL Analog Ground Pins12NC No Connect13AVDD DLL Analog Supply Pin14OSC1Single Ended Input Clock(or Crystal Oscillator Input)15OSC2Crystal Oscillator Input17CLKSEL Controls CLKOUT1 Rate64CLKOUT2Clock Output Generated from InputClock (DLL Multiplier Settingand CLKOUT2 Divide Factor)65CLKOUT1Clock Output Generated fromInput Clock (1ϫ if CLKSEL = 1or /2 if CLKSEL = 0)Various Pins1AUX_ADC_A1Auxiliary ADC A Input 13, 4, 13AVDD Analog Power Pins2, 9AGND Analog Ground Pins5SIGDELT Digital Output fromProgrammable Sigma-Delta6AUX_DAC_A Auxiliary DAC A Output7AUX_DAC_B Auxiliary DAC B Output8AUX_DAC_C Auxiliary DAC C Output33, 36, 53,DVDD Digital Power Supply Pin59, 61, 66,9334, 35, 52,DGND Digital Ground Pin58, 60, 67,9454SCLK Serial Bus Clock Input55SDO Serial Bus Data Bit56SDIO Serial Bus Data Bit57SEN Serial Bus Enable63RESETB Reset (SPI Registers and Logic) 95AUX_SPI_do Optional Auxiliary ADC Serial BusData Out Bit96AUX_SPI_clk Optional Auxiliary ADC Serial BusData Out Latch Clock97AUX_SPI_csb Optional Auxiliary ADC Serial BusChip Select Bit128AUX_ADC_A2Auxiliary ADC A Input 2126AUX_ADC_B1Auxiliary ADC B Input 1125AUX_ADC_B2Auxiliary ADC B Input 2127AUX_ADC_REF Auxiliary ADC ReferencePin No.Mnemonic FunctionReceive Pins68/70–79D0A to10-/12-Bit ADC Output ofD9A/D11A Receive Channel A80/82–91D0B to10-/12-Bit ADC Output ofD9B/D11B Receive Channel B92RxSYNC Synchronization Clock forChannel A and Channel B Rx Paths98, 99,AVDD Analog Supply Pins104, 105,117, 118,123, 124,100, 103,AGND Analog Ground Pins106, 109,110, 112,113, 116,119, 122,101REFT_B Top Reference Decoupling forChannel B ADC102REFB_B Bottom Reference Decouplingfor Channel B ADC107VIN+B Receive Channel B Differential (+) Input108VIN–B Receive Channel B Differential (؊) Input111VREF Internal ADC Voltage Reference114VIN–A Receive Channel A Differential (؊) Input115VIN+A Receive Channel A Differential (+) Input120REFB_A Bottom Reference Decoupling forChannel A ADC121REFT_A Top Reference Decoupling forChannel A ADCTransmit Pins18, 20AVDD Analog Supply Pins23, 3219, 24,AGND Analog Ground Pins27, 28, 3121REFIO Reference Output, 1.2 V Nominal22FSADJ Full-Scale Current Adjust25IOUT–A Transmit Channel A DACDifferential (؊) Output26IOUT+A Transmit Channel A DACDifferential (+) Output29IOUT+B Transmit Channel B DACDifferential (+) Output30IOUT–B Transmit Channel B DACDifferential (؊) Output37–48/50Tx11/Tx1312-/14-Bit Transmit DAC Datato Tx0(Interleaved Data when Required)51TxSYNC Synchronization Input for Transmitter62MODE/Configures Default Timing Mode,TxBLANK*Controls Tx Digital Power Down*The logic level of the Mode/TxBLANK pin at power up defines the default timingmode; a logic low configures Normal Operation, logic high configures AlternateOperation Mode.PIN FUNCTION DESCRIPTIONSREV. 0AD9860/AD9862DEFINITIONS OF SPECIFICATIONSDifferential Nonlinearity Error (DNL, No Missing Codes)An ideal converter exhibits code transitions that are exactly 1LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 10-bit resolution indicate that all 1024 codes respectively, must be present over all operating ranges.Integral Nonlinearity Error (INL)Linearity error refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” The point used as “negative full scale” occurs 1/2LSB before the first code transition. “Positive full scale” is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line.Phase NoiseSingle-sideband phase noise power is specified relative to the carrier (dBc/Hz) at a given frequency offset (1 kHz) from the carrier. Phase noise can be measured directly in Single Tone Trans-mit Mode with a spectrum analyzer that supports noise marker measurements. It detects the relative power between the carrier and the offset (1 kHz) sideband noise and takes the resolution bandwidth (rbw) into account by subtracting 10 log(rbw). It also adds a correction factor that compensates for the implementation of the resolution bandwidth, log display, and detector characteristic. Output Compliance RangeThe range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance.Spurious-Free Dynamic Range (SFDR)The difference, in dB, between the rms amplitude of the DAC’s output signal (or ADC’s input signal) and the peak spurious signal over the specified bandwidth (Nyquist bandwidth unless otherwise noted).Pipeline Delay (Latency)The number of clock cycles between conversion initiation and the associated output data being made available.Offset ErrorFirst transition should occur for an analog value 1/2 LSB above –full scale. Offset error is defined as the deviation of the actual transition from that point.Gain ErrorThe first code transition should occur at an analog value 1/2LSB above –full scale. The last transition should occur for an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.Aperture DelayThe aperture delay is a measure of the Sample-and-Hold Ampli-fier (SHA) performance and specifies the time delay between the rising edge of the sampling clock input to when the input signal is held for conversion.Aperture Uncertainty (Jitter)Aperture jitter is the variation in aperture delay for successivesamples and is manifested as noise on the input to the ADC.Input Referred NoiseThe rms output noise is measured using histogram techniques.The ADC output code’s standard deviation is calculated in LSB and converted to an equivalent voltage. This results in a noisefigure that can be referred directly to the input of the AD9860/ AD9862.Signal-to-Noise and Distortion (S/N+D, SINAD) RatioS/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.Effective Number of Bits (ENOB)For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula:N=()SINAD dB–..176602it is possible to get a measure of performance expressed as N,the effective number of bits. Thus, effective number of bits fora device for sine wave inputs at a given input frequency can becalculated directly from its measured SINAD.Signal-to-Noise Ratio (SNR)SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR isexpressed in decibels.Total Harmonic Distortion (THD)THD is the ratio of the rms sum of the first six harmoniccomponents to the rms value of the measured input signal and is expressed as a percentage or in decibels.Power Supply RejectionPower supply rejection specifies the converter’s maximum full-scale change when the supplies are varied from nominal to minimum and maximum specified voltages.Channel-to-Channel Isolation (Crosstalk)In an ideal multichannel system, the signal in one channel will not influence the signal level of another channel. The channel-to-channel isolation specification is a measure of the change that occurs to a grounded channel as a full-scale signal is applied to another channel.REV. 0–8––9–FREQUENCY – MHzTPC 1.AD9862 Tx Output 6 MHzSingle Tone; CLKIN = 32 MHz;DLL 4ϫ SettingFREQUENCY – MHzMAGNITUDE–dBm–20–4020406080100110120–60–80140TPC 4.TxDAC Generating anOFDM Signal; CLKIN = 64 MHz,DLL 2ϫ Settingf OUT – MHz5203510152530THD–dBcTPC 7.TxDAC HarmonicDistortion vs. f OUTFREQUENCY – MHzTPC 2.AD9862 Tx Output 6 MHzSingle Tone; CLKIN = 64 MHz;DLL 2ϫ SettingFREQUENCY – MHzMAGNITUDE–dBm20406080100110120140TPC 5.TxDAC Generating anOFDM Signal; CLKIN = 64 MHz,DLL 2ϫ SettingFREQUENCY– MHzSNR–dB74737271706968TPC 8.Signal-to-Noise Ratio (SNR)vs. f OUTFREQUENCY – MHzTPC 3.AD9862 Tx Output 6 MHzSingle Tone; CLKIN = 128 MHz;DLL 1ϫ SettingFREQUENCY – MHzMAGNITUDE–dBm–20–40–60–80–100–120TPC 6.Zoomed in Plot of FourNotched Carriers of OFDM Signal;CLKIN = 64 MHz, DLL 2ϫ SettingCARRIER FREQUENCY – MHz5IMD–dBc20–60–65–70–75–80–85–9010152530–50–55–95TPC 9.Two Tone Intermodulationvs. f OUT1 (f OUT2 = f OUT1 + 1 MHz)REV. 0AD9860/AD9862FFT OUTPUT – MHz5FFTMAGNITUDE–dBFS20–20–40–60–8010152530–100–120TPC 10.ADC Dual Tone FFT withBuffer Tones at 4.5 MHz and 5.5 MHzf IN – MHz52TPC 13.AD9862 Rx SINADvs. fINat 64 MSPSf IN – MHzTPC 16.AD9860 Rx SINADvs. f IN at 64 MSPSFFT OUTPUT – MHz5FFTMAGNITUDE–dBFS20–20–40–60–8010152530–100–120TPC 11.ADC Dual Tone FFT withoutBuffer Tones at 4.5 MHz and 5.5 MHzf IN – MHzSINAD–dBcTPC 14.AD9862 Rx SINADvs. f IN at 32 MSPSf IN – MHzSINAD–dBc62TPC 17.AD9860 Rx SINADvs. f IN at 32 MSPSFFT OUTPUT – MHz5FFTMAGNITUDE–dBFS20–20–40–60–8010152530–100–120TPC 12.ADC Dual Tone FFT(undersampling) without BufferTones at 69.5 MHz and 70.5 MHzf IN – MHz020050SINAD–dBc150250100300TPC 15.AD9862 Rx SINADvs. f IN at 16 MSPSf IN – MHzSINAD–dBc62TPC 18.AD9860 Rx SINADvs. f IN at 16 MSPSREV. 0–10–AD9860/AD9862INPUT FREQUENCY – MHzT H D – d B c–60–65–70–75–80–85–90–50–55–95–100TPC 19.Rx THD vs. f IN ,F ADC = 64 MSPSINPUT FREQUENCY – MHzS F D R – d B c–60–65–70–75–80–85–90–50–55–95–100TPC 22.Rx SFDR @ 64 MSPSINPUT FREQUENCY – MHzR E L A T I V E A T T E N U A T I O N – d B10–1–2–3–4–5–6TPC 25.Rx Input Attenuationf IN – MHzT H D – d B c–75–80–85–90–70–65–60–55–50TPC 20.Rx THD vs. f IN ,F ADC = 32 MSPS f IN – MHzS F D R – d B c–75–80–85–90–70–65–60–55–50–95TPC 23.Rx SFDR @ 32 MSPS f IN – MHzI N P U T I M P E D A N C E – ⍀60250240230220210200190204080100270260180280TPC 26.Rx Input Buffer Impedance vs. f INf IN – MHzT H D – d B c–75–80–85–90–70–65–60–55–50TPC 21.Rx THD vs. f IN ,F ADC = 16 MSPSf IN – MHz020050S F D R – d B c–75–80–85–90–70150250100–65–60–55–50300–95TPC 24.Rx SFDR @ 16 MSPSf ADC – MSPS04010R x A N A L O G P O W E R – m W30020010004003050205006007008007060TPC 27.Rx Analog Power ConsumptionAD9860/AD9862REGISTER MAP (0x00–0x3F)1NOTES1When writing to a register with unassigned register bit(s), a logic low must be written to the unassigned bit(s). By default, after power up or RESET, all registers are set low, except for the bits in the shaded boxes, which are set high.2DecimalAD9860/AD9862REGISTER BIT DEFINITIONSREGISTER 0: GENERALBIT 7: SDIO BiDir (Bidirectional)Default setting is low, which indicates SPI serial port uses dedi-cated input and output lines (i.e., 4-wire interface), SDIO and SDO Pins, respectively. Setting this bit high configures the serial port to use the SDIO Pin as a bidirectional data pin.BIT 6: LSB FirstDefault setting is low, which indicates MSB first SPI Port Access Mode. Setting this bit high configures the SPI port access to LSB first mode.BIT 5: Soft ResetWriting a high to this register resets all the registers to their default values and forces the DLL to relock to the input clock. The Soft Reset Bit is a one shot register and is cleared immediately after the register write is completed.REGISTER 1: Rx PWRDWNBIT 7: V REF, diff (Power-Down)Setting this bit high will power down the ADC’s differential references (i.e., REFT and REFB).BIT 6: V REF (Power-Down)Setting this register bit high will power down the ADC reference circuit (i.e., V REF).BIT 5: Rx Digital (Power-Down)Setting this bit high will power down the digital section of the receive path of the chip. Typically, any unused digital blocks are automatically powered down.BIT 4/3: Rx Channel B/Rx Channel A (Power-Down)Either ADC or both ADCs can be powered down by setting the appropriate register bit high. The entire Rx channel is powered down, including the differential references, input buffer, and the internal digital block. The bandgap reference remains active for quick recovery.BIT 2/1: Buffer B/Buffer A (Power-Down)Setting either of these bits high will power down the input buffer circuits for the respective channel. The input buffer should be powered down when bypassed. By default, these bits are low and the input buffers are enabled.BIT 0: All Rx (Power-Down)Setting this bit high powers down all circuits related to the receive path.REGISTER 2/3: Rx A/Rx BBIT 7: Bypass Buffer A/Bypass Buffer BSetting either of these bits high will bypass the respective input buf-fer circuit. When the buffer is bypassed, the input signal is routed directly to the switched capacitor SHA input of the RxPGA. When operating with buffer bypassed, it should be powered down.BIT 0–4: RxPGA A/RxPGA BThese 5-bit straight binary registers (Bit 0 is the LSB, Bit 4 is the MSB) provide control for the programmable gain amplifiers in the dual receive paths. A 0 dB to 20 dB gain range is accom-plished through a switched capacitor network with fast settling of a few clock cycles. The step size is approximately 1 dB. The register default setting is minimum gain or hex00. The maximum setting for these registers is hex14.REGISTER 4: Rx MISCBIT 2: HS (High Speed) Duty CycleSetting this bit high optimizes duty cycle of the internal ADC sampling clock. It is recommended that this bit be set high in high speed applications when clock duty cycle affects noise and distortion performance the most. This bit should be set high in conjunction with Clk Dut Enable register bit.BIT 1: Shared RefSetting this bit high forces the dual receive ADCs into a mode to share their differential references to provide superior gain matching. When this option is enabled, the REFT of Channel A and Channel B should be connected together off-chip and the REFB of both channels should be connected.BIT 0: Clk DutySetting this bit high enables an on-chip duty cycle stabilizer (DCS) circuit to generate the internal clock for the Rx block. This option is useful for adjusting for high speed input clocks with skewed duty cycle. The DCS Mode can be used with ADC sampling frequencies over 40 MHz.REGISTER 5: Rx I/F (INTERFACE)BIT 4: Three-stateSetting this bit high will force both Rx data output buses, including the RxSYNC Pin, into a three-state mode.BIT 3: Rx RetimeThe Rx path can use either of the clock outputs, CLKOUT1 or CLKOUT2, to latch the Rx output data. Since CLKOUT1 and CLKOUT2 have slight phase offsets, this provides some timing flexibility with the interface. By default, this bit is low and the Rx output latches use CLKOUT1. Setting this bit will force the Rx output latches to use CLKOUT2.BIT 2: Twos ComplementDefault data format for the Rx data is straight binary. Setting this bit high will generate two’s complement data.BIT 1: Inv RxSyncWhen the receive data is multiplexed onto one data port (i.e., Mux Mode Enabled), the RxSYNC Pin can be used to decode which channel generated the current output data at the active port. Default condition is that RxSYNC is high when Channel A is at the output and is low when Channel B is at the output. Setting this bit high reverses this synchronization.BIT 0: Mux OutSetting this bit high enables the Rx Mux Mode. Default setting is low, which is Dual Port Mode, (i.e., non Rx Mux Mode). When in Rx Mux Mode, both Rx channels share the same output data bus, pins D0A to D9A (for AD9860) or D0A to D11A (for AD9862). The other Rx output bus (pins D0B to D9B or D0B to D11B) outputs a low logic.REGISTER 6: Rx DigitalBIT 3: 2 ChannelSetting this bit low disables the Rx B output data port (pins D0B to D9B or D11B), forcing the output pins to zero. By default, the bit is high and both data paths are active.BIT 2: Keep –veThis bit selects whether the receive Hilbert filter will filter positive or negative frequencies, assuming the filter is enabled. By default this bit is low, which passes positive frequencies. Setting this bit high will configure the filter to pass negative frequencies.BIT 1: HilbertThis bit enables or disables the Hilbert filter in the receive path. By default, this bit is low, which disables the receive Hilbert filter. Setting this bit high enables the receive Hilbert filter.BIT 0: DecimateThis register enables or disables the decimation filters. By default, the register setting is low and the decimation filter is disabled.。

AD8607AR-REEL中文资料

–40°C < TA < +85°C –40°C < TA < +125°C
–40°C < TA < +85°C –40°C < TA < +125°C
0 V < VCM < 5 V –40°C < TA < +125°C RL = 10 kΩ, 0.5 V <VO < 4.5 V
AD8607/AD8609
These amplifiers use a patented trimming technique that achieves superior precision without laser trimming. The parts are fully specified to operate from 1.8 V to 5.0 V single supply or from ±0.9 V to ±2.5 V dual supply. The combination of low offsets, low noise, very low input bias currents, and low power consumption make the AD8603/AD8607/AD8609 especially useful in portable and loop-powered instrumentation.
元器件交易网
AD8603/AD8607/AD8609
TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Typical Performance Characteristics ............................................. 6 Applications..................................................................................... 12

AD8610ARZ-REEL资料

REV.DInformation furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 Fax: 781/326-8703© 2004 Analog Devices, Inc. All rights reserved.AD8610/AD8620 Precision, Very Low Noise,Low Input Bias Current, Wide BandwidthJFET Operational AmplifierFUNCTIONAL BLOCK DIAGRAMS8-Lead MSOP and SOIC(RM-8 and R-8 Suffixes)؊؉VV؉OUTNULLNCNC = NO CONNECT8-Lead SOIC(R-8 Suffix)؊؉V INB INB ؉FEATURESLow Noise 6 nV/√HzLow Offset Voltage: 100 ␮V MaxLow Input Bias Current 10 pA Max Fast Settling: 600 ns to 0.01%Low DistortionUnity Gain StableNo Phase ReversalDual-Supply Operation: ؎5 V to ؎13 V APPLICATIONSPhotodiode AmplifierATEInstrumentationSensors and ControlsHigh Performance FiltersFast Precision IntegratorsHigh Performance AudioGENERAL DESCRIPTIONThe AD8610/AD8620 is a very high precision JFET input amplifier featuring ultralow offset voltage and drift, very low input voltage and current noise, very low input bias current, and wide bandwidth. Unlike many JFET amplifiers, the AD8610/AD8620 input bias current is low over the entire operating temperature range. The AD8610/AD8620 is stable with capacitive loads of over 1000 pF in noninverting unity gain; much larger capacitive loads can be driven easily at higher noise gains. The AD8610/AD8620 swings to within 1.2 V of the supplies even with a 1 kΩ load, maximizing dynamic range even with limited supply voltages. Outputs slew at 50 V/µs in either inverting or noninverting gain configurations, and settle to 0.01% accuracy in less than 600 ns. Combined with the high input impedance, great precision, and very high output drive, the AD8610/AD8620 is an ideal amplifier for driving high performance A/D inputs and buffering D/A converter outputs. Applications for the AD8610/AD8620 include electronic instru-ments; ATE amplification, buffering, and integrator circuits; CAT/MRI/ultrasound medical instrumentation; instrumentation quality photodiode amplification; fast precision filters (including PLL filters); and high quality audio.The AD8610/AD8620 is fully specified over the extended industrial (–40°C to +125°C) temperature range. The AD8610 is available in the narrow 8-lead SOIC and the tiny MSOP8 surface-mount packages. The AD8620 is available in the narrow 8-lead SOIC package. MSOP8 packaged devices are available only in tape and reel.元器件交易网AD8610/AD8620–SPECIFICATIONS(@ V S = ؎5.0 V, V CM = 0 V, T A = 25؇C, unless otherwise noted.) Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICSOffset Voltage (AD8610B)V OS45100µV–40°C < T A < +125°C80200µV Offset Voltage (AD8620B)V OS45150µV–40°C < T A < +125°C80300µV Offset Voltage (AD8610A/AD8620A)V OS85250µV+25°C < T A < 125°C90350µV–40°C < T A < +125°C150850µV Input Bias Current I B–10+2+10pA–40°C < T A < +85°C–250+130+250pA–40°C < T A < +125°C–2.5+1.5+2.5nA Input Offset Current I OS–10+1+10pA–40°C < T A < +85°C–75+20+75pA–40°C < T A < +125°C–150+40+150pA Input Voltage Range–2+3V Common-Mode Rejection Ratio CMRR V CM = –2.5 V to +1.5 V9095dB Large Signal Voltage Gain A VO R L = 1 kΩ, V O = –3 V to +3 V100180V/mV Offset Voltage Drift (AD8610B)∆V OS/∆T–40°C < T A < +125°C0.51µV/°C Offset Voltage Drift (AD8620B)∆V OS/∆T–40°C < T A < +125°C0.5 1.5µV/°C Offset Voltage Drift (AD8610A/AD8620A)∆V OS/∆T–40°C < T A < +125°C0.8 3.5µV/°C OUTPUT CHARACTERISTICSOutput Voltage High V OH R L = 1 kΩ, –40°C < T A < +125°C 3.84V Output Voltage Low V OL R L = 1 kΩ, –40°C < T A < +125°C–4–3.8V Output Current I OUT V OUT > ±2 V±30mA POWER SUPPLYPower Supply Rejection Ratio PSRR V S = ±5 V to ±13 V100110dB Supply Current/Amplifier I SY V O = 0 V 2.5 3.0mA–40°C < T A < +125°C 3.0 3.5mA DYNAMIC PERFORMANCESlew Rate SR R L = 2 kΩ4050V/µs Gain Bandwidth Product GBP25MHz Settling Time t S A V = +1, 4 V Step, to 0.01%350ns NOISE PERFORMANCEVoltage Noise e n p-p0.1 Hz to 10 Hz 1.8µV p-p Voltage Noise Density e n f = 1 kHz6nV/√Hz Current Noise Density i n f = 1 kHz5fA/√Hz Input Capacitance C INDifferential8pF Common-Mode15pF Channel Separation C Sf = 10 kHz137dBf = 300 kHz120dB Specifications subject to change without notice.–2–REV. DREV. D AD8610/AD8620–3–ELECTRICAL SPECIFICATIONS (@ V S= ؎13 V, VCM = 0 V, T A = 25؇C, unless otherwise noted.)ParameterSymbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage (AD8610B)V OS 45100µV –40°C < T A < +125°C 80200µV Offset Voltage (AD8620B)V OS 45150µV –40°C < T A < +125°C 80300µV Offset Voltage (AD8610A/AD8620A)V OS 85250µV +25°C < T A < 125°C 90350µV –40°C < T A < +125°C 150850µV Input Bias Current I B –10+3+10pA –40°C < T A < +85°C –250+130+250pA –40°C < T A < +125°C –3.5+3.5nA Input Offset CurrentI OS–10+1.5+10pA –40°C < T A < +85°C –75+20+75pA –40°C < T A < +125°C–150+40+150pA Input Voltage Range–10.5+10.5V Common-Mode Rejection Ratio CMRR V CM = –10 V to +10 V90110dB Large Signal Voltage GainA VOR L = 1 k Ω, V O = –10 V to +10 V 100200V/mV Offset Voltage Drift (AD8610B)∆V OS /∆T –40°C < T A < +125°C 0.51µV/°C Offset Voltage Drift (AD8620B)∆V OS /∆T –40°C < T A < +125°C 0.5 1.5µV/°C Offset Voltage Drift (AD8610A/AD8620A)∆V OS /∆T –40°C < T A < +125°C0.83.5µV/°COUTPUT CHARACTERISTICS Output Voltage High V OH R L = 1 k Ω, –40°C < T A < +125°C +11.75+11.84VOutput Voltage Low V OL R L = 1 k Ω, –40°C < T A < +125°C –11.84–11.75V Output CurrentI OUT V OUT > 10 V±45mA Short Circuit Current I SC ±65mA POWER SUPPLYPower Supply Rejection Ratio PSRR V S = ±5 V to ±13 V 100110dB Supply Current/Amplifier I SYV O = 0 V3.0 3.5mA –40°C < T A < +125°C 3.54.0mA DYNAMIC PERFORMANCE Slew RateSR R L = 2 k Ω4060V/µs Gain Bandwidth Product GBP 25MHz Settling Timet S A V = 1, 10 V Step, to 0.01%600ns NOISE PERFORMANCE Voltage Noisee n p-p 0.1 Hz to 10 Hz 1.8µV p-p Voltage Noise Density e nf = 1 kHz 6nV/√Hz Current Noise Density i n f = 1 kHz5fA/√Hz Input Capacitance C IN Differential 8pF Common-Mode 15pF Channel Separation C Sf = 10 kHz 137dB f = 300 kHz120dBSpecifications subject to change without notice.REV. D–4–AD8610/AD8620ORDERING GUIDETemperature Package Package ModelRangeDescription Option BrandingAD8610AR–40°C to +125°C 8-Lead SOIC RN-8AD8610AR-REEL –40°C to +125°C 8-Lead SOIC RN-8AD8610AR-REEL7–40°C to +125°C 8-Lead SOIC RN-8AD8610ARM-REEL –40°C to +125°C 8-Lead MSOP RM-8B0A AD8610ARM-R2–40°C to +125°C 8-Lead MSOP RM-8B0AAD8610ARZ *–40°C to +125°C 8-Lead SOIC RN-8AD8610ARZ-REEL *–40°C to +125°C 8-Lead SOIC RN-8AD8610ARZ-REEL7*–40°C to +125°C 8-Lead SOIC RN-8AD8610BR–40°C to +125°C 8-Lead SOIC RN-8AD8610BR-REEL –40°C to +125°C 8-Lead SOIC RN-8AD8610BR-REEL7–40°C to +125°C 8-Lead SOIC RN-8AD8610BRZ *–40°C to +125°C 8-Lead SOIC RN-8AD8610BRZ-REEL *–40°C to +125°C 8-Lead SOIC RN-8AD8610BRZ-REEL7*–40°C to +125°C 8-Lead SOIC RN-8AD8620AR–40°C to +125°C 8-Lead SOIC RN-8AD8620AR-REEL –40°C to +125°C 8-Lead SOIC RN-8AD8620AR-REEL7–40°C to +125°C 8-Lead SOIC RN-8AD8620BR–40°C to +125°C 8-Lead SOIC RN-8AD8620BR-REEL –40°C to +125°C 8-Lead SOIC RN-8AD8620BR-REEL7–40°C to +125°C8-Lead SOICRN-8*Pb-free partABSOLUTE MAXIMUM RATINGS *Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27.3 V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V S–– to V S+Differential Input Voltage . . . . . . . . . . . . . . .± Supply Voltage Output Short-Circuit Duration to GND . . . . . . . . . .Indefinite Storage Temperature RangeR, RM Packages . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C Operating Temperature RangeAD8610/AD8620 . . . . . . . . . . . . . . . . . . . .–40°C to +125°C Junction Temperature RangeR, RM Packages . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C Lead Temperature Range (Soldering, 10 sec) . . . . . . . . 300°C*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Package Type ␪JA *␪JC Unit 8-Lead MSOP (RM)19044°C/W 8-Lead SOIC (RN)15843°C/W*θJA is specified for worst-case conditions; i.e., θJA is specified for a device soldered in circuit board for surface-mount packages.CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8610/AD8620 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.REV. D Typical Performance Characteristics–AD8610/AD8620–5–INPUT OFFSET VOL T AGE – ␮V1486421012N U M B E R O F A MP L I F I E R STPC 1.Input Offset Voltage at ±13 VI N P U T O F F S E T V O L T A G E –␮V600400–600200–200–400TEMPERATURE – ؇CTPC 4.Input Offset Voltage vs.Temperature at ±5 V (300 Amplifiers)SUPPL Y VOL T AGE – ؎V3.01.502.51.00.52.0013123456789101112S U P P L Y C U R R E N T – m ATPC 7.Supply Current vs.Supply Voltage I N P U TO F F S E T V O L T A G E – ␮V600400؊6002000؊200؊400TEMPERATURE – ؇CTPC 2.Input Offset Voltage vs.Temperature at ±13 V (300 Amplifiers)T C V OS – ␮V/؇C141210864200.20.61.01.41.82.22.6N U M B E R O FA M P L I F I E R S TPC 5.Input Offset Voltage DriftTEMPERATURE – ؇C2.553.052.852.652.952.75S U P P L Y C U R R E N T – m A؊40TPC 8.Supply Current vs.Temperature at ±13 V INPUT OFFSET VOL T AGE – ␮V148642101201618؊250250؊15050150؊50N U M B E R O F A M P L I F I E R STPC 3.Input Offset Voltage at ±5 VCOMMON-MODE VOL T AGE – V3.63.42.02.82.62.42.23.23.0I N P U T BI A S C U R R E N T –p ATPC 6.Input Bias Current mon-Mode VoltageTEMPERATURE – ؇C2.302.652.602.402.502.552.452.35S U P P L Y C U R R E N T – m A؊40TPC 9.Supply Current vs.Temperature at ±5 VREV. D–6–AD8610/AD8620O U T P U T V O L T A G E T O S U P P L Y R A I L – VRESIST ANCE LOAD – ⍀100M10M 1M 100k 10k 1k10000.20.40.60.81.01.21.41.61.8TPC 10.Output Voltage to Supply Rail vs. Load 12.0511.8012.0011.9511.9011.85O U T P U T V O L T A G E H I G H –VTEMPERA TURE – ؇CTPC 13.Output Voltage High vs. Temperature at ±13 VFREQUENCY – Hz10k100k 1M 1k10M 100MC L O S ED -L O O P G A I N – d B؊40؊20206040TPC 16.Closed-Loop Gain vs.FrequencyTEMPERA TURE – ؇C4.254.203.954.154.104.054.00O U T P U T V O L T A G E H I G H – VTPC 11.Output Voltage High vs.Temperature at ±5 VTEMPERA TURE – ؇C؊11.80؊12.05؊11.85؊11.90؊11.95؊12.00O U T P U T V O L T A G E L O W – VTPC 14.Output Voltage Low vs.Temperature at ±13 VTEMPERA TURE – ؇C260100A V O – V /m V220180140240200160120TPC 17.A VO vs. Temperature at ±13 VTEMPERA TURE – ؇C؊3.95؊4.05؊4.30؊4.10؊4.15؊4.20؊4.25؊4.00O U T P U T V O L T A G E L O W – VTPC 12.Output Voltage Low vs.Temperature at ±5 VG A I N – d B40206080100120؊20؊40؊60؊80FREQUENCY – MHzP H A S E – D e g r e e s90450135180225270؊45؊90؊135؊180TPC 15.Open-Loop Gainand Phase vs. FrequencyTEMPERA TURE – ؇C190100180160140120170150130110A V O – V /m V TPC 18.A VO vs. Temperature at ±5 VREV. D AD8610/AD8620–7–P S R R – d BFREQUENCY – Hz60M10k 100k 1M 10M 1001kTPC 19.PSRR vs. Frequency at ±13 V C M R R – d BFREQUENCY – Hz1060M10k 100k 1M 10M1001k 14010080604020120TPC 22.CMRR vs. Frequency TIME – 1s/DIVP -P V O L T A G E N O I S E – 1␮V /D I VTPC 25.0.1 Hz to 10 Hz Input VoltageNoise P S R R – d B122121116120119118117TEMPERATURE – ؇CTPC 21.PSRR vs. TemperatureTIME – 4␮s/DIVV O L T A G E – 300m V /D I VTPC 24.Negative OvervoltageRecoveryFREQUENCY – Hz1k100M10k100k1M 10M Z O U T – ⍀TPC 27.Z OUT vs. FrequencyP S R R – d B–401008060400120–2020160140FREQUENCY – Hz60M10k 100k 1M 10M1001kTPC 20.PSRR vs. Frequency at ±5 VTIME – 4␮s/DIVV O L T A G E – 300m V /D I V0V0VTPC 23.Positive Overvoltage RecoveryFREQUENCY –Hz1,00010011011M10010k101k100kV O L T A G E N O I S E D E N S I T Y – n V TPC 26.Input Voltage Noise vs.FrequencyREV. D–8–AD8610/AD8620FREQUENCY – HzZ O U T – ⍀1009008070605040302010TPC 28.Z OUT vs. FrequencyCAP ACIT ANCE – pF4035030255201510110k 101001k S M A L L S I G N A L O V E R S H O O T – %TPC 31.Small Signal Overshoot vs.Load CapacitanceTIME – 400ns/DIVV O L T A G E – 5V /D I VTPC 34.+SR at G = +1TEMPERA TURE – ؇CI B –p A30002500025851252000150********TPC 29.Input Bias Current vs.TemperatureTIME – 400␮s/DIVV O L T A G E – 5V /D I VTPC 32.No Phase ReversalTIME – 400ns/DIVV O L T A G E – 5V /D I VTPC 35.–SR at G = +1CAP ACIT ANCE – pF4035030255201510110k101001kS M A L L S I G N A L O V E R S H O O T – %TPC 30.Small Signal Overshoot vs.Load CapacitanceTIME – 1␮s/DIVV O L T A G E – 5V /D I VTPC rge Signal Response at G = +1TIME – 1␮s/DIVV O L T A G E – 5V /D I VTPC rge Signal Response at G = –1REV. DAD8610/AD8620–9–TIME – 400ns/DIVV O L T A G E – 5V /D I VTPC 37.+SR at G = –1TIME – 400ns/DIVV O L T A G E – 5V /D I VTPC 38.–SR at G = –1V IN20V p-pCS(dB) = 20 log (V OUT /10 ؋ V IN )Figure 1.Channel Separation Test CircuitFUNCTIONAL DESCRIPTIONThe AD8610/AD8620 is manufactured on Analog Devices, Inc.’s proprietary XFCB (eXtra Fast Complementary Bipolar) process.XFCB is fully dielectrically isolated (DI) and used in conjunc-tion with N-channel JFET technology and trimmable thin-film resistors to create the world’s most precise JFET input amplifier.Dielectrically isolated NPN and PNP transistors fabricated on XFCB have F T greater than 3 GHz. Low T C thin film resistors enable very accurate offset voltage and offset voltage tempcotrimming. These process breakthroughs allowed Analog Devices’world class IC designers to create an amplifier with faster slew rate and more than 50% higher bandwidth at half of the current consumed by its closest competition. The AD8610 is uncondi-tionally stable in all gains, even with capacitive loads well in excess of 1 nF. The AD8610B achieves less than 100 µV of offset and 1 µV/°C of offset drift, numbers usually associated with very high precision bipolar input amplifiers. The AD8610 is offered in the tiny 8-lead MSOP as well as narrow 8-lead SOIC surface-mount packages and is fully specified with supply voltages from ±5 V to ±13 V. The very wide specified temperature range, up to 125°C, guarantees superior operation in systems with little or no active cooling.The unique input architecture of the AD8610 features extremely low input bias currents and very low input offset voltage. Low power consumption minimizes the die temperature and maintains the very low input bias current. Unlike many competitive JFET amplifiers, the AD8610/AD8620 input bias currents are low even at elevated temperatures. Typical bias currents are less than 200pA at 85°C. The gate current of a JFET doubles every 10°C resulting in a similar increase in input bias current over temperature.Special care should be given to the PC board layout to minimize leakage currents between PCB traces. Improper layout and board handling generates leakage current that exceeds the bias current of the AD8610/AD8620.FREQUENCY – kHz35050100150200250300138136120128126124122132130134C S – d BFigure 2.AD8620 Channel Separation GraphPower ConsumptionA major advantage of the AD8610/AD8620 in new designs is the saving of power. Lower power consumption of the AD8610makes it much more attractive for portable instrumentation and for high-density systems, simplifying thermal management, and reducing power supply performance requirements. Compare the power consumption of the AD8610/AD8620 versus the OPA627in Figure 3.TEMPERA TURE – ؇C8765432S U P P L Y C U R R E N T – m AFigure 3.Supply Current vs. TemperatureREV. D–10–AD8610/AD8620Driving Large Capacitive LoadsThe AD8610 has excellent capacitive load driving capability and can safely drive up to 10 nF when operating with ±5 V supply.Figures 4 and 5 compare the AD8610/AD8620 against the OPA627in the noninverting gain configuration driving a 10 k Ω resistor and 10,000 pF capacitor placed in parallel on its output, with a square wave input set to a frequency of 200 kHz. The AD8610 has much less ringing than the OPA627 with heavy capacitive loads.TIME – 2␮s/DIVV O L T A G E – 20m V /D IVFigure 4.OPA627 Driving C L = 10,000 pFTIME – 2␮s/DIVV O L T A G E – 20m V /D IVFigure 5.AD8610/AD8620 Driving C L = 10,000 pFThe AD8610/AD8620 can drive much larger capacitances without any external compensation. Although the AD8610/AD8620 is stable with very large capacitive loads, remember that this capacitive loading will limit the bandwidth of the amplifier. Heavy capacitive loads will also increase the amount of overshoot and ringing at the output. Figures 7 and 8 show the AD8610/AD8620 and the OPA627in a noninverting gain of +2 driving 2 µF of capacitance load. The ringing on the OPA627 is much larger in magnitude and continues more than 10 times longer than the AD8610.2␮FFigure 6.Capacitive Load Drive Test CircuitTIME – 20␮s/DIVV O L T A G E – 50m V /D I VFigure 7.OPA627 Capacitive Load Drive, A V = +2TIME – 20␮s/DIVV O L T A G E – 50m V /D I VFigure 8.AD8610/AD8620 Capacitive Load Drive, A V = +2Slew Rate (Unity Gain Inverting vs. Noninverting)Amplifiers generally have a faster slew rate in an inverting unity gain configuration due to the absence of the differential input capacitance. Figures 9 through 12 show the performance of the AD8610 configured in a gain of –1 compared to the OPA627.The AD8610 slew rate is more symmetrical, and both the positive and negative transitions are much cleaner than in the OPA627.REV. D AD8610/AD8620–11–TIME – 400ns/DIVV O L T A G E – 5V /D I VFigure 9.(+SR) of AD8610/AD8620 in Unity Gain of –1TIME – 400ns/DIVV O L T A G E – 5V /D I VFigure 10.(+SR) of OPA627 in Unity Gain of –1TIME – 400ns/DIVV O L T A G E – 5V /D I VFigure 11.(–SR) of AD8610/AD8620 in Unity Gain of –1TIME – 400ns/DIVV O L T A G E – 5V /D IVFigure 12.(–SR) of OPA627 in Unity Gain of –1The AD8610 has a very fast slew rate of 60 V/µs even when config-ured in a noninverting gain of +1. This is the toughest condition to impose on any amplifier since the input common-mode capacitance of the amplifier generally makes its SR appear worse. The slew rate of an amplifier varies according to the voltage difference between its two inputs. To observe the maximum SR as specified in the AD8610 data sheet, a difference voltage of about 2 V between the inputs must be ensured. This will be required for virtually any JFET op amp so that one side of the op amp input circuit is com-pletely off, maximizing the current available to charge and discharge the internal compensation capacitance. Lower differential drive voltages will produce lower slew rate readings. A JFET-input op amp with a slew rate of 60 V/µs at unity gain with V IN = 10 V might slew at 20 V/µs if it is operated at a gain of +100 with V IN = 100mV.The slew rate of the AD8610/AD8620 is double that of the OPA627when configured in a unity gain of +1 (see Figures 13 and 14).TIME – 400ns/DIVV O L T A G E – 5V /D I VFigure 13.(+SR) of AD8610/AD8620 in Unity Gain of +1REV. D–12–AD8610/AD8620diodes greatly interfere with many application circuits such as precision rectifiers and comparators. The AD8610 is free from these limitations.+13V 14VFigure 16.Unity Gain FollowerNo Phase ReversalMany amplifiers misbehave when one or both of the inputs are forced beyond the input common-mode voltage range. Phase reversal is typified by the transfer function of the amplifier,effectively reversing its transfer polarity. In some cases, this can cause lockup and even equipment damage in servo systems, and may cause permanent damage or nonrecoverable parameter shifts to the amplifier itself. Many amplifiers feature compensation circuitry to combat these effects, but some are only effective for the inverting input. The AD8610/AD8620 is designed to prevent phase reversal when one or both inputs are forced beyond their input common-mode voltage range.TIME – 400␮s/DIVV O L T A G E– 5V /D I VFigure 17.No Phase ReversalTHD Readings vs. Common-Mode VoltageTotal harmonic distortion of the AD8610/AD8620 is well below 0.0006% with any load down to 600 Ω. The AD8610/AD8620outperforms the OPA627 for distortion, especially at frequen-cies above 20 kHz.FREQUENCY – HzT H D +N – %Figure 18.AD8610 vs. OPA627 THD + Noise @ V CM= 0 VTIME – 400ns/DIVV O L T A G E – 5V /D I VFigure 14.(+SR) of OPA627 in Unity Gain of +1The slew rate of an amplifier determines the maximum frequency at which it can respond to a large signal input. This frequency (known as full-power bandwidth, or FPBW) can be calculated from the equation:FPBW SRV PEAK =×()2πfor a given distortion (e.g., 1%).V O L T A G E – 10V /D I VTIME – 400ns/DIVFigure 15.AD8610 FPBWInput Overvoltage ProtectionWhen the input of an amplifier is driven below V EE or above V CC by more than one V BE , large currents will flow from the substrate through the negative supply (V–) or the positive supply (V+),respectively, to the input pins, which can destroy the device. If the input source can deliver larger currents than the maximum forward current of the diode (>5 mA), a series resistor can be added to protect the inputs. With its very low input bias and offset current, a large series resistor can be placed in front of the AD8610 inputs to limit current to below damaging levels. Series resistance of 10 k Ωwill generate less than 25 µV of offset. This 10 k Ω will allow input voltages more than 5 V beyond either power supply. Thermal noise generated by the resistor will add 7.5 nV/√Hz to the noise of the AD8610. For the AD8610/AD8620, differential voltages equal to the supply voltage will not cause any problem (see Figure 15).In this context, it should also be noted that the high breakdown voltage of the input FETs eliminates the need to include clamp diodes between the inputs of the amplifier, a practice that is mandatory on many precision op amps. Unfortunately, clampREV. D AD8610/AD8620–13–FREQUENCY – HzT H D + N – %Figure 19.THD + Noise vs. FrequencyNoise vs. Common-Mode VoltageAD8610 noise density varies only 10% over the input range as shown in Table I.Table I.Noise vs. Common-Mode VoltageV CM at F = 1 kHz (V)Noise Reading (nV/√Hz )–107.21–5 6.890 6.73+5 6.41+107.21Settling TimeThe AD8610 has a very fast settling time, even to a very tight error band, as can be seen from Figure 20. The AD8610 is configured in an inverting gain of +1 with 2 k Ω input and feedback resistors.The output is monitored with a 10×, 10 M, 11.2 pF scope probe.ERROR BAND – %1.2k0.001100.01S E T T L I N G T I M E – n s0.118004001.0k600200Figure 20.AD8610 Settling Time vs. Error BandERROR BAND – %1.2k1.0k 0S E T T L I N G T I M E – n s800600200400Figure 21.OPA627 Settling Time vs. Error BandThe AD8610/AD8620 maintains this fast settling when loaded with large capacitive loads as shown in Figure 22.C L – pF02000500S E T T L I N G T I M E – ␮s100015003.02.00.01.02.51.50.5Figure 22.AD8610 Settling Time vs. Load CapacitanceC L – pF02000500S E T T L I N G T I M E – ␮s10001500Figure 23.OPA627 Settling Time vs. Load Capacitance Output Current CapabilityThe AD8610 can drive very heavy loads due to its high output current. It is capable of sourcing or sinking 45 mA at ±10 V output.The short circuit current is quite high and the part is capable of sinking about 95 mA and sourcing over 60 mA while operating withREV. D–14–AD8610/AD8620supplies of ±5 V. Figures 24 and 25 compare the load current versus output voltage of AD8610/AD8620 and OPA627.LOAD CURRENT – A100.10.000011D E L T A F R O M R E S P E C T I V E R A I L – V10.00010.0010.010.1Figure 24.AD8610 Dropout from ±13 V vs. Load CurrentLOAD CURRENT – A100.10.000011D E L T A F R O M R E S P E C T I V E R A I L – V10.00010.0010.010.1Figure 25.OPA627 Dropout from ±15 V vs. Load CurrentAlthough operating conditions imposed on the AD8610 (±13 V)are less favorable than the OPA627 (±15 V), it can be seen that the AD8610 has much better drive capability (lower headroom to the supply) for a given load current.Operating with Supplies Greater than ±13 VThe AD8610 maximum operating voltage is specified at ±13 V.When ±13 V is not readily available, an inexpensive LDO can provide ±12 V from a nominal ±15 V supply.Input Offset Voltage AdjustmentOffset of AD8610 is very small and normally does not require additional offset adjustment. However, the offset adjust pins can be used as shown in Figure 26 to further reduce the dc offset. By using resistors in the range of 50 k Ω, offset trim range is ±3.3 mV.+V OUTSFigure 26.Offset Voltage Nulling CircuitProgrammable Gain Amplifier (PGA)The combination of low noise, low input bias current, low input offset voltage, and low temperature drift make the AD8610 a perfect solution for programmable gain amplifiers. PGAs are often used immediately after sensors to increase the dynamic range of the measurement circuit. Historically, the large ON resistance of switches, combined with the large I B currents of amplifiers,created a large dc offset in PGAs. Recent and improved monolithic switches and amplifiers completely remove these problems. A PGA discrete circuit is shown in Figure 27. In Figure 27, when the 10 pA bias current of the AD8610 is dropped across the (<5 Ω) R ON of the switch, it results in a negligible offset error.When high precision resistors are used, as in the circuit of Figure 27,the error introduced by the PGA is within the 1/2 LSB requirement for a 16-bit system.Figure 27.High Precision PGA1. Room temperature error calculation due to R ON and I B :∆Ω∆∆V I R Total Offset Offset V Total Offset Offset Trimmed V Total Offset OS B ON OSOS =×=×==+=+=+≅25105105pA pV () (_) V pV V AD8610AD8610µµ2. Full temperature error calculation due to R ON and I B :∆ΩV I R OS B ON (C)(C)(C)pA .nV @@@85858525015375°=°×°=×=3. Temperature coefficient of switch and AD8610/AD8620combined is essentially the same as the T C V OS of the AD8610: ∆∆∆∆∆∆∆∆V T total V T V T I R V T total OS OS OS B ON OS /()/()/()/().V/C .nV/C .V/C =+×=°+°≅°AD86100500605µµ。

AD8326ARP-REEL资料

High Output Power Programmable CATV Line Driver AD8326
FUNCTIONAL BLOCK DIAGRAM
VCC (7 PINS) BYP
AD8326
VIN+ DIFF OR SINGLE INPUT AMP VOUT+ VERNIER
ATTENUATION CORE
1 dB Compression Point Differential Output Impedance OVERALL PERFORMANCE Worst Harmonic Distortion
Max Gain, f = 10 MHz Transmit Enable and Transmit Disable Mode f = 14 MHz, VOUT = 67 dBmV @ Max Gain f = 21 MHz, VOUT = 67 dBmV @ Max Gain f = 42 MHz, VOUT = 67 dBmV @ Max Gain f = 65 MHz, VOUT = 67 dBmV @ Max Gain 16 QAM, VOUT = 67 dBmV Adj Ch Wid = Tr Ch Wid = 160 KSYM/SEC Min to Max Gain Max Gain, VIN = 0 V to 0.25 V p-p Min Gain, TXEN = 0, 65 MHz, V IN = 0.25 V p-p Max Gain, TXEN = 0, 42 MHz, V IN = 0.25 V p-p Max Gain, TXEN = 0, 65 MHz, V IN = 0.25 V p-p All Gains, SLEEP, 65 MHz, V IN = 0.25 V p-p

AD648KR-REEL7中文资料

元器ormance 400 ␮A max Quiescent Current 10 pA max Bias Current, Warmed Up (AD648C) 300 ␮V max Offset Voltage (AD648C) 3 ␮V/؇ C max Drift (AD648C) 2 ␮V p-p Noise, 0.1 Hz to 10 Hz AC Performance 1.8 V/␮ s Slew Rate 1 MHz Unity Gain Bandwidth Available in Plastic Mini-DIP, Cerdip, Plastic SOIC and Hermetic Metal Can Packages MIL-STD-883B Parts Available Surface Mount (SOIC) Package Available in Tape and Reel in Accordance with EIA-481A Standard Single Version: AD548 PRODUCT DESCRIPTION
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

AD9661AKR-REEL资料

VREF –50 25 0.1 –10 130 –32 0.95 120 2.50 2 1.0
VREF + 1.6 +50 1.6 0 +32 1.05
V µA MHz V µA MHz mV V/V mA V mA µA MHz ns ns ns ns ns ns nA V pF V V V V µA mA V mV/°C mA mA/mA V Ω V mA
CHOLD = 33 pF, RF = 1 kΩ, CF = 2 pF
VOUT = 2.5 V PULSE = LOW, DISABLE = LOW PULSE = LOW, DISABLE = HIGH Output Current –3 dB
5.25 5.0 1.0
2.9 3.2
200 3.9 3.7 1.5 1.5 13 3
LASER DIODE
OUTPUT
8
AD9661A
ANALOG POWER MONITOR VREF
IMONITOR
1:1
SENSE IN IMONITOR 1.0V
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703

AD7874ARZ-REEL中文资料

One Technology Way, P.O. Box 9106, Norwood, M329-4700 Fax: 617/326-8703
元器件交易网
AD7874–SPECIFICATIONS external. All specifications T
Parameter SAMPLE-AND-HOLD Acquisition Time2 to 0.01% Droop Rate2, 3 –3 dB Small Signal Bandwidth3 Aperture Delay2 Aperture Jitter2, 3 Aperture Delay Matching2 SAMPLE-AND-HOLD AND ADC DYNAMIC PERFORMANCE Signal-to-Noise Ratio Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion 2nd Order Terms 3rd Order Terms Channel-to-Channel Isolation2 DC ACCURACY Resolution Relative Accuracy Differential Nonlinearity Positive Full-Scale Error4 Negative Full-Scale Error4 Full-Scale Error Match Bipolar Zero Error Bipolar Zero Error Match ANALOG INPUTS Input Voltage Range Input Current REFERENCE OUTPUTS REF OUT REF OUT Error @ +25°C TMIN to TMAX REF OUT Temperature Coefficient Reference Load Change REFERENCE INPUT Input Voltage Range Input Current Input Capacitance3 LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN3 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL DB0–DB11 Floating-State Leakage Current Floating-State Output Capacitance Output Coding POWER REQUIREMENTS VDD VSS IDD ISS Power Dissipation A Version B Version S Version Units 2 1 500 0 40 200 4 2 1 500 0 40 200 4 2 2 500 0 40 200 4 µs max mV/ms max kHz typ ns min ns max ps typ ns max

AD7417ARU-REEL中文资料

REV.GAD7416/AD7417/AD7418 10-Bit Digital Temperature Sensor (AD7416) and Four Single-Channel ADCs (AD7417/AD7418)Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 Fax: 781/326-8703© 2004 Analog Devices, Inc. All rights reserved.FEATURES10-Bit ADC with 15 ␮s and 30 ␮s Conversion Times Single and Four Single-Ended Analog Input Channels On-Chip Temperature Sensor: –40؇C to +125؇COn-Chip Track-and-HoldOvertemperature IndicatorAutomatic Power-Down at the End of a Conversion Wide Operating Supply Range: 2.7 V to 5.5 VI2C® Compatible Serial InterfaceSelectable Serial Bus Address Allows Connection of up to Eight AD7416/AD7417s to a Single BusAD7416 Is a Superior Replacement for LM75 APPLICATIONSData Acquisition with Ambient Temperature Monitoring Industrial Process ControlAutomotiveBattery-Charging ApplicationsPersonal ComputersFUNCTIONAL BLOCK DIAGRAMSV DDOTIA0A1A2VOTISCLSDAA2A1A0CONVSTA IN1A IN2A IN3A IN4NC NC GNDNC = NO CONNECTVSCLSDA A IN1REFCONVSTGENERAL DESCRIPTIONThe AD7417 and AD7418 are 10-bit, 4-channel and single-channel ADCs with an on-chip temperature sensor that can operate from a single 2.7 V to 5.5 V power supply. The devices contain a 15 µs successive approximation converter, a 5-channel multiplexer, a temperature sensor, a clock oscilla-tor, a track-and-hold, and a reference (2.5 V). The AD7416 is a temperature-monitoring only device in an 8-lead package. The temperature sensor on the parts can be accessed via multi-plexer Channel 0. When Channel 0 is selected and a conversion is initiated, the resulting ADC code at the end of the conversion gives a measurement of the ambient temperature (±1°C @ 25°C). On-chip registers can be programmed with high and low tem-perature limits, and an open-drain overtemperature indicator (OTI) output is provided, which becomes active when a pro-grammed limit is exceeded.A configuration register allows programming of the sense of the OTI output (active high or active low) and its operating mode (comparator or interrupt). A programmable fault queue counter allows the number of out-of-limit measurements that must occur before triggering the OTI output to be set to prevent spurious triggering of the OTI output in noisy environments.(continued on page 7)AD7416/AD7417/AD7418AD7417/AD7418–SPECIFICATIONS(V DD = 2.7 V to 5.5 V, GND = 0 V, REF IN = 2.5 V, unless otherwise noted.) Parameter A Version B Version1Unit Test Conditions/CommentsDC ACCURACY Any Channel.Resolution1010BitsMinimum Resolution for Which NoMissing Codes Are Guaranteed1010BitsRelative Accuracy2±1±1LSB max This Specification Is Typical for V DD of3.6 V to 5.5 V.Differential Nonlinearity2±1±1LSB max This Specification Is Typical for V DD of3.6 V to 5.5 V.Gain Error2±3±3LSB max External Reference.±10±10LSB max Internal Reference.Gain Error Match2±0.6±0.6LSB max AD7417 Only.Offset Error2±4±4LSB maxOffset Error Match±0.7±0.7LSB max AD7417 Only.ANALOG INPUTSInput Voltage Range V REF V REF V max00V minInput Leakage Current3±1±1µA maxInput Capacitance1010pF maxTEMPERATURE SENSOR1Measurement ErrorAmbient Temperature 25°C±2±1°C maxT MIN to T MAX±3±2°C maxTemperature Resolution1/41/4°C/LSBCONVERSION RATETrack-and-Hold Acquisition Time4400400ns max Source Impedance < 10 Ω.Conversion TimeTemperature Sensor3030µs max Typically 27 µs.Channels 1 to 41515µs max Typically 10 µs.REFERENCE INPUT5, 6REF IN Input Voltage Range6 2.625 2.625V max 2.5 V + 5%.2.375 2.375V min 2.5 V – 5%.Input Impedance4040kΩ minInput Capacitance1010pF maxON-CHIP REFERENCE Nominal 2.5 V.Reference Error6±25±25mV maxTemperature Coefficient68080ppm/°C typDIGITAL INPUTSInput High Voltage, V IH V DD× 0.7V DD× 0.7V minInput Low Voltage, V IL V DD× 0.3V DD× 0.3V maxInput Leakage Current11µA maxDIGITAL OUTPUTSOutput Low Voltage, V OL0.40.4V max I OL = 3 mA.Output High Current11µA max V OH = 5 V.POWER REQUIREMENTSV DD 5.5 5.5V max For Specified Performance.2.7 2.7V minI DD Logic Inputs = 0 V or V DD.Normal Operation600600µA maxPower-Down11µA max50 nA Typically.Auto Power-Down Mode V DD = 3 V. See Operating Modes.10 SPS Throughput Rate66µW typ1 kSPS Throughput Rate6060µW typ10 kSPS Throughput Rate600600µW typPower-Down33µW max Typically 0.15 µW.–2–REV. GREV. G AD7416/AD7417/AD7418–3–NOTES 1B Version applies to AD7417 only with temperature range of –40°C to +85°C. A Version temperature range is –40°C to +125°C. For V DD = 2.7 V, T A = 85°C max and temperature sensor measurement error = ±3°C.2See Terminology.3Refers to the input current when the part is not converting. Primarily due to reverse leakage current in the ESD protection diodes.4Sample tested during initial release and after any redesign or process change that may affect this parameter.5On-chip reference shuts down when external reference is applied.6The accuracy of the temperature sensor is affected by reference tolerance. The relationship between the two is explained in the Temperature Sensor section.Specifications subject to change without notice.AD7416–SPECIFICATIONS(V DD = 2.7 V to 5.5 V, GND = 0 V, REF IN = 2.5 V, unless otherwise noted.)ParameterMinTypMax Unit Test Conditions/Comments TEMPERATURE SENSOR AND ADC Accuracy±2.0°C T A = –25°C to +100°C (V DD = 3 V min)1±3.0°C T A = –40°C to +125°C (V DD = 3 V min)1Resolution10Bits Temperature Conversion Time 40µs Update Rate, t R 400µs OTI Delay 1 × t R6 × t R ms Depends on Fault Queue Setting Supply Current1.0mA I 2C Active 350600µA I 2C Inactive 0.2 1.5µA Shutdown ModeT OTI Default Temperature 80°C T HYST Default Temperature 75°C DIGITAL INPUTSInput High Voltage, V IH V DD × 0.7V DD + 0.5V Input Low Voltage, V IL –0.3V DD × 0.3V Input High Current, I IH +0.005+1.0µA V IN = 5 V Input Low Current, I IL –0.005–1.0µA V IN = 0 VInput Capacitance, C IN 20pF All Digital Inputs DIGITAL OUTPUTSOutput Low Voltage, V OL 0.4V I OL = 3 mA Output High Current 1µA V OH = 5 VOutput Fall Time, t f250ns C L = 400 pF, I O = 3 mA OS Output Low Voltage, V OL0.8V I OUT = 4 mAAC ELECTRICAL CHARACTERISTICS 2AD7416/AD7417/AD7418Serial Clock Period, t 12.5µs See Figure 1Data In Setup Time to SCL High, t 250ns See Figure 1Data Out Stable after SCL Low, t 30ns See Figure 1SDA Low Setup Time to SCL Low (Start Condition), t 450nsSee Figure 1SDA High Hold Time after SCL High (Stop Condition), t 550ns See Figure 1SDA and SCL Fall Time, t 6300nsSee Figure 1NOTES 1For V DD = 2.7 V to 3 V, T A max = 85°C and accuracy = ±3°C.2Sample tested during initial release and after any redesign or process change that may affect this parameter.Specifications subject to change without notice.SCLSDA DATA INSDADATA OUTFigure 1. Diagram for Serial Bus TimingREV. G–4–AD7416/AD7417/AD7418AD7417 PIN FUNCTION DESCRIPTIONPin No.Mnemonic Description1, 16NC No Connection. Do not connect anything to this pin.2SDA Digital I/O. Serial bus bidirectional data. Push-pull output.3SCL Digital Input. Serial bus clock.4OTIThis is a logic output. The overtemperature indicator (OTI) is set if the result of a conversion on Channel 0 (temperature sensor) is greater than an 8-bit word in the overtemperature register (OTR).The signal is reset at the end of a serial read operation. Open-drain output.5REF INReference Input. An external 2.5 V reference can be connected to the AD7417 at this pin. To enable the on-chip reference, the REFIN pin should be tied to GND. If an external reference is connected to the AD7417, the internal reference will shut down.6GND Ground reference for track-and-hold, comparator and capacitor DAC, and digital circuitry.7–10A IN1 to A IN4Analog Input Channels. The AD7417 has four analog input channels. The input channels are single-ended with respect to GND. The input channels can convert voltage signals in the range 0 V to V REF . A chan-nel is selected by writing to the configuration register of the AD7417. (See Control Byte section.)11A2Digital Input. The highest programmable bit of the serial bus address.12A1Digital Input. The middle programmable bit of the serial bus address.13A0Digital Input. The lowest programmable bit of the serial bus address.14V DD Positive Supply Voltage, 2.7 V to 5.5 V.15CONVSTLogic Input Signal. Convert start signal. The rising edge of this signal fully powers up the part. The power-up time for the part is 4 µs. If the CONVST pulse is greater than 4 µs, the falling edge of CONVST places the track-and-hold mode into hold mode and initiates a conversion. If the pulse is less than 4 µs,an internal timer ensures that the track-and-hold does not go into hold and conversion is not initiated until the power-up time has elapsed. The track-and-hold goes into track mode again at the end of con-version. (See Operating Mode section.)AD7417 PIN CONFIGURATIONSOIC/TSSOPNC SDA SCL OTI REF IN GND A A V DDA IN4A IN3REV. G AD7416/AD7417/AD7418–5–AD7416 PIN FUNCTION DESCRIPTIONPin No.Mnemonic Description1SDA Digital I/O. Serial bus bidirectional data. Push-pull output.2SCL Digital Input. Serial bus clock.3OTIThis is a logic output. The OTI is set if the result of a conversion on Channel 0 (temperature sensor) is greater that an 8-bit word in the OTR. The signal is reset at the end of a serial read operation. Open-drain output.4GND Ground reference for track-and-hold, comparator and capacitor DAC, and digital circuitry.5A2Digital Input. The highest programmable bit of the serial bus address.6A1Digital Input. The middle programmable bit of the serial bus address.7A0Digital Input. The lowest programmable bit of the serial bus address.8V DDPositive Supply Voltage, 2.7 V to 5.5 V.AD7418 PIN FUNCTION DESCRIPTIONPin No.Mnemonic Description1SDA Digital I/O. Serial bus bidirectional data. Push-pull output.2SCL Digital Input. Serial bus clock.3OTIThis is a logic output. The OTI is set if the result of a conversion on Channel 0 (temperature sensor) is greater that an 8-bit word in the OTR. The signal is reset at the end of a serial read operation. Open-drain output.4GND Ground reference for track-and-hold, comparator and capacitor DAC, and digital circuitry.5A INAnalog Input Channel. The input channel is single-ended with respect to GND. The input channel can convert voltage signals in the range 0 V to V REF . The analog input channel is selected by writing to the configuration register of the AD7418 and choosing Channel 4. (See Control Byte section.)6REF INReference Input. An external 2.5 V reference can be connected to the AD7418 at this pin. To enable the on-chip reference, the REF IN pin should be tied to GND. If an external reference is connected to the AD7418, the internal reference will shut down.7V DD Positive Supply Voltage, 2.7 V to 5.5 V.8CONVSTLogic Input Signal. Convert start signal. The rising edge of this signal fully powers up the part. The power-up time for the part is 4 µs. If the CONVST pulse is greater than 4 µs, the falling edge ofCONVST places the track-and-hold mode into hold mode and initiates a conversion. If the pulse is less than 4 µs, an internal timer ensures that the track-and-hold does not go into hold and conversion is not initiated until the power-up time has elapsed. The track-and-hold goes into track mode again at the end of conversion. (See Operating Mode section.)AD7416 PIN CONFIGURATIONSOIC/MSOPV DD A0A2A1AD7418 PIN CONFIGURATIONSOIC/MSOPV DD REF INA INAD7416/AD7417/AD7418ABSOLUTE MAXIMUM RATINGS1(T A = 25°C, unless otherwise noted.)V DD to AGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3V to +7V V DD to DGND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3V to +7VAnalog Input Voltage to AGNDA IN1 to A IN4 . . . . . . . . . . . . . . . . . . .–0.3 V to V DD + 0.3 V Reference Input Voltage to AGND2 . .–0.3 V to V DD + 0.3VDigital Input Voltage to DGND . . . . .–0.3 V to V DD + 0.3 VDigital Output Voltage to DGND . . . .–0.3 V to V DD + 0.3 V Operating Temperature RangeA Version . . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +125°CB Version . . . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C Storage Temperature Range . . . . . . . . . . . .–65°C to +150°CJunction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°CTSSOP, Power Dissipation . . . . . . . . . . . . . . . . . . . . 450 mW ␪JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 120°C/W Lead Temperature, Soldering . . . . . . . . . . . . . . . . . .260°CVapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .220°C 16-Lead SOIC Package, Power Dissipation . . . . . . . . 450 mW ␪JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 100°C/W Lead Temperature, SolderingVapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°CInfrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C 8-Lead SOIC Package, Power Dissipation . . . . . . . . . 450 mW ␪JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 157°C/W Lead Temperature, SolderingVapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C MSOP Package, Power Dissipation . . . . . . . . . . . . . . 450 mW ␪JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206°C/W Lead Temperature, SolderingVapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C NOTES1Stresses above those listed under Absolute Maximum Ratings may cause perma-nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.2If the reference input voltage is likely to exceed VDDby more than 0.3 V (e.g., during power-up) and the reference is capable of supplying 30 mA or more, it is recommended to use a clamping diode between the REF IN pin and V DD pin. The diagram below shows how the diode should be connected.CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readilyaccumulate on the human body and test equipment and can discharge without detection. Although theAD7416/AD7417/AD7418 features proprietary ESD protection circuitry, permanent damage mayoccur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautionsare recommended to avoid performance degradation or loss of functionality.REV. G–6–REV. G AD7416/AD7417/AD7418–7–ORDERING GUIDETemperature Temperature Package Package ModelRangeError DescriptionBrandingOption AD7416ACHIPS DieAD7416AR–40°C to +125°C ±2°C 8-Lead Standard Small Outline Package (SOIC)RN-8AD7416AR-REEL –40°C to +125°C ±2°C 8-Lead Standard Small Outline Package (SOIC)RN-8AD7416AR-REEL7–40°C to +125°C ±2°C 8-Lead Standard Small Outline Package (SOIC)RN-8AD7416ARZ *–40°C to +125°C ±2°C 8-Lead Standard Small Outline Package (SOIC)RN-8AD7416ARZ-REEL *–40°C to +125°C ±2°C 8-Lead Standard Small Outline Package (SOIC)RN-8AD7416ARZ-REEL7*–40°C to +125°C ±2°C 8-Lead Standard Small Outline Package (SOIC)RN-8AD7416ARM–40°C to +125°C ±2°C 8-Lead Micro Small Outline Package (MSOP)C6A RM-8AD7416ARM-REEL –40°C to +125°C ±2°C 8-Lead Micro Small Outline Package (MSOP)C6A RM-8AD7416ARM-REEL7–40°C to +125°C ±2°C 8-Lead Micro Small Outline Package (MSOP)C6A RM-8AD7416ARMZ *–40°C to +125°C ±2°C 8-Lead Micro Small Outline Package (MSOP)C6A RM-8AD7416ARMZ-REEL *–40°C to +125°C ±2°C 8-Lead Micro Small Outline Package (MSOP)C6A RM-8AD7416ARMZ-REEL7*–40°C to +125°C ±2°C 8-Lead Micro Small Outline Package (MSOP)C6ARM-8AD7417ACHIPS DieAD7417AR–40°C to +125°C ±2°C 16-Lead Standard Small Outline Package (SOIC)RN-16AD7417AR-REEL –40°C to +125°C ±2°C 16-Lead Standard Small Outline Package (SOIC)RN-16AD7417AR-REEL7–40°C to +125°C ±2°C 16-Lead Standard Small Outline Package (SOIC)RN-16AD7417ARU–40°C to +125°C ±2°C 16-Lead Thin Shrink Small Outline Package (TSSOP)RU-16AD7417ARU-REEL –40°C to +125°C ±2°C 16-Lead Thin Shrink Small Outline Package (TSSOP)RU-16AD7417ARU-REEL7–40°C to +125°C ±2°C 16-Lead Thin Shrink Small Outline Package (TSSOP)RU-16AD7417BR–40°C to +85°C ±1°C 16-Lead Standard Small Outline Package (SOIC)RN-16AD7417BR-REEL –40°C to +85°C ±1°C 16-Lead Standard Small Outline Package (SOIC)RN-16AD7417BR-REEL7–40°C to +85°C ±1°C 16-Lead Standard Small Outline Package (SOIC)RN-16AD7418ACHIPS DieAD7418AR–40°C to +125°C ±2°C 8-Lead Standard Small Outline Package (SOIC)RN-8AD7418AR-REEL –40°C to +125°C ±2°C 8-Lead Standard Small Outline Package (SOIC)RN-8AD7418AR-REEL7–40°C to +125°C ±2°C 8-Lead Standard Small Outline Package (SOIC)RN-8AD7418ARM–40°C to +125°C ±2°C 8-Lead Micro Small Outline Package (MSOP)C7A RM-8AD7418ARM-REEL –40°C to +125°C ±2°C 8-Lead Micro Small Outline Package (MSOP)C7A RM-8AD7418ARM-REEL7–40°C to +125°C ±2°C 8-Lead Micro Small Outline Package (MSOP)C7ARM-8AD7418ARUZ *–40°C to +125°C ±2°C 16-Lead Thin Shrink Small Outline Package (TSSOP)RU-16AD7418ARUZ-REEL *–40°C to +125°C ±2°C 16-Lead Thin Shrink Small Outline Package (TSSOP)RU-16AD7418ARUZ-REEL7*–40°C to +125°C±2°C16-Lead Thin Shrink Small Outline Package (TSSOP)RU-16EVAL-AD7416/AD7417/Evaluation BoardAD7418EB*Pb-Free PartAD7416/AD7417/AD7418(continued from page 1)An I2C compatible serial interface allows the AD7416/AD7417/ AD7418 registers to be written to and read back. The three LSBs of the AD7416/AD7417’s serial bus address can be selected, which allows up to eight AD7416/AD7417s to be connected to a single bus.The AD7417 is available in a narrow body, 0.15'', 16-lead, small outline IC (SOIC) and in a 16-lead, thin shrink, small outline package (TSSOP). The AD7416 and AD7418 are available in 8-lead SOIC and MSOP packages.PRODUCT HIGHLIGHTS1.The AD7416/AD7417/AD7418 have an on-chip temperaturesensor that allows an accurate measurement of the ambient temperature (±1°C @ 25°C, ±2°C overtemperature) to be made. The measurable temperature range is –40°C to +125°C.An overtemperature indicator is implemented by carrying out a digital comparison of the ADC code for Channel 0 (temperature sensor) with the contents of the on-chip over-temperature register.2.The AD7417 offers a space-saving 10-bit A/D solution withfour external voltage input channels, an on-chip temperature sensor, an on-chip reference, and clock oscillator.3.The automatic power-down feature enables the AD7416/AD7417/AD7418 to achieve superior power performance. At slower throughput rates, the part can be programmed to operate in a low power shutdown mode, allowing further savings in power consumption.TERMINOLOGYRelative AccuracyRelative accuracy or endpoint nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function.Differential NonlinearityThis is the difference between the measured and the ideal 1LSB change between any two adjacent codes in the ADC.Offset ErrorThis is the deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, i.e., GND + 1 LSB.Offset Error MatchThis is the difference in offset error between any two channels. Gain ErrorThis is the deviation of the last code transition (1111 . . . 110) to (1111 . . . 111) from the ideal, i.e., VREF – 1 LSB, after the offset error has been adjusted out.Gain Error MatchThis is the difference in gain error between any two channels. Track-and-Hold Acquisition TimeTrack-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1/2 LSB, after the end of conversion (the point at which the track-and-hold returns to track mode). It also applies tosituations where a change in the selected input channel takes place or where there is a step input change on the input voltage applied to the selected A IN input of the AD7417 or AD7418. It means that the user must wait for the duration of the track-and-hold acquisition time after the end of conversion or after a channel change/step input change to A IN before starting another conver-sion, to ensure that the part operates to specification.CIRCUIT INFORMATIONThe AD7417 and AD7418 are single-channel and four-channel,15 µs conversion time, 10-bit ADCs with on-chip temperaturesensor, reference, and serial interface logic functions on a single chip. The AD7416 has no analog input channel and is intended for temperature measurement only. The ADC section consists of a conventional successive approximation converter based around a capacitor DAC. The AD7416, AD7417, and AD7418 are capable of running on a 2.7 V to 5.5 V power supply, andthe AD7417 and AD7418 accept an analog input range of 0 V to +VREF. The on-chip temperature sensor allows an accurate measurement of the ambient device temperature to be made.The working measurement range of the temperature sensor is –40°C to +125°C. The parts require a 2.5 V reference that can be provided from the part’s own internal reference or from anexternal reference source.CONVERTER DETAILSConversion is initiated on the AD7417/AD7418 by pulsing the CONVST input. The conversion clock for the part is internally generated so no external clock is required except when reading from and writing to the serial port. The on-chip track-and-hold goes from track to hold mode and the conversion sequence isstarted on the falling edge of the CONVST signal. A conversion is also initiated in the automatic conversion mode every time a read or write operation to the AD7416/AD7417/AD7418 takes place. In this case, the internal clock oscillator (which runs the automatic conversion sequence) is restarted at the end of theread or write operation. The track-and-hold goes into holdapproximately 3 µs after the read or write operation is complete and a conversion is then initiated. The result of the conversion is available either 15 µs or 30 µs later, depending on whether an analog input channel or the temperature sensor is selected. The track-and-hold acquisition time of the AD7417/AD7418 is 400 ns.A temperature measurement is made by selecting the Channel 0of the on-chip mux and carrying out a conversion on this channel.A conversion on Channel 0 takes 30 µs to complete. Tempera-ture measurement is explained in the Temperature Measurement section of this data sheet.The on-chip reference is not available to the user, but REF INcan be overdriven by an external reference source (2.5 V only).All unused analog inputs should be tied to a voltage within the nominal analog input range to avoid noise pickup. For mini-mum power consumption, the unused analog inputs should be tied to GND.REV. G –8–REV. GAD7416/AD7417/AD7418–9–TYPICAL CONNECTION DIAGRAMFigure 2 shows a typical connection diagram for the ing the A0, A1, and A2 pins allows the user to select from up to eight AD7417s on the same serial bus, if desired. An external 2.5 V reference can be connected at the REF IN pin. If an exter-nal reference is used, a 10 µF capacitor should be connected between REF IN and GND. SDA and SCL form the 2-wire I 2C compatible interface. For applications where power consump-tion is of concern, the automatic power-down at the end of a conversion should be used to improve power performance. See Operating Modes section of this data sheet.OPTIONAL EXTERNAL REFERENCEFigure 2. Typical Connection DiagramANALOG INPUTSFigure 3 shows an equivalent circuit of the analog input struc-ture of the AD7417 and AD7418. The two diodes, D1 and D2,provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 200 mV. This will cause these diodes to become forward-biased and start conducting current into the substrate. The maximum current these diodes can conduct without causing irreversible damage to the part is 20 mA. The capacitor C2 in Figure 3 is typically about 4 pF and can prima-rily be attributed to pin capacitance. The resistor R1 is a lumped component made up of the on resistance of a multiplexer and a switch. This resistor is typically about 1 k Ω. The capacitor C1 is the ADC sampling capacitor and has a capacitance of 3 pF.A BALANCEFigure 3. Equivalent Analog Input CircuitON-CHIP REFERENCEThe AD7416/AD7417/AD7418 has an on-chip 1.2 V band gap reference that is gained up by a switched capacitor amplifier to give an output of 2.5 V. The amplifier is only powered up at the start of the conversion phase and is powered down at the end of the conversion. The on-chip reference is selected by connecting the REF IN pin to analog ground. This causes SW1 (see Figure 4)to open and the reference amplifier to power up during a conver-sion. Therefore, the on-chip reference is not available externally.An external 2.5 V reference can be connected to the REF IN pin.This has the effect of shutting down the on-chip reference circuitry.Figure 4. On-Chip ReferenceTEMPERATURE MEASUREMENTA common method of measuring temperature is to exploit thenegative temperature coefficient of a diode, or the base-emitter voltage of a transistor, operated at a constant current. Unfortu-nately, this technique requires calibration to null out the effect of the absolute value of V BE , which varies from device to device.The technique used in the AD7416/AD7417/AD7418 is to measure the current change in V BE when the device is operated at two different currents.This is given by∆V KT q n N BE =×()/1where:K is Boltzmann ’s constant.q is the charge on the electron (1.6 × 10-19 Coulombs).T is the absolute temperature in Kelvins.N is the ratio of the two currents.OUT ؉OUT ؊Figure 5. Temperature Measurement Technique。

AD8572AR-REEL7资料

Zero-Drift, Single-Supply, Rail-to-RailInput/Output Operational AmplifiersAD8571/AD8572/AD8574 Rev. BInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. O ne Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.FEATURESLow offset voltage: 1 μVInput offset drift: 0.005 μV/°CRail-to-rail input and output swing5 V/2.7 V single-supply operationHigh gain, CMRR, PSRR: 130 dBUltralow input bias current: 20 pALow supply current: 750 μA/op ampOverload recovery time: 50 μsNo external capacitors requiredAPPLICATIONSTemperature sensorsPressure sensorsPrecision current sensingStrain gage amplifiersMedical instrumentationThermocouple amplifiersGENERAL DESCRIPTIONThis family of amplifiers has ultralow offset, drift, and bias current. The AD8571, AD8572, and AD8574 are single, dual, and quad amplifiers, respectively, featuring rail-to-rail input and output swings. All are guaranteed to operate from 2.7 V to 5 V single supply.The AD857x family provides benefits previously found only in expensive auto-zeroing or chopper-stabilized amplifiers. Using Analog Devices, Inc. topology, these zero-drift amplifiers combine low cost with high accuracy. (No external capacitors are required.) Using a patented spread-spectrum auto-zero technique, the AD857x family eliminates the intermodulation effects from interaction of the chopping function with the signal frequency in ac applications.With an offset voltage of only 1 μV and drift of 0.005 μV/°C, the AD857x family is perfectly suited for applications where error sources cannot be tolerated. Position and pressure sensors, medical equipment, and strain gage amplifiers benefit greatly from nearly zero drift over their operating temperature range. Many more systems require the rail-to-rail input and output swings provided by the AD857x family.V+OUT ANCNC–IN A+IN AV–NC114-1NC = NO CONNECTNC–IN A+IN AV–114-4Figure 1. 8-Lead MSOP(RM Suffix)Figure 2. 8-Lead SOIC(R Suffix)–IN A+IN AV–OUT B–IN B+IN BOUT A V+114-2–IN A+IN AV–OUT B–IN B+IN BOUT A V+114-5 (RU Suffix)Figure 4. 8-Lead SOIC(R Suffix)OUT A–IN A+IN AV++IN B–IN BOUT B114-3OUT A–IN A+IN AV++IN B–IN BOUT B114-6Figure 5. 14-Lead TSSOP(RU Suffix)Figure 6. 14-Lead SOIC(R Suffix)The AD857x family is specified for the extended industrial/ automotive (−40°C to +125°C) temperature range. The AD8571 single amplifier is available in 8-lead MSOP and narrow 8-lead SOIC packages. The AD8572 dual amplifier is available in8-lead narrow SOIC and 8-lead TSSOP surface mount packages. The AD8574 quad amplifier is available in narrow 14-lead SOIC and 14-lead TSSOP packages.AD8571/AD8572/AD8574Rev. B | Page 2 of 24TABLE OF CONTENTSFeatures..............................................................................................1 Applications.......................................................................................1 General Description.........................................................................1 Pin Configurations...........................................................................1 Revision History...............................................................................2 Specifications.....................................................................................3 5 V Electrical Characteristics......................................................3 2.7 V Electrical Characteristics...................................................4 Absolute Maximum Ratings............................................................5 Thermal Characteristics..............................................................5 ESD Caution..................................................................................5 Typical Performance Characteristics.............................................6 Functional Description..................................................................14 Amplifier Architecture..............................................................14 Basic Auto-Zero Amplifier Theory..........................................14 Auto-Zero Phase.........................................................................14 Amplification Phase...................................................................15 High Gain, CMRR, PSRR..........................................................16 Maximizing Performance T hrough Proper Layout................16 1/f Noise Characteristics...........................................................17 Random Auto-Zero Correction Eliminates Intermodulation Distortion....................................................................................17 Broadband and External Resistor Noise Considerations..........18 Output Overdrive Recovery......................................................18 Input Overvoltage Protection...................................................18 Output Phase Reversal...............................................................18 Capacitive Load Drive...............................................................19 Power-Up Behavior....................................................................19 Applications.....................................................................................20 5 V Precision Strain Gage Circuit............................................20 3 V Instrumentation Amplifier................................................20 High Accuracy Thermocouple Amplifier...............................20 Precision Current Meter............................................................21 Precision Voltage Comparator..................................................21 Outline Dimensions.......................................................................22 Ordering Guide.. (23)REVISION HISTORY09/06—Rev. A to Rev. BUpdated Format..................................................................Universal Renumbered Figures..........................................................Universal Changes to Figure 50......................................................................14 Changes to Figure 51......................................................................15 Changes to Figure 66......................................................................21 Updated Outline Dimensions.......................................................22 Changes to Ordering Guide..........................................................23 07/03—Rev. 0 to Rev. ARenumbered Figures..........................................................Universal Changes to Ordering Guide.............................................................4 Change to Figure 15.......................................................................16 Updated Outline Dimensions. (19)10/99—Revision 0: Initial VersionAD8571/AD8572/AD8574Rev. B | Page 3 of 24SPECIFICATIONS5 V ELECTRICAL CHARACTERISTICSV S = 5 V , V CM = 2.5 V , V O = 2.5 V , T A = 25°C, unless otherwise noted. Table 1.Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V OS 1 5 μV −40°C ≤ T A ≤ +125°C 10 μV Input Bias Current I B 10 50 pA −40°C ≤ T A ≤ +125°C 1.0 1.5 nA Input Offset Current I OS 20 70 pA −40°C ≤ T A ≤ +125°C 150 200 pA Input Voltage Range 0 5 V Common-Mode Rejection Ratio CMRR V CM = 0 V to 5 V 120 140 dB −40°C ≤ T A ≤ +125°C 115 130 dBLarge Signal Voltage Gain 1A VO R L = 10 kΩ, V O = 0.3 V to 4.7 V 125 145 dB −40°C ≤ T A ≤ +125°C 120 135 dB Offset Voltage Drift ∆V OS /∆T −40°C ≤ T A ≤ +125°C 0.005 0.04 μV/°C OUTPUT CHARACTERISTICS Output Voltage High V OH R L = 100 kΩ to GND 4.99 4.998 V −40°C to +125°C 4.99 4.997 V R L = 10 kΩ to GND 4.95 4.98 V −40°C to +125°C 4.95 4.975 V Output Voltage Low V OL R L = 100 kΩ to V+ 1 10 mV −40°C to +125°C 2 10 mV R L = 10 kΩ to V+ 10 30 mV −40°C to +125°C 15 30 mV Short-Circuit Limit I SC ±25 ±50 mA −40°C to +125°C ±40 mA Output Current I O ±30 mA −40°C to +125°C ±15 mA POWER SUPPLY Power Supply Rejection Ratio PSRR V S = 2.7 V to 5.5 V 120 130 dB −40°C ≤ T A ≤ +125°C 115 130 dB Supply Current/Amplifier I SY V O = 0 V 850 975 μA −40°C ≤ T A ≤ +125°C 1000 1075 μA DYNAMIC PERFORMANCE Slew Rate SR R L = 10 kΩ 0.4 V/μs Overload Recovery Time 0.05 0.3 ms Gain Bandwidth Product GBP 1.5 MHz NOISE PERFORMANCE Voltage Noise e n p-p 0 Hz to 10 Hz 1.3 μV p-p e n p-p 0 Hz to 1 Hz 0.41 μV p-p Voltage Noise Density e n f = 1 kHz 51 nV/√Hz Current Noise Density i n f = 10 Hz 2 fA/√Hz1Gain testing is dependent upon test bandwidth.AD8571/AD8572/AD8574Rev. B | Page 4 of 242.7 V ELECTRICAL CHARACTERISTICS V S = 2.7 V , V CM = 1.35 V , V O = 1.35 V , T A = 25°C, unless otherwise noted.Table 2.Parameter Symbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage V OS 1 5 μV −40°C ≤ T A ≤ +125°C 10 μV Input Bias Current I B 10 50 pA −40°C ≤ T A ≤ +125°C 1.0 1.5 nA Input Offset Current I OS 10 50 pA −40°C ≤ T A ≤ +125°C 150 200 pA Input Voltage Range 0 2.7 V Common-Mode Rejection Ratio CMRR V CM = 0 V to 2.7 V 115 130 dB −40°C ≤ T A ≤ +125°C 110 130 dB Large Signal Voltage Gain 1A VO R L = 10 kΩ, V O = 0.3 V to 2.4 V 110 140 dB −40°C ≤ T A ≤ +125°C 105 130 dB Offset Voltage Drift ∆V OS /∆T −40°C ≤ T A ≤ +125°C 0.005 0.04 μV/°C OUTPUT CHARACTERISTICS Output Voltage High V OH R L = 100 kΩ to GND 2.685 2.697 V −40°C to +125°C 2.685 2.696 V R L = 10 kΩ to GND 2.67 2.68 V −40°C to +125°C 2.67 2.675 V Output Voltage Low V OL R L = 100 kΩ to V+ 1 10 mV −40°C to +125°C 2 10 mV R L = 10 kΩ to V+ 10 20 mV −40°C to +125°C 15 20 mV Short-Circuit Limit I SC ±10 ±15 mA −40°C to +125°C ±10 mA Output Current I O ±10 mA −40°C to +125°C ±5 mA POWER SUPPLY Power Supply Rejection Ratio PSRR V S = 2.7 V to 5.5 V 120 130 dB −40°C ≤ T A ≤ +125°C 115 130 dB Supply Current/Amplifier I SY V O = 0 V 750 900 μA −40°C ≤ T A ≤ +125°C 950 1000 μA DYNA MIC PERFOR MANCE Slew Rate SR R L = 10 kΩ 0.5 V/μs Overload Recovery Time 0.05 ms Gain Bandwidth Product GBP 1 MHz NOISE PERFOR MANCE Voltage Noise e n p-p 0 Hz to 10 Hz 2.0 μV p-p Voltage Noise Density e n f = 1 kHz 94 nV/√Hz Current Noise Density i n f = 10 Hz 2 fA/√Hz1Gain testing is dependent upon test bandwidth.AD8571/AD8572/AD8574Rev. B | Page 5 of 24ABSOLUTE MAXIMUM RATINGSTable 3.Parameter RatingSupply Voltage 6 VInput Voltage GND to V S + 0.3 VDifferential Input Voltage 1 ±5.0 VESD (Human Body Model) 2000 VOutput Short-Circuit Duration to GND IndefiniteStorage Temperature RangeRM, RU, and R Packages −65°C to +150°COperating Temperature RangeAD8571A/AD8572A/AD8574A −40°C to +125°CJunction Temperature RangeRM, RU, and R Packages −65°C to +150°C Lead Temperature Range (Soldering, 60 sec) 300°C1Differential input voltage is limited to ±5.0 V or the supply voltage, whichever is less.Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.THERMAL CHARACTERISTICSθJA is specified for the worst-case conditions, that is, θJA is specified for a device soldered in a circuit board for SOIC and TSSOP packages. Table 4. Thermal Resistance Package Type θJA θJC Unit 8-Lead MSOP (RM) 190 44 °C/W 8-Lead TSSOP (RU) 240 43 °C/W 8-Lead SOIC (R) 158 43 °C/W 14-Lead TSSOP (RU) 180 36 °C/W 14-Lead SOIC (R) 120 36 °C/W ESD CAUTIONAD8571/AD8572/AD8574Rev. B | Page 6 of 24TYPICAL PERFORMANCE CHARACTERISTICS180012010060204080140160–1.5–2.5–0.50.5 1.5 2.5N U M B E R O F A M P L I F I E R SOFFSET VOLTAGE (µV)01104-007Figure 7. Input Offset Voltage Distribution at 2.7 V50403020100–20–10–30I N P U T B I A S C U R R E N T (p A )INPUT COMMON-MODE VOLTAGE (V)01104-008Figure 8. Input Bias Current vs. Common-Mode Voltage1500–200010005000–1000–1500–500012345I N P U T B I A S C U R R E N T (p A )COMMON-MODE VOLTAGE (V)V S = 5V T A = 125°C01104-009Figure 9. Input Bias Current vs. Common-Mode Voltage 180012010060204080140160N U M B E R O F A M P L I F I E R SOFFSET VOLTAGE (µV)01104-010Figure 10. Input Offset Voltage Distribution at 5 V121086420123465N U M B E R O F A M P L I F I E R SINPUT OFFSET DRIFT (nV/°C)01104-011Figure 11. Input Offset Voltage Drift Distribution at 5 V10k1k1001010.1O U T P U T V O L T A G E (m V )LOAD CURRENT (mA)01104-012Figure 12. Output Voltage to Supply Rail vs. Output Current at 5 VAD8571/AD8572/AD8574Rev. B | Page 7 of 2410k1k 1001010.1O U T P U T V O L T A G E (m V )LOAD CURRENT (mA)01104-013Figure 13. Output Voltage to Supply Rail vs. Output Current at 2.7 V 1000750500250I N P U T B I A S C UR R E N T (p A )TEMPERATURE (°C)01104-014Figure 14. Bias Current vs. Temperature1.00.80.60.40.2S U P P L Y C U R R E N T (m A )TEMPERATURE (°C)01104-015Figure 15. Supply Current vs. Temperature 8002001003004005006007000S U P P L Y C U R R E N T P E R A M P L I F I E R (µA )SUPPLY VOLTAGE (V)01104-016Figure 16. Supply Current vs. Supply Voltage45901351802252700604050102030–100–40–30–20O P E N -L O O P G A I N (d B )P H A S E S H I F T (D e g r e e s )FREQUENCY (Hz)01104-017Figure 17. Open-Loop Gain and Phase Shift vs. Frequency at 2.7 V45901351802252700604050102030–100–40–30–2010k100k 1M10M 100MO P E N -LO O P G A I N (d B )P H A S E S H I F T (D e g r e e s )FREQUENCY (Hz)01104-018Figure 18. Open-Loop Gain and Phase Shift vs. Frequency at 5 VAD8571/AD8572/AD8574Rev. B | Page 8 of 24604050102030–100–40–30–2010010k1k1M100k10MC L O S ED -L O O P G A I N (d B )FREQUENCY (Hz)01104-019Figure 19. Closed-Loop Gain vs. Frequency at 2.7 V 604050102030–100–40–30–20C L O S ED -L O O P G A I N (d B )FREQUENCY (Hz)01104-020Figure 20. Closed-Loop Gain vs. Frequency at 5 V3002402701501802109012003060O U T P U T I M P E D A N C E (Ω)FREQUENCY (Hz)01104-021Figure 21. Output Impedance vs. Frequency at 2.7 V3002402701501802109012003060O U T P U T I M P E D A N C E (Ω)FREQUENCY (Hz)01104-022Figure 22. Output Impedance vs. Frequency at 5 V01104-023Figure 23. Large Signal Transient Response at 2.7 V01104-024Figure 24. Large Signal Transient Response at 5 VAD8571/AD8572/AD8574Rev. B | Page 9 of 2401104-025Figure 25. Small Signal Transient Response at 2.7 V 01104-026Figure 26. Small Signal Transient Response at 5 V101001k10kCAPACITANCE (pF)01104-027S M A L L S I G N A L O V E R S H O O T(%)50450403530252015105Figure 27. Small Signal Overshoot vs. Load Capacitance at 2.7 V450510152025303540S M A L L S I G N A L O V E R S H O O T (%)CAPACITANCE (pF)01104-028Figure 28. Small Signal Overshoot vs. Load Capacitance at 5 V0V V INV OUT0VBOTTOM SCALE: 1V/DIV TOP SCALE: 200mV/DIV01104-029Figure 29. Positive Overvoltage Recovery0VV IN V OUT0VBOTTOM SCALE: 1V/DIV TOP SCALE: 200mV/DIV01104-030Figure 30. Negative Overvoltage RecoveryAD8571/AD8572/AD8574Rev. B | Page 10 of 2401104-031Figure 31. No Phase ReversalC M R R (d B )FREQUENCY (Hz)14080100120600204001104-032Figure 32. CMRR vs. Frequency at 2.7 VC M R R (d B )FREQUENCY (Hz)1408010012060204001104-033Figure 33. CMRR vs. Frequency at 5 VP S R R (d B )FREQUENCY (Hz)14010012001104-034Figure 34. PSRR vs. Frequency at ±1.35 V10010k 1k 10MP S R R (d B )FREQUENCY (Hz)1408010012060204001104-0351M 100kFigure 35. PSRR vs. Frequency at ±2.5 VO U T P U T S W I N G (V p -p )FREQUENCY (Hz)3.01.52.02.51.000.501104-036Figure 36. Maximum Output Swing vs. Frequency at 2.7 VAD8571/AD8572/AD8574Rev. B | Page 11 of 24O U T P U T S W I N G (V p -p )FREQUENCY (Hz)01104-037Figure 37. Maximum Output Swing vs. Frequency at 5 V 0V01104-038Figure 38. 0.1 Hz to 10 Hz Noise at 2.7 V01104-039Figure 39. 0.1 Hz to 10 Hz Noise at 5 V31236420826010415652e n (n V H z )FREQUENCY (kHz)01104-040Figure 40. Voltage Noise Density at 2.7 V from 0 Hz to 2.5 kHz961126480324816e n (n V H z )FREQUENCY (kHz)1104-041Figure 41. Voltage Noise Density at 2.7 V from 0 Hz to 25 kHz156182104130527826e n (n V H z )FREQUENCY (kHz)01104-042Figure 42. Voltage Noise Density at 5 V from 0 Hz to 2.5 kHzAD8571/AD8572/AD8574Rev. B | Page 12 of 24961126480324816e n (n V H z )FREQUENCY (kHz)01104-043Figure 43. Voltage Noise Density at 5 V from 0 Hz to 25 kHz 180210120150609030e n (n V H z )FREQUENCY (kHz)01104-044Figure 44. Voltage Noise Density at 5 V from 0 Hz to 10 Hz150145140130135125P O W E R S U P P L Y R E J E C T I O N (d B )TEMPERATURE (°C)01104-045Figure 45. Power Supply Rejection vs. Temperature50304010–30–10200–40–20–50–75–50–250255075100125150S H OR T -C I R C U I T C U R R E N T (m A )TEMPERATURE (°C)01104-046Figure 46. Output Short-Circuit Current vs. TemperatureAD8571/AD8572/AD8574Rev. B | Page 13 of 24100608020–60–20400–80–40–100–75–50–25255075100125150S H O R T -C I R C U I T C U R R E N T (m A )TEMPERATURE (°C)01104-047Figure 47. Output Short-Circuit Current vs. TemperatureO U T P U T V O L T A G E S W I N G (m V )TEMPERATURE (°C)100250200015025507512517522501104-048Figure 48. Output Voltage to Supply Rail vs. TemperatureO U T P U T V O L T A G E S W I N G (m V )TEMPERATURE (°C)100250200015025507512517522501104-049Figure 49. Output Voltage to Supply Rail vs. TemperatureAD8571/AD8572/AD8574Rev. B | Page 14 of 24FUNCTIONAL DESCRIPTIONThe AD8571/AD8572/AD8574 are CMOS amplifiers that achieve their high degree of precision through randomfrequency auto-zero stabilization. The autocorrection topology allows the AD857x to maintain its low offset voltage over a wide temperature range, and the randomized auto-zero clockeliminates any intermodulation distortion (IMD) errors at the amplifier output.The AD857x can be run from a single-supply voltage as low as 2.7 V . The extremely low offset voltage of 1 μV and no IMD products allows the amplifier to be easily configured for high gains without risk of excessive output voltage errors. This makes the AD857x an ideal amplifier for applications requiring both dc precision and low distortion for ac signals. The extremely small temperature drift of 5 nV/°C ensures a minimum of offset voltage error over its entire temperature range of −40°C to +125°C. These combined features make the AD857x an excellent choice for a variety of sensitive measurement and automotive applications.AMPLIFIER ARCHITECTUREEach AD857x op amp consists of two amplifiers: a main amplifier and a secondary amplifier that is used to correct the offset voltage of the main amplifier. Both consist of a rail-to-rail input stage, allowing the input common-mode voltage range to reach both supply rails. The input stage consists of an NMOS differential pair operating concurrently with a parallel PMOS differential pair. The outputs from the differential input stages are combined in another gain stage whose output is used to drive a rail-to-rail output stage.The wide voltage swing of the amplifier is achieved by using two output transistors in a common-source configuration. The output voltage range is limited by the drain-to-source resistance of these transistors. As the amplifier is required to source or sink more output current, the voltage drop across these transistors increases due to their on resistance (rds). Simply put, the output voltage does not swing as close to the rail under heavy output current conditions as it does with light output current. This is a characteristic of all rail-to-rail output amplifiers. Figure 12 and Figure 13 show how close the output voltage can get to the rails with a given output current. The output of the AD857x is short-circuit protected to approximately 50 mA of current.The AD857x amplifiers have exceptional gain, yielding greater than 120 dB of open-loop gain with a load of 2 kΩ. Because the output transistors are configured in a common-source configura-tion, the gain of the output stage, and thus the open-loop gain of the amplifier, is dependent on the load resistance. Open-loop gain decreases with smaller load resistances. This is another characteristic of rail-to-rail output amplifiers.BASIC AUTO-ZERO AMPLIFIER THEORYAutocorrection amplifiers are not a new technology. Various IC implementations have been available for more than 15 years and some improvements have been made over time. The AD857x design offers a number of significant performance improve-ments over older versions while attaining a very substantial reduction in device cost. This section offers a simplified explanation of how the AD857x is able to offer extremely low offset voltages and high open-loop gains.As noted in the Amplifier Architecture section, each AD857x op amp contains two internal amplifiers. One is used as the primary amplifier, the other as an autocorrection, or nulling, amplifier. Each amplifier has an associated input offset voltage that can be modeled as a dc voltage source in series with the noninverting input. In Figure 50 and Figure 51, these are labeled as V OSX , where X denotes the amplifier associated with the offset: A for the nulling amplifier, B for the primary amplifier. The open-loop gain for the +IN and −IN inputs of each amplifier is given as A X . Both amplifiers also have a third voltage input with an associated open-loop gain of B X . There are two modes of operation determined by the action of two sets of switches in the amplifier: an auto-zero phase and an amplification phase.AUTO-ZERO PHASEIn this phase, all φA switches are closed and all φB switches are opened. Here, the nulling amplifier is taken out of the gain loop by shorting its two inputs together. Of course, there is a degree of offset voltage, shown as V OSA , inherent in the nulling amplifier that maintains a potential difference between the +IN and −IN inputs. The nulling amplifier feedback loop is closed through φA 2 and V OSA appears at the output of the nulling amp and on C M1, an internal capacitor in the AD857x. Mathematically, we can express this in the time domain as][][][t V B t V A t V OA A OSA A OA −= (1)this also can be expressed as[][]AOSA A OA B t V A t V +=1 (2)This shows that the offset voltage of the nulling amplifier times a gain factor appears at the output of the nulling amplifier and thus on the C M1 capacitor.AD8571/AD8572/AD8574Rev. B | Page 15 of 24V IN+V IN–V 01104-050Figure 50. Auto-Zero Phase of the AmplifierAMPLIFICATION PHASEWhen the φB switches close and the φA switches open for the amplification phase, this offset voltage remains on C M1 and essentially corrects any error from the nulling amplifier. The voltage across C M1 is designated as V NA . The potential difference between the two inputs to the primary amplifier is designated as V IN , or V IN = (V IN+ − V IN–). The output of the nulling amplifier can then be expressed as[][][][]t V B t V t V A t V NA A OSA IN A OA −−=( (3)V IN+VIN–V 01104-051Figure 51. Output Phase of the AmplifierBecause φA is now open and there is no place for C M1 to discharge, the voltage (V NA ) at the present time (t) is equal to the voltage at the output of the nulling amp (V OA ) at the time when φA was closed. If the period of the autocorrection switching frequency is designated as T S , then the amplifier switches between phases every 0.5 × T S . Therefore, in the amplification phase[]⎥⎦⎤⎢⎣⎡−=S NA NA T t V t V 21 (4) and substituting Equation 4 and Equation 2 into Equation 3yields[][][]AS OSA A A OSA A IN A OA B T t V B A t V A t V A t V +⎥⎦⎤⎢⎣⎡−−+=121(5) For the sake of simplification, it can be assumed that the autocorrection frequency is much faster than any potential change in V OSA or V OSB . This is a good assumption since changes in offset voltage are a function of temperature variation orlong-term wear time, both of which are much slower than the auto-zero clock frequency of the AD857x. This effectively makes the V OS time invariant, and Equation 5 can be rewritten as[][]()AOSAA A OSA A A IN A OAB V B A V B A t V A t V +−++=11 (6)or[][]⎟⎟⎠⎞⎜⎜⎝⎛++=A OSA IN A OA B V t V A t V 1 (7) Here, the auto-zeroing becomes apparent. Note that the V OSterm is reduced by a 1 + B A factor. This shows how the nulling amplifier has greatly reduced its own offset voltage error even before correcting the primary amplifier. Thus, the primary amplifier output voltage is the voltage at the output of the AD857x amplifier. It is equal to[][]()NB B OSB IN B OUT V B V t V A t V ++= (8)In the amplification phase, V OA = V NB , so this can be rewritten as[][][]⎥⎥⎦⎤⎢⎢⎣⎡⎟⎟⎠⎞⎜⎜⎝⎛++++=A OSA IN A B OSB B IN B OUT B V t V A B V A t V A t V 1 (9) combining terms yields[][]()OSBB AOSAB A B A B IN OUT V A B V B A B A A t V t V ++++=1 (10)The AD857x architecture is optimized in such a way thatA A = AB and B A = B B and B A >> 1. In addition, the gain product to A A B B is much greater than A B . Thus, Equation 10 can be simplified to[][])(OSB OSA A A A IN OUT V V A B A t V t V ++= (11)Most obvious is the gain product of both the primary and nulling amplifiers. This A A B A term is what gives the AD857x its extremely high open-loop gain. To understand how V OSA and V OSB relate to the overall effective input offset voltage of thecomplete amplifier, set up the generic amplifier equation of )(,EFFOS INOUTV V k V +×= (12)where k is the open-loop gain of an amplifier and V OS , EFF is its effective offset voltage. Putting Equation 12 into the form of Equation 11 gives[][]A A EFF OS A A IN OUT B A V B A t V t V ,+= (13) ThereforeAOSBOSA EFF OS B V V V +≈, (14)。

FPGA可编程逻辑器件芯片AD8606ARMZ-REEL中文规格书

3.0
OUTPUT SWING (V p-p)
2.5
VS = 2.7V
2.0
VIN = 2.6V p-p
TA = 25°C
RL = 2kΩ
1.5
AV = 1
1.0
0.5
0
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 38. Closed-Loop Output Voltage Swing vs. Frequency (FPBW)
The offset voltage causes a dark current induced by the shunt resistance of the Diode RD. These error terms are combined at the output of the amplifier. The error voltage is written as
Data Sheet
FEATURES
Low offset voltage: 65 μV maximum Low input bias currents: 1 pA maximum Low noise: 8 nV/√Hz Wide bandwidth: 10 MHz High open-loop gain: 1000 V/mV Unity gain stable Single-supply operation: 2.7 V to 5.5 V 5-ball WLCSP for single (AD8605) and 8-ball WLCSP for
OUTPUT IMPEDANCE (Ω)
100 90 VS = 2.7V
80

AD620AR-REEL中文资料

CONNECTION DIAGRAM 8-Lead Plastic Mini-DIP (N), Cerdip (Q)
and SOIC (R) Packages
RG 1 –IN 2 +IN 3 –VS 4
AD620
TOP VIEW
8 RG 7 +VS 6 OUTPUT 5 REF
1000. Furthermore, the AD620 features 8-lead SOIC and DIP packaging that is smaller than discrete designs, and offers lower power (only 1.3 mA max supply current), making it a good fit for battery powered, portable (or remote) applications.
LOW NOISE 9 nV/√Hz, @ 1 kHz, Input Voltage Noise 0.28 ␮V p-p Noise (0.1 Hz to 10 Hz)
EXCELLENT AC SPECIFICATIONS 120 kHz Bandwidth (G = 100) 15 ␮s Settling Time to 0.01%
APPLICATIONS Weigh Scales ECG and Medical Instrumentation Transducer Interface Data Acquisition Systems Industrial Process Controls Battery Powered and Portable Equipment
Model
Conditions

AD8606ARZ中文资料

1
4
9 –IN C 8 OUT C
AD8605 ONLY
图3. 5引脚WLCSP(CB后缀)
图4. 14引脚SOIC_N(R后缀)
OUT A –IN A +IN A V+ +IN B –IN B OUT B 1 14 OUT D –IN D +IN D V– +IN C –IN C OUT C
7
8
图5. 8引脚MSOP(RM后缀)、 8引脚SOIC_N(R后缀)
V+ OUT B –IN B +IN B
AD8608
TOP VIEW (Not to Scale)
02731-003
元器件交易网
AD8605/AD8606/AD8608
目录
特性 ...................................................................................................... 1 应用 ...................................................................................................... 1 概述 ...................................................................................................... 1 引脚配置 ............................................................................................. 1 修订历史 ............................................................................................. 3 5 V电气规格 ....................................................................................... 4 2.7 V电气规格 .................................................................................... 6 绝对最大额定值 ................................................................................ 8 ESD警告 ......................................................................................... 8 典型性能参数 .................................................................................... 9 应用信息 ........................................................................................... 16 输出反相 ...................................................................................... 16 最大功耗 ...................................................................................... 16 输入过压保护 ............................................................................. 16 总谐波失真加噪声 .................................................................... 16 含源电阻的总噪声 .................................................................... 17 通道隔离 ...................................................................................... 17 容性负载驱动 ............................................................................. 17 光敏度 .......................................................................................... 18 WLCSP组装考虑 ........................................................................ 18 I-V转换应用 ..................................................................................... 19 光电二极管前置放大器应用................................................... 19 音频和PDA应用 ......................................................................... 19 仪表放大器 ................................................................................. 20 DAC转换...................................................................................... 20 外形尺寸 ........................................................................................... 21 订购指南 ...................................................................................... 24

FPGA可编程逻辑器件芯片AD8552ARUZ-REEL中文规格书

The total noise (en, ) TOTAL is expressed in volts per square root Hertz, and the equivalent rms noise over a certain bandwidth can be found as
en = en,TOTAL × BW
[ ( ) ] en _ TOTAL = en2 + 4kTrS + inRS 2 12
(15)
Where: en = the input voltage noise density of the amplifier. in = the input current noise of the amplifier. RS = source resistance connected to the noninverting terminal. k = Boltzmann’s constant (1.38 × 10−23 J/K). T = ambient temperature in Kelvin (K = 273.15 + °C).
01101-004
OUT A 1 –IN A 2 +IN A 3 V– 4
AD8552
8 V+ 7 OUT B 6 –IN B 5 +IN B
Figure 4. 8-Lead SOIC (R Suffix)
OUT A –IN A +IN A V+
+IN B –IN B OUT B
1
14
AD8554
7
The AD8551/AD8552/AD8554 provide the benefits previously found only in expensive auto-zeroing or chopper-stabilized amplifiers. Using Analog Devices, Inc. topology, these new zero-drift amplifiers combine low cost with high accuracy. No external capacitors are required.

AD8606ARM资料

Precision Low Noise CMOS Rail-to-RailInput/Output Operational AmplifiersAD8605/AD8606/AD8608 Rev.DInformation furnished by Analog Devices is believed to be accurate and reliable.However, no responsibility is assumed by Analog Devices for its use, nor for anyinfringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: Fax: 781.326.8703© 2004 Analog Devices, Inc. All rights reserved.FEATURESLow offset voltage: 65 µV maximumLow input bias currents: 1 pA maximumLow noise: 8 nV/√HzWide bandwidth: 10 MHzHigh open-loop gain: 120 dBUnity gain stableSingle-supply operation: 2.7 V to 5.5 VMicroCSP™GENERAL DESCRIPTIONThe AD8605, AD8606, and AD86081 are single, dual, and quad rail-to-rail input and output, single-supply amplifiers. They feature very low offset voltage, low input voltage and current noise, and wide signal bandwidth. They use Analog Devices’ patented DigiTrim® trimming technique, which achieves superior precision without laser trimming.The combination of low offsets, low noise, very low input bias currents, and high speed makes these amplifiers useful in a wide variety of applications. Filters, integrators, photodiode amplifiers, and high impedance sensors all benefit from the combination of performance features. Audio and other ac applications benefit from the wide bandwidth and low distortion. Applications for these amplifiers include optical control loops, portable and loop-powered instrumentation, and audio amplification for portable devices.The AD8605, AD8606, and AD8608 are specified over the extended industrial temperature range (−40°C to +125°C). The AD8605 single is available in the 5-lead SOT-23 and 5-bump MicroCSP packages. The 5-bump MicroCSP offers the smallest available footprint for any surface-mount operational amplifier. The AD8606 dual is available in an 8-lead MSOP package and a narrow SOIC surface-mount package. The AD8608 quad is available in a 14-lead TSSOP and a narrow 14-lead SOIC package. MicroCSP, SOT, MSOP, and TSSOP versions are available in tape and reel only.1 Protected by U.S. Patent No. 5,969,657; other patents pending. APPLICATIONSPhotodiode amplificationBattery-powered instrumentationMultipole filtersSensorsBarcode scannersAudioFUNCTIONAL BLOCK DIAGRAMSV+V–2731-D-1–IN AV–+IN AOUT B–IN BV++IN BOUT A2731-D-5 Figure 1. 5-Lead SOT-23 (RT Suffix) Figure 2. 8-Lead SOIC (R Suffix)AD8605 ONLYOUT V+V–+IN–IN13542TOP VIEW(BUMP SIDE DOWN)2731-D-6OUT D–IN D+IN DV–+IN C–IN COUT C2731-D-4Figure 3. 5-Bump MicroCSP(CB Suffix)Figure 4. 14-Lead SOIC (R Suffix)OUT B–IN B+IN BV+2731-D-3OUT A–IN A+IN AV++IN B–IN BOUT B–IN D+IN DV–OUT D–IN COUT C+IN C2731-D-2 Figure 5. 8-Lead MSOP (RM Suffix) Figure 6. 14-Lead TSSOP (RU Suffix)AD8605/AD8606/AD8608Rev. D | Page 2 of 20TABLE OF CONTENTS5 V Electrical Specifications............................................................3 2.7 V Electrical Specifications.........................................................5 Absolute Maximum Ratings............................................................6 ESD Caution..................................................................................6 Typical Performance Characteristics.............................................7 Application Information................................................................13 Output Phase Reversal...............................................................13 Maximum Power Dissipation...................................................13 Input Overvoltage Protection...................................................13 THD + Noise...............................................................................13 Total Noise Including Source Resistors...................................14 Channel Separation....................................................................14 Capacitive Load Drive...............................................................14 Light Sensitivity..........................................................................15 MicroCSP Assembly Considerations.......................................15 I-V Conversion Applications........................................................16 Photodiode Preamplifier Applications....................................16 Audio and PDA Applications...................................................16 Instrumentation Amplifiers......................................................17 D/A Conversion.........................................................................17 Outline Dimensions.......................................................................18 Ordering Guide.. (19)REVISION HISTORY5/04—Data Sheet Changed from Rev. C to Rev. DUpdated Format.............................................................Universal Edit to Light Sensitivity Section...............................................16 Updated Outline Dimensions...................................................19 Changes to Ordering Guide......................................................20 7/03—Data Sheet Changed from Rev. B to Rev. CChanges to Features.......................................................................1 Change to General Description...................................................1 Addition to Functional Block Diagrams....................................1 Addition to Absolute Maximum Ratings...................................4 Addition to Ordering Guide........................................................4 Change to Equation In Maximum Power DissipationSection........................................................................................11 Added Light Sensitivity Section.................................................12 Added New Figure 8 and Renumbered Subsequent Figures.13 Added New MicroCSP Assembly Considerations Section....13 Changes to Figure 9.....................................................................13 Change to Equation in Photodiode PreamplifierApplications Section ................................................................13 Changes to Figure 12...................................................................14 Change to Equation in D/A Conversion Section....................14 Updated Outline Dimensions (15)3/03—Data Sheet Changed from Rev. A to Rev. BChanges to Functional Block Diagram.......................................1 Changes to Absolute Maximum Ratings....................................4 Changes to Ordering Guide ....................................................... 4 Changes to Figure 9 ....................................................................13 Updated Outline Dimensions....................................................15 11/02—Data Sheet Changed from Rev. 0 to Rev. AChange to Electrical Characteristics...........................................2 Changes to Absolute Maximum Ratings....................................4 Changes Ordering Guide .............................................................4 Change to TPC 6 ..........................................................................5 Updated Outline Dimensions. (15)AD8605/AD8606/AD8608Rev. D | Page 3 of 205 V ELECTRICAL SPECIFICATIONSTable 1. @ V S = 5 V, V CM = V S /2, T A = 25°C, unless otherwise noted.ParameterSymbol Conditions Min Typ Max Unit INPUT CHARACTERISTICS Offset VoltageV OS AD8605/AD8606 V S = 3.5 V, V CM = 3 V 20 65 µV AD8608 V S = 3.5 V, V CM = 2.7 V 20 75 µV V S = 5 V, V CM = 0 V to 5 V 80 300 µV−40°C < T A < +125°C 750 µV Input Bias Current I B 0.2 1 pA AD8605/AD8606 −40°C < T A < +85°C 50 pA AD8605/AD8606 −40°C < T A < +125°C 250 pA AD8608 −40°C < T A < +85°C 100 pA AD8608−40°C < T A < +125°C 300 pA Input Offset Current I OS 0.1 0.5 pA −40°C < T A < +85°C 20 pA−40°C < T A < +125°C 75 pA Input Voltage Range0 5 V Common-Mode Rejection Ratio CMRR V CM = 0 V to 5 V 85 100 dB−40°C < T A < +125°C 75 90 dB Large Signal Voltage Gain A VO V O = 0.5 V to 4.5 V 300 1,000 V/mVR L = 2 kΩ, V CM = 0 V Offset Voltage DriftAD8605/AD8606 ∆V OS /∆T 1 4.5 µV/°C AD8608∆V OS /∆T 1.5 6.0 µV/°C INPUT CAPACITANCECommon-Mode Input Capacitance 8.8 pF Differential Input Capacitance 2.59 pF OUTPUT CHARACTERISTICS Output Voltage High V OH I L = 1 mA 4.96 4.98 V I L = 10 mA 4.7 4.79 V−40°C < T A < +125°C 4.6 V Output Voltage Low V OL I L = 1 mA 20 40 mV I L = 10 mA 170 210 mV−40°C < T A < +125°C 290 mV Output CurrentI OUT ±80 mA Closed-Loop Output Impedance Z OUT f = 1 MHz, A V = 1 10 Ω POWER SUPPLYPower Supply Rejection Ratio PSRR AD8605/AD8606 V S = 2.7 V to 5.5 V 80 95 dB AD8608 V S = 2.7 V to 5.5 V 77 92 dB−40°C < T A < +125°C 70 90 dB Supply Current/Amplifier I SY V O = 0 V 1 1.2 mA−40°C < T A < +125°C 1.4 mA DYNAMIC PERFORMANCE Slew Rate SR R L = 2 kΩ 5 V/µs Settling Timet S To 0.01%, 0 V to 2 V step < 1 µs Full Power Bandwidth BW P < 1% distortion 360 kHz Gain Bandwidth Product GBP 10 MHz Phase Margin ϕO 65 DegreesAD8605/AD8606/AD8608Rev. D | Page 4 of 20AD8605/AD8606/AD8608 2.7 V ELECTRICAL SPECIFICATIONSRev. D | Page 5 of 20AD8605/AD8606/AD8608Rev. D | Page 6 of 20ABSOLUTE MAXIMUM RATINGSStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3.Parameter Rating Supply Voltage 6 V Input Voltage GND to V S Differential Input Voltage 6 VOutput Short-Circuit Durationto GNDObserve Derating Curves Storage Temperature Range All Packages −65°C to +150°C Operating Temperature Range AD8605/AD8606/AD8608 −40°C to +125°C Junction Temperature Range All Packages −65°C to +150°CLead Temperature Range(Soldering, 60 sec)300°C Table 4. Package TypePackage TypeθJA 1 θJC Unit 5-Bump MicroCSP (CB) 220 220 °C/W 5-Lead SOT-23 (RT) 230 92 °C/W 8-Lead MSOP (RM) 210 45 °C/W 8-Lead SOIC (R) 158 43 °C/W 14-Lead SOIC (R) 120 36 °C/W 14-Lead TSSOP (RU)18035°C/W1θJA is specified for worst-case conditions, i.e., θJA is specified for device in socket for PDIP packages;θJA is specified for device soldered onto a circuit board for surface-mount packages.ESD CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.AD8605/AD8606/AD8608Rev. D | Page 7 of 20TYPICAL PERFORMANCE CHARACTERISTICSOFFSET VOLTAGE (mV)N U M B E R O F A M P L I F I E R S450040000200015001000500300025003500300–200–1000100200–30002731-D -007Figure 7. Input Offset Voltage DistributionTCVOS (mV/°C)124.80.4N U M B E R O F A M P L I F I E R S0.8 1.62.43.24.0168424204.40 1.2 2.0 2.8 3.602731-D -008Figure 8. AD8608 Input Offset Voltage Drift DistributionTCVOS (mV/°C)20100N U M B E R O F A M P L I F I E R S14621216841802731-D -009Figure 9. AD8605/AD8606 Input Offset Voltage Drift Distribution–300I N P U T O F F S E T V O L T A G E (mV )COMMON-MODE VOLTAGE (V)02731-D -010Figure 10. Input Offset Voltage vs. Common-Mode Voltage(200 Units, 5 Wafer Lots, Including Process Skews)TEMPERATURE (°C)360160012525I N P U T B I A S C U R R E NT (p A )5075100240802002801204032002731-D -011Figure 11. Input Bias Current vs. TemperatureLOAD CURRENT (mA)0.001100.01V S Y –V O U T (m V )0.1102731-D -012Figure 12. Output Voltage to Supply Rail vs. Load CurrentAD8605/AD8606/AD8608Rev. D | Page 8 of 20TEMPERATURE (°C)O U T P U T V O L T A G E (V )–40–25–10520355065809511012502731-D -013Figure 13. Output Voltage Swing vs. Temperature0.25000.1500.0500.2000.100TEMPERATURE (°C)O U T P U T V O L T A G E (V )–40–25–10520355065809511012502731-D -014Figure 14. Output Voltage Swing vs. TemperatureG A I N (d B )10080–1006040200–20–40–60–80225180–22513590450–45–90–135–180P H A S E (D e g r e e s )FREQUENCY (Hz)02731-D -015Figure 15. Open-Loop Gain and Phase vs. Frequency FREQUENCY (Hz)65O U T P U T S W I N G (V p -p )431202731-D -016Figure 16. Closed-Loop Output Voltage SwingFREQUENCY (Hz)100900O U T P U T I M P E D A N C E (Ω)807020605030104002731-D -017Figure 17. Output Impedance vs. FrequencyFREQUENCY (Hz)10kC M R R (d B )100k 1M 201201k10M9080706050403011010002731-D -018Figure 18. Common-Mode Rejection Ratio vs. FrequencyAD8605/AD8606/AD8608Rev. D | Page 9 of 20FREQUENCY (Hz)1k10M 10kP S R R (d B )100k1M02731-D -019Figure 19. PSRR vs. FrequencyCAPACITANCE (pF)45400S M A L L S I G N A L O V E R S H O O T (%)353010252015502731-D -020Figure 20. Small Signal Overshoot vs. Load CapacitanceTEMPERATURE (°C)2.0–1.5S U P P L Y C U R R E N T /A M P L I F I E R (m A )1.01.50.5–1.0–0.50–50125–35–20951105203550658002731-D -021Figure 21. Supply Current vs. TemperatureSUPPLY VOLTAGE (V)1.00.40S U P P L Y C U R R E N T /A M P L I F I E R (m A )0.90.50.30.10.70.60.20.805.04.54.03.53.02.52.01.51.00.502731-D -022Figure 22. Supply Current vs. Supply VoltageTIME (1s/DIV)V O L T A G EN O I S E (1µV /D I V )02731-D -023Figure 23. 0.1 Hz to 10 Hz Input Voltage NoiseTIME (200ns/DIV)V O L T A G E (50m V /D I V )02731-D -024Figure 24. Small Signal Transient ResponseAD8605/AD8606/AD8608Rev. D | Page 10 of 20TIME (400ns/DIV)V O L T A G E (1V /D I V)02731-D -025Figure 25. Large Signal Transient ResponseTIME (400ns/DIV)0V 0V02731-D -026Figure 26. Negative Overload RecoveryTIME (400ns/DIV)0V 0V02731-D -027Figure 27. Positive Overload Recovery FREQUENCY (kHz)3620432281282416V O L T A G E N O I S E D E N S I T Y (n V /H z )1.00.90.80.70.60.50.40.30.20.102731-D -028Figure 28. Voltage Noise Density06.720.113.426.840.233.553.646.9FREQUENCY (kHz)V O L T A G E N O I S E D E N S I T Y (n V /H z )198765432102731-D-029Figure 29. Voltage Noise Density 014.944.729.859.699.474.5119.2104.3FREQUENCY (Hz)V O L T A G E N O I S E D E N S I T Y (n V /H z )10090807060504030201002731-D -030Figure 30. Voltage Noise Density180016000N U M B E R O F A M P L I F I E R S800600400200120010001400OFFSET VOLTAGE (µV)300–200–100200–300010002731-D -031Figure 31. Input Offset Voltage Distribution300200–300I N P U T O F F S E T V O L T A G E (µV )100–200–10002731-D -032Figure 32. Input Offset Voltage vs. Common-Mode Voltage(200 Units, 5 Wafer Lots, Including Process Skews)LOAD CURRENT (mA)0.001100.01O U T P U T V O L T A G E (m V )0.1102731-D -033Figure 33. Output Voltage to Supply Rail vs. Load Current TEMPERATURE (°C)2.6802.6752.6505201255035O U T P U T V O L T A G E (V )6580951102.6652.6552.6702.660–10–25–4002731-D -034Figure 34. Output Voltage Swing vs. Temperature0.0450.02500.0350.0150.0050.0300.0400.0200.010TEMPERATURE (°C)5201255035O U T P U T V O L T A G E (V )658095110–10–25–4002731-D -035Figure 35. Output Voltage Swing vs. TemperatureFREQUENCY (Hz)10k100M100kG A I N (dB )10080–1006040200–20–40–60–80225180–2251350–45–90–135–180P H A S E (D e g r e e s )1M10M02731-D -036Figure 36. Open-Loop Gain and Phase vs. FrequencyFREQUENCY (Hz)3.02.501k10M10kO U T P U T S W I N G (V p -p )100k1M2.01.50.51.002731-D -037Figure 37. Closed-Loop Output Voltage Swing vs. FrequencyFREQUENCY (Hz)1009001k100M10kO U T P U T I M P E D A N C E (Ω)100k 1M 10M807020605030104002731-D -038Figure 38. Output Impedance vs. FrequencyCAPACITANCE (pF)60500101k100S M A L L S I G N A L O V E R S H O O T(%)3020104002731-D -039Figure 39. Small Signal Overshoot vs. Load CapacitanceTIME (1s/DIV)V O L T A G E N O I S E (1µV /D I V )02731-D -040Figure 40. 0.1 Hz to 10 Hz Input Voltage NoiseTIME (200ns/DIV)V O L TA G E (50m V /D I V )02731-D -041Figure 41. Small Signal Transient ResponseTIME (400ns/DIV)V O L T A G E (1V /DI V )02731-D -042Figure 42. Large Signal Transient ResponseAPPLICATION INFORMATIONOUTPUT PHASE REVERSALPhase reversal is defined as a change in polarity at the output of the amplifier when a voltage that exceeds the maximum input common-mode voltage drives the input.Phase reversal can cause permanent damage to the amplifier; it may also cause system lockups in feedback loops. The AD8605 does not exhibit phase reversal even for inputs exceeding the supply voltage by more than 2 V .TIME (4µs/DIV)V O L T A G E (2V /D I V )02731-D -043Figure 43. No Phase ReversalMAXIMUM POWER DISSIPATIONPower dissipated in an IC causes the die temperature to increase. This can affect the behavior of the IC and the application circuit performance.The absolute maximum junction temperature of the AD8605/ AD8606/AD8608 is 150°C. Exceeding this temperature could cause damage or destruction of the device. The maximum power dissipation of the amplifier is calculated according to the following formula:JAA J DISS T T P θ−=where:T J = junction temperature T A = ambient temperatureθJA = junction to-ambient-thermal resistanceFigure 44 compares the maximum power dissipation with temperature for the various AD8605 family packages.TEMPERATURE (°C)1.00.80010020P O W E R D I S S I P A T I O N (W )4060800.60.40.22.01.81.61.41.202731-D -044Figure 44. Maximum Power Dissipation vs. TemperatureINPUT OVERVOLTAGE PROTECTIONThe AD8605 has internal protective circuitry. However, if the voltage applied at either input exceeds the supplies by more than 2.5 V , external resistors should be placed in series with the inputs. The resistor values can be determined by the formula()()mA R V V S S IN 5200≤Ω+−The remarkable low input offset current of the AD8605 (<1 pA) allows the use of larger value resistors. With a 10 kΩ resistor at the input, the output voltage has less than 10 nV of error voltage. A 10 kΩ resistor has less than 13 nV/√Hz of thermal noise at room temperature.THD + NOISETotal harmonic distortion is the ratio of the input signal in V rms to the total harmonics in V rms throughout the spectrum. Harmonic distortion adds errors to precision measurements and adds unpleasant sonic artifacts to audio systems.The AD8605 has a low total harmonic distortion. Figure 45 shows that the AD8605 has less than 0.005% or −86 dB of THD + N over the entire audio frequency range. The AD8605 is configured in positive unity gain, which is the worst case, and with a load of 10 kΩ.FREQUENCY (Hz)0.10.010.00012020k100T H D + N (%)1k0.00110k 02731-D -045Figure 45. THD + NTOTAL NOISE INCLUDING SOURCE RESISTORSThe low input current noise and input bias current of theAD8605 make it the ideal amplifier for circuits with substantial input source resistance such as photodiodes. Input offset voltage increases by less than 0.5 nV per 1 kΩ of source resistance at room temperature and increases to 10 nV at 85°C. The total noise density of the circuit is()S S n n TOTAL n TR k R i e e 422,++=where:e n is the input voltage noise density of the AD8605 i n is the input current noise density of the AD8605 R S is the source resistance at the noninverting terminal k is Boltzmann’s constant (1.38 × 10−23 J/K)T is the ambient temperature in Kelvin (T = 273 + °C) For example, with R S = 10 kΩ, the total voltage noise density is roughly 15 nV/√Hz .For R S < 3.9 k Ω, e n dominates and e n,TOTAL ≈ e n .The current noise of the AD8605 is so low that its total density does not become a significant term unless R S is greater than 6 MΩ. The total equivalent rms noise over a specific bandwidth is expressed as()BW e E TOTAL n n ,=where BW is the bandwidth in hertz.Note that the analysis above is valid for frequencies greater than 100 Hz and assumes relatively flat noise, above 10 kHz. For lower frequencies, flicker noise (1/f) must be considered.CHANNEL SEPARATIONChannel separation, or inverse crosstalk, is a measure of the signal feed from one amplifier (channel) to an other on the same IC.The AD8606 has a channel separation of greater than −160 dB up to frequencies of 1 MHz, allowing the two amplifiers to amplify ac signals independently in most applications.C H A N N E L S E P A R A T I O N (d B )FREQUENCY (Hz)10M 1M 100k 10k 1k100100M–200–40–60–80–100–120–140–160–18002731-D -046Figure 46. Channel Separation vs. FrequencyCAPACITIVE LOAD DRIVEThe AD8605 can drive large capacitive loads without oscillation. Figure 47 shows the output of the AD8606 in response to a 200 mV input signal. In this case, the amplifier was configured in positive unity gain, worst case for stability, while driving a 1,000 pF load at its output. Driving larger capacitive loads in unity gain may require the use of additional circuitry.TIME (10µs/DIV)V O L T A G E (100m V /D I V)02731-D -047Figure 47. Capacitive Load Drive without SnubberA snubber network, shown in Figure 48, helps reduce the signal overshoot to a minimum and maintain stability. Although this circuit does not recover the loss of bandwidth induced by large capacitive loads, it greatly reduces the overshoot and ringing. This method does not reduce the maximum output swing of the amplifier.Figure 49 shows a scope photograph of the output at the snubber circuit. The overshoot is reduced from over 70% to less than 5%, and the ringing is eliminated by the snubber. Optimum values for R S and C S are determined experimentally.Figure 48. Snubber Network ConfigurationTIME (10µs/DIV)V O L T A G E (100m V /D I V )02731-D -048Figure 49. Capacitive Load Drive with SnubberTable 5 summarizes a few optimum values for capacitive loads. Table 5.C L (pF) R S (Ω) C S (pF) 500 100 1,000 1,000 70 1,000 2,00060800An alternate technique is to insert a series resistor inside the feedback loop at the output of the amplifier. Typically, the value of this resistor is approximately 100 Ω. This method also reduces overshoot and ringing but causes a reduction in the maximum output swing.LIGHT SENSITIVITYThe AD8605ACB (MicroCSP package option) is essentially a silicon die with additional post fabrication dielectric and intermetallic processing designed to contact solder bumps on the active side of the chip. With this package type, the die is exposed to ambient light and is subject to photoelectric effects. Light sensitivity analysis of the AD8605ACB mounted on standard PCB material reveals that only the input bias current (I B ) parameter is impacted when the package is illuminated directly by high intensity light. No degradation in electrical performance is observed due to illumination by low intensity (0.1 mW/cm 2) ambient light. Figure 50 shows that I B increases with increasing wavelength and intensity of incident light; I B can reach levels as high as 4500 pA at a light intensity of 3 mW/cm 2 and a wavelength of 850 nm. The light intensitiesshown in Figure 50 are not normal for most applications, i.e., even though direct sunlight can have intensities of 50 mW/cm 2, office ambient light can be as low as 0.1 mW/cm 2.When the MicroCSP package is assembled on the board with the bump-side of the die facing the PCB, reflected light from the PCB surface is incident on active silicon circuit areas and results in the increased I B . No performance degradation occurs due to illumination of the backside (substrate) of the AD8605ACB. The AD8605ACB is particularly sensitive to incident light with wavelengths in the near infrared range (NIR, 700 nm to 1000 nm). Photons in this waveband have a longer wavelength and lower energy than photons in the visible (400 nm to 700 nm) and near ultraviolet bands (NUV , 200 nm to 400 nm); therefore, they can penetrate more deeply into the active silicon. Incident light with wavelengths greater than 1100 nm has no photo-electric effect on the AD8605ACB because silicon is trans-parent to wave lengths in this range. The spectral content of conventional light sources varies: sunlight has a broad spectral range, with peak intensity in the visible band that falls off in the NUV and NIR bands; fluorescent lamps have significant peaks in the visible but not in the NUV or NIR bands.Efforts have been made at a product level to reduce the effect of ambient light; the under bump metal (UBM) has been designed to shield the sensitive circuit areas on the active side (bump-side) of the die. However, if an application encounters any light sensitivity with the AD8605ACB, shielding the bump side of the MicroCSP package with opaque material should eliminate this effect. Shielding can be accomplished using materials such as silica filled liquid epoxies that are used in flip chip underfill techniques.WAVELENGTH (nm)35000350I N P U T B I A S C U RR E N T (p A )2500300020005001000150045055065075085040004500500002731-D -050Figure 50. AD8605ACB Input Bias Current Response to Direct Illumination ofVarying Intensity and WavelengthMICROCSP ASSEMBLY CONSIDERATIONSFor detailed information on MicroCSP PCB assembly and reliability, refer to ADI Application Note AN-617 on the ADI website .。

ADG1201BRJZ-REEL7中文资料

Low Capacitance, Low Charge Injection,±15 V/+12 V i CMOS SPST in SOT-23ADG1201/ADG1202 Rev. 0Information furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.FEATURES2.4 pF off capacitance<1 pC charge injectionLow leakage; 0.6 nA maximum @ 85°C 120 Ω on resistanceFully specified at ±15 V, +12 VNo V L supply required3 V logic-compatible inputsRail-to-rail operation6-lead SOT-23 package APPLICATIONSAutomatic test equipmentData acquisition systemsBattery-powered systemsSample-and-hold systemsAudio signal routingVideo signal routing Communication systemsFUNCTIONAL BLOCK DIAGRAMS DINDINSWITCHES SHOWN FOR A LOGIC “1” INPUT6576-1Figure 1.GENERAL DESCRIPTIONThe ADG1201/ADG1202 are monolithic complementary metal-oxide semiconductor (CMOS) devices containing an SPST switch designed in an i CMOS® (industrial CMOS) process. i CMOS is a modular manufacturing process combining high voltage CMOS and bipolar technologies. It enables the development of a wide range of high perform-ance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, i CMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size.The ultralow capacitance and charge injection of these switches make them ideal solutions for data acquisition and sample-and-hold applications, where low glitch and fast settling are required. Fast switching speed coupled with high signal bandwidth make the parts suitable for video signal switching. i CMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and battery-powered instruments.The ADG1201/ADG1202 contain a single-pole/single-throw (SPST) switch. Figure 1 shows that with a logic input of 1, the switch of the ADG1201 is closed and that of the ADG1202 is open. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. PRODUCT HIGHLIGHTS1.Ultralow capacitance.2.<1 pC charge injection.3.Ultralow leakage.4. 3 V logic-compatible digital inputs: V IH = 2.0 V, V IL = 0.8 V.5.No V L logic power supply required.6.SOT-23 package.ADG1201/ADG1202Rev. 0 | Page 2 of 16TABLE OF CONTENTSFeatures .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Dual Supply ................................................................................... 3 Single Supply ................................................................................. 4 Absolute Maximum Ratings ............................................................5 ESD Caution...................................................................................5 Pin Configuration and Function Descriptions ..............................6 Typical Performance Characteristics ..............................................7 Test Circuits ..................................................................................... 10 Terminology .................................................................................... 12 Outline Dimensions ....................................................................... 13 Ordering Guide .. (13)REVISION HISTORY2/08—Revision 0: Initial VersionADG1201/ADG1202Rev. 0 | Page 3 of 16SPECIFICATIONSDUAL SUPPLYV DD = 15 V ± 10%, V SS = −15 V ± 10%, GND = 0 V , unless otherwise noted. Table 1.B Version 1Parameter 25°C −40°C to +85°C −40°C to+125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range V DD to V SS V On Resistance (R ON ) 120 Ω typ V DD = +13.5 V, V SS = −13.5 V 200 240 270 Ω max V S = ±10 V, I S = −1 mA; see Figure 20 On Resistance Flatness (R FLAT(ON)) 20 Ω typ V S = −5 V, 0 V, and +5 V; I S = −1 mA 60 72 79 Ω max LEAKAGE CURRENTS V DD = +16.5 V, V SS = −16.5 V Source Off Leakage, I S (Off) ±0.004 nA typ V S = ±10 V, V D = ±10 V; see Figure 21 ±0.1 ±0.6 ±1 nA max Drain Off Leakage, I D (Off) ±0.004 nA typ V S = ±10 V, V D = ±10 V; see Figure 21 ±0.1 ±0.6 ±1 nA max Channel On Leakage, I D , I S (On) ±0.04 nA typ V S = V D = ±10 V; see Figure 22 ±0.15 ±0.6 ±1 nA max DIGITAL INPUTS Input High Voltage, V INH 2.0 V min Input Low Voltage, V INL 0.8 V max Input Current, I INL or I INH 0.005 μA typ V IN = V INL or V INH ±0.1 μA max Digital Input Capacitance, C IN 2.5 pF typDYNAMIC CHARACTERISTICS 2t ON 140 ns typ R L = 300 Ω, C L = 35 pF 170 200 230 ns max V S = 10 V; see Figure 26 t OFF 90 ns typ R L = 300 Ω, C L = 35 pF 105 130 141 ns max V S = 10 V; see Figure 26 Charge Injection −0.8 pC typ V S = 0 V, R S = 0 Ω, C L = 1 nF; see Figure 27 Off Isolation 80 dB typ R L = 50 Ω, C L = 5 pF , f = 1 MHz; see Figure 23 Total Harmonic Distortion + Noise 0.15 % typ R L = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz −3 dB Bandwidth 660 MHz typ R L = 50 Ω, C L = 5 pF; see Figure 24 C S (Off) 2.4 pF typ V S = 0 V, f = 1 MHz 3 pF max V S = 0 V, f = 1 MHz C D (Off) 2.8 pF typ V S = 0 V, f = 1 MHz 3.3 pF max V S = 0 V, f = 1 MHz C D , C S (On) 4.7 pF typ V S = 0 V, f = 1 MHz 5.6 pF max V S = 0 V, f = 1 MHz POWER REQUIREMENTS V DD = +16.5 V, V SS = −16.5 V I DD 0.001 μA typ Digital inputs = 0 V or V DD 1.0 μA max I DD 60 μA typ Digital inputs = 5 V 95 μA max I SS 0.001 μA typ Digital inputs = 0 V, 5 V or V DD 1.0 μA max V DD /V SS ±5 to ±16.5 V min/max GND = 0 V1 Temperature range for B version is −40°C to +125°C. 2Guaranteed by design, not subject to production test.ADG1201/ADG1202Rev. 0 | Page 4 of 16SINGLE SUPPLYV DD = 12 V ± 10%, V SS = 0 V , GND = 0 V , unless otherwise noted. Table 2.B Version 1Parameter 25°C −40°C to +85°C −40°C to+125°C Unit Test Conditions/Comments ANALOG SWITCH Analog Signal Range 0 V to V DD V On Resistance (R ON ) 300 Ω typ V DD = 10.8 V, V SS = 0 V 475 567 625 Ω max V S = 0 V to 10 V, I S = −1 mA; see Figure 20 On Resistance Flatness (R FLA T(ON)) 60 Ω typ V S = 3 V, 6 V, and 9 V, I S = −1 mA LEAKAGE CURRENTS V DD = 13.2 V, V SS = 0 V Source Off Leakage, I S (Off) ±0.006 nA typ V S = 1 V or 10 V, V D = 10 V or 1 V; see Figure 21 ±0.1 ±0.6 ±1 nA max Drain Off Leakage, I D (Off) ±0.006 nA typ V S = 1 V or 10 V, V D = 10 V or 1 V; see Figure 21 ±0.1 ±0.6 ±1 nA max Channel On Leakage, I D , I S (On) ±0.04 nA typ V S = V D = 1 V or 10 V; see Figure 22 ±0.15 ±0.6 ±1 nA max DIGITAL INPUTS Input High Voltage, V INH 2.0 V min Input Low Voltage, V INL 0.8 V max Input Current, I INL or I INH 0.001 μA typ V IN = V INL or V INH ±0.1 μA max Digital Input Capacitance, C IN 3 pF typDYNAMIC CHARACTERISTICS 2t ON 190 ns typ R L = 300 Ω, C L = 35 pF 250 295 340 ns max V S = 8 V; see Figure 26 t OFF 120 ns typ R L = 300 Ω, C L = 35 pF 155 190 210 ns max V S = 8 V; see Figure 26 Charge Injection 0.8 pC typ V S = 6 V, R S = 0 Ω, C L = 1 nF; see Figure 27 Off Isolation 80 dB typ R L = 50 Ω, C L = 5 pF, f = 1 MHz;see Figure 23−3 dB Bandwidth 520 MHz typ R L = 50 Ω, C L = 5 pF; see Figure 24 C S (Off) 2.7 pF typ V S = 6 V, f = 1 MHz 3.3 pF max V S = 6 V, f = 1 MHz C D (Off) 3.1 pF typ V S = 6 V, f = 1 MHz 3.6 pF max V S = 6 V, f = 1 MHz C D , C S (On) 5.3 pF typ V S = 6 V, f = 1 MHz 6.3 pF max V S = 6 V, f = 1 MHz POWER REQUIREMENTS V DD = 13.2 V I DD 0.001 μA typ Digital inputs = 0 V or V DD 1.0 μA max I DD 60 μA typ Digital inputs = 5 V 95 μA max V DD +5/+16.5 V min/max V SS = 0 V, GND = 0 V1 Temperature range for B version is −40°C to +125°C. 2Guaranteed by design, not subject to production test.ADG1201/ADG1202Rev. 0 | Page 5 of 16ABSOLUTE MAXIMUM RATINGST A = 25°C, unless otherwise noted. Table 3.Parameter Rating V DD to V SS 35 V V DD to GND −0.3 V to +25 V V SS to GND +0.3 V to −25 V Analog Inputs 1 V SS – 0.3 V to V DD + 0.3 V or30 mA, whichever occurs firstDigital Inputs 1GND – 0.3 V to V DD + 0.3 V or30 mA, whichever occurs firstPeak Current, S or D 100 mA (pulsed at 1 ms, 10%duty cycle maximum) Continuous Current perChannel, S or D30 mA Operating Temperature Range −40°C to +125°C Industrial (B Version) Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 6 Lead SOT-23 θJA ,Thermal Impedance 229.6°C/W θJC , Thermal Impedance 91.99°C/WReflow Soldering PeakTemperature, Pb-free260°C 1Overvoltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given.Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.ESD CAUTIONADG1201/ADG1202Rev. 0 | Page 6 of 16PIN CONFIGURATION AND FUNCTION DESCRIPTIONS06576-002V DDGND V SS IN DSFigure 2. SOT-23 Pin ConfigurationTable 4. Pin Function DescriptionsPin No. Mnemonic Description1 V DD Most Positive Power Supply Potential.2 GND Ground (0 V) Reference.3 V SS Most Negative Power Supply Potential.4 S Source Terminal. Can be an input or output.5 D Drain Terminal. Can be an input or output.6 INLogic Control Input.Table 5. ADG1201/ADG1202 Truth TableADG1201 IN ADG1202 IN Switch Condition1 0 On 0 1 OffADG1201/ADG1202Rev. 0 | Page 7 of 16TYPICAL PERFORMANCE CHARACTERISTICSSOURCE OR DRAIN VOLTAGE (V)O N R E S I S T A N C E (Ω)200180160140120100608002040Figure 3. On Resistance as a Function of V D (V S ) for Dual SupplySOURCE OR DRAIN VOLTAGE (V)O N R E S I S T A N C E (Ω)450400350300250150200050100Figure 4. On Resistance as a Function of V D(V S ) for Dual SupplySOURCE OR DRAIN VOLTAGE (V)O N R E S I S T A N C E (Ω)450400350300250150200050100Figure 5. On Resistance as a Function of V D (V S ) for Single Supply SOURCE OR DRAIN VOLTAGE (V)O N R E S I S T A N C E (Ω)25015020005010006576-006Figure 6. On Resistance as a Function of V D(V S ) for DifferentTemperatures, Dual SupplySOURCE OR DRAIN VOLTAGE (V)O N R E S I S T A N C E (Ω)60040050030020010006576-007Figure 7. On Resistance as a Function of V D (V S ) for DifferentTemperatures, Single SupplyL E A K A G E C U R R E N T (p A )0–450–40006576-02820015010050–50–100–150–200–250–300–350TEMPERATURE (ºC)Figure 8. Leakage Currents as a Function of Temperature, Dual SupplyADG1201/ADG1202Rev. 0 | Page 8 of 16L E A K A G E C U R R E N T (p A )0–250100150–50–100–150–20050TEMPERATURE (ºC)Figure 9. Leakage Currents as a Function of Temperature, Dual SupplyL E A K A G E C U R R E N T (p A )0–200100080300250200150–50–100–15050204060100120TEMPERATURE (ºC)Figure 10. Leakage Currents as a Function of Temperature, Single Supply120006576-021LOGIC LEVEL, INx (V)I D D (µA )100806040202468101214Figure 11. I DD vs. Logic Level0.5–0.5–151506576-022INPUT VOLTAGE (V)C H A R G E I N J E C T I O N (p C )–10–5510Figure 12. Charge Injection vs. Source Voltage3000–4012006576-023TEMPERATURE (ºC)T I M E (n s )–20020406080100Figure 13. T ON /T OFF Times vs. Temperature–12010k1G06576-016FREQUNCY (Hz)O F F I S O L A T I O N (d B )100k 1M 10M 100M –20–40–60–80–100Figure 14. Off Isolation vs. FrequencyADG1201/ADG1202Rev. 0 | Page 9 of 16–1410k1G06576-0017FREQUNCY (Hz)I N S E R T I O N L O S S (d E )100k 1M 10M 100M0–2–4–6–8–10–12Figure 15. On Response vs. FrequencyFREQUENCY (Hz)T H D + N (%)1010.10.01101001k10k 100k06576-024Figure 16. THD + N vs. Frequency–151506576-018INPUT VOLTAGE (V)C A P A C I T A N C E (p F )–10–5510Figure 17. Capacitance vs. Input Voltage, Dual Supply201206576-019INPUT VOLTAGE (V)C A P A C I T A N C E (p F )65.554.543.532.5246810Figure 18. Capacitance vs. Input Voltage, Single Supply0–10006576-025FREQUENCY (Hz)A C P S R R (dB )–10–20–30–40–50–60–70–80–90Figure 19. ACPSRR vs. FrequencyADG1201/ADG1202Rev. 0 | Page 10 of 16TEST CIRCUITSV 06576-008Figure 20. On ResistanceV S06576-009Figure 21. Off Leakage06576-010Figure 22. On LeakageOFF ISOLATION = 20 LOGOUT V S06576-013Figure 23. Off IsolationINSERTION LOSS = 20 LOGOUT V OUT WITHOUT SWITCH06576-014Figure 24. BandwidthV V 06576-015Figure 25. THD + NoiseV SVV INV INV OUT6576-11Figure 26. Switching TimesADG1201V INV INV OUTOFFONV V6576-12 Figure 27. Charge InjectionTERMINOLOGYI DDThe positive supply current.I SSThe negative supply current.V D (V S)The analog voltage on Terminal D and Terminal S.R ONThe ohmic resistance between D and S.R FLAT(ON)Flatness is defined as the difference between the maximum and minimum value of on resistance, as measured over the specified analog signal range.I S (Off)The source leakage current with the switch off.I D (Off)The drain leakage current with the switch off.I D, I S (On)The channel leakage current with the switch on.V INLThe maximum input voltage for Logic 0.V INHThe minimum input voltage for Logic 1.I INL (I INH)The input current of the digital input.C S (Off)The off switch source capacitance, measured with referenceto ground.C D (Off)The off switch drain capacitance, measured with referenceto ground. C D, C S (On)The on switch capacitance, measured with reference to ground.C INThe digital input capacitance.t ONThe delay between applying the digital control input and the output switching on. See Figure 26.t OFFThe delay between applying the digital control input and the output switching off. See Figure 26.Charge InjectionA measure of the glitch impulse transferred from the digital input to the analog output during switching.Off IsolationA measure of unwanted signal coupling through an off switch. CrosstalkA measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. BandwidthThe frequency at which the output is attenuated by 3 dB.On ResponseThe frequency response of the on switch.Insertion LossThe loss due to the on resistance of the switch.THD + NThe ratio of the harmonic amplitude plus noise of the signal to the fundamental.ACPSRR (AC Power Supply Rejection Ratio)Measures the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation isthe ACPSRR.OUTLINE DIMENSIONS0.220.08COMPLIANT TO JEDEC STANDARDS MO-178-ABFigure 28. 6-Lead Small Outline Transistor Package [SOT-23](RJ-6)Dimensions shown in millimetersORDERING GUIDEModel Temperature Range Package Description Package Option Branding ADG1201BRJZ-R21 −40°C to +125°C 6-Lead Small Outline Transistor Package [SOT-23] RJ-6 S25 ADG1201BRJZ-REEL71 −40°C to +125°C 6-Lead Small Outline Transistor Package [SOT-23] RJ-6 S25ADG1202BRJZ-R21−40°C to +125°C 6-Lead Small Outline Transistor Package [SOT-23] RJ-6 S26 ADG1202BRJZ-REEL71 −40°C to +125°C 6-Lead Small Outline Transistor Package [SOT-23] RJ-6 S261Z = RoHS Compliant Part.NOTESNOTESNOTES©2008 Analog Devices, Inc. All rights reserved. Trademarks andregistered trademarks are the property of their respective owners.D06576-0-2/08(0)。

FPGA可编程逻辑器件芯片AD8629ARZ-REEL7中文规格书

VOS −55°C ≤ TA ≤ +125°C
IB −55°C ≤ TA ≤ +125°C
IOS −55°C ≤ TA ≤ +125°C
CMRR AVO ∆VOS/∆T
VCM = 0 V to 5 V −55°C ≤ TA ≤ +125°C RL = 10 kΩ, VO = 0.3 V to 4.7 V −55°C ≤ TA ≤ +125°C −55°C ≤ TA ≤ +125°C
AD8629-EP
PIN CONFIGURATION
OUT A 1 –IN A 2 +IN A 3 V– 4
AD8629-EP
TOP VIEW (Not to Scale)
8 V+ 7 OUT B 6 –IN B 5 +IN B
12890-001
Figure 1. 8-Lead SOIC_N (R-8)
1 The differential input voltage is limited to ±5 V or the supply voltage, whichever is less.
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

AD7729ARUZ-REEL;AD7729ARUZ-REEL7;AD7729ARZ-RL;AD7729ARU-REEL;中文规格书,Datasheet资料

REV.0Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.aAD7729One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781/329-4700World Wide Web Site: Fax: 781/326-8703© Analog Devices, Inc., 1998Dual Sigma-Delta ADC with Auxiliary DACFUNCTIONAL BLOCK DIAGRAMASDI ASDIFS ASCLK ASDO ASDOFSASEBSDI BSDIFS BSCLK BSDO BSDOFSBSEMCLK RxON RESETBAUXDACIRxP IRxNQRxP QRxNREFCAP REFOUTFEATURES+3 V Supply VoltageBaseband Serial Port (BSPORT)Differential IRx and QRx ADC ChannelsTwo 15-Bit Sigma-Delta A/D Converters FIR Digital Filters 64 dB SNROutput Word Rate 270.83 kHz Twos Complement Coding On-Chip Offset Calibration Power-Down Mode Auxiliary D/A ConverterAuxiliary Serial Port (ASPORT)On-Chip Voltage Reference Low Power28-Lead TSSOP/28-Lead SOIC APPLICATIONS GSM Basestations PagersGENERAL DESCRIPTIONThis monolithic 3 V CMOS device is a low power, two-channel,input port with signal conditioning. The receive path is com-posed of two high performance sigma-delta ADCs with digital filtering. A common bandgap reference feeds the ADCs.A control DAC is included for such functions as AFC. The auxil-iary functions can be accessed via the auxiliary port (ASPORT).This device is available in a 28-lead TSSOP package or a 28-lead SOIC package./–2–REV. 0AD7729–SPECIFICATIONS 1ParameterAD7729A Units Test Conditions/CommentsREFERENCE REFCAPAbsolute Voltage, V REFCAP 1.3 ± 5%V min/max REFCAP TC 50ppm/°C typ 0.1µF Capacitor Required from REFCAP to AGNDREFOUTAbsolute Voltage, V REFOUT 1.3 ± 10%V min/max REFOUT TC 50ppm/°C typ 0.1µF Capacitor Required from REFOUT to AGND ADC CHANNEL SPECIFICATIONS RxON = 1Resolution15Bits ADC Signal Range 2 V REFCAPV p-p V BIASV REFCAP /2 to (AVDD – V REFCAP /2)Volts Differential V REFCAP to (AVDD – V REFCAP )VoltsSingle-EndedDifferential Signal Range V BIAS ± V REFCAP /2V min/max For Both Positive and Negative Analog InputsSingle-Ended Signal Range V BIAS ± V REFCAP V min/max For Positive Analog Inputs; Negative Analog Inputs = V BIASInput Sample Rate 13MSPS Output Word Rate 270.83kHz DC AccuracyPrecalibration Offset Error ±45mV typ Post Calibration Offset Error ±10mV max Post Calibration Offset Error TC 50µV/°C typ TC = Temperature CoefficientInput Resistance (DC) 1.23M Ω typ Input Capacitance10pF typ Dynamic Specifications Input Frequency = 67.7 kHzDynamic Range67dB typ Signal to (Noise + Distortion)64dB min Gain Error±1dB max Input Frequency = 67.7 kHz, wrt 1.3 V ±0.5dB max Input Frequency = 67.7 kHz, wrt V REFCAPGain Match Between Channels ±0.2dB max Filter Settling Time 47µs typ Frequency Response Does Not Include Input Antialias RC Circuit0kHz–70 kHz ±0.05dB max/min 85 kHz –1dB max 96 kHz –3.0dB max 135 kHz –55dB max >170 kHz–55dB max Absolute Group Delay23µs typ Group Delay Between Channels (0 kHz–96 kHz)5ns typCodingTwos Complement AUXILIARY CONVERTER 2Resolution 10Bits Output Range Code 0002/32 × V REFCAP VOffset Error ±35mV max Code 3FF 2 V REFCAP VGain Error –60mV min +100mV maxDC AccuracyMaximum Output for Specified Accuracy = AVDD –0.2V or 2.6 V, Whichever Is LowerIntegral Nonlinearity ±4LSB max Differential Nonlinearity ±2LSB max Guaranteed Monotonic to 9 Bits Update Rate 540kHz max Load Resistance 10k Ω min See Figure 1Load Capacitance 50pF max See Figure 1I SINK50µA typ Full-Scale Settling Time 4µs typ LSB Settling Time 2µs typCodingBinary(AVDD1 = AVDD2 = +3 V ؎ 10%; DVDD1 = DVDD2 = +3 V ؎ 10%; DGND = AGND =0V, f CLK= 13 MHz; RxPOWER1 = 0; RxPOWER0 = 1; MCLKDIV = 0; T A= T MINto T MAXunless otherwise noted)/–3–REV. 0AD7729The above values are in mA. /AD7729–4–REV. 0TIMING CHARACTERISTICSLimit atParameterT A = –40؇C to +105؇CUnitsDescriptionAUXILIARY FUNCTIONS Clock Signals See Figure 2.t 176ns min MCLK Period t 230.4ns min MCLK Width Low t 330.4ns min MCLK Width Hight 4t 1ns min ASCLK Period. See Figures 4 and 6.t 50.4 × t 1ns min ASCLK Width Low t 60.4 × t 1ns min ASCLK Width Hight 1020ns min ASDI/ASDIFS Setup Before ASCLK Low t 1110ns min ASDI/ASDIFS Hold After ASCLK Low t 1215ns max ASDOFS Delay from ASCLK High t 130ns min ASDOFS Hold After ASCLK High t 140ns min ASDO Hold After ASCLK High t 1515ns max ASDO Delay from ASCLK Hight 1610ns min ASDIFS Low to ASDI LSB Read by ASPORT t 17t 4 + 15ns minInterval Between Consecutive ASDIFS Pulses Receive Section Clock Signals See Figures 5 and 7.t 7t 1ns min BSCLK Period t 80.4 × t 1ns min BSCLK Width Low t 90.4 × t 1ns min BSCLK Width Hight 1820ns min BSDI/BSDIFS Setup Before BSCLK Low t 1910ns min BSDI/BSDIFS HoldAfter BSCLK Low t 2015ns max BSDOFS Delay from BSCLK High t 210ns min BSDOFS Hold After BSCLK High t 220ns min BSDO Hold After BSCLK High t 2315ns max BSDO Delay from BSCLK Hight 2410ns min BSDIFS Low to ASDI LSB Read by BSPORT t 25t 7 + 15ns minInterval Between Consecutive BSDIFS PulsesASCLK = MCLK/(2 × ASCLKRATE). ASCLKRATE can have a value from 0...1023. When ASCLKRATE = 0, ASCLK = 13 MHz.BSCLK = MCLK/(2 × BSCLKRATE). BSCLKRATE can have a value from 0...1023. When BSCLKRATE = 0, BSCLK = 13 MHz.Specifications subject to change without notice.(AVDD1 = AVDD2 = +3 V ؎ 10%; DVDD1 = DVDD2 = +3 V ؎ 10%; AGND = DGND = 0 V;T A = T MIN to T MAX , unless otherwise noted)Table II.Receive Section Signal RangesBaseband Section Signal Range V REFCAP 1.3 V ± 5%V REFOUT1.3 V ± 10%ADCADC Signal Range 2 V REFCAPV BIASDifferential Input V REFCAP /2 to (AVDD1 – V REFCAP /2)Single-Ended Input V REFCAP to (AVDD1 – V REFCAP )Signal Range Differential V BIAS ± V REFCAP /2Single-EndedV BIAS ± V REFCAPTable III.Auxiliary Section Signal RangesAUXDAC Signal Range Output Code Code 0002/32 × V REFCAP Code 3FF2 V REFCAP/AD7729–5–REV. 0TIMING DIAGRAMSNOTEFigure 6.Auxiliary Serial Port ASPORTBSE (I)BSCLK (O)BSDIFS (I)BSDOFS (O)BSDI (I)BSDO (O)Figure 7.Baseband Serial Port BSPORTFigure 2.Clock TimingTO OUTPUT PINFigure 3.Load Circuit for Timing SpecificationsMCLK*ASCLK *ASCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE).Figure 4.ASCLKMCLK*BSCLK*BSCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE).Figure 5.BSCLK/AD7729–6–REV. 0ABSOLUTE MAXIMUM RATINGS*(T A = +25°C unless otherwise stated)AVDD, DVDD to GND . . . . . . . . . . . . . . . . –0.3 V to +7 V AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Digital I/O Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V Analog I/O Voltage to AGND . . . . –0.3 V to AVDD + 0.3 V Operating Temperature RangeIndustrial (A Version) . . . . . . . . . . . . . . . –40°C to +105°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C TSSOPθJA Thermal Impedance . . . . . . . . . . . . . . . . . . . +122°C/W Lead Temperature, SolderingVapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C SOICθJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . +72°C/W Lead Temperature, SolderingVapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C*Stresses above those listed under Absolute Maximum Ratings may cause perma-nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.ORDERING GUIDETemperature PackagePackage Model Range Descriptions OptionsAD7729AR–40°C to +105°C Small Outline IC R-28(SOIC)AD7729ARU –40°C to +105°C Thin Shrink Small RU-28Outline (TSSOP)CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection.Although the AD7729 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.PIN CONFIGURATION/AD7729–7–REV. 0PIN FUNCTION DESCRIPTIONSPinNumber Mnemonic Function15MCLK Master Clock Input. MCLK is driven from a 13 MHz crystal. The active levels for MCLK are determined by the value of DVDD2.13RESETBActive Low Reset Signal. This input resets the entire AD7729 chip, resetting the control registers and clearing the digital filters. The logic input levels (V INH and V INL ) for RESETB are determined by the value of DVDD2.Power Supply 6AVDD1Analog Power Supply Connection for the Rx Section and the Bandgap Reference.5AVDD2Analog Power Supply Connection for the Auxiliary Section.7AGND Analog Ground Connection.25DVDD1Digital Power Supply Connection.24DVDD2Digital Power Supply Connection for the Serial Interface Section. This power supply also sets the threshold voltages for RxON, RESETB and MCLK.23DGNDDigital Ground Connection.Analog Signal and Reference 1, 2IRxP, IRxN Differential Analog Input for I Receive Channel.3, 4QRxP, QRxN Differential Analog Input for Q Receive Channel.26AUXDAC Analog Output Voltage from the 10-Bit Auxiliary DAC AUXDAC. This DAC is used for functions such as Automatic Gain Control (AGC). The DAC possesses a register that is accessible via the ASPORT or BSPORT. The DAC may be individually powered down.28REFCAP A bypass capacitor to AGND of 0.1 µF is required for the on-chip reference. The capacitor should be fixed to this pin.27REFOUTBuffered Reference Output, which has a nominal value of 1.3 V. A bypass capacitor (to AGND) of 0.1 µF is required on this pin.Auxiliary Serial Port (ASPORT)10ASCLK Serial Clock used to clock data or control bits to and from the auxiliary serial port (ASPORT).The frequency of ASCLK is programmable and is equal to the frequency of the master clock (MCLK) divided by an integer number.9ASDI Serial Data Input of ASPORT. Both data and control information are input on this pin.8ASDIFS Input Framing Signal for ASDI Serial Transfers.20ASDO Serial Data Output of ASPORT. Both data and control information are output on this pin.ASDO is in three-state when no information is being transmitted, thereby allowing external control.21ASDOFS Output Framing Signal for ASDO Serial Transfers.22ASEASPORT Enable. When ASE is low, the ASPORT is put into three-state thereby allowing external control of the serial bus.Baseband Serial Port (BSPORT)16BSCLK Output serial clock used to clock data or control bits to and from the baseband serial port (BSPORT). The frequency of BSCLK is programmable and is equal to the frequency of the master clock (MCLK) divided by an integer number.12BSDI Serial Data Input of BSPORT. Both data and control information are input on this pin.11BSDIFS Input Framing Signal for BSDI Serial Transfers.17BSDO Serial Data Output of BSPORT. Both data and control information are output on this pin.BSDO is in three-state when no information is being transmitted, thereby allowing external control.18BSDOFS Output Framing Signal for BSDO Serial Transfers.19BSE BSPORT Enable. When BSE is low, the BSPORT is put into three-state thereby allowing external control of the serial bus.ADCs 14RxONReceive Section Power-On Digital Input. The receive section is powered up by taking pin RxON high. The receive section can alternatively be powered up by programming bit RxON in baseband control register BCRA. When the powering up/down of the receive section isbeing controlled by pin RxON, bit RxON should equal zero. Similarly, when the powering up/down of the receive section is being controlled by bit RxON, pin RxON should be tied low.The logic input levels (V INH and V INL ) for RxON are determined by the value of DVDD2./AD7729–8–REV. 0TERMINOLOGYAbsolute Group DelayAbsolute group delay is the rate of change of phase versus fre-quency, dø/df. It is expressed in microseconds.Differential NonlinearityThis is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the DAC or ADC.Dynamic RangeDynamic Range is the ratio of the maximum output signal to the smallest output signal the converter can produce (1 LSB), ex-pressed logarithmically, in decibels (dB = 201og 10 (ratio)). For an N-bit converter, the ratio is theoretically very nearly equal to 2N (in dB, 20Nlog10(2) = 6.02N). However, this theoretical value is degraded by converter noise and inaccuracies in the LSB weight.Gain ErrorThis is a measure of the output error between an ideal DAC and the actual device output with all 1s loaded after offset error has been adjusted out. In the AD7729, gain error is specified for the auxiliary section.Gain Matching Between ChannelsThis is the gain matching between the IRx and QRx channel and is expressed in dBs.Group Delay Between ChannelsThis is the difference between the group delay of the I and Q channels and is a measure of the phase matching characteristics of the two.Integral NonlinearityThis is the maximum deviation from a straight line passing through the endpoints of the auxiliary DAC transfer function.Output RateThis is the rate at which data words are made available (270.833 kHz).Offset ErrorThis is the amount of offset, wrt V REF in the auxiliary DAC and is expressed in mVs.Output Signal SpanThis is the output signal range for the auxiliary DAC section.Sampling RateThis is the rate at which the modulators on the receive channels sample the analog input.Settling TimeThis is the digital filter settling time in the AD7729 receive section. On initial power-up or after returning from the power-down mode, it is necessary to wait this amount of time to get useful data.Signal Input SpanThe input signal range for the I and Q channels is biased about V REF .Signal to (Noise + Distortion) RatioThis is the measured ratio of signal to (noise + distortion) at the output of the receive channel. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f S /2), excluding dc.The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quan-tization noise. The theoretical signal to (noise + distortion) ratio for a sine wave is given by:Signal to (Noise + Distortion ) = (6.02N + 1.76) dB/AD7729–9–REV. 0FUNCTIONAL DESCRIPTIONBASEBAND CODEC Receive SectionThe receive section consists of I and Q receive channels, each comprising of a simple switched-capacitor filter followed by a 15-bit sigma-delta ADC. On-board digital filters, which form part of the sigma-delta ADCs, also perform critical system-level filtering. Their amplitude and phase response characteristics provide excellent adjacent channel rejection. The receive sec-tion is also provided with a low power sleep mode to place the receive section on standby between receive bursts, drawing only minimal current.Switched Capacitor InputThe receive section analog front-end is sampled at 13 MHz by a switched-capacitor filter. The filter has a zero at 6.5 MHz as shown in Figure 8a. The receive channel also contains a digital low-pass filter (further details are contained in the following section) which operates at a clock frequency of 6.5 MHz. Due to the sampling nature of the digital filter, the passband is re-peated about the operating clock frequency and at multiples of the clock frequency (Figure 8b). Because the first null of the switched-capacitor filter coincides with the first image of the digital filter, this image is attenuated by an additional 30 dBs (Figure 8c), further simplifying the external antialiasing require-ments (see Figures 9 and 10).FRONT-END ANALOG FILTERTRANSFER FUNCTIONa)Switched-Cap Filter Frequency ResponseMHzDIGITAL FILTERTRANSFER FUNCTIONb)Digital Filter Frequency ResponseSYSTEM FILTERTRANSFER FUNCTIONc)Overall System Response of the Receive ChannelFigure 8.The circuitry of Figure 9 implements first-order low-pass filters with a 3 dB point at 338 kHz; these are the only filters that must be implemented external to the baseband section to pre-vent aliasing of the sampled signal.Figure 9.Example Circuit for Differential InputFigure 10 shows the recommended single-ended analog input circuit.V Figure 10.Example Circuit for Single-Ended Input/AD7729–10–REV. 0V BIAS + V REF /2V BIASV BIAS – V REF /2V O L T A G EIRxN QRxNIRxP QRxP10 (00)00 ... 0001 (11)ADC CODEFigure 11.ADC Transfer Function for Differential OperationV BIAS + V REFV BIASV BIAS – V REFV O L T A G EIRxN QRxNIRxP QRxP10 (00)00 ... 0001 (11)ADC CODEFigure 12.ADC Transfer Function for Single-Ended Operation Sigma-Delta ADCThe AD7729 receive channels employ a sigma-delta conversion technique, which provides a high-resolution 15-bit output for both I and Q channels with system filtering being implemented on-chip.The output of the switched-capacitor filter is continuously sampled at 6.5 MHz (master clock/2), by a charge-balanced modulator, and is converted into a digital pulse train whose duty cycle contains the digital information. Due to the high oversampling rate, which spreads the quantization noise from 0MHz to 3.25MHz (F S /2), the noise energy contained in the band of interest is reduced (Figure 13a). To reduce the quanti-zation noise still further, a high order modulator is employed to shape the noise spectrum, so that most of the noise energy is shifted out of the band of interest (Figure 13b).The digital filter that follows the modulator removes the large out-of-band quantization noise (Figure 13c), while converting the digital pulse train into parallel 15-bit-wide binary data. The15-bit I and Q data, which is in twos complement format, is made available via a serial port.INTEREST3.25MHza) Effect of High Oversampling RatioBAND OF INTEREST3.25MHzb) Use of Noise Shaping to Further Improve SNRBAND OF INTEREST3.25MHzc) Use of Digital Filtering to Remove the Out- of-Band Quantization Noise Figure 13.Digital FilterThe digital filters used in the AD7729 receive section carry out two important functions. Firstly, they remove the out-of-band quantization noise which is shaped by the analog modulator.Secondly, they are also designed to perform system level filter-ing, providing excellent rejection of the neighboring channels.Digital filtering has certain advantages over analog filtering.Firstly, since digital filtering occurs after the A/D conversion process, it can remove noise injected during the conversion process. Analog filtering cannot do this. Secondly, the digital filter combines low passband ripple with a steep roll-off, while also maintaining a linear phase response. This is very difficult to achieve with analog filters.However, analog filtering can remove noise superimposed on the analog signal before it reaches the ADC. Digital filtering cannot do this and noise peaks riding on signals near full-scale have the potential to saturate the analog modulator, even though the average value of the signal is within limits. To allevi-ate this problem, the AD7729 has overrange headroom built into the sigma-delta modulator and digital filter which allows overrange excursions of 100 mV./分销商库存信息:ANALOG-DEVICESAD7729ARUZ-REEL AD7729ARUZ-REEL7AD7729ARZ-RL AD7729ARU-REEL AD7729ARU-REEL7AD7729ARZ AD7729ARUZ AD7729ARU。

FPGA可编程逻辑器件芯片AD822ARZ-REEL7中文规格书

Good dc performance 800 µV maximum input offset voltage 2 µV/°C typical offset voltage drift 25 pA maximum input bias current
Low noise 13 nV/√Hz at 10 kHz No phase inversion
TMIN to TMAX
Test Conditions/Comments VCM = 0 V to 2 V VCM = 0 V to 2 V
ISINK = 20 µA ISOURCE = 20 µA ISINK = 2 mA ISOURCE = 2 mA ISINK = 15 mA ISOURCE = 15 mA
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AD822
ABSOLUTE MAXIMUM RATINGS
Table 4. Parameter Supply Voltage Internal Power Dissipation
8-Lead PDIP (N) 8-Lead SOIC_N (R) 8-Lead MSOP (RM) Input Voltage1
2 VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference between the highest possible output voltage (VOH) and the positive supply voltage (VCC).