STK401-130中文资料

合集下载

zl30109中文资料_数据手册_IC数据表

1Features•Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E•Supports ITU-T G.823 and G.824 for 2048kbit/s and 1544kbit/s interfaces•Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces •Simple hardware control interface•Accepts two input references and synchronizes to any combination of 2kHz, 8kHz, 1.544MHz,2.048MHz, 8.192MHz, 16.384MHz or 19.44MHz inputs•Provides a range of clock outputs: 1.544MHz, 2.048MHz, 16.384MHz, 19.44MHz and either 4.096MHz and 8.192MHz or 32.768MHz and 65.536MHz•Hitless reference switching between anycombination of valid input reference frequencies •Provides 5 styles of 8kHz framing pulses and a 2kHz multi-frame pulse•Holdover frequency accuracy of 1.5 x 10-7•Lock, Holdover and selectable Out of Range indication•Selectable loop filter bandwidth of 1.8Hz or 922Hz•Less than 24 ps rms intrinsic jitter on the19.44MHz output clock, compliant with OC-3 and STM-1 jitter specifications•Less than 0.6ns pp intrinsic jitter on all output clocks•External master clock source: clock oscillator or crystalApplications•Synchronization and timing control for DSLAM, Gateway and PBX systems that require Stratum 4/4E timing•Line Card synchronization for SDH/PDH applications•Clock and frame pulse source for ST-BUS, GCI and other time division multiplex (TDM) busesNovember 2005ZL30109DS1/E1 System Synchronizer with19.44MHz OutputData SheetFigure 1 - Functional Block DiagramReference MonitorMode ControlVirtual ReferenceIEEE 1149.1aFeedbackTIE Corrector EnableState MachineFrequency Select MUXTIE Corrector CircuitMODE_SEL1:0TCK REF1RSTREF_SELTIE_CLROSCo OSCi Master ClockTDOREF0TDI TMS TRSTHOLDOVER BW_SEL HMS LOCK REF_FAIL0REF_FAIL1DPLLOUT_SELMUXOOR_SEL C2oE1SynthesizerDS1SynthesizerSONET/SDH SynthesizerC4/C65o C8/C32o C16o F4/F65o F8/F32o C1.5o C19o F2koF16o Ordering InformationZL30109QDG 64 Pin TQFP Trays, Bake & Drypack ZL30109QDG164 pin TQFP*Trays, Bake & Drypack*Pb Free Matte Tin -40°C to +85°CZL30109Data Sheet DescriptionThe ZL30109 DS1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk DS1 and E1 transmission equipment. The 19.44MHz output makes the ZL30109 also suitable for SDH line card applications.The ZL30109 generates a 19.44MHz clock and ST-BUS and TDM bus clocks and framing signals that are phase locked to one of two input references. It helps ensure system reliability by monitoring its references for accuracy and stability and by maintaining stable output clocks during reference switching operations and during short periods when a reference is unavailable.The ZL30109 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.ZL30109Data SheetTable of Contents1.0 Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52.0 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62.1 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103.1 Reference Select Multiplexer (MUX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103.2 Reference Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103.3 Time Interval Error (TIE) Corrector Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133.4 Digital Phase Lock Loop (DPLL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163.5 Frequency Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173.6 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173.7 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174.0 Control and Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174.1 Out of Range Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174.2 Loop Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184.3 Output Clock and Frame Pulse Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184.4 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184.4.1 Freerun Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184.4.2 Holdover Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194.4.3 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194.5 Reference Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205.0 Measures of Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215.1 Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215.2 Jitter Generation (Intrinsic Jitter). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215.3 Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215.4 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215.5 Frequency Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225.6 Holdover Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225.7 Pull-in Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225.8 Lock Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225.9 Phase Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225.10 Time Interval Error (TIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225.11 Maximum Time Interval Error (MTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225.12 Phase Continuity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225.13 Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226.0 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236.1 Power Supply Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236.2 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236.2.1 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236.2.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246.3 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246.4 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257.0 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267.2 Performance Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33ZL30109Data SheetList of FiguresFigure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3 - Reference Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4 - Behaviour of the Dis/Re-qualify Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5 - DS1 Mode Out-of-Range Limits (OOR_SEL=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6 - E1 Mode Out-of-Range Limits (OOR_SEL=1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 7 - Timing Diagram of Hitless Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 8 - Timing Diagram of Hitless Mode Switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 9 - DPLL Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 10 - Mode Switching in Normal Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 11 - Reference Switching in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 12 - Clock Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 13 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 14 - Power-Up Reset Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 15 - Timing Parameter Measurement Voltage Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 16 - Input to Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 17 - Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 18 - SONET/SDH Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32ZL30109Data Sheet1.0 Change SummaryChanges from July 2005 Issue to November 2005 Issue. Page, section, figure and table numbers refer to this current issue.Changes from November 2004 Issue to July 2005 Issue. Page, section, figure and table numbers refer to this current issue.Page Item Change1Features Added description for hitless reference switching.23Section 6.1Removed power supply decoupling circuit and includedreference to synchronizer power supply decoupling application note.Page Item Change8RST pin Specified clock and frame pulse outputs forced to high impedance.10REF0 pinSpecified seven possible reference input frequencies.27Table “DC Electrical Characteristics*“Corrected Schmitt trigger levels.33Table “Performance Characteristics* - Functional“Gave more detail on Lock Time conditions.ZL30109Data Sheet2.0 Physical Description2.1 Pin ConnectionsFigure 2 - Pin Connections (64 pin TQFP, please see Note 1)Note 1: The ZL30109 uses the TQFP shown in the package outline designated with the suffix QD, the ZL30109does not use the e-Pad TQFP .ZL3010934363840424446486462605856525054161412108642OSCo NC GND OUT_SEL C1.5o MODE_SEL1V DD AV DD IC NC RSTNC AGNDF4/F65o V DD REF1NC ICC 8/C 32o F 2k o C 2o A G N DA V D DC 19o F 8/F 32o C 4/C 65o REF_SEL1820222426303228C 16o F16o TIE_CLR OOR_SELICOSCi A V D DA V D DA V D DA V C O R EA G N D A G N D A G N D NC NC IC ICMODE_SEL0NC BW_SELREF0V C O R EL O C K H M ST R S T G N DT D O T M S H O L D O V E R I C T C K T D I V C O R EA V C O R EG N D R E F _F A I L 0R E F _F A I L 1ZL30109Data Sheet2.2 Pin DescriptionPin DescriptionPin # Name Description1GND Ground. 0 V.2V CORE Positive Supply Voltage. +1.8 V DC nominal.3LOCK Lock Indicator (Output). This output goes to a logic high when the PLL is frequencylocked to the selected input reference.4HOLDOVER Holdover (Output). This output goes to a logic high whenever the PLL goes intoholdover mode.5REF_FAIL0Reference 0 Failure Indicator (Output). A logic high at this pin indicates that the REF0 reference frequency has exceeded the out-of-range limit set by the OOR_SEL pin or thatit is exhibiting abrupt phase or frequency changes.6IC Internal bonding Connection. Leave unconnected.7REF_FAIL1Reference 1 Failure Indicator (Output). A logic high at this pin indicates that the REF1 reference frequency has exceeded the out-of-range limit set by the OOR_SEL pin or thatit is exhibiting abrupt phase or frequency changes.8TDO Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled.9TMS Test Mode Select (Input). JTAG signal that controls the state transitions of the TAPcontroller. This pin is internally pulled up to V DD. If this pin is not used then it should beleft unconnected.10TRST Test Reset (Input). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-up to ensure thatthe device is in the normal functional state. This pin is internally pulled up to V DD. Ifthis pin is not used then it should be connected to GND.11TCK Test Clock (Input): Provides the clock to the JTAG test logic. If this pin is not used then it should be pulled down to GND.12V CORE Positive Supply Voltage. +1.8 V DC nominal.13GND Ground. 0 V.14AV CORE Positive Analog Supply Voltage. +1.8 V DC nominal.15TDI Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to V DD. If this pin is not used then it should be leftunconnected.16HMS Hitless Mode Switching (Input). The HMS circuit controls phase accumulation during the transition from Holdover or Freerun mode to Normal mode on the same reference. Alogic low at this pin will cause the ZL30109 to maintain the delay stored in the TIEcorrector circuit when it transitions from Holdover or Freerun mode to Normal mode. Alogic high on this pin will cause the ZL30109 to measure a new delay for its TIE correctorcircuit thereby minimizing the output phase movement when it transitions from Holdoveror Freerun mode to Normal mode.17MODE_SEL0Mode Select 0 (Input). This input combined with MODE_SEL1 determines the mode(Normal, Holdover or Freerun) of operation, see Table4 on page18.18MODE_SEL1Mode Select 1 (Input). See MODE_SEL0 pin description.ZL30109Data Sheet Pin Description (continued)Pin # Name Description19RST Reset (Input). A logic low at this input resets the device. On power up, the RST pin must be held low for a minimum of 300ns after the power supply pins have reachedthe minimum supply voltage. When the RST pin goes high, the device will transitioninto a Reset state for 3ms. In the Reset state all clock and frame pulse outputs will beforced into high impedance.20OSCo Oscillator Master Clock (Output). For crystal operation, a 20MHz crystal is connected from this pin to OSCi. This output is not suitable for driving other devices. For clockoscillator operation, this pin must be left unconnected.21OSCi Oscillator Master Clock (Input). For crystal operation, a 20MHz crystal is connected from this pin to OSCo. For clock oscillator operation, this pin must be connected to aclock source.22IC Internal Connection. Leave unconnected.23GND Ground. 0V.24NC No internal bonding Connection. Leave unconnected.25V DD Positive Supply Voltage. +3.3 V DC nominal.26OUT_SEL Output Selection (Input).This input selects the signals on the combined output clock and frame pulse pins, see Table3 on page18.27IC Internal Connection. Connect this pin to ground.28IC Internal Connection. Connect this pin to ground.29AV DD Positive Analog Supply Voltage. +3.3 V DC nominal.30NC No internal bonding Connection. Leave unconnected.31NC No internal bonding Connection. Leave unconnected.32C1.5o Clock 1.544MHz (Output). This output is used in DS1 applications.This clock output pad includes a Schmitt input which serves as a PLL feedback path;proper transmission-line termination should be applied to maintain reflections belowSchmitt trigger levels.33AGND Analog Ground. 0 V34AGND Analog Ground. 0 V35AV CORE Positive Analog Supply Voltage. +1.8 V DC nominal.36AV DD Positive Analog Supply Voltage. +3.3 V DC nominal.37AV DD Positive Analog Supply Voltage. +3.3 V DC nominal.38F2ko Multi Frame Pulse (Output). This is a 2kHz 51ns active high framing pulse, whichmarks the beginning of a multi frame.This clock output pad includes a Schmitt input which serves as a PLL feedback path;proper transmission-line termination should be applied to maintain reflections belowSchmitt trigger levels.ZL30109Data Sheet Pin Description (continued)Pin # Name Description39C19o Clock 19.44MHz (Output). This output is used in SONET/SDH applications.This clock output pad includes a Schmitt input which serves as a PLL feedback path;proper transmission-line termination should be applied to maintain reflections belowSchmitt trigger levels.40AGND Analog Ground.0V41AGND Analog Ground.0V42C4/C65o Clock 4.096MHz or 65.536MHz (Output). This output is used for ST-BUS operation at2.048Mbps, 4.096Mbps or 65.536MHz (ST-BUS 65.536Mbps). The output frequency isselected via the OUT_SEL pin.43C8/C32o Clock 8.192MHz or 32.768MHz (Output). This output is used for ST-BUS and GCIoperation at 8.192Mbps or for operation with a 32.768MHz clock. The output frequencyis selected via the OUT_SEL pin.44AV DD Positive Analog Supply Voltage. +3.3 V DC nominal.45AV DD Positive Analog Supply Voltage. +3.3 V DC nominal.46C2o Clock 2.048MHz (Output). This output is used for standard E1 interface timing and for ST-BUS operation at 2.048Mbps.This clock output pad includes a Schmitt input which serves as a PLL feedback path;proper transmission-line termination should be applied to maintain reflections belowSchmitt trigger levels.47C16o Clock 16.384MHz (Output). This output is used for ST-BUS operation with a16.384MHz clock.This clock output pad includes a Schmitt input which serves as a PLL feedback path;proper transmission-line termination should be applied to maintain reflections belowSchmitt trigger levels.48F8/F32o Frame Pulse (Output). This is an 8kHz 122ns active high framing pulse (OUT_SEL=0) or it is an 8kHz 31ns active high framing pulse (OUT_SEL=1), which marks thebeginning of a frame.This clock output pad includes a Schmitt input which serves as a PLL feedback path;proper transmission-line termination should be applied to maintain reflections belowSchmitt trigger levels.49F4/F65o Frame Pulse ST-BUS 2.048Mbps or ST-BUS at 65.536MHz clock (Output). Thisoutput is an 8kHz 244ns active low framing pulse (OUT_SEL=0), which marks thebeginning of an ST-BUS frame. This is typically used for ST-BUS operation at2.048Mbps and 4.096Mbps. Or this output is an 8kHz 15ns active low framing pulse(OUT_SEL=1), typically used for ST-BUS operation with a clock rate of 65.536MHz.50F16o Frame Pulse ST-BUS 8.192Mbps (Output). This is an 8kHz 61ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUSoperation at 8.192Mbps.51AGND Analog Ground.0V52IC Internal Connection. Connect this pin to ground.ZL30109Data Sheet Pin Description (continued)Pin # Name Description53REF_SEL Reference Select (Input). This input selects the input reference that is used forsynchronization, see Table5 on page20. This pin is internally pulled down to GND.54NC No internal bonding Connection. Leave unconnected.55REF0Reference (Input). This is one of two (REF0, REF1) input reference sources used forsynchronization. One of seven possible frequencies may be used: 2kHz, 8kHz,1.544MHz,2.048MHz, 8.192MHz, 16.384MHz, or 19.44MHz. This pin is internallypulled down to GND.56NC No internal bonding Connection. Leave unconnected.57REF1Reference (Input). See REF0 pin description.58NC No internal bonding Connection. Leave unconnected.59IC Internal Connection. Connect this pin to ground.60OOR_SEL Out Of Range Selection (Input). This pin selects the out of range reference rejection limits, see Table1 on page17.61V DD Positive Supply Voltage. +3.3 V DC nominal.62NC No internal bonding Connection. Leave unconnected.63TIE_CLR TIE Corrector Circuit Reset (Input). A logic low at this input resets the Time IntervalError (TIE) correction circuit resulting in a realignment of the input phase with the outputphase.64BW_SEL Filter Bandwidth Selection (Input). This pin selects the bandwidth of the DPLL loopfilter, see Table2 on page18. Set continuously high to track jitter on the input referenceclosely or set temporarily high to allow the ZL30109 to quickly lock to the input reference.3.0 Functional DescriptionThe ZL30109 is a DS1/E1 System Synchronizer providing timing (clock) and synchronization (frame) signals to interface circuits for DS1 and E1 Primary Rate Digital Transmission links and OC-3/STM-1 links, as well as a 19.44MHz output for SDH line card applications. Figure 1 is a functional block diagram which is described in the following sections.3.1 Reference Select Multiplexer (MUX)The ZL30109 accepts two simultaneous reference input signals and operates on their rising edges. One of them, the primary reference (REF0) or the secondary reference (REF1) signal can be selected as input to the TIE corrector circuit based on the reference selection (REF_SEL) input.3.2 Reference MonitorThe input references are monitored by two independent reference monitor blocks, one for each reference. The block diagram of a single reference monitor is shown in Figure 3. For each reference clock, the frequency is detected and the clock is continuously monitored for three independent criteria that indicate abnormal behavior of the reference signal, for example; long term drift from its nominal frequency or excessive jitter. To ensure proper operation of the reference monitor circuit, the minimum input pulse width restriction of 15nsec must be observed.ZL30109Data Sheet •Reference Frequency Detector : This detector determines whether the frequency of the reference clock is2kHz, 8kHz, 1.544MHz, 2.048MHz, 8.192MHz, 16.384MHz or 19.44MHz and provides this information to the various monitor circuits and the phase detector circuit of the DPLL.•Precise Frequency Monitor : This circuit determines whether the frequency of the reference clock is within the applicable out-of-range limits selected by the OOR_SEL pin, see Figure 5, Figure 6 and Table 1. It will take the precise frequency monitor up to 10 s to qualify or disqualify the input reference.•Coarse Frequency Monitor (CFM): This circuit monitors the reference frequency over intervals ofapproximately 30 µs to quickly detect large frequency changes.•Single Cycle Monitor (SCM): This detector checks the period of a single clock cycle to detect large phase hits or the complete loss of the clock.Figure 3 - Reference Monitor CircuitExceeding the thresholds of any of the monitors forces the corresponding REF_FAIL pin to go high. The single cycle and coarse frequency failure flags force the DPLL into Holdover mode and feed a timer that disqualifies the reference input signal when the failures are present for more than 2.5s. The single cycle and coarse frequency failures must be absent for 10s to let the timer re-qualify the input reference signal as valid. Multiple failures of less than 2.5s each have an accumulative effect and will disqualify the reference eventually. This is illustrated in Figure 4.Reference Frequency Detector Single Cycle Monitor Precise Frequency MonitorCoarse Frequency Monitor dis/requalify timerREF0 / REF1OR OR REF_DIS= reference disrupted.This is an internal signal.Mode select state machine HOLDOVERREF_DIS REF_FAIL0 / REF_FAIL1ZL30109Data SheetSCM or CFM failurecurrent REFtimer2.5 s10 sREF_FAILHOLDOVERFigure 4 - Behaviour of the Dis/Re-qualify TimerWhen the incoming signal returns to normal (REF_FAIL=0), the DPLL returns to Normal mode with the output signal locked to the input signal. Each of the monitors has a built-in hysteresis to prevent flickering of the REF_FAIL status pin at the threshold boundaries. The precise frequency monitor and the timer do not affect the mode (Holdover/Normal) of the DPLL.Figure 5 - DS1 Mode Out-of-Range Limits (OOR_SEL=0)。

ISP1301中文资料

ISP1301Universal Serial Bus On-The-Go transceiverRev. 01 — 14 April 2004Product data1.General descriptionThe ISP1301 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver devicethat is fully compliant with Universal Serial Bus Speciﬁcation Rev.2.0and On-The-GoSupplement to the USB Speciﬁcation Rev.1.0a. The ISP1301 can transmit andreceive serial data at both full-speed (12Mbit/s) and low-speed (1.5Mbit/s) datarates.It is ideal for use in portable electronics devices, such as mobile phones, digital stillcameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audioplayers. It allows USB Application Speciﬁc Integrated Circuits (ASICs),Programmable Logic Devices (PLDs) and any system chip set (with the USB host ordevice function built-in but without the USB physical layer)to interface to the physicallayer of the USB.The ISP1301 can interface to devices with digital I/O voltages in the range of1.65V to3.6V.The ISP1301 is available in HVQFN24 package.2.Featuress Fully complies with:x Universal Serial Bus Speciﬁcation Rev.2.0x On-The-Go Supplement to the USB2.0 Speciﬁcation Rev.1.0ax On-The-Go Transceiver Speciﬁcation (CEA–2011) Rev.1.0s Can transmit and receive serial data at both full-speed (12Mbit/s) and low-speed(1.5Mbit/s) data ratess Ideal for system ASICs or chip sets with built-in USB OTG dual-role cores Supports mini USB analog car kit interfaces Supports various serial data interface protocols; transparent general-purposebuffer mode allows you to control the direction of data transfers Supports data line and V BUS pulsing session requests Contains Host Negotiation Protocol (HNP) command and status registerss Supports serial I2C-bus™ interface for OTG status and command controlss 2.7V to4.5V power supply input range for the ISP1301s Built-in charge pump regulator outputs 5V at current greater than 8mAs Supports external charge pumps Supports wide range interfacing I/O voltage(V DD_LGC=1.65V to3.6V)for digitalcontrol logicss8kV built-in electrostatic discharge(ESD)protection on the DP,DM,V BUS and IDliness Full industrial grade operation from−40°C to+85°Cs Available in a small HVQFN24 (4×4mm2) halogen-free and lead-free package.3.Applicationss Mobile phones Digital cameras Personal digital assistants Digital video recorder.4.AbbreviationsASIC —Application-Speciﬁc Integrated CircuitATX —Analog USB transceiverHNP —Host Negotiation ProtocolESD —ElectroStatic DischargeI2C-bus —Inter IC-busIC —Integrated CircuitOTG —On-The-GoPDA —Personal Digital AssistantSE0 —Single-Ended zeroSOF —Start-of-FrameSRP —Session Request ProtocolUSB —Universal Serial BusUSB-IF —USB Implementers Forum.5.Ordering informationTable 1:Ordering informationType number PackageName Description VersionISP1301BS HVQFN24plastic thermal enhanced very thin quadﬂat package;no leads; 24terminals; body 4×4×0.85mmSOT616-16.Block diagramFig 1.Block diagram.3.3 V DC-DC REGULATORV REG(3V3)004aaa195LEVEL SHIFTERSERIAL CONTROLLERUSBTRANSCEIVERCOMPARATORSID DETECTORPULL-UP AND PULL-DOWN RESISTORSV BUS CHARGE PUMPV BUS RESET_NSUSPENDSPEED VM VP RCV SE0/VMDAT/VP OE_N/INT_N91413121110684INT_NADR/PSWSDA SCL 321517DGND AGNDV DD_LGCV BAT2221C2C1V BUS19CGND 23ID18DM 15DP1672024exposed die padCARKIT INTERRUPT DETECTORISP13017.Pinning information7.1PinningFig 2.Pin conﬁguration HVQFN24 (top view).Fig 3.Pin conﬁguration HVQFN24 (bottom view).879101112232422212019321654161718131415ISP1301BSSPEEDINT_N RESET_NSCL SDA ADR/PSWV D D _L G CC G N DC 2C 1V B A T V B U S SE0/VMDAT/VP DM DP AGND ID V R E G (3V 3)O E _N /I N T _NV MV PR C VS U S P E N D004aaa542terminal 1232422212019879101112456123151413181716ISP1301BSADR/PSWSDA SCL RESET_NINT_N SPEED V R E G (3V 3)S U S P E N DO E _N /I N T _NV MV PR C VIDAGND DP DM DAT/VP SE0/VM V D D _L G CC 2C 1V B A TV B U SC G N DDGND(exposed die pad)004aaa196Bottom view7.2Pin descriptionTable 2:Pin description[1]Symbol[2]Pin Type[3]ResetvalueDescriptionADR/PSW1I/O high-Z ADR input —sets the least-signiﬁcant I2C-busaddress bit of the ISP1301; latched-on reset(including power-on reset)PSW output —enables or disables the externalcharge pump after resetbidirectional; push-pull input; three-state output SDA2I/OD high-Z serial I2C-bus data input and outputbidirectional; push-pull input; open-drain output SCL3I/OD high-Z serial I2C-bus clock input and outputbidirectional; push-pull input; open-drain output RESET_N4I-asynchronous reset; active LOWpush-pull inputINT_N5OD high-Z interrupt output; active LOWopen-drain outputSPEED6I-speed selection input for the ATX;effective whenbit SPD_SUSP_CTRL=0:•LOW: low-speed•HIGH: full-speed.push-pull inputV REG(3V3)7P-output of the internal voltage regulator; anexternal decoupling capacitor of 0.1µF isrequiredSUSPEND8I-suspend selection input for A TX; effective whenbit SPD_SUSP_CTRL=0:•LOW: normal operating•HIGH: suspend.push-pull inputOE_N/ INT_N 9I/O high-Z OE_N input —enable driving DP and DM whenin the USB modeINT_N output —interrupt (push pull) whensuspended and bit OE_INT_EN=1bidirectional; push-pull input; three-state outputVM10O-single-ended DM receiver outputpush-pull outputVP11O-single-ended DP receiver outputpush-pull outputRCV12O0differential receiver output; reﬂects thedifferential value of DP and DMpush-pull output[1] A detailed description of these pins can be found in Section 8.9.[2]Symbol names ending with underscore N (for example, NAME_N) indicate active LOW signals.[3]I =input; O =output; I/O =digital input/output; OD =open-drain output; AI/O =analog input/output;P =power or ground pin.[4]High-Z when pin OE_N/INT_N is LOW. Driven LOW when pin OE_N/INT_N is HIGH.SE0/VM13I/O-[4]SE0 (input and output) —SE0 function in DA T_SE0 USB modeVM (input and output) —VM function in VP_VM USB modebidirectional; push-pull input; three-state outputDA T/VP 14I/O -[4]DAT (input and output) —DAT function in DA T_SE0 USB modeVP (input and output) —VP function in VP_VM USB modebidirectional; push-pull input; three-state outputDM 15AI/O -USB data minus pin (D −)DP 16AI/O -USB data plus pin (D+)AGND 17P -analog groundID18AI/O-identiﬁcation detector input and output;connected to the ID pin of the USB mini receptacleV BUS19AI/O -V BUS line input and output of the USB interface;place an external decoupling capacitor of 0.1µF close to this pinV BAT 20P -supply voltage (2.7V to 4.5V)C121AI/O -charge pump capacitor pin 1; typically use a 100nF capacitor between pins C1 and C2C222AI/O -charge pump capacitor pin 2; typically use a 100nF capacitor between pins C1 and C2CGND 23P -ground for the charge pumpV DD_LGC 24P-supply voltage for the interface logic signals (1.65V to 3.6V)DGNDexposed die padP -digital groundTable 2:Pin description [1]…continued Symbol [2]Pin Type [3]Reset value Description8.Functional description8.1Serial controllerThe serial controller includes the following functions:•I2C-bus slave interface•Interrupt generator•Mode Control registers•OTG registers•Interrupt related registers•Device identiﬁcation registers.The serial controller acts as an I2C-bus slave, and uses the SCL and SDA pins tocommunicate with the OTG controller.For more details on serial controller, see Section11.8.2V BUS charge pumpThe charge pump supplies current to the V BUS line. It can operate in any of thefollowing modes:•Output 5V at current greater than 8mA•Pull-up V BUS to 3.3V through a resistor (R VBUS(PU)) for initiating V BUS pulsing SRP•Pull-down V BUS to ground through a resistor (R VBUS(PD)) for discharging V BUSbefore initiating SRP.8.3V BUS comparatorsV BUS comparators provide indications regarding the voltage level on V BUS.8.3.1V BUS valid comparatorThis comparator is used by an A-device to determine whether or not the voltage onV BUS is at a valid level for operation. The minimum threshold for the V BUS validcomparator is 4.4V. Any voltage on V BUS below this threshold is considered to be afault. During power up, it is expected that the comparator output will be ignored.8.3.2Session valid comparatorThe session valid comparator is a TTL-level input that determines when V BUS is highenough for a session to start.Both the A-device and the B-device use this comparatorto detect when a session is being started.The A-device also uses this comparator toindicate when a session is completed. The session valid threshold of the ISP1301 isbetween 0.8V and2.0V.8.3.3Session end comparatorThe session end comparator determines when V BUS is below the B-device sessionend threshold of 0.2V to0.8V.8.4ID detectorIn either the active or suspended power mode,the ID detector senses the condition of the ID line and differentiates between the following three conditions:•Pin ID is ﬂoating; bit ID_FLOAT=1•Pin ID is shorted to ground; bit ID_GND=1•Pin ID is connected to ground through resistor R ACC_ID; bit ID_FLOA T=0 and bitID_GND=0.The ID detector also has a switch that can be used to ground pin ID. This switch is controlled by bit ID_PULLDOWN in the serial controller.8.5Pull-up and pull-down resistorsThe pull-up and pull-down resistors include the following switchable resistors:•Pin DP pull-up•Pin DP pull-down•Pin DM pull-up•Pin DM pull-down.The pull-up resistor is a context variable as described in the ECN_27%_Resistordocument. The variable pull-up resistor hardware is implemented to meet the USB ECN_27% speciﬁcation.8.6USB transceiver (ATX)The behavior of the USB transceiver depends on the operation mode of the ISP1301:•In the USB mode, the USB transceiver block performs USB full-speed orlow-speed transceiver functions. This includes differential driver, differentialreceiver and single-ended receivers.•In the transparent general purpose buffer mode or the UART mode, the USBtransceiver block functions as a level shifter between the pins DAT/VP and SE0/VMand the pins DP and DM.8.7 3.3V DC-DC regulatorThe built-in3.3V DC-DC regulator conditions the supply voltage(V BA T)for use in the ISP1301:•V BA T=3.6V to 4.5V: the regulator will output 3.3V±10%•V BA T<3.6V: the regulator will be bypassed.The output of the regulator can be monitored on the V REG(3V3) pin.8.8Car kit interrupt detectorThe car kit interrupt detector is a comparator that detects when the DP line is below the car kit interrupt threshold V PH_CR_INT (0.4V to0.6V). The car kit interruptdetector is enabled in the audio mode only (bit AUDIO_EN=1).8.9Detailed description of pins8.9.1ADR/PSWThe ADR/PSW pin has two functions. On reset (including power-on reset), the level on this pin is latched as ADR_REG,which represents the least signiﬁcant bit (LSB)of the I 2C address of the ISP1301. If bit ADR_REG =0, the I 2C-bus address for the ISP1301 is 0101100 (0x2C); if bit ADR_REG =1, the I 2C-bus address for the ISP1301 is 0101101 (0x2D).After reset, the ADR/PSW pin can be programmed as an output. If in the Mode Control 2 register bit PSW_OE =1, then the ADR/PSW output will be enabled. The logic level will be determined by bit ADR_REG. If bit ADR_REG =0, then theADR/PSW pin will drive HIGH.If bit ADR_REG =1,then the ADR/PSW pin will drive LOW.The ADR/PSW pin can be used to turn on or off the external charge pump. TheISP1301built-in charge pump supports V BUS current at 8mA.If the application needs more current support (for example, 50mA), an external charge pump may beneeded. In this case, the ADR/PSW pin can act as a power switch for the external charge pump.Figure 4 shows an example of using external charge pump.8.9.2SCL and SDAThe SCL (serial clock) and SDA (serial data) signals implement a two-wire serial I 2C-bus.8.9.3RESET_NActive LOW asynchronous reset for all digital logic.Either connect this pin to V DD_LGC for power-on reset or apply a minimum of 10µs LOW pulse for hardware reset.8.9.4INT_NThe INT_N (interrupt) pin is asserted while an interrupt condition exists. It isdeasserted when the Interrupt Latch register is cleared.The INT_N pin is open-drain,and, therefore, can be connected using a wired-AND with other interrupt signals.Fig ing external charge pump.004aaa437CHARGE PUMPADR/PSWV BUS+3.3 V100 k Ω4.7 µFV BUS ID DM DPGNDV OUTV IN ON/OFFV BATISP13018.9.5OE_N/INT_NPin OE_N/INT_N is normally an input to the ISP1301.When bit TRANSP_EN=0 and bit UART_EN=0, the OE_N/INT_N pin controls the direction of DAT/VP, SE0/VM, DP and DM as indicated in Table4.When suspended (either pin SUSPEND=HIGH or bit SUSPEND_REG=1) and bit OE_INT_EN=1, pin OE_N/INT_N becomes a push-pull output (active LOW) toindicate the interrupt condition.8.9.6SE0/VM, DAT/VP, RCV, VM and VPThe ISP1301 transmits USB data on the USB line under the following conditions:•Bit TRANSP_EN=0•Bit UART_EN=0•Pin OE_N/INT_N=LOW.T able10 shows the operation of the SE0/VM and DAT/VP pins during the transmitoperation. The RCV pin is not used during transmit.The ISP1301 receives USB data from the USB line under the following conditions:•Bit TRANSP_EN=0•Bit UART_EN=0•Pin OE_N/INT_N=HIGH.T able12 shows the operation of the SE0/VM, DA T/VP and RCV pins during thereceive operation.The VP and VM pins are single-ended receiver outputs of the DP and DM pins,respectively.8.9.7DP and DMThe DP(data plus)and DM(data minus)pins implement the USB data signals.When in the transparent general-purpose buffer mode, the ISP1301 operates as a levelshifter between the (DAT/VP, SE0/VM) and (DP, DM) pins.8.9.8IDThe ID (identiﬁcation) pin is connected to the ID pin on the USB mini receptacle. An internal pull-up resistor (to V REG(3V3)) is connected to this pin. When bitID_PULLDOWN is set, the ID pin will be shorted to ground.8.9.9V BUSThis pin acts as an input to the V BUS comparator or an output from the charge pump.When the VBUS_DRV bit of the OTG Control register is asserted, the ISP1301 tries to drive V BUS to a voltage of 4.4V to5.25V with an output current capability of atleast 8mA.8.9.10V BATThis pin is an input and supplies power to the ISP1301.The ISP1301operates when V BA T is between 2.7V and 4.5V .8.9.11C1 and C2The C1 and C2 pins are for connecting the ﬂying capacitor of the charge pump. The output current capacity of the charge pump depends on the value of the capacitor.For maximum efﬁciency, place capacitors as close as possible to the pins.[1]For output voltage V BUS > 4.7V (bit VBUS_VLD =1).[2]For V BA T =3.0V to 4.5V .8.9.12V DD_LGCThis pin is an input and sets logic thresholds.It also powers the pads of the following logic pins:•ADR/PSW•DAT/VP , SE0/VM and RCV •VM and VP •INT_N •OE_N/INT_N •RESET_N •SPEED •SUSPEND •SCL and SDA.8.9.13AGND, CGND and DGNDAGND, CGND and DGND are ground pins for analog, charge pump and digitalcircuits,respectively.These pins can be connected separately or together depending on the system performance requirements.Fig 5.Charge pump capacitor.Table 3:Recommended charge pump capacitor valueC ext I L (max)[1]47nF 8mA 100nF18mA [2]004aaa278I L ISP1301V BUSC1C2C ext9.Modes of operationThere are four types of modes in the ISP1301:•Power modes•Direct I2C-bus mode•USB modes•Transparent modes.9.1Power modesThe power modes of the ISP1301 are as follows:•Active power mode: power is on.•USB suspend mode:to reduce power consumption,the USB differential receiver ispowered down.•Global power-down mode: set bit GLOBAL_PWR_DN=1 of the Mode Control2register; the differential transmitter and receiver, clock generator, charge pump,and all biasing circuits are turned off to reduce power consumption to the minimumpossible; for details on waking up the clock, see Section12.9.2Direct I2C-bus modeIn the direct I2C-bus mode, an external I2C-bus master (OTG controller) directlycommunicates with the serial controller through the SCL and SDA lines. The serialcontroller has a built-in I2C-bus slave function.In this mode, an external I2C-bus master can access the internal registers of thedevice (Status, Control, Interrupt, and so on) through the I2C-bus interface.The supported I2C-bus bit rate is 100kbit/s (maximum).The ISP1301is in the direct I2C-bus mode when either bit TRANSP_EN bit=0or pinOE_N/INT_N is deasserted.9.3USB modesThe four USB modes of the ISP1301 are:•VP_VM unidirectional mode•VP_VM bidirectional mode•DAT_SE0 unidirectional mode•DAT_SE0 bidirectional mode.In the VP_VM USB mode, the DAT/VP pin is used for the VP function, the SE0/VMpin is used for the VM function, and the RCV pin is used for the RCV function.In the DA T_SE0USB mode,the DAT/VP pin is used for the DAT function,the SE0/VMpin is used for the SE0 function, and the RCV pin is not used.In the unidirectional mode, the DAT/VP and SE0/VM pins are always inputs. In thebidirectional mode, the direction of these signals depends on the OE_N/INT_N input.T able 6 speciﬁes the functionality of the device during the four USB modes.The ISP1301 is in the USB mode when both the TRANSP_EN and UART_EN bits are cleared.9.4Transparent modes9.4.1Transparent general-purpose buffer modeIn the transparent general-purpose buffer mode, the DA T/VP and SE0/VM pins are connected to the DP and DM pins, respectively. Using bits TRANSP_BDIR1 and TRANSP_BDIR0 of the Mode Control 2 register as speciﬁed in Table 8, you can control the direction of data transfer. The ISP1301 is in the transparent general-purpose buffer mode if bit TRANSP_EN =1 and bit DAT_SE0=1.9.4.2Transparent UART modeWhen in the transparent UART mode, the ATX behaves as two logic level translator between the following pins:•For TxD signal: from SE0/VM (V DD_LGC level) to DM (+3.3V level)•For RxD signal: from DP (+3.3V level) to DAT/VP (V DD_LGC level).In the UART mode, the OTG controller is allowed to connect a UART to the DA T/VP and SE0/VM pins of the ISP1301.The UART mode is entered by setting the UART_EN bit in the Mode Control 1register. The UART mode is equivalent to one of the transparent general purpose buffer mode (bit TRANSP_BDIR1=1, bit TRANSP_BDIR0=0).9.4.3Summary tables[1]Conditions:a)bit SPD_SUSP_CTRL =0 and pin SUSPEND =HIGH, or b)bit SPD_SUSP_CTRL =1 and bit SUSPEND_REG =0.Table 4: Device operating modesModeUSB suspend condition [1]Bit DAT_SE0PinOE_N/INT_N Bit TRANSP _EN Bit UART _ EN DescriptionDirect I 2C-bus mode Direct I 2C-bus modeX X X 0X X X HIGH 1X X1X 1X USB modes USB suspend mode 1X X 00see T able 5 and T able 7USB functional mode 0X X 00ATX is fully functional; see T able 6Transparent modes T ransparent general-purpose buffer modeX 1X 10ATX is not functional; see T able 8T ransparent UART modeX XXX1DA T/VP <=DP (RxD signal of UART)SE0/VM =>DM (TxD signal of UART);ATX is not functional[1]In the USB suspend mode, the ISP1301 can drive the DP and DM lines, if the OE_N/INT_N input (when the OE_INT_EN bit is not set) is LOW. In such a case, these outputs are driven as in the USB functional modes,but with the full-speed characteristics,irrespective of the value of the SPEED input pin or the SPEED_REG bit.[1]Some of the modes and signals are provided to achieve backward compatibility with IP cores.[2]TxD+ and TxD − are single-ended inputs for driving the DP and DM outputs, respectively, in the single-ended mode.[3]RxD+ and RxD − are the outputs of the single-ended receivers connected to DP and DM, respectively.[4]TxD is the input for driving DP and DM in the DA T_SE0 mode.[5]FSE0 is for forcing an SE0 on the DP and DM lines in the DA T_SE0 mode.[6]RxD is the output of the differential receiver.[7]RSE0 is an output indicating that an SE0 has been received on the DP and DM lines.Table 5:USB suspend mode: I/OPinFunctionDP as output can be driven if pin OE_N/INT_N is active LOW, otherwise high-Z [1]DM as output can be driven if pin OE_N/INT_N is active LOW, otherwise high-Z [1]V BUS can be driven depending on bit VBUS_DRV SCL connected to SCL I/O of the I 2C-bus slave SDAconnected to SDA I/O of the I 2C-bus slaveTable 6:USB functional modes: I/O values [1]USB modeBit Pin DAT_SE0BI_DI OE_N/INT_N DAT/VP SE0/VM VP VM RCV VP_VM unidirectional 00X TxD+[2]TxD −[2]RxD+[3]RxD −[3]RxD [3]bidirectional01LOW TxD+[2]TxD −[2]01HIGH RxD+[3]RxD −[3]DA T_SE0unidirectional 10X TxD [4]FSE0[5]bidirectional11LOW TxD [4]FSE0[5]11HIGHRxD [6]RSE0[7]Table 7:USB suspend mode: I/O valuesUSB suspend mode Input pin Output pin DPDM DAT/VP SE0/VM VP VM RCV DA T_SE0(bit DA T_SE0=1)LOW LOW LOW HIGH LOW LOW LOW HIGH LOW HIGH LOW HIGH LOW LOW LOW HIGH LOW LOW LOW HIGH LOW HIGHHIGH HIGH LOW HIGH HIGH LOW VP_VM(bit DA T_SE0=0)LOW LOW LOW LOW LOW LOW LOW HIGH LOW HIGH LOW HIGH LOW LOW LOW HIGH LOW HIGH LOW HIGH LOW HIGHHIGHHIGHHIGHHIGHHIGHLOWB transceiver10.1Differential driverThe operation of the driver is described in Table 9.The register bits and the pins used in the column heading are described in Section 11.1 and Section 8.9, respectively.[1]Can be controlled by using either the SUSPEND pin or the SUSPEND_REG bit.10.2Differential receiverT able 11 describes the operation of the differential receiver. The register bits and the pins used in the column heading are described in Section 11.1 and Section 8.9,respectively.Table 8:Transparent general-purpose buffer modeBit TRANSP_BDIR[1:0]Direction of the data ﬂow 00DA T/VP =>DP SE0/VM =>DM 01DA T/VP =>DP SE0/VM <=DM 10DA T/VP <=DP SE0/VM =>DM 11DA T/VP <=DPSE0/VM <=DMTable 9:Transceiver driver operation setting Suspend [1]Bit TRANSP_EN Pin OE_N/INT_N BitDAT_SE0Differential driver00LOW 0output value from DA T/VP to DP and SE0/VM to DMLOW1output value from DAT/VP to DP and DM if SE0/VM is 0; otherwise, drive both DP and DM LOW10LOW X output value from DA T/VP to DP and DM X X HIGH X high-Z X1XXhigh-ZTable 10:USB functional mode: transmit operationUSB mode Input pin Output pin DAT/VP SE0/VM DP DM DA T_SE0LOW LOW LOW HIGH HIGH LOW HIGH LOW LOW HIGH LOW LOW HIGHHIGH LOW LOW VP_VM LOW LOW LOW LOW HIGH LOW HIGH LOW LOW HIGH LOW HIGH HIGHHIGHHIGHHIGHThe detailed behavior of the receive transceiver operation is given in Table 12.[1]Can be controlled by using either the SUSPEND pin or the SUSPEND_REG bit.[1]Can be controlled by using either the SUSPEND pin or the SUSPEND_REG bit.Table 11:Differential receiver operation settings Suspend [1]BitTRANSP_EN PinOE_N/INT_N BitDAT_SE0Differential receiver 1X X X 0X X LOW X 0X 1X X 000HIGH 1output differential value from DP and DM to DA T/VP and RCV 0HIGHoutput differential value from DP and DM to RCVTable 12:USB functional mode: receive operation USB mode Suspend [1]Input pin Output pin DP DM DAT/VP SE0/VM RCVDA T_SE00LOW LOW RCV HIGH last value of RCV DA T_SE00HIGH LOW HIGH LOW HIGH DA T_SE00LOW HIGH LOW LOW LOWDA T_SE00HIGH HIGH RCV LOW last value of RCV DA T_SE01LOW LOW LOW HIGH LOW DA T_SE01HIGH LOW HIGH LOW LOW DA T_SE01LOW HIGH LOW LOW LOW DA T_SE01HIGH HIGH HIGH LOW LOWVP_VM 0LOW LOW LOW LOW last value of RCV VP_VM 0HIGH LOW HIGH LOW HIGH VP_VM 0LOW HIGH LOW HIGH LOWVP_VM 0HIGH HIGH HIGH HIGH last value of RCV VP_VM 1LOW LOW LOW LOW LOW VP_VM 1HIGH LOW HIGH LOW LOW VP_VM 1LOW HIGH LOW HIGH LOW VP_VM1HIGHHIGHHIGHHIGHLOW11.Serial controller11.1Register mapT able 13 provides an overview of the serial controller registers.[1]The R/S/C access type represents a ﬁeld that can be read, set or cleared (set to 0). A register can be read from either of the indicated addresses—set or clear. Writing logic 1 to the set address causes the associated bit to be set. Writing logic 1 to the clear address causes the associated bit to be cleared. Writing logic 0 to an address has no effect.11.1.1Device identiﬁcation registersVendor ID register (Read: 00H–01H):Table 14 provides the bit allocation of the Vendor ID register.Product ID register (Read: 02H–03H):The bit allocation of this register is given in T able 15.Table 13:Serial controller registersRegister Width (bits)Access [1]Memory address Functionality ReferenceVendor ID 16R 00–01H device identiﬁcation registers Section 11.1.1on page 17Product ID 16R 02–03H Version ID 16R 14–15H Mode Control 18R/S/C Set —04H Clear —05H mode control registers Section 11.1.2on page 18Mode Control 28R/S/C Set —12H Clear —13H OTG Control 8R/S/C Set —06H Clear —07H OTG registers Section 11.1.3on page 19OTG Status 8R 10H Interrupt Source 8R 08H interrupt related registers Section 11.1.4on page 20Interrupt Latch 8R/S/C Set —0AH Clear —0BH Interrupt Enable Low 8R/S/C Set —0CH Clear —0DH Interrupt Enable High8R/S/CSet —0EH Clear —0FHTable 14:Vendor ID register: bit description Bit Symbol Access Value Description15to 0VENDORID [15:0]R04CCHPhilips Semiconductors’ Vendor IDTable 15:Product ID register: bit description Bit Symbol Access Value Description15to 0PRODUCTID [15:0]R1301HProduct ID of the ISP1301Version ID register (Read: 14H–15H):Table 16 shows the bit allocation of this register.11.1.2Mode control registersMode Control 1 register (Set/Clear: 04H/05H):The bit allocation of the Mode Control 1 register is given in T able 17.Mode Control 2 register (Set/Clear: 12H/13H):For the bit allocation of this register,see T able 19.Table 16:Version ID register: bit description Bit Symbol Access Value Description15to 0VERSIONID [15:0]R0210HVersion number of the ISP1301Table 17:Mode Control 1 register: bit allocationBit 76543210Symbol -UART_ENOE_INT_ENBDIS_ACON_ENTRANSP_ENDA T_SE0SUSPEND _REGSPEED_REGReset -0000000AccessR/S/CR/S/C R/S/CR/S/CR/S/CR/S/CR/S/CR/S/CTable 18:Mode Control 1 register: bit description Bit SymbolDescription 7-reserved6UART_EN When set, the A TX is in the transparent UART mode.5OE_INT_EN When set and when in the suspend mode, pin OE_N/INT_N becomes an output and is asserted when an interrupt occurs.4BDIS_ACON_EN Enables the A-device to connect if the B-device disconnect is detected; see Section 11.33TRANSP_EN When set, the A TX is in the transparent mode.2DA T_SE00 —VP_VM mode1 —DAT_SE0 mode; see T able 6 and T able 71SUSPEND_REGSets the ISP1301 in the suspend mode, if bit SPD_SUSP_CTRL =1.0 —active-power mode 1 —USB suspend mode0SPEED_REGSets the rise time and the fall time of the transmit driver in USB modes, if bit SPD_SUSP_CTRL =1.0 —USB low-speed mode 1 —USB full-speed mode。

T912-A2K-001-10中文资料

® resistance films to achieve the precise ratio performance Caddock Tetrinox® MG 650 Caddock Tetrinox resistance films to achieve thesource precise ratio performance ® resistance and stability required by highly accurate amplifier circuits, reference Caddock's Micronox ﬁlms are the ofvoltage Preconditioning for Power and Voltage Ratings and stability required by highly accurate amplifier circuits, reference and stability required by highly accurate amplifier circuits,voltage voltage reference MG 655 Now with Extended Resistance Range to 10,000 Megohms and Additional Models circuits and precision bridge circuits. the Type MG Precision High Voltage Resistors' outstanding All power ratings and maximum operating voltage ratings circuits and precision bridge circuits. circuits and of precision br

二极管封装大全

军用电子器件目录JUN YONG DIAN ZI QI JIAN MU LU（2005年版）济南半一电子有限公司目录半导体器件选用注意事项 (1)第一部分：二极管 (8)一. 开关二极管 (8)1. 锗金键开关二极管2AK1～20系列 (8)2. 锗金键检波二极管2AP1～31B系列 (9)3. 肖特基检波二极管SP1～31B系列（替代2AP1～31B） (10)4. 肖特基开关二极管SK1～20系列（替代2AK1～20） (11)5. 肖特基开关检波二极管2DKOlO、020、O3O型（替代2AK1～20、2AP1～31B）··126. 硅开关二极管2CK70～86、2CK49～56系列 (13)7. 硅开关二极管1N、1S、1SS、BAV系列 (16)8. 玻璃钝化封装大电流开关二极管RG0.5～5系列 (17)二. 整流二极管 (18)1. 玻封快速硅整流二极管2CZ50～57系列 (18)2. 玻璃钝化整流管1N、RL、6A系列 (19)3. 玻璃钝化高速整流管SF11G～66G系列 (20)4. 贴片玻璃钝化整流管S1～5系列 (21)5. 贴片高速整流管ES1～5系列 (22)6. 肖特基二极管SR0620～510、1N5817～5822系列 (23)7. 肖特基二极管SR735～4060系列 (24)8. 贴片肖特基二极管SS1～36、SS110系列 (25)三. 电压调整（稳压）二极管 (26)1. 硅稳压二极管2CW50～78系列 (26)2. 硅稳压二极管2CW100～121系列 (27)3. 硅稳压二极管ZW50～78系列 (28)4. 硅稳压二极管ZW100～121系列 (29)5. 硅稳压二极管2CW5221～5255（1N5221～5255）系列 (30)6. 硅稳压二极管2CW4728A～4754A（1N4728A～4754A）系列 (31)7. 硅稳压二极管1N746A～759A、1N957A～974A系列 (32)8. 硅稳压二极管1N4352B～4358B系列 (33)9. 硅稳压二极管HZ2～36系列 (34)10. 硅稳压二极管BZX55/C系列 (35)11. 硅稳压二极管BZX85/C系列 (36)四. 电压基准二极管 (37)1. 硅基准稳压二极管2DW14～18系列 (37)2. 硅平面温度补偿二极管2DW230～236系列 (38)五. 电流调整（稳流）二极管 (39)1. 稳流管2DH1～36系列 (39)六. 瞬变电压抑制二极管 (40)1. 单双向瞬变电压抑制二极管TVS500～534系列 (40)2. 单双向瞬变电压抑制二极管TVS1000～1034系列 (41)3. 单双向瞬变电压抑制二极管TVS1500～1534系列 (42)4. 单双向瞬变电压抑制二极管TVS5000～5034系列 (43)第二部分：晶体管 (44)一. 双极型晶体管 (44)1. 硅NPN型平面高频小功率三极管3DG110、3DG111、3DG130系列 (44)2. 硅NPN型外延平面高反压三极管3DG182系列 (45)3. 硅NPN型平面三极管3DK101、3DK106、3DK21系列 (46)4. 硅PNP型外延平面高频小功率三极管3CG111、3CG120、3CG130系列 (47)5. 硅PNP型外延平面高频小功率三极管3CK2、3CK120、3CK130系列 (48)6. 硅PNP型外延平面高频高反压小功率三极管3CG182、3CG184、2N2907系列 (49)7. 硅NPN低频大功率晶体管3DD1～8系列 (50)8. 硅NPN达林顿功率晶体管FH6～8系列 (53)二. 场效应晶体管 (54)1. N沟道MOS型场效应晶体管IRF120～823系列 (54)2. P沟道MOS型场效应晶体管IRF9130～9643系列 (56)3. N沟道结型场效应晶体管3DJ2、3DJ6/66、3DJ7/67/304、3DJ8/68系列 (57)三. 部分替代俄型号晶体管 (59)第三部分：半导体分立器件组件 (60)一. 说明 (60)二. 产品型号 (61)1. 200mA～2A玻璃钝化芯片整流桥DF、1W、RB、W系列 (61)2. 1～4A玻璃钝化芯片整流桥2W、GBP、GBL系列 (62)3. 4～15A玻璃钝化芯片整流桥GBU、GBP系列 (63)4. 15～35A玻璃钝化芯片整流桥GBPC系列 (64)5. 定制式三相整流桥 (65)6. 2Д906A型硅二极管矩阵 (65)7. 双向限幅器SXF0.25～5.8系列 (65)第四部分：电路及模块 (66)一. 集成稳压器 (66)1. 固定输出三端正稳压器CW7800系列 (66)2. 固定输出三端负稳压器CW7900系列 (66)3. 可调输出三端正稳压器CW117系列 (67)4. 可调输出三端负稳压器CW137系列 (67)5. 定制式5V以下电压基准DCW系列 (68)第五部分：外形图 (69)半导体器件选用注意事项半导体器件（以下简称器件）的质量问题，不仅有器件本身所固有的质量和可靠性问题，也有由于用户选择或使用不当造成的器件失效问题。

8302001SA中文资料

PACKAGING INFORMATIONOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)83020012A ACTIVE LCCC FK201None Call TI Level-NC-NC-NC 8302001RA ACTIVE CDIP J201None Call TI Level-NC-NC-NC 8302001SA ACTIVE CFP W201None Call TI Level-NC-NC-NC JM38510/37203B2A ACTIVE LCCC FK201None Call TI Level-NC-NC-NC JM38510/37203BRA ACTIVE CDIP J201None Call TI Level-NC-NC-NC SN54ALS373AJ ACTIVE CDIP J201None Call TI Level-NC-NC-NC SN54AS373J ACTIVE CDIP J201None Call TI Level-NC-NC-NC SN74ALS373ADBLE OBSOLETE SSOP DB20None Call TI Call TISN74ALS373ADBR ACTIVE SSOP DB202000Pb-Free(RoHS)CU NIPDAU Level-2-260C-1YEAR/Level-1-235C-UNLIMSN74ALS373ADW ACTIVE SOIC DW2025Pb-Free(RoHS)CU NIPDAU Level-2-250C-1YEAR/Level-1-235C-UNLIMSN74ALS373ADWR ACTIVE SOIC DW202000Pb-Free(RoHS)CU NIPDAU Level-2-250C-1YEAR/Level-1-235C-UNLIMSN74ALS373AN ACTIVE PDIP N2020Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NC SN74ALS373AN3OBSOLETE PDIP N20None Call TI Call TISN74ALS373ANSR ACTIVE SO NS202000Pb-Free(RoHS)CU NIPDAU Level-2-260C-1YEAR/Level-1-235C-UNLIMSN74AS373DW ACTIVE SOIC DW2025Pb-Free(RoHS)CU NIPDAU Level-2-250C-1YEAR/Level-1-235C-UNLIMSN74AS373DWR ACTIVE SOIC DW202000Pb-Free(RoHS)CU NIPDAU Level-2-250C-1YEAR/Level-1-235C-UNLIMSN74AS373N ACTIVE PDIP N2020Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NC SN74AS373N3OBSOLETE PDIP N20None Call TI Call TISN74AS373NSR ACTIVE SO NS202000Pb-Free(RoHS)CU NIPDAU Level-2-260C-1YEAR/Level-1-235C-UNLIMSNJ54ALS373AFK ACTIVE LCCC FK201None Call TI Level-NC-NC-NC SNJ54ALS373AJ ACTIVE CDIP J201None Call TI Level-NC-NC-NC SNJ54ALS373AW ACTIVE CFP W201None Call TI Level-NC-NC-NC SNJ54AS373FK ACTIVE LCCC FK201None Call TI Level-NC-NC-NC SNJ54AS373J ACTIVE CDIP J201None Call TI Level-NC-NC-NC(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan-May not be currently available-please check /productcontent for the latest availability information and additional product content details.None:Not yet available Lead(Pb-Free).Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Green(RoHS&no Sb/Br):TI defines"Green"to mean"Pb-Free"and in addition,uses package materials that do not contain halogens,including bromine(Br)or antimony(Sb)above0.1%of total product weight.(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. T esting and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. T o minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation.Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAmplifiers Audio /audioData Converters Automotive /automotiveDSP Broadband /broadbandInterface Digital Control /digitalcontrolLogic Military /militaryPower Mgmt Optical Networking /opticalnetwork Microcontrollers Security /securityTelephony /telephonyVideo & Imaging /videoWireless /wirelessMailing Address:Texas InstrumentsPost Office Box 655303 Dallas, Texas 75265Copyright 2005, Texas Instruments Incorporated。

CD4013中文资料及应用

CD4013中文资料(真值表,引脚图,电气参数等)CD4013中文资料(真值表,引脚图,电气参数等)CD4013功能:CD4013是一双D触发器,由两个相同的、相互独立的数据型触发器构成。

每个触发器有独立的数据、置位、复位、时钟输入和Q及Q输出，此器件可用作移位寄存器，且通过将Q输出连接到数据输入，可用作计算器和触发器。

在时钟上升沿触发时，加在D输入端的逻辑电平传送到Q输出端。

置位和复位与时钟无关，而分别由置位或复位线上的高电平完成。

CD4013 Truth Table 真值表功能:CL (Note 1) D R S Q Q↑0 0 0 0 1↑ 1 0 0 1 0↓x 0 0 Q Qx x 1 0 0 1x x 0 1 1 0x x 1 1 1 1CD4013引脚图:图１CD4013引脚图CD4013内部结构图:图２CD4013内部电路图图3 CD4013逻辑图CD4013电气参数:Absolute Maximum Ratings 绝对最大额定值:DC Supply Voltage 直流供电电压 (VDD) -0.5 VDC to +18 VDC Input Voltage输入电压 (VIN) -0.5 VDC to VDD +0.5 VDC Storage Temperature Range储存温度范围 (TS) -65℃ to +150℃Recommended Operating Conditions 建议操作条件:DC Electrical Characteristics 直流电气特性:AC Electrical Characteristics 交流电气特性:图4 切换时间波形CD4013应用电路：图5（左）和图（右）中的CD4013是CMOS双D触发器，这类电路置位和复位信号是高电平有效，由于开关闭合时电容可视为短路而产生高电平，使RD=1，Q=0；若将此信号加到SD，则SD=1，Q=1;置位、复位过后，电容充电而使RD（SD）变为0，电路可进入计数状态。

STK401-060中文资料

Speciﬁed Transformer Supply (RP-25 or Equivalent)
No. 4680—2/8
元器件交易网
STK401-060
Equivalent Circuit
Sample PCB Layout for 2-Channel or 3-Channel Ampliﬁers
The STK401-060 is a thick-ﬁlm audio power ampliﬁer IC belonging to a series in which all devices are pin compatible. This allows a single PCB design to be used to construct ampliﬁers of various output capacity simply by changing hybrid ICs. Also, this series is part of a new, larger series that comprises mutually similar devices with the same pin compatibility. This makes possible the development of a 2-channel ampliﬁer from a 3-channel ampliﬁer using the same PCB. In addition, this new series features 6/3Ω drive in order to support the low impedance of modern speakers.
元器件交易网
Ordering number: EN 4680B

2SK4013中文资料

Characteristics
Continuous drain reverse current (Note 1)
Pulse drain reverse current
(Note 1)
Forward voltage (diode)
Reverse recovery time
Reverse recovery charge
Thermal Characteristics
2
Characteristics
Symbol
Max
Unit
Thermal resistance, channel to case Thermal resistance, channel to ambient
Rth (ch-c) Rth (ch-a)
2.78
temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/Derating Concept and Methods) and individual reliability data (i.e. reliability test report and estimated failure rate, etc).

IH401A资料

SemiconductorApril 1999IH401AQUAD Varafet Analog SwitchFeatures•r DS(ON) (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Ω•I D(OFF) (Typ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10pA •Switching Times (R L = 1k Ω)-t ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns -t OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75ns •Built-In Overvoltage Protection . . . . . . . . . . . . . .±25V •Charge Injection Error (Typ) into 0.01µF Capacitor . . 3mV •C ISS (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <1pF •Can Be Used for Hybrid ConstructionDescriptionThe IH401A is made up of 4 monolithically constructed combinations of varacitor type diode and a N-Channel JFET .The JFET itself is very similar to the popular 2N4391, and the driver diode is specially designed, such that its capacitance is a strong function of the voltage across it. The driver diode is electrically in series with the gate of the N-Channel FET and simulates a back-to-back diode structure. This structure is needed to prevent forward biasing the source-to-gate or drain-to-gate junctions of the JFET when used in switching applications.Previous applications of JFETs required the addition of diodes, in series with the gate, and then perhaps a gate-to-source referral resistor or a capacitor in parallel with the diode; therefore, at least 3 components were required to perform the switch function. The IH401A does this same job in one component (with a great deal better performance characteristics).Like a standard JFET, the practically perform a solid state switch function translator should be added to drive the diode.This translator takes the TTL levels and converts them to voltages required to drive the diode/FET system (typically a 0V to -15V translation and a 3V to +15V shift). With ±15V power supplies, the IH401A will typically switch 22V P-P at any frequency from DC to 20MHz, with less than 50Ωr DS(ON).PinoutIH401A (CERDIP)TOP VIEWPart Number InformationPART NUMBER TEMP. RANGE(o C)PACKAGE IH401A-55 to 12516 Ld CERDIP1415169131********45768S 1D 1DR 1DR 2S 2D 2D 4DR 4DR 3S 3D 3S 4CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.File Number3128.2O B S OL E T E PR O D U C TN O R E C O M M E N D E D R E P L A C E M E N T C a l l C e n t r a l A p p l i c a t i o n s 1-800-442-7747o r e m a i l: c e n t a p p @ha r r i s .c o mAbsolute Maximum Ratings Thermal InformationSupply VoltageV S to V D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35V V G to V S, V D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35V Operating ConditionsTemperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .55o C to 125o C Maximum Junction T emperature (Ceramic Package). . . . . . . . .175o C Storage Temperature Range. . . . . . . . . . . . . . . . . . .-65o C to 150o C Lead T emperature (Soldering, 10s). . . . . . . . . . . . . . . . . . . . .300o CCAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.Electrical Speciﬁcations At 25o C/125o CPARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Switch “ON” Resistance r DS(ON)V DRIVE = 15V,V DRAIN = -10V,I D = 10mA-3550ΩPinch-Off Voltage V P I D = 1nA, V DS = 10V245VSwitch “OFF” Current or “OFF” Leakage I D(OFF)V DRIVE = -15V,V SOURCE = -10V,V DRAIN = +10V-10±500pASwitch “OFF” Leakage at 125o C I D(OFF)V DRIVE = -15V,V SOURCE = -10V,V DRAIN = +10V-0.2550nASwitch “OFF” Current I S(OFF)V DRIVE = -15V,V DRAIN = -10V,V SOURCE = +10V-10±500pASwitch “OFF” Leakage at 125o C I S(OFF)V DRIVE = -15V,V SOURCE = -10V,V DRAIN = +10V-0.350nASwitch Leakage When Turned “ON”I D(ON) =I S(ON)V D = V S = -10V,V DRIVE= +15V-0.02±2nAAC Input Voltage Range without Distortion V ANALOG See Figure 22022-V P-P Charge Injection Amplitude V INJECT See Figure 3-3-mV P-PDiode Reverse Breakdown Voltage. This Correlates to Overvoltage Protection BV DIODE V D = V S = -V,I DRIVE = 1µA,DRIVE = 0V-30-45-VGate to Source or Gate to Drain Reverse Breakdown Voltage BV GSS V DRIVE = -V,V D = V S = 0V,DRIVE = 1µA3041-VMaximum Current Switch can Deliver (Pulsed)I DSS V DRIVE = 15V,V S = 0V,D = +10V3555-mA Switch “ON” Time (Note 1)t ON See Figure 1-50-nsSwitch “OFF” Time (Note 1)t OFF See Figure 1-150-nsNOTE:1.Driving waveform must be >100ns rise and fall time.ApplicationsIH401A FamilyIn general, the IH401A family can be used in any application formally using a JFET/isolation diode combination (2N4391or similar). Like standard FET circuits, the IH401A requires a translator for normal analog switch function. The translator is used to boost the TTL input signals to the ±15V analog supply levels which allow the IH401A to handle ±10V analog signals. A typical simple PNP translator is shown in Figure 4.Although this simple PNP circuit represents a minimum of components, it requires open collector TTL input and t (OFF)is limited by the collector load resistor (approximately 1.5µs for 10k Ω). Improved switching speed can be obtained by increasing the complexity of the translator stage.A translator which overcomes the problems of the simple PNP stage is the Harris IH6201 (See Note). This translator driving an IH401A varafet produces the following typical features:NOTE:The IH6201 is a dual translator (two independent translatorsper package) constructed from monolithic CMOS technology.The schematic of one-half IH6201, driving one-fourth of an IH401A, is shown in Figure 5.A very useful feature of this system is that one-half of an IH6201 and one-half of an IH401A can combine to make a SPDT switch, or an IH6201 plus an IH401A can make a dual SPDT analog switch. (See Figure 8)Test CircuitsFIGURE 1.SWITCHING TIME TEST CIRCUIT AND WAVEFORMSFIGURE 2.ANALOG INPUT VOLTAGE RANGE TEST CIRCUIT FIGURE 3.CHARGE INJECTION TEST CIRCUIT-15V+15VSTROBE INPUTSIGNAL V OUT-15V1k Ω+5V+15V 0V -15V10%+5Vt ON90%90%-5V0V 0V 10%10%t OFFt ON 90%t OFF-5V SIGNAL +5V SIGNAL STROBE INPUT1k ΩV IN V OUT+15Vf = 1kHC = 0.01µFV OUT0V-15VFIGURE 4.TYPICAL SIMPLE PNP TRANSLATOR0V+15VR L1/4 OF IH401AFROM TTL OPEN COLLECTOR LOGICANALOG SIGNALS INANALOG OUT 10k Ω+15V-15V 10k Ω•t ON time of approx. 200ns •t OFF time of approx. 80ns break before make switch•TTL compatible strobing levels of•I D(ON)+ I S(ON) typically 20pA up to ±10V analog signals •I D(OFF)or I S(OFF) typically 20pA•Quiescent current drain of approx. 100nA in either “ON” or “OFF” case0.4V2.4VTypical Application Schematic(1/2 of IH401A, Driving 1/4 of an IH401A)Switching InformationNOTE:Either switch is turned on when strobe input goes high.FIGURE 6.DUAL SPST ANALOG SWITCHFIGURE 7.DPDT ANALOG SWITCHNOTE:Each transistor output has a θ and output.θ is just the inverse of θ, i.e., (θ output is 180 degrees out of phase with respect to θ output).FIGURE 5.IH6201 DRIVING AN IH401A0.4V2.4Vθ +15V-15VDV++15V10k ΩGND4k ΩTTL OR CMOS INPUT STROBEV--15V20k Ω2k Ω+5VV L V 1TRANSLATOR (IH6201)1k Ω1k Ωθθ+15V-15VSVARAFETθ -15V+15V14151691312111012345768IH401A14151691312111012345768θ1-15V +5V +15V IH62010V3VT 2L 1θ20V3VT 2L 214151691312111012345768IH401A14151691312111012345768θ1θ1-15V+5V +15V IH62010V3VT 2L 1FIGURE 8.DUAL SPDT ANALOG SWITCHFIGURE 9.DUAL DPST ANALOG SWITCHSwitching Information (Continued)14151691312111012345768IH401A14151691312111012345768θ1θ1θ2θ2T 2L INPUT 1-15V +5V +15V IH6201T 2L INPUT 214151691312111012345768IH401A14151691312111012345768θ1θ2T 2L INPUT-15V +5V +15V IH6201T 2L INPUT。

STK400-040中文资料

• Few external circuits
Compared to those series used until now, capacitors and boot-strap resistors for external circuits can be greatly reduced.
SSAANNYYOOEElleeccttrriiccCCoo..,,LLttdd..SSeemmiiccoonndduuccttoorrBBuussssiinneessssHHeeaaddqquuaarrtteerrss
Hz
55
kΩLeabharlann 1.2mVrms–70
0
+70
mV
Notes • Use rated power supply for test unless otherwise specified.
• When measuring available time for short-circuit and output noise voltage use transformer power supply indicated below.
fL =
1 2π X C3 (13, 23,) X R3 (13, 23)
For the purpose of achieving voltage gains prior to reduction, it is best that C3, C13 and C23 are large. However, because the shock noise which occurs when the system power is turned on tends to increase, values larger than those absolutely necessary should be avoided.

401C923M6R3AH8中文资料

Type 401C –55 °C to 105 °C Low-ESR, Wide Temperature Grade2,000 h at 85 °C per EIA IS-749 with 85 ºC ripple current∆ Capacitance ±10% ESR 200% of limit DCL 100% of limit4,000 h at 105ºC with rated voltage∆ Capacitance ±10% ESR 200% of limit DCL 100% of limit500 h at +105 °C, capacitance, ESR and DCL, will meet initialrequirements10 to 55 Hz, 0.06” and 10 g max, 2 h each planeThe Type 401C is the wide-temperature, low-voltage version of the Type 450C. It is ideal for high-ripple current military and industrial applications that need full performance at cold temperatures. It also excels as a power-supply output capacitor because of its exceptionally low ESR. The extended cathode foil of the 401C assures cool operation and heat ﬂow from the capacitor element to the can in all mounting orientations.Highlights• Better value than large snap-in capacitors • Ripple Currents to >50 amps at 55 °C • ESRs to 3.5 m Ω• > 90% capacitance at –40 °C• Thermal-Pak™ extended cathode constructionSpeciﬁcationsOperating Temperature:Rated Voltage:Capacitance:DC Leakage Current:Cold Impedance:Ripple Current Multipliers:EIA Ripple Life:Life Test:Shelf Life Test: Vibration: The Ultimate in Cold Performance and ESRFrequency–55 °C to 105 °C 6.3 to 250 Vdc380 µF to 570,000 µF ± 20%≤ 1.5 √CV µA, 4 mA max, 5 minutes –55 °C multiple of 25 °C Z ≤ 3Ambient Temperature45 °C 55 °C 65 °C 75 °C 85 ºC 95 ºC 105 °C 1.661.521.371.201.000.750.3650 Hz 60 Hz 120 Hz 360 Hz 1 kHz 5 kHz 10 kHz & up6.3 to 50 V 0.850.90 1.00 1.05 1.10 1.10 1.1063 to 250 V0.500.531.001.151.151.201.20Complies with the EU Directive 2002/95/EC requirementrestricting the use of Lead (Pb), Mercury (Hg), Cadmium (Cd), Hexavalent chromium (Cr(VI)), PolyBrominated Biphenyls (PBB) and PolyBrominated Diphenyl Ethers (PBDE).元器件交易网Type 401C –55 °C to 105 °C Low-ESR, Wide Temperature GradeOutline DrawingsCase DimensionsPart Numbering System401CType Terminal8InsulationAKCase Code100Voltage M Tolerance393Capacitance(blank) = Straight Leads 0 = Bare can8 = PVC andStandoffs9 = Polyester and Standoffs100 = 100 V 450 = 100 V M = ±20%T = –10% +50% U = –10% +75%242 = 2400 µF 221 = 220 µFCase InchesMillimeters Code D ± .031 L MAX C ± .015 S ± .031 E ± .031 F ± .015 D ± .78 L MAX C ± .78 S ± .78 E ± .78 F ± .38AK 1.375 1.750.500.1750.250.5534.9344.4512.70 4.45 6.3513.97 AA 1.375 2.250.500.1750.250.5534.9357.1512.70 4.45 6.3513.97 AH 1.375 2.750.500.1750.250.5534.9869.8512.70 4.45 6.3513.97 AB 1.375 3.250.500.1750.250.5534.9382.5512.70 4.45 6.3513.97 AJ 1.375 3.750.500.1750.250.5534.9395.2512.70 4.45 6.3513.97 AC 1.375 4.250.500.1750.250.5534.93107.9512.70 4.45 6.3513.97 AD 1.375 4.750.500.1750.250.5534.93120.6512.70 4.45 6.3513.97 AE 1.375 5.250.500.1750.250.5534.93133.3512.70 4.45 6.3513.97 AF 1.375 5.750.500.1750.250.5534.93146.0512.70 4.45 6.3513.97 EA 1.75 2.250.700.3750.350.9044.4557.1517.789.538.8922.86 EH 1.75 2.750.700.3750.350.9044.4569.8517.789.538.8922.86 EB 1.75 3.250.700.3750.350.9044.4582.5517.789.538.8922.86 EJ 1.75 3.750.700.3750.350.9044.4595.2517.789.538.8922.86 EC 1.75 4.250.700.3750.350.9044.45107.9517.789.538.8922.86 ED 1.75 4.750.700.3750.350.9044.45120.6517.789.538.8922.86 EE 1.75 5.250.700.3750.350.9044.45133.3517.789.538.8922.86 EF 1.75 5.750.700.3750.350.9044.45146.0517.789.538.8922.86 BA 2.00 2.250.800.4250.40 1.0050.8057.1520.3210.8010.1625.40 BH 2.00 2.750.800.4250.40 1.0050.8069.8520.3210.8010.1625.40 BB 2.00 3.250.800.4250.40 1.0050.8082.5520.3210.8010.1625.40 BJ 2.00 3.750.800.4250.40 1.0050.8095.2520.3210.8010.1625.40 BC 2.00 4.250.800.4250.40 1.0050.80107.9520.3210.8010.1625.40 BD 2.00 4.750.800.4250.40 1.0050.80120.6520.3210.8010.1625.40 BE 2.00 5.250.800.4250.40 1.0050.80133.2520.3210.8010.1625.40 BF2.005.750.800.4250.401.0050.80146.0520.3210.8010.1625.40元器件交易网Type 401C –55 °C to 105 °C Low-ESR, Wide Temperature GradeTypical Performance Curves元器件交易网Type 401C –55 °C to 105 °C Low-ESR, Wide Temperature Grade RatingsESR Max.25 ºC 120 Hz 20kHz Ripple Amps,85 ºC120 Hz 20 kHz(A) (A)NominalSizeD X L(in)ESR Max.25 ºC120 Hz 20kHzRipple Amps,85 ºC120 Hz 20 kHz(A) (A)NominalSizeD X L(in)Cap. (µF)Catalog PartNumberCap.(µF)Catalog PartNumber6.3 Vdc (9 Vdc Surge) 380000401C384M7R5EE87.20 5.1027.5030.50 1 3/4 X 5 1/842000401C423M6R3AK8 33.4022.708.409.20 1 3/8 X 1 5/8 420000401C424M7R5BD8 5.20 3.9030.9033.40 2 X 4 5/8 66000401C663M6R3AA8 23.0016.1010.8011.80 1 3/8 X 2 1/8 440000401C444M7R5EF8 6.70 4.8030.3033.40 1 3/4 X 5 5/8 92000401C923M6R3AH8 16.8012.0013.0014.20 1 3/8 X 2 5/8 500000401C504M7R5BE8 4.80 3.6032.6035.80 2 X 5 1/8 100000401C104M6R3EA8 21.2015.0011.9013.40 1 3/4 X 2 1/8 560000401C564M7R5BF8 4.50 3.5034.0037.90 2 X 5 5/8 120000401C124M6R3AB8 14.608.5015.4017.00 1 3/8 X 3 1/8 10 Vdc (15 Vdc Surge)140000401C144M6R3AJ8 12.307.3017.7019.20 1 3/8 X 3 5/8 31000401C313M010AK8 33.4022.708.409.20 1 3/8 X 1 5/8 150000401C154M6R3BA8 12.7010.3016.4017.20 2 X 2 1/8 50000401C503M010AA8 23.0016.1010.8011.80 1 3/8 X 2 1/8 150000401C154M6R3EH8 15.1010.7015.1016.90 1 3/4 X 2 5/8 69000401C693M010AH8 16.8012.0013.0014.20 1 3/8 X 2 5/8 170000401C174M6R3AC8 10.80 6.4019.7021.30 1 3/8 X 4 1/8 81000401C813M010EA8 21.2013.3011.9013.40 1 3/4 X 2 1/8 200000401C204M6R3AD8 9.70 5.8021.5023.10 1 3/8 X 4 5/8 91000401C913M010AB8 14.609.5015.4017.00 1 3/8 X 3 1/8 200000401C204M6R3BH8 9.307.3020.5022.10 2 X 2 5/8 110000401C114M010AJ8 12.308.0017.7019.20 1 3/8 X 3 5/8 200000401C204M6R3EB8 11.908.4018.2020.40 1 3/4 X 3 1/8 110000401C114M010BA8 12.7010.3016.4017.20 2 X 2 1/8 230000401C234M6R3AE8 9.00 5.4023.3024.90 1 3/8 X 5 1/8 120000401C124M010EH8 15.109.5015.1016.90 1 3/4 X 2 5/8 250000401C254M6R3BB8 7.40 5.8024.2026.00 2 X 3 1/8 130000401C134M010AC8 10.807.1019.7021.30 1 3/8 X 4 1/8 250000401C254M6R3EJ8 10.007.1020.5022.80 1 3/4 X 3 5/8 150000401C154M010AD8 9.70 6.4021.5023.10 1 3/8 X 4 5/8 260000401C264M6R3AF8 8.40 5.1025.1026.70 1 3/8 X 5 5/8 150000401C154M010BH8 9.307.3020.5022.10 2 X 2 5/8 290000401C294M6R3EC8 8.70 6.2022.6025.20 1 3/4 X 4 1/8 150000401C154M010EB8 11.907.5018.2020.40 1 3/4 X 3 1/8 310000401C314M6R3BJ8 6.50 4.9026.6028.80 2 X 3 5/8 170000401C174M010AE8 9.00 5.9023.3024.90 1 3/8 X 5 1/8 350000401C354M6R3ED8 7.80 5.6025.0027.80 1 3/4 X 4 5/8 180000401C184M010EJ8 10.00 6.3020.5022.80 1 3/4 X 3 5/8 370000401C374M6R3BC8 5.70 4.3029.0030.80 2 X 4 1/8 190000401C194M010AF8 8.40 5.6025.1026.70 1 3/8 X 5 5/8 390000401C394M6R3EE8 7.20 5.1027.5030.50 1 3/4 X 5 1/8 190000401C194M010BB8 7.40 5.8024.2026.00 2 X 3 1/8 420000401C424M6R3BD8 5.20 3.9030.9033.40 2 X 4 5/8 230000401C234M010EC8 8.70 5.5022.6025.20 1 3/4 X 4 1/8 440000401C444M6R3EF8 6.70 4.8030.3033.40 1 3/4 X 5 5/8 240000401C244M010BJ8 6.50 4.9026.6028.80 2 X 3 5/8 510000401C514M6R3BE8 4.80 3.6032.6035.80 2 X 5 1/8 260000401C264M010ED8 7.80 5.0025.0027.80 1 3/4 X 4 5/8 570000401C574M6R3BF8 4.50 3.5034.0037.90 2 X 5 5/8 280000401C284M010BC8 5.70 4.3029.0030.80 2 X 4 1/87.5 Vdc (10 Vdc Surge) 290000401C294M010EE8 7.20 4.6027.5030.50 1 3/4 X 5 1/841000401C413M7R5AK8 33.4022.708.409.20 1 3/8 X 1 5/8 330000401C334M010BD8 5.20 3.9030.9033.40 2 X 4 5/862000401C623M7R5AA8 23.0016.1010.8011.80 1 3/8 X 2 1/8 340000401C344M010EF8 6.70 4.3030.3033.40 1 3/4 X 5 5/8 90000401C903M7R5AH8 16.8012.0013.0014.20 1 3/8 X 2 5/8 390000401C394M010BE8 4.80 3.6032.6035.80 2 X 5 1/8 100000401C104M7R5EA8 21.2015.0011.9013.40 1 3/4 X 2 1/8 440000401C444M010BF8 4.50 3.5034.0037.90 2 X 5 5/8 120000401C124M7R5AB8 14.609.5015.4017.00 1 3/8 X 3 1/8 16 Vdc (24 Vdc Surge)140000401C144M7R5AJ8 12.308.0017.7019.20 1 3/8 X 3 5/8 20000401C203M016AK8 34.7023.008.309.10 1 3/8 X 1 5/8 140000401C144M7R5BA8 12.7010.3016.4017.20 2 X 2 1/8 33000401C333M016AA8 23.9016.3010.6011.70 1 3/8 X 2 1/8 150000401C154M7R5EH8 15.1010.7015.1016.90 1 3/4 X 2 5/8 46000401C463M016AH8 17.4011.2012.8014.20 1 3/8 X 2 5/8 170000401C174M7R5AC8 10.807.1019.7021.30 1 3/8 X 4 1/8 53000401C533M016EA8 21.5015.9011.8013.30 1 3/4 X 2 1/8 190000401C194M7R5AD8 9.70 6.4021.5023.10 1 3/8 X 4 5/8 60000401C603M016AB8 14.908.9015.2016.90 1 3/8 X 3 1/8 190000401C194M7R5BH8 9.307.3020.5022.10 2 X 2 5/8 74000401C743M016AJ8 12.507.5017.5019.10 1 3/8 X 3 5/8 190000401C194M7R5EB8 11.908.4018.2020.40 1 3/4 X 3 1/8 75000401C753M016BA8 12.7010.2016.4017.40 2 X 2 1/8 230000401C234M7R5AE8 9.00 5.9023.3024.90 1 3/8 X 5 1/8 78000401C783M016EH8 15.3011.3014.9016.80 1 3/4 X 2 5/8 240000401C244M7R5EJ8 10.007.1020.5022.80 1 3/4 X 3 5/8 89000401C893M016AC8 11.00 6.6019.5021.20 1 3/8 X 4 1/8 250000401C254M7R5AF8 8.40 5.6025.1026.70 1 3/8 X 5 5/8 100000401C104M016AD8 9.407.3020.4022.10 2 X 2 5/8 250000401C254M7R5BB8 7.40 5.8024.2026.00 2 X 3 1/8 100000401C104M016BH8 12.008.9018.1020.30 1 3/4 X 3 1/8 290000401C294M7R5EC8 8.70 6.2022.6025.20 1 3/4 X 4 1/8 100000401C104M016EB8 9.90 6.0021.3023.00 1 3/8 X 4 5/8 300000401C304M7R5BJ8 6.50 4.9026.6028.80 2 X 3 5/8 120000401C124M016AE8 9.10 5.5023.1024.80 1 3/8 X 5 1/8 340000401C344M7R5ED8 7.80 5.6025.0027.80 1 3/4 X 4 5/8 130000401C134M016AF8 8.60 5.2024.9026.60 1 3/8 X 5 5/8 370000401C374M7R5BC8 5.70 4.3029.0030.80 2 X 4 1/8 130000401C134M016BB8 7.50 5.8024.0026.00 2 X 3 1/8 元器件交易网Type 401C –55 °C to 105 °C Low-ESR, Wide Temperature GradeESR Max.25 ºC 120 Hz 20 kHz (mΩ) (mΩ)Ripple Amps,85 ºC120 Hz 20 kHz(A) (A)NominalSizeD X L(in)ESR Max.25 ºC120 Hz 20 kHz(mΩ) (mΩ)Ripple Amps,85 ºC120 Hz 20 kHz(A) (A)NominalSizeD X L(in)Cap. (µF)Catalog PartNumberCap.(µF)Catalog PartNumber130000401C134M016EJ8 10.107.5020.3022.80 1 3/4 X 3 5/8 66000401C663M025AD8 10.70 6.8020.4022.80 1 3/8 X 4 5/8 150000401C154M016EC8 8.80 6.6022.5025.10 1 3/4 X 4 1/8 66000401C663M025EB8 12.808.8017.5020.20 1 3/4 X 3 1/8 160000401C164M016BJ8 6.60 5.0026.4028.80 2 X 3 5/8 75000401C753M025AE8 9.90 6.3022.2024.60 1 3/8 X 5 1/8 170000401C174M016ED8 7.90 6.0024.9027.70 1 3/4 X 4 5/8 81000401C813M025EJ8 10.707.4019.7022.60 1 3/4 X 3 5/8 180000401C184M016BC8 5.80 4.4028.8030.70 2 X 4 1/8 83000401C833M025BB8 8.00 6.1023.4025.80 2 X 3 1/8 190000401C194M016EE8 7.30 5.5027.4030.40 1 3/4 X 5 1/8 84000401C843M025AF8 9.20 5.9023.9026.40 1 3/8 X 5 5/8 220000401C224M016BD8 5.20 4.0030.7033.30 2 X 4 5/8 96000401C963M025EC8 9.30 6.5021.8025.00 1 3/4 X 4 1/8 220000401C224M016EF8 6.80 5.2030.1033.40 1 3/4 X 5 5/8 100000401C104M025BJ8 7.00 5.1025.7028.60 2 X 3 5/8 260000401C264M016BE8 4.80 3.7032.4035.70 2 X 5 1/8 110000401C114M025ED8 8.40 5.8024.2027.50 1 3/4 X 4 5/8 280000401C284M016BF8 4.60 3.5033.8037.90 2 X 5 5/8 120000401C124M025BC8 6.10 4.5028.1030.60 2 X 4 1/820 Vdc (30 Vdc Surge) 130000401C134M025EE8 7.70 5.3026.6030.20 1 3/4 X 5 1/817000401C173M020AK8 37.9023.708.409.10 1 3/8 X 1 5/8 140000401C144M025BD8 5.50 4.1029.9033.20 2 X 4 5/8 26000401C263M020AA8 26.0016.8010.9011.70 1 3/8 X 2 1/8 140000401C144M025EF8 7.10 5.0029.3033.20 1 3/4 X 5 5/8 33000401C333M020AH8 18.9012.4013.2014.10 1 3/8 X 2 5/8 160000401C164M025BE8 5.10 3.8031.7035.60 2 X 5 1/8 45000401C453M020EA8 22.3015.5011.6013.30 1 3/4 X 2 1/8 180000401C184M025BF8 4.80 3.6033.1037.70 2 X 5 5/8 50000401C503M020AB8 15.609.9015.1016.80 1 3/8 X 3 1/8 40 Vdc (60 Vdc Surge)58000401C583M020BA8 13.2010.4016.1017.30 2 X 2 1/8 8200401C822M040AK8 44.2025.907.608.80 1 3/8 X 1 5/8 61000401C613M020AJ8 13.108.3017.1019.00 1 3/8 X 3 5/8 12000401C123M040AA8 30.2018.309.7011.40 1 3/8 X 2 1/8 64000401C643M020EH8 15.8011.0014.7016.80 1 3/4 X 2 5/8 20000401C203M040EA8 24.7016.5011.0013.10 1 3/4 X 2 1/8 73000401C733M020AC8 11.507.3019.1021.10 1 3/8 X 4 1/822000401C223M040AH8 22.1013.6011.9013.80 1 3/8 X 2 5/8 82000401C823M020BH8 9.807.5020.1022.00 2 X 2 5/823000401C233M040AB8 17.8010.7013.7016.50 1 3/8 X 3 1/8 84000401C843M020EB8 12.408.7017.8020.30 1 3/4 X 3 1/8 27000401C273M040BA8 14.7011.1015.1017.10 2 X 2 1/8 85000401C853M020AD8 10.30 6.6020.9022.90 1 3/8 X 4 5/828000401C283M040AJ8 14.909.0015.2018.60 1 3/8 X 3 5/8 96000401C963M020AE8 9.50 6.1022.6024.70 1 3/8 X 5 1/830000401C303M040EH8 17.5011.7013.9016.50 1 3/4 X 2 5/8 100000401C104M020AF8 10.407.3020.0022.70 1 3/4 X 3 5/834000401C343M040AC8 13.007.9016.5020.70 1 3/8 X 4 1/8 100000401C104M020BB8 7.70 5.9023.7025.90 2 X 3 1/838000401C383M040BH8 10.808.0019.0021.80 2 X 2 5/8 100000401C104M020EJ8 8.90 5.8024.4026.50 1 3/8 X 5 5/839000401C393M040AD8 11.607.1018.1022.50 1 3/8 X 4 5/8 120000401C124M020EC8 9.10 6.4022.1025.00 1 3/4 X 4 1/839000401C393M040EB8 13.709.2016.9020.00 1 3/4 X 3 1/8 130000401C134M020BJ8 6.80 5.0026.0028.70 2 X 3 5/8 45000401C453M040AE8 10.70 6.6019.7024.30 1 3/8 X 5 1/8 140000401C144M020ED8 8.10 5.7024.5027.60 1 3/4 X 4 5/849000401C493M040EJ8 11.407.7019.1022.50 1 3/4 X 3 5/8 150000401C154M020BC8 6.00 4.5028.5030.70 2 X 4 1/8 50000401C503M040BB8 8.60 6.3022.5025.70 2 X 3 1/8 160000401C164M020EE8 7.50 5.3027.0030.30 1 3/4 X 5 1/850000401C503M040AF8 9.90 6.2021.3026.10 1 3/8 X 5 5/8 170000401C174M020BD8 5.40 4.0030.3033.20 2 X 4 5/8 58000401C583M040EC8 9.90 6.7021.1024.80 1 3/4 X 4 1/8 180000401C184M020EF8 7.00 4.9029.7033.30 1 3/4 X 5 5/8 61000401C613M040BJ8 7.50 5.3025.0028.40 2 X 3 5/8 220000401C224M020BE8 4.90 3.7032.1035.70 2 X 5 1/8 68000401C683M040ED8 8.90 6.0023.4027.40 1 3/4 X 4 5/8 240000401C244M020BF8 4.70 3.5033.5037.80 2 X 5 5/8 73000401C733M040BC8 6.50 4.7027.0030.40 2 X 4 1/825 Vdc (35 Vdc Surge) 77000401C773M040EE8 8.10 5.5025.9030.00 1 3/4 X 5 1/813000401C133M025AK8 41.0024.408.109.00 1 3/8 X 1 5/884000401C843M040BD8 5.90 4.2029.1033.00 2 X 4 5/8 20000401C203M025AA8 28.1017.2010.5011.60 1 3/8 X 2 1/8 86000401C863M040EF8 7.60 5.2028.5033.00 1 3/4 X 5 5/8 33000401C333M025AH8 20.3012.8012.8014.00 1 3/8 X 2 5/8 100000401C104M040BE8 5.40 3.9030.9035.40 2 X 5 1/8 35000401C353M025EA8 23.0015.8011.4013.20 1 3/4 X 2 1/8110000401C114M040BF8 5.10 3.7031.8037.50 2 X 5 5/8 38000401C383M025AB8 16.3010.1014.6016.70 1 3/8 X 3 1/8 50 Vdc (75 Vdc Surge)45000401C453M025BA8 13.6010.6015.9017.30 2 X 2 1/85600401C562M050AK8 46.6027.307.208.40 1 3/8 X 1 5/8 48000401C483M025AJ8 13.608.5016.7018.90 1 3/8 X 3 5/88400401C842M050AA8 30.2019.309.2010.80 1 3/8 X 2 1/8 50000401C503M025EH8 16.3011.2014.4016.70 1 3/4 X 2 5/811000401C113M050AH8 22.5014.3011.6013.10 1 3/8 X 2 5/8 57000401C573M025AC8 11.907.5018.7021.00 1 3/8 X 4 1/814000401C143M050EA8 28.3018.9010.0011.80 1 3/4 X 2 1/8 63000401C633M025BH8 10.107.6019.8021.90 2 X 2 5/815000401C153M050AB8 18.1011.3013.4015.70 1 3/8 X 3 1/8 元器件交易网Type 401C –55 °C to 105 °C Low-ESR, Wide Temperature GradeESR Max.25 ºC 120 Hz 20 kHz (mΩ) (mΩ)Ripple Amps,85 ºC120 Hz 20 kHz(A) (A)NominalSizeD X L(in)ESR Max.25 ºC120 Hz 20 kHz(mΩ) (mΩ)Ripple Amps,85 ºC120 Hz 20 kHz(A) (A)NominalSizeD X L(in)Cap. (µF)Catalog PartNumberCap.(µF)Catalog PartNumber18000401C183M050BA8 18.7014.4012.4014.80 2 X 2 1/8 75 Vdc (100 Vdc Surge)19000401C193M050AJ8 15.109.5014.6017.80 1 3/8 X 3 5/8 2500401C252M075AK8 93.8046.00 5.70 6.40 1 3/8 X 1 5/8 20000401C203M050EH8 20.0013.4012.7015.00 1 3/4 X 2 5/8 4100401C412M075AA8 59.0029.107.608.60 1 3/8 X 2 1/8 23000401C233M050AC8 13.008.3015.3019.90 1 3/8 X 4 1/8 6600401C662M075AH8 39.8019.709.7010.70 1 3/8 X 2 5/8 26000401C263M050BH8 13.7010.2015.9018.90 2 X 2 5/8 7900401C792M075EA8 41.0021.209.0010.70 1 3/4 X 2 1/8 27000401C273M050AD8 12.207.4016.7021.70 1 3/8 X 4 5/8 8200401C822M075AB8 30.3015.1011.4013.10 1 3/8 X 3 1/8 27000401C273M050EB8 15.6010.5015.5018.20 1 3/4 X 3 1/8 10000401C103M075BA8 30.8017.509.0014.30 2 X 2 1/8 30000401C303M050AE8 11.20 6.8018.1023.40 1 3/8 X 5 1/8 10000401C103M075AJ8 24.6012.4012.2015.00 1 3/8 X 3 5/8 33000401C333M050EJ8 13.008.8017.6020.50 1 3/4 X 3 5/8 11000401C113M075EH8 28.7014.9011.4013.60 1 3/4 X 2 5/8 34000401C343M050AF8 10.40 6.4019.4025.20 1 3/8 X 5 5/8 12000401C123M075AC8 20.9010.7012.9017.00 1 3/8 X 4 1/8 34000401C343M050BB8 10.808.1018.9022.40 2 X 3 1/8 14000401C143M075BH8 18.309.4014.2018.70 1 3/8 X 4 5/8 39000401C393M050EC8 11.207.6019.5022.70 1 3/4 X 4 1/8 14000401C143M075AD8 21.7012.3013.0017.80 2 X 2 5/8 41000401C413M050BJ8 9.30 6.8022.6025.00 2 X 3 5/8 15000401C153M075EB8 22.3011.7013.9016.60 1 3/4 X 3 1/8 46000401C463M050ED8 10.00 6.8021.7025.20 1 3/4 X 4 5/8 16000401C163M075AE8 16.308.5015.5020.40 1 3/8 X 5 1/8 50000401C503M050BC8 8.10 5.9024.3026.90 2 X 4 1/8 18000401C183M075BB8 14.907.9016.9022.20 1 3/8 X 5 5/8 52000401C523M050EE8 9.10 6.2024.1027.80 1 3/4 X 5 1/8 18000401C183M075EJ8 18.309.7015.8018.70 1 3/4 X 3 5/8 58000401C583M050EF8 8.40 5.8026.6030.60 1 3/4 X 5 5/8 18000401C183M075AF8 16.809.7015.4021.60 2 X 3 1/8 58000401C583M050BD8 7.20 5.3026.1029.20 2 X 4 5/8 22000401C223M075EC8 15.708.3017.6020.80 1 3/4 X 4 1/8 60000401C603M050BE8 6.50 4.8028.0031.70 2 X 5 1/8 23000401C233M075BJ8 13.908.1021.3024.10 2 X 3 5/8 70000401C703M050BF8 6.10 4.5028.9033.90 2 X 5 5/8 25000401C253M075ED8 13.807.4019.7023.20 1 3/4 X 4 5/863 Vdc (90 Vdc Surge) 27000401C273M075BC8 12.007.0020.4026.00 2 X 4 1/84800401C482M063AK8 50.0028.20 6.908.30 1 3/8 X 1 5/8 28000401C283M075EE8 12.40 6.7021.8025.70 1 3/4 X 5 1/8 7200401C722M063AA8 32.4019.608.9010.70 1 3/8 X 2 1/8 31000401C313M075BD8 10.60 6.2022.3028.30 2 X 4 5/8 11000401C113M063AH8 24.1014.7011.2013.00 1 3/8 X 2 5/8 33000401C333M075EF8 12.80 6.2024.3028.40 1 3/4 X 5 5/8 12000401C123M063EA8 26.0019.309.9011.80 1 3/4 X 2 1/8 37000401C373M075BE8 9.30 5.6024.4030.80 2 X 5 1/8 13000401C133M063AB8 19.0011.6013.0015.60 1 3/8 X 3 1/8 41000401C413M075BF8 8.60 5.2026.2032.90 2 X 5 5/8 15000401C153M063BA8 19.3014.7011.9014.80 2 X 2 1/8 100 Vdc (140 Vdc Surge)16000401C163M063AJ8 15.809.7014.2017.70 1 3/8 X 3 5/8 1400401C142M100AK8 118.0034.70 4.30 6.20 1 3/8 X 1 5/8 17000401C173M063EH8 18.3013.7012.5014.90 1 3/4 X 2 5/8 2200401C222M100AA8 73.1020.90 5.908.50 1 3/8 X 2 1/8 19000401C193M063AC8 13.608.5014.9019.80 1 3/8 X 4 1/8 3500401C352M100AH8 46.5014.007.5010.60 1 3/8 X 2 5/8 22000401C223M063BH8 14.1010.4015.3018.90 2 X 2 5/8 4100401C412M100EA8 44.7017.508.0010.30 1 3/4 X 2 1/8 23000401C233M063EB8 12.707.6016.3021.50 1 3/8 X 4 5/8 4600401C462M100AB8 36.0011.009.1012.90 1 3/8 X 3 1/8 23000401C233M063AD8 14.3010.7015.3018.10 1 3/4 X 3 1/8 5300401C532M100BA8 37.5016.508.2011.90 2 X 2 1/8 26000401C263M063AE8 11.607.0017.7023.30 1 3/8 X 5 1/8 5700401C572M100AJ8 29.609.2010.5014.70 1 3/8 X 3 5/8 28000401C283M063EJ8 11.908.9017.3020.40 1 3/4 X 3 5/8 6000401C602M100EH8 31.3012.4010.2013.10 1 3/4 X 2 5/8 29000401C293M063BB8 10.80 6.6019.1025.10 1 3/8 X 5 5/8 6800401C682M100AC8 25.308.1011.9016.50 1 3/8 X 4 1/8 29000401C293M063AF8 11.108.2018.1022.40 2 X 3 1/8 7500401C752M100BH8 26.3011.7010.6015.30 2 X 2 5/8 34000401C343M063EC8 10.307.7019.2022.60 1 3/4 X 4 1/8 7900401C792M100EB8 22.207.2013.2018.10 1 3/8 X 4 5/8 36000401C363M063BJ8 9.60 6.9022.2024.90 2 X 3 5/8 7900401C792M100AD8 24.209.7012.5015.90 1 3/4 X 3 1/8 39000401C393M063ED8 9.20 6.9021.4025.10 1 3/4 X 4 5/8 9000401C902M100AE8 19.90 6.6014.5019.80 1 3/8 X 5 1/8 42000401C423M063BC8 8.30 6.0024.0026.80 2 X 4 1/8 9700401C972M100EJ8 19.908.1014.1018.00 1 3/4 X 3 5/8 45000401C453M063EE8 8.30 6.3023.7027.70 1 3/4 X 5 1/8 10000401C103M100BB8 20.409.2012.6018.20 2 X 3 1/8 50000401C503M063BD8 7.70 5.9026.3030.50 1 3/4 X 5 5/8 10000401C103M100AF8 18.10 6.2015.8021.40 1 3/8 X 5 5/8 50000401C503M063EF8 7.40 5.4025.8029.10 2 X 4 5/8 12000401C123M100BJ8 15.80 6.9016.3023.60 2 X 4 1/8 59000401C593M063BE8 6.70 4.8027.7031.70 2 X 5 1/8 12000401C123M100EC8 17.007.0015.8020.00 1 3/4 X 4 1/8 66000401C663M063BF8 6.20 4.5028.6033.80 2 X 5 5/8 12000401C123M100BC8 16.907.6015.5022.30 2 X 3 5/8 元器件交易网Type 401C –55 °C to 105 °C Low-ESR, Wide Temperature GradeESR Max.25 ºC 120 Hz 20 kHz (mΩ) (mΩ)Ripple Amps,85 ºC120 Hz 20 kHz(A) (A)NominalSizeD X L(in)ESR Max.25 ºC120 Hz 20 kHz(mΩ) (mΩ)Ripple Amps,85 ºC120 Hz 20 kHz(A) (A)NominalSizeD X L(in)Cap. (µF)Catalog PartNumberCap.(µF)Catalog PartNumber13000401C133M100ED8 14.90 6.2017.6022.20 1 3/4 X 4 5/8 2500401C252M200EB8 89.0058.108.4010.80 2 X 2 5/8 15000401C153M100BD8 13.40 5.7019.6024.60 1 3/4 X 5 1/8 2500401C252M200AD8 81.8054.407.7011.00 1 3/8 X 4 5/8 15000401C153M100EE8 13.60 6.3017.9025.60 2 X 4 5/8 2500401C252M200BH8 80.4055.607.6010.90 1 3/4 X 3 1/8 17000401C173M100EF8 13.80 5.3021.8027.20 1 3/4 X 5 5/8 2800401C282M200AE8 75.4049.208.6012.00 1 3/8 X 5 1/8 18000401C183M100BE8 11.80 5.5019.8028.10 2 X 5 1/8 3100401C312M200EJ8 65.4045.208.7012.40 1 3/4 X 3 5/8 20000401C203M100BF8 10.80 5.1021.4030.30 2 X 5 5/8 3300401C332M200AF8 66.6044.7010.1012.90 2 X 3 1/8 150 Volts (200 Volts Surge) 3300401C332M200BB8 70.1045.109.5012.90 1 3/8 X 5 5/8 710401C711M150AK8 342.00245.00 2.60 3.60 1 3/8 X 1 5/8 3700401C372M200EC8 55.2038.209.8013.90 1 3/4 X 4 1/8 1100401C112M150AA8 228.00164.00 3.70 5.00 1 3/8 X 2 1/8 4000401C402M200BJ8 53.9036.4012.0015.90 2 X 3 5/8 1500401C152M150AH8 159.00114.00 4.50 6.30 1 3/8 X 2 5/8 4400401C442M200ED8 47.8033.2011.0015.60 1 3/4 X 4 5/8 1700401C172M150EA8 145.00101.00 5.307.10 1 3/4 X 2 1/8 4800401C482M200BC8 45.5030.8012.9017.30 2 X 4 1/8 1900401C192M150AB8 122.0087.20 5.507.70 1 3/8 X 3 1/8 4900401C492M200EE8 42.3029.4012.4017.50 1 3/4 X 5 1/8 2500401C252M150AJ8 112.0078.807.008.60 2 X 2 1/8 5500401C552M200EF8 42.1027.4014.0018.90 2 X 4 5/8 2500401C252M150BA8 98.8071.00 6.408.90 1 3/8 X 3 5/8 5500401C552M200BD8 38.0026.4013.9019.50 1 3/4 X 5 5/8 2600401C262M150EH8 100.0070.30 6.709.00 1 3/4 X 2 5/8 6200401C622M200BE8 37.7024.3014.8020.60 2 X 5 1/8 2900401C292M150AC8 83.4059.907.4010.20 1 3/8 X 4 1/8 7000401C702M200BF8 34.3021.9015.5022.20 2 X 5 5/8 3400401C342M150AD8 80.2057.008.9011.00 2 X 2 5/8 250 Vdc (300 Vdc Surge)3400401C342M150EB8 77.0054.008.3011.10 1 3/4 X 3 1/8 380401C381M250AK8 510.00285.00 2.20 3.30 1 3/8 X 1 5/8 3400401C342M150BH8 72.3052.008.2011.30 1 3/8 X 4 5/8 610401C611M250AA8 309.00190.00 3.10 4.70 1 3/8 X 2 1/8 3900401C392M150AE8 63.9046.009.2012.40 1 3/8 X 5 1/8 860401C861M250AH8 215.00132.00 3.90 6.00 1 3/8 X 2 5/8 4200401C422M150EJ8 62.6043.909.5012.60 1 3/4 X 3 5/8 960401C961M250EA8 222.00113.00 4.40 6.60 1 3/4 X 2 1/8 4400401C442M150AF8 62.9041.4010.1013.50 1 3/8 X 5 5/8 1100401C112M250AB8 165.00101.00 4.707.30 1 3/8 X 3 1/8 4500401C452M150BB8 60.1044.2010.7013.20 2 X 3 1/8 1300401C132M250AJ8 134.0082.50 5.508.30 1 3/8 X 3 5/8 5000401C502M150EC8 52.9037.2010.7014.10 1 3/4 X 4 1/8 1400401C142M250EH8 149.0091.20 5.908.30 2 X 2 1/8 5500401C552M150BJ8 48.6036.3012.9016.20 2 X 3 5/8 1400401C142M250BA8 154.0078.60 5.608.50 1 3/4 X 2 5/8 5800401C582M150ED8 45.9032.3012.0015.80 1 3/4 X 4 5/8 1700401C172M250AC8 101.0062.40 6.9010.30 1 3/8 X 4 5/8 6600401C662M150BC8 41.1031.2013.7017.60 2 X 4 1/8 1700401C172M250AD8 100.0062.20 6.6010.00 1 3/8 X 4 1/8 6700401C672M150EE8 40.6028.6013.5017.50 1 3/4 X 5 1/8 1800401C182M250EB8 118.0060.40 6.9010.40 1 3/4 X 3 1/8 7300401C732M150BD8 38.0028.0014.7019.20 2 X 4 5/8 1900401C192M250BH8 103.0063.307.6010.60 2 X 2 5/8 7400401C742M150EF8 36.5025.7015.1019.30 1 3/4 X 5 5/8 2000401C202M250AE8 88.8054.907.7011.20 1 3/8 X 5 1/8 8400401C842M150BE8 34.1025.2015.7020.90 2 X 5 1/8 2300401C232M250EJ8 79.3049.208.6012.20 1 3/8 X 5 5/8 9400401C942M150BF8 31.0023.0016.8022.60 2 X 5 5/8 2300401C232M250AF8 96.0049.107.9011.80 1 3/4 X 3 5/8 200 Vdc (250 Vdc Surge) 2500401C252M250BB8 79.3048.709.1012.70 2 X 3 1/8 520401C521M200AK8 370.00233.00 2.50 3.50 1 3/8 X 1 5/8 2800401C282M250EC8 81.0041.508.9013.30 1 3/4 X 4 1/8 810401C811M200AA8 247.00156.00 3.40 4.90 1 3/8 X 2 1/8 3000401C302M250BJ8 64.5039.7011.0015.70 2 X 3 5/8 1100401C112M200AH8 172.00111.00 4.20 6.10 1 3/8 X 2 5/8 3100401C312M250ED8 70.2036.0010.1014.90 1 3/4 X 4 5/8 1300401C132M200EA8 151.0096.20 4.807.00 1 3/4 X 2 1/8 3600401C362M250EE8 62.0031.9011.3016.70 1 3/4 X 5 1/8 1500401C152M200AB8 132.0086.60 5.207.50 1 3/8 X 3 1/8 3700401C372M250BC8 54.5033.6011.9017.20 2 X 4 1/8 1800401C182M200AJ8 124.0080.80 6.608.40 2 X 2 1/8 3900401C392M250EF8 55.6028.6012.7018.60 1 3/4 X 5 5/8 1800401C182M200BA8 107.0071.80 6.008.80 1 3/8 X 3 5/8 4200401C422M250BD8 47.3029.2012.8018.70 2 X 4 5/8 1900401C192M200EH8 105.0072.40 6.208.90 1 3/4 X 2 5/8 4800401C482M250BE8 41.9025.9013.6020.00 2 X 5 1/8 2200401C222M200AC8 90.2061.80 6.9010.10 1 3/8 X 4 1/8 5300401C532M250BF8 37.6023.3014.4021.20 2 X 5 5/8 元器件交易网。

TPS40180资料

FEATURES CONTENTSDESCRIPTIONAPPLICATIONS•Stackable to 8Phases,Multiple Controllers Description 1Can Occupy Any Phase•2-V to 40-V Power Stage Operation Range Device Ratings3•eTrim™in System Reference Voltage Trim to Electrical Characteristics 4Tighten Overall Output Voltage Tolerance,Terminal Information 7Reference is Better Than 0.75%Un-Trimmed Typical Characteristics 10•VDD From 4.5V to 15V,With Internal 5-V RegulatorApplication Information 15•Supports Output Voltage From 0.7V to 5.8V Design Example35•Supports Pre-Biased Outputs •10-µA Shutdown Current•Programmable Switching Frequency up to The TPS40180is a stackable single-phase 1-MHz per Phasesynchronous buck controller.Stacking allows a modular power supply design where multiple modules •Current Feedback Control With Forced Current can be connected in parallel to achieve the desired Sharing (Patents Pending)output power capability if the output power •Resistive Divider Sets Input Undervoltage requirement cannot be provided by one module.Lockout and HysteresisStacked modules can be configured to switch at •True Remote Sensing Differential Amplifier different times while running at the same base frequency creating a multiple phase supply.Up to •Resistive or Inductor’s DCR Current Sensingeight phases can be configured,and multiple modules can be set up to switch on the same phase if required.Input and output ripple current reduction •Graphic Cards occurs as well when modules are stacked.Stacked •Serversmodules can be used to generate separate output rails,load share into a single rail or a combination of •Networking Equipmentthe two while sharing phase information to reduce •Telecommunications Equipment ripple currents at the input of the system.•Distributed DC Power SystemsThe TPS40180is optimized for low-output voltage (from 0.7-V to 5.8-V),high-output current applications powered from a 2-V to 40-V supply.The TPS40180converts from 15-V input to 0.7-V output at 1MHz.Each phase can be operated at a switching frequency up to 1MHz,resulting in an effective ripple frequency of up to 8MHz at the input and the output.With eTrim™,the TPS40180gives the user the capability to trim the reference voltage on the device to compensate for external component tolerances,tightening the overall system accuracy and allowing tighter specifications for output voltage of the converter.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.eTrim is a trademark of Texas Instruments.PRODUCTION DATA information is current as of publication date.Copyright ©2007,Texas Instruments IncorporatedProducts conform to specifications per the terms of the Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.V IN (+)V IN (-)V OUT (+)V OUT (-)TPS40180SLVS753B–FEBRUARY 2007–REVISED NOVEMBER 2007These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.ORDERING INFORMATIONPACKAGE (1)TAPE AND REEL QUANTITYPART NUMBER 250TPS40180RGET Plastic 24-Pin QFN (RGE)3000TPS40180RGER(1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TI website at .TYPICAL APPLICATION2Submit Documentation FeedbackCopyright ©2007,Texas Instruments IncorporatedProduct Folder Link(s):TPS40180DEVICE RATINGSABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED OPERATING CONDITIONSELECTROSTATIC DISCHARGE(ESD)PROTECTION PACKAGE DISSIPATION RATINGS(1)TPS40180 SLVS753B–FEBRUARY2007–REVISED NOVEMBER2007TPS40180UNITVDD,UVLO,RT,SS–0.3to16V I Input voltage range VFB,VOUT,GSNS,VSH,ILIM,BP5,PSEL,CS+,CS–,VS+,VS––0.3to6BOOT–HDRV–0.3to6SW,HDRV–1to44V O Output voltage range SW,HDRV,transient<50ns–5to44VDIFFO,LDRV,PVCC,CLKIO,PGOOD,COMP–0.3to6PGOOD(eTrim™usage only)–0.3to22T J Operating junction temperature range-40to150°CT stg Storage temperature range-55to150(1)Stresses beyond those listed under"absolute maximum ratings"may cause permanent damage to the device.These are stress ratingsonly,and functional operation of the device at these or any other conditions beyond those indicated under"recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.MIN NOM MAX UNIT VDD,UVLO 4.515SW–140V I V BOOT-SW 5.5All Other Pins0 5.8RT25µA PSEL150T J Operating junction temperature-40105°CMIN NOM MAX UNITHuman Body Model(HBM)2500V Charged Device Model(CDM)1500THERMAL IMPEDANCEJUNCTION-TO-AMBIENT AIRFLOW(LFM)T A=25°C POWER RATING(W)T A=85°C POWER RATING(W) (°C/W)42Natural Convection 2.380.95035200 2.85 1.1432400 3.10 1.25(1)Ratings based on JEDEC High Thermal Conductivity(High K)Board.For more information on the test method,see TI Technical BriefSZZA017.Copyright©2007,Texas Instruments Incorporated Submit Documentation Feedback3Product Folder Link(s):TPS40180ELECTRICAL CHARACTERISTICSTPS40180SLVS753B–FEBRUARY 2007–REVISED NOVEMBER 2007V VDD =12V,V BP5=5V,V PVCC =5V,–40°C <T J <85°C (unless otherwise noted)PARAMETERTEST CONDITIONS MIN TYP MAX UNIT VDD INPUT SUPPLY V VDD Operating voltage range 4.51215V I VDDSD Shutdown current V UVLO <0.5V50µA BP5INPUT SUPPLYV BP5Operating voltage range 4.3 5.0 5.5V I BP5Operating current235mA V BP5UV Rising undervoltage turn on threshold 4.04.25 4.5V V BP5UVH BP5UVLO hysteresis 225mVPVCC REGULATORV PVCC Output voltage 4.5V <V VDD <15V4.35.05.5V I PVCC Output current 050mAOSCILLATORF OSC Oscillator frequency R RT =64.9k Ω360415454kHz Oscillator frequency range 1501000V RMP Ramp voltage (1)420500525mV V RTCKLSLV RT pin clock slave voltage threshold 2VDIGITAL CLOCK SIGNAL (CLKIO)R CLKH Pull Up Resistance (1)27ΩR CLKL Pull Down Resistance(1)27I CLKIOLK Leakage current in high impedance V RT <2V,V PSEL =5V1µAstate (1)UVLO PIN PVCC regulator enabled 0.80.9 1.5V UVLO(on)V PWM switching enabled 1.9 2.0 2.1I UVLO Hysteresis bias current91215µAPULSE WIDTH MODULATORD MAX 8phase CLK scheme 87.5%Maximum duty cycle 6phase CLK scheme83%t ON(min)Minimum pulse width (1)75nsVSHARE V VSHCurrent share reference;Ramp valley R LOAD =20k Ω 1.7 1.8 1.9VvoltageERROR AMPLIFIER I IB Input bias current at FB pinV FB =0.7V–2000200nA V REF Trimmed FB control voltage (includes 695700705mV differential sense amp offset I OH COMP source current V COMP =1.1V,V FB =0.6V 12mA I OL COMP sink current V COMP =1.1V,V FB =0.8V12EA GBWP Gain bandwidth product (1)812MHz A OLOpen loop gain(1)6090dBSOFTSTART Charging Current:device Enabled,I SS1Before First PWM Pulse and During 6.57.58.2Hiccup Fault RecoveryµACharging Current After First PWM I SS2121517PulseV SS_FE Fault Enable Threshold0.8VVoltage loop slave mode threshold V BP5-V SSSLVV BP5=5Vvoltage0.75CURRENT LIMIT I ILIMThreshold setting current21.523.525.5µA(1)Specified by design.Not production tested .4Submit Documentation FeedbackCopyright ©2007,Texas Instruments IncorporatedProduct Folder Link(s):TPS40180TPS40180 SLVS753B–FEBRUARY2007–REVISED NOVEMBER2007ELECTRICAL CHARACTERISTICS(continued)V VDD=12V,V BP5=5V,V PVCC=5V,–40°C<T J<85°C(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITCURRENT SENSE AMPLIFIERV ISOFST Input offset voltage–2.50 2.5mVI IB_CS Input bias current100nAG CS Gain at PWM Input0.2V≤V ICM≤5.8V11.2512.513.75V/VV ICM Input common mode range0 5.8VV DIFFMX Maximum differential input voltage–6060mV DIFFERENTIAL REMOTE VOLTAGE SENSE AMPLIFIERG RVS Gain0.7V<V(VOUT)–V(GSNS)<5.8V0.995 1.000 1.005V/VV(VOUT)–V(GSNS)=2V,V(DIFFO)>1.98V,2V(VDD)–V(VOUT)>2VI DIFFOH DIFFO source current mAV(VOUT)–V(GSNS)=5.8V,V(DIFFO)>5.6V,1V(VDD)–V(VOUT)=1VI DIFFOL DIFFO sink current V(VOUT)–V(GSNS)=2V,V(DIFFO)≥2.02V2mABW DIFFA Unity gain bandwidth(2)58MHzInput resistance,inverting DIFFO to GSNS60R INDIFFA kΩInput resistance,noninverting OUT to GND60PSEL PINI ISEL Bias current21.523.525.5µAV MNCLK Master mode,no output on CLKIO000.5V M8PH Master mode,6phase CLKIO0.50.70.9V M6PH Master mode,8phase CLKIO0.9V SSTDBY Slave mode,standby state 3.4Clock slave mode,8phase CLKIO,45°V S45000.2 phase slot(2)Clock slave mode,8phase CLKIO,90°V S900.20.350.5 phase slot(2)Slave mode,8phase CLKIO,135°V S1350.50.70.9 phase slot(2)Clock slave mode,8phase CLKIO,V S1800.9 1.1 1.3 180°phase slot(2)Clock slave mode,8phase CLKIO,V S225 1.3 1.6 1.9 225°phase slot(2)V Clock slave mode,8phase CLKIO,V S270 1.9 2.25 2.6 270°phase slot(2)Clock slave mode,8phase CLKIO,V S315 2.6 3.0 3.4 315°phase slot(2)Clock slave mode,6phase CLKIO,V S0 1.9 2.25 2.6 0phase slot(2)Clock slave mode,6phase CLKIO,60°V S60000.2 phase slot(2)Clock slave mode,6phase CLKIO,V S1200.20.350.5 120°phase slot(2)Clock slave mode,6phase CLKIO,V S1800.50.70.9 180°phase slot(2)Clock slave mode,6phase CLKIO,V S2400.9 1.1 1.3 240°phase slot(2)Clock slave mode,6phase CLKIO,V S300 1.3 1.6 1.9 300°phase slot(2)(2)Specified by design.Not production tested.Copyright©2007,Texas Instruments Incorporated Submit Documentation Feedback5Product Folder Link(s):TPS40180TPS40180SLVS753B–FEBRUARY 2007–REVISED NOVEMBER 2007ELECTRICAL CHARACTERISTICS (continued)V VDD =12V,V BP5=5V,V PVCC =5V,–40°C <T J <85°C (unless otherwise noted)PARAMETERTEST CONDITIONSMIN TYP MAXUNITGATE DRIVERS R HDRV(on)HDRV Pull Up Resistance V BOOT =5V,V (SW)=0V,I HDRV =100mA 123R HDRV(off)HDRV Pull Down Resistance V BOOT =5V,V SW =0V,I HDRV =100mA 0.512ΩR LDRV(on)LDRV pull up resistance V PVCC =5V,I LDRV =100mA 12 3.5R LDRV(off)LDRV pull down resistance V PVCC =5V,I LDRV =100mA0.30.75 1.5t HDRV(r)HDRV rise time (3)2575t HDRV(f)2575HDRV fall time (3)C LOAD =3.3nF nst LDRV(r)LDRV rise time (3)2575t LDRV(f)LDRV fall time (3)1060POWER GOODV FBPG_H Powergood high FB voltage threshold 764787798V FBPG_L Powergood low FB voltage threshold 591611626mV V FBPG(hyst)Powergood threshold hysteresis 3060T PGDLY Powergood delay time(3)10µs V PGL Powergood low level output voltage I PG =2mA 0.350.40V I PGLK Powergood leakage current V PG =5V1µAOVERVOLTAGE AND UNDERVOLTAGEV FB_U FB pin under voltage threshold 565580595mVV FB_O FB pin over voltage threshold 792810828THERMAL SHUTDOWNT TSD Shutdown Temperature (3)126135144T TSD(hyst)40Hysteresis (3)°CT WRN Warning Temperature (3)106115124T WR(hyst)Hysteresis (3)10(3)Specified by design.Not production tested .6Submit Documentation FeedbackCopyright ©2007,Texas Instruments IncorporatedProduct Folder Link(s):TPS40180TERMINAL INFORMATION TPS40180SLVS753B–FEBRUARY2007–REVISED NOVEMBER2007TERMINAL FUNCTIONSTERMINALI/O DESCRIPTIONNAME NO.FB1I Inverting input to the internal error amplifier.Normally this pin is at the reference voltage of700mV.Output of the remote sense amplifier.Amplifier is fixed gain of1differential mode and is used for output DIFFO2Ovoltage sensing at the load to eliminate distribution drops.Positive input to the remote sense amplifier.Amplifier is fixed gain of1differential mode and is used for VOUT3Ioutput voltage sensing at the load to eliminate distribution drops.Negative input to the remote sense amplifier.Amplifier is fixed gain of1differential mode and is used for GSNS4Ioutput voltage sensing at the load to eliminate distribution drops.Pin is either an input or an output.If the chip is configured as a voltage loop master the valley voltage isoutput on this pin and is distributed to the slave devices.If configured as a voltage loop slave,the master VSH5I/OVSH pin is connected here and the device uses the master valley voltage reference to improve currentsharing.Programs the overcurrent limit of the device.Connecting a resistor from this pin to VSH and another toVOUT on the voltage loop master sets a voltage above P is not allowed to exceed this voltage.If ILIM6I the load current requirements force COMP to this level for seven clock cycles,an overcurrent event isdeclared,and the system shuts down and enter a hiccup fault recovery mode.The controller attempts torestart after a time period given by seven soft-start cycles.Soft-start input.This pin determines the startup ramp time for the converter as well as overcurrent and otherfault recovery timing.The voltage at this pin is applied as a reference to the error amplifier.While thisvoltage is below the precision700mV reference,it acts as the dominant reference to the error ampproviding a closed loop startup.After it rises above the700mV precision reference,the700mV precisionSS7Ireference dominates and the output regulates at the programmed level.In case of an overcurrent event,theconverter attempts to restart after a period of time defined by seven soft-start cycles.Additionally this pin isused to configure the chip as a voltage loop master or slave.If the pin is tied to VDD or PVCC at power up,the device is in voltage loop slave mode.Otherwise,the device is a voltage loop master.Frequency programming pin.Connecting a resistor from this pin to GND sets the switching frequency of the RT8I device.If this pin is connected to VDD or PVCC,the device is a clock slave and gets its time base fromCLKIO of the clock master device.Phase addressing is done on PSEL.Signal level ground connection for the device.All low level signals at the device should be referenced to this GND9–pin.No power level current should be allowed to flow through the GND pin copper areas on the board.Connect to the thermal pad area,and from there to the PGND copper area.Electrically quiet5-V supply for the internal circuitry inside the device.If VDD is above5V,connect a20-ΩBP510I resistor from PVCC to this pin and a100-nF capacitor from this pin to GND.For VDD at5V,this pin can be tied directly to VDD or through a20-Ωresistor with a100-nF decoupling capacitor to reduce internal noise.UVLO input for the device.A resistor divider from VDD sets the turn on voltage for the device.Below this UVLO11I voltage,the device is in a low quiescent current state.Pulling this pin to ground shuts down the device,and is used as a system shutdown method.VDD12I Power input for the LDO on the device.Common connection for the power circuits on the device.This pin should be electrically close to the source PGND13–of the FET connected to LDRV.Connected to GND only at the thermal pad for best results.LDRV14O Gate drive output for the low-side or rectifier FET.Output of the on board LDO.This is the power input for the drivers and bootstrap circuit.The5.3-V output PVCC15O on this pin is used for external circuitry as long as the total current required to drive the gates of theswitching FETs and external loads is less than50mA.Connect a1µF capacitor from this pin to GND.This pin is connected to the source of the high-side or switch FET and is the return path for the floatingSW16Ohigh-side driver.Gate drive output for the high-side FET.High-side FET turn-on time must not be greater than minimum HDRV17Oon-time.See electrical characteristics table for the minimum on time of the pulse width modulator.Bootstrap pin for the high-side driver.A100-nF capacitor is connected from this pin to SW and provides BOOT18Ipower to the high-side driver when the high-side FET is turned on.Clock and phase timing output while the device is configured as a clock master.In clock slave mode,the CLKIO19I/Omaster CLKIO pin is connected to the slave CLKIO pin to provide time base information to the slave.Power good output.This open drain output pulls low when the device is in any state other than in normal PGOOD20O regulation.Active soft-start,UVLO,overcurrent,undervoltage,overvoltage or overtemperature warning(115°C junction)causes this output to pull low.Copyright©2007,Texas Instruments Incorporated Submit Documentation Feedback7Product Folder Link(s):TPS40180789101112TPS40180RGE PACKAGE (BOTTOM VIEW)242322212019123456181716151413COMP CS-CS+PSEL PGOOD CLKIOF BD I F F OV O U TG S N SV S HI L I MP V C CL D R VP G N DB O O TH D R VS WSS RT GND BP5UVLO VDDTPS40180TPS40180SLVS753B–FEBRUARY 2007–REVISED NOVEMBER 2007TERMINAL FUNCTIONS (continued)TERMINAL I/ODESCRIPTIONNAME NO.Phase select pin.For a clock master,a resistor from this pin to GND determines the CLKIO output.When configured as a clock slave,a resistor from the pin to GND selects the phase relationship that the slave has PSEL 21I with the master.Allowing this pin to float causes the slave to drop off line to shed the phase when current demands are light for improved overall efficiency.See the Application Information section for more details.CS+22I Positive input to the current sense amplifier.CS–23I Negative input to the current sense amplifier COMP24OOutput of the error amplifier.Figure 1.Device Pin Out8Submit Documentation FeedbackCopyright ©2007,Texas Instruments IncorporatedProduct Folder Link(s):TPS40180FB DIFFO GSNSVOVSH ILIMCOMP RT CLKIO PSEL CS+CS-BOOT HDRVSWLDRVPGNDVDDPVCCGNDBP5SSUVLO PGOODTPS40180SLVS753B–FEBRUARY 2007–REVISED NOVEMBER 2007Figure 2.Functional Block DiagramCopyright ©2007,Texas Instruments Incorporated Submit Documentation Feedback9Product Folder Link(s):TPS40180TYPICAL CHARACTERISTICS023461-50-30-1010309050701105T J -Junction Temperature -°CI V D D -I n p u t C u r r e n t -mA-0.8-0.40.20.40.60-0.6V I S O F S T -C u r r e n t S e n s e O f f s e t V o l t a g e -mV-0.2-50-30-101030905070110T J -Junction Temperature -°C-1.01.00.5-0.5G C S -C u r r e n t S e n s e G a i n -V /V %-50-30-101030905070110T J -Junction Temperature -°C21.521.020.523.524.023.022.022.5I I L I M -C u r r e n t L i m i t C u r r e n t -m A-50-30-101030905070110TJ -Junction Temperature -°C20.0TPS40180SLVS753B–FEBRUARY 2007–REVISED NOVEMBER 2007INPUT SHUTDOWN CURRENTCURRENT SENSE AMPLIFIER OFFSET VOLTAGEvsvsJUNCTION TEMPERATUREJUNCTION TEMPERATUREFigure 3.Figure 4.RELATIVE CURRENT SENSE GAINCURRENT LIMITvsvsJUNCTION TEMPERATUREJUNCTION TEMPERATUREFigure 5.Figure 6.10Submit Documentation FeedbackCopyright ©2007,Texas Instruments IncorporatedProduct Folder Link(s):TPS401801.7901.8051.8101.7951.800V V S H -C u r r e n t S h a r e R e f e r e n c e V o l t a g e -V-50-30-101030905070110T J -Junction Temperature -°C200220235245250225210215230240205V B P 5U V H -U V L O H y s t e r e s i s -m V-50-30-101030905070110T J -Junction Temperature -°CG R V S -R e m o t e V o l t a g e S e n s e A m p l i f i e r G a i n -V /V-50-30-101030905070110T J -Junction Temperature -°C-0.05-0.04-0.03-0.020.05-0.0100.010.020.040.0357111315917I S S x -S o f t -S t a r t C h a r g e C u r r e n t -m A-50-30-101030905070110T J -Junction Temperature -°CUVLO HYSTERESISCURRENT SHARE RE VOLTAGEvsvsJUNCTION TEMPERATUREJUNCTION TEMPERATUREFigure 7.Figure 8.SOFTSTART CHARGE CURRENTREMOTE VOLTAGE SENSE AMPLIFIERvsvsJUNCTION TEMPERATUREJUNCTION TEMPERATUREFigure 9.Figure 10.00.20.61.41.61.82.0R x D R V -D r i v e r R e s i s t a n c e -W0.40.81.21.0-50-30-101030905070110T J -Junction Temperature -°C500550650700750850900800600-50-30-101030905070110T J -Junction Temperature -°CV F B P G -P o w e r G o o d F B T h r e s h o l d V o l t a g e -V02010304050V F B P G (h y s t )-P ow e r G o o d F B H y s t e r e s i s -m V-50-30-101030905070110T J -Junction Temperature -°C0100300400500700200600-50-30-101030905070110T J -Junction Temperature -°CV P G L -P o w e r G o o d L o w T h r e s h o l d V o l t a g e -mVDRIVER RESISTANCEPOWER GOOD THRESHOLD VOLTAGEvsvsJUNCTION TEMPERATUREJUNCTION TEMPERATUREFigure 11.Figure 12.POWER GOOD LOW THRESHOLD VOLTAGEPOWER GOOD FB HYSTERESISvsvsJUNCTION TEMPERATUREJUNCTION TEMPERATUREFigure 13.Figure 14.820860900940920980V U V L O -U n d e r v o l t a g e L o c k o u t T h r e s h o l d -V-50-30-101030905070110T J -Junction Temperature -°C840880960550600700650750850900450400500800V V F B _x -F e e d b a c k V o l t a g e T h r e s h o l d s -m V-50-30-101030905070110T J -Junction Temperature -°C1.9851.9902.0102.0151.9952.0252.0002.0052.020V U V L O -U V L O P W M E n a b l e T h r e s h o l d -V-50-30-101030905070110T J -Junction Temperature -°C10.010.210.811.411.812.011.210.610.411.611.0I U V L O -H y s t e r e s i s C u r r e n t -m A-50-30-101030905070110T J -Junction Temperature -°CUNDERVOLTAGE AND OVERVOLTAGE THRESHOLDUVLO ENABLE THRESHOLDvsvsJUNCTION TEMPERATUREJUNCTION TEMPERATUREFigure 15.Figure 16.UVLO HYSTERESIS CURRENTUVLO PWM ENABLE THRESHOLD VOLTAGEvsvsJUNCTION TEMPERATUREJUNCTION TEMPERATUREFigure 17.Figure 18.V F B -R e l a t i v e F e e d b a c k V o l t a g e C h a n g e -%-50-30-101030905070110T J -Junction Temperature -°C00.050.150.250.300.10-0.10-0.15-0.20-0.050.2002010304050I I B -F e e d b a c k B i a s C u r r e n t -n A-50-30-101030905070110T J -Junction Temperature -°C155253545-2-110345-4-5-33f O S C -R e l a t i v e O s c i l l a t o r F r e q u e n c y -%-50-30-101030905070110T J -Junction Temperature -°CRELATIVE FEEDBACK REFERENCE VOLTAGE CHANGEFEEDBACK BIAS CURRENTvsvsJUNCTION TEMPERATUREJUNCTION TEMPERATUREFigure 19.Figure 20.RELATIVE OSCILLATOR FREQUENCYvsJUNCTION TEMPERATUREFigure 21.APPLICATION INFORMATIONIntroductionProgramming the Operating Frequency()f f 54RT 2SWSW 3.67510 2.82410R 5.355´´=+-(1)Programming the soft-start Time´=REFSSSS SS V C T I (2)The TPS40180is a versatile single-phase controller that can be used as a building block for a more complex power system,or as a stand alone power supply controller.In either system,the TPS40180provides an excellent power conversion solution and supports such features as pre-bias startup,intelligent fault handling capability with graceful shutdown and restart even with multiple modules sharing a common load.Remote load voltage sense for improved load regulation where it counts,at the load,thermal shutdown,remote enable and power good indication features help solve the problems faced by the power supply designer.To ease application to a specific task,there are several user programmable features including closed loop soft-start time,operating frequency and current limit level.More complex power solutions are readily supported by the TPS40180.The device can be configured to run in a master/slave configuration where a master can control several slaves.Several options are possible including a single output multiple phase supply sharing phase timing information to reduce input and output ripple,a multiple output supply that shares phase switching timing information to reduce input ripple currents and a combination approach that has multiple outputs sharing phase information where each output can use multiple phases.Phase information in all cases comes from a single device designated the clock master.Current sharing information is passed from the device designated voltage loop master for each output to the slaves for that particular output rail by connecting the COMP pin of the master to the COMP pin of the slaves.The clock master is also the voltage loop master in one of the rails of a multiple output supply;whereas,the other rails are controlled by a voltage loop master that is a clock slave to the single clock master device.A resistor is connected from the RT pin to GND to select the operating frequency of the converter.The relationship between the desired operating frequency and the timing resistance is given by Equation 1:where•R RT is the timing resistance in k Ω•f SW is the desired switching frequency in kHzIf this is a clock master,the switching frequency above is the per-phase switching frequency.The soft-start time is programmable by connecting a capacitor from the SS pin to GND.An internal current source charges this capacitor providing a linear ramp voltage.This ramp voltage is the effective reference to the error amplifier while it is less that the 700-mV internal reference.The time required for the SS pin to ramp from GND to 700mV is the soft-start time.For outputs that are not pre-biased,that time is given in Equation 2.where•t SS is the soft-start time in seconds•C SS is the capacitor from SS to GND in µF •I SS is the soft-start current in µA,15-µA typicalIf the output of the converter has a pre-existing voltage on it,the device the soft-start happens a little differently.The SS pin current is held to a lower value than normal until the PWM becomes active.This occurs as the SS pin voltage exceeds the FB pin voltage and the COMP pin moves up into the ramp range,causing the first pulse.At that point,the SS pin current is shifted to 15µA nominal.Figure 22and Figure 23illustrate this.VV o l t a g e -Vt -TimeV o l t a g e -VV OUTFigure 22.Soft-Start Waveform for Pre-Biased OutputsFigure 23.Soft-Start ImplementationUsing Figure 22provides:SS PREBIAS BAIS SS1BIAS C V R t1I R1R æö´=´ç÷+èø(3)SS PREBIAS BIASREF SS2BIAS C V R t2V I R1R æöæö´=´-ç÷ç÷ç÷+èøèø(4)=+SS T t1t2(5)TrackingUDG-07027where•t 1is the time to the first PWM pulse in seconds•t 2is the time from the first PWM pulse until regulation in seconds •C (SS)is the SS pin capacitor in µF•I (SS1)is the SS1pin charging current in µA,7.5µA •I (SS2)is the SS2pin charging current in µA,15µA •T SS is the total soft-start timeThe TPS40180can function in a tracking mode,where the output tracks some other voltage.To do this,a voltage divider is connected from the voltage to be tracked to GND,with the tap of the divider connected to the SS pin of the TPS40180.See Figure 24.The capacitors C1and C2are required for two purposes.First they provide a means for timing of restart attempts.Second,they provide for matching output voltage ramp up rate of the TPS40180to the controlling external supply.Figure 24.Tracking Setup。

基于LoRa的无线人体红外探测器设计

基于LoRa的无线人体红外探测器设计发表时间：2018-07-03T10:23:14.283Z 来源：《电力设备》2018年第7期作者：吕士如[导读] 摘要：针对传统人体红外探测器功耗大，结构复杂，无法进行远距离传输等缺点，本文提出一种基于LoRa的无线人体红外探测器的方案。

（蚌埠依爱消防电子有限责任公司安徽蚌埠 233010）摘要：针对传统人体红外探测器功耗大，结构复杂，无法进行远距离传输等缺点，本文提出一种基于LoRa的无线人体红外探测器的方案。

分析了目前人体红外探测器的国内外现状，介绍了基于LoRa 的人体红外探测器的系统构成以及工作原理，详细介绍了硬件电路、工作原理以及软件流程。

关键词：LoRa；人体红外；无线监控；报警器一、引言LoRa作为低功耗广域网（LPWAN）的一种长距离通信技术，近些年备受关注。

随着物联网距离由近及远的发展，势必对传统行业应用和商务模式带来新的变革[1]。

LoRa是低功耗广域网通信技术中的一种，是物理层或无线调制用于建立长距离通信链路。

许多传统的无线系统使用频移键控（FSK）调制作为物理层，因为它是一种实现低功耗的非常有效的基于线性调频扩频调制，它保持了像FSK调制相同的低功耗特性，但明显地增加了通信距离[2]。

二、探测原理在室温条件下，任何物品均有辐射。

温度越高的物体，红外辐射越强。

人体都有恒定的体温，一般在37度，红外辐射也最为稳定，会发出波长10μm左右的红外线。

探测器就是靠10μm的红外线来工作的。

探测器主要由光学系统、热传感器（或称为红外传感器）及报警控制器等部分组成。

热释电红外传感器(pir) 和菲涅尔透镜是红外探测器的两个关键性的元件。

传感器它能将波长为8—12um之间的红外信号变化转变为电信号，并且对自然界中的白光信号具有抑制作用，因此在红外探测器的警戒区内，当无人体移动时，热释电红外感应器感应到的只是背景温度，当人体进人警戒区，通过菲涅尔透镜，热释电红外感应器感应到的是人体温度与背景温度的差异信号，因此，红外探测器的基本原理就是感应移动物体与背景物体的温度的差异。

可控硅参数说明及中英文对照表

mA
ID
Off-state leakage current
断态漏电流
-
mA
VGT
Triggering gate voltage
门极触发电压
—可以选择Vgt 25度时max值的β倍;β为门极触发电压—结温特性系数,查数据手册可得,取特性曲线中最低工作温度时的系数;若对器件工作环境温度无特殊需要,通常选择时β取1~1.2倍即可;
A
VTM
Peak on-state voltage drop
通态峰值电压
指器件通过规定正向峰值电流IFM整流管或通态峰值电流ITM晶闸管时的峰值电压也称峰值压降该参数直接反映了器件的通态损耗特性影响着器件的通态电流额定能力;
V
IDRM
Maximum forward or reverse leakage current
通态流上升率
当双向可控硅或闸流管在门极电流触发下导通,门极临近处立即导通,然后迅速扩展至整个有效面积;这迟后的时间有一个极限,即负载电流上升率的许可值;过高的dIT/dt可能导致局部烧毁,并使T1-T2 短路;假如过程中限制dIT/dt到一较低的值,双向可控硅可能可以幸存;因此,假如双向可控硅的VDRM在严重的、异常的电源瞬间过程中有可能被超出或导通时的dIT/dt有可能被超出,可在负载上串联一个几μH的不饱和空心电感;
℃
Tstg
Storage Temperature Range
贮存温度
-
℃
TL
Max.Lead Temperature for Soldering Purposes
引脚承受焊锡极限温度
-
℃
Rthj-mb
Thermal Resistance Junction tomounting base