第五章IP复用

Package of Soft IP - cont.
Verification Files
Bus functional models/monitors used in testbench (optional) Testbench files, including representative verification tests
Main Barriers


Types of IP: Design View
Soft IP
Synthesizable RTL source codes Verilog, VHDL High flexibility, low predictability Netlist, ready for place & route Technology dependent Medium flexibility, medium predictability
Package of Hard IP - cont.
System Integration Files - models
Full functional model Timing model Test model Power model Physical model
Check the Quality of IP
Types of IP: Design View – cont.
IP规范书
结构设计
文档
电路设计
验证工具
SoftIP 综合 FirmIP
布线布局
HardIP MPW IC产品 验证板
测试
硅片验证
IP发布
Outline
IP market Problems of IP reuse Types of IP IP package IP design and modeling Summary
Package of Soft IP
• Product files • Verification Files • Documentation Files • System Integration Files
Package of Soft IP
Product files
Synthesizable Verilog/VHDL codes for the IP and its sub-blocks Application notes, including Verilog/VHDL design examples that instantiate the IP Synthesis scripts and timing constraints Scripts for scan insertion and ATPG Reference Library Installation script
Package of Hard IP
• Product files • Verification Files • Test patterns for manufacturing test • Documentation Files • System Integration Files
Package of Hard IP
Firm IP:
Hard IP
Layout, GDSII, fixed technology Low flexibility, high predictability
When and Why Use Hard IP
The design is pushing performance to the limit of the silicon process The design requires some full custom design The value of the hard IP is so great that the hard IP provider does not want the chip designers to have access to the RTL The hard IP provider wishes to prevent the possibility of the user modifying the macro Analog IP
《SoC设计方法与实现》
郭炜 郭筝 谢憬
第五章
IP复用的设计方法
Outline
IP market Problems of IP reuse Types of IP IP package IP design and modeling Summary
What is IP
• Silicon Intellectual Property (SIP or IP) • “ By IP “ should be understood as
Silicon IP as well as software IP such as embedded software

In this chapter, we will discussing Silicon IP only.
Reasons for using IP
• Reducing risk • Reducing silicon cost • Reducing design time



Higher entrance barrier Less competitor Higher invest yield
Key Success Factors

Predominant Market Technical Capability Software and System Support Technical Patent Software/Platform Support Application/System Cooperators
Outline
IP market Problems of IP reuse Types of IP IP package IP design and modeling Summary
Types of IP: Application View
Star IP
Star IP
IP Exchange Organization – D & R
Design and Reuse (D & R)
A global collaboration network for sharing design resources in the SoC industry Categorized IP database sharing Silicon IP/Verification IP/Software IP IP management software IP/SoC industry updates
Major Problem with IP Reuse
• Integration • Quality • Verification
IP Exchange Organization – VSIA
Virtual Socket Interface Alliance (VSIA)
Hardware Dependent Software Development Working Group Implementation Development Working Group IP Protection Development Working Group Manufacturing Related Test Development Working Group On-Chip Buses Development Working Group Platform Based Design Development Working Group Virtual Component Quality Development Working Group Virtual Component Transfer Development Working Group Functional Verification Development Working Group
• VSIA Alliance provide Quality IP Metric
spreadsheets:

Vendor Assessment Soft IP Integration Soft IP Development Software IP Analog IP Library IP Hard IP
Documentation Files
User guide/functional specification Datasheet
Package of Soft IP -cont.
System Integration Files
Bus functional models of other system components Cycle-based/emulation models as appropriate to the particular IP and/or its testbenches and BFMs Recommendation of commercially available software required for hardware/software cosimulation and system integration, as appropriate for particular IP
Compatibility

IP Protection

Design reuse cost ቤተ መጻሕፍቲ ባይዱinimization