外文翻译-关于直接数字频率合成器

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直接数字频率合成器原理

直接数字频率合成器原理直接数字频率合成器（Direct Digital Frequency Synthesizer，简称DDFS）是一种用于产生高精度、稳定的频率信号的电子设备。

它通过数字电路实现频率的直接合成，可以产生任意频率的信号，并且具有快速调谐、高精度以及低相位噪声等优点。

本文将介绍DDFS的工作原理及其在实际应用中的重要性。

一、工作原理DDFS的核心组成部分是相位累加器（Phase Accumulator）、频率控制字（Frequency Control Word）和查表器（Look-up Table）。

相位累加器通过不断累加频率控制字的值，从而产生一个随时间线性增加的相位值。

查表器中存储了正弦波的采样值，通过查表器可以根据相位值得到对应的正弦波样本。

最后，通过数模转换器将数字信号转换为模拟信号输出。

具体来说，DDFS的工作原理如下：1. 频率控制字：频率控制字是一个二进制数，用于控制相位累加器的累加速度。

频率控制字的大小决定了相位累加器每个时钟周期累加的值，从而决定了输出信号的频率。

2. 相位累加器：相位累加器是一个寄存器，用于存储当前的相位值。

相位累加器的值会在每个时钟周期根据频率控制字的大小进行累加。

相位累加器的位数决定了相位的分辨率，位数越多，相位分辨率越高，输出信号的频率分辨率也越高。

3. 查表器：查表器中存储了一个周期内的正弦波样本值（或余弦波样本值），通过查表器可以根据相位累加器的值得到对应的正弦波样本值。

4. 数模转换器：数模转换器将数字信号转换为模拟信号输出。

通常使用的是高速数模转换器，能够将数字信号以高速率转换为模拟信号输出。

二、应用领域DDFS在许多领域中都有广泛的应用，其中包括通信、雷达、测量、音频处理等。

1. 通信领域：在通信系统中，DDFS被广泛应用于频率合成器、频率调制器和频率解调器等模块中。

通过DDFS可以快速、精确地合成所需的信号频率，实现高速数据传输和频谱分析等功能。

毕业设计(论文)-直接数字频率合成器设计[管理资料]

直接数字频率合成器设计The Design of Direct Digital Frequency Synthesizer摘要利用可编程逻辑阵列FPGA（Field Programmable Gate Array）实现DDS专用电路芯片，主要特点是能满足用户对特殊功能的要求，而且在使用过程中也灵活地改变系统结构。

，并不能满足所有的要求。

本文在对现有DDS技术的大量文献调研的基础上，提出了符合FPGA结构的DDS设计。

方案利用QuartusⅡ开发工具在ALTERA FLEX10K系列器件上进行了实现。

关键词直接数字频率合成器单片机数模转换温度漂移补偿AbstractThe main features of realization of dedicated direct digital frequency synthesizer circuit chips using FPGA are the ability to meet user requirements for special functions, but also flexibility change structural of the system in the use of the process. Although commercial DDS dedicated chip circuit provide a lot of opportunities for the designers and meet the needs of many occasions, there are its limitations and cannot meet all the requirements. On a large number of investigation of existing research literature，the papers involves the proposed structure of the direct digital frequency synthesizer FPGA design. The Programmer uses the Quartus II development tool for designing the Altera FLEX10K series devices.Keywords DDS MCU DAC Temperature drift compensation目录前言 (1)第1章设计思路及原理 (2)研究意义 (2)总体设计任务 (2)设计思路及原理 (3)DDS工作原理框图 (3)具体工作过程 (3)第2章系统电路的设计及原理 (5)系统框图 (5)各模块具体实现原理分析和说明 (5)相位累加器模块 (5)ROM查找表模块 (10)单片机输入输出控制模块 (12)温漂误差补偿 (13)D/A转换模块 (18)滤波输出电路模块 (19)软件仿真结果 (19)第3章硬件电路的构建 (21)FPGA芯片的选择与使用 (21)硬件连接电路图 (23)第4章实验开发系统系统 (25)实验开发系统的选择与使用 (25)实验过程与结果分析 (27)总结....................................................................................... 错误!未定义书签。

外文翻译数字频率合成器

附录2：外文原文，译文Modulating Direct Digital Synthesizer In the pursuit of more complex phase continuous modulation techniques, the control of the output waveform becomes increasingly more difficult with analog circuitry. In these designs, using a non-linear digital design eliminates the need for circuit board adjustments over yield and temperature. A digital design that meets these goals is a Direct Digital Synthesizer DDS. A DDS system simply takes a constant reference clock input and divides it down a to a specified output frequency digitally quantized or sampled at the reference clock frequency. This form of frequency control makes DDS systems ideal for systems that require precise frequency sweeps such as radar chirps or fast frequency hoppers. With control of the frequency output derived from the digital input word, DDS systems can be used as a PLL allowing precise frequency changes phase continuously. As will be shown, DDS systems can also be designed to control the phase of the output carrier using a digital phase word input. With digital control over the carrier phase, a high spectral density phase modulated carrier can easily be generated.This article is intended to give the reader a basic understanding of a DDS design, and an understanding of the spurious output response. This article will also present a sample design running at 45MHz in a high speed field programmable gate array from QuickLogic.A basic DDS system consists of a numerically controlled oscillator (NCO) used to generate the output carrier wave, and a digital to analog converter (DAC) used to take the digital sinusoidal word from the NCO and generate a sampled analog carrier. Since the DAC output is sampled at the reference clock frequency, a wave form smoothing low pass filter is typically used to eliminate alias components. Figure 1 is a basic block diagram of a typical DDS system generation of the output carrier from the reference sample clock input is performed by the NCO. The basic components of the NCO are a phase accumulator and a sinusoidal ROM lookup table. An optional phase modulator can also be include in the NCO design. This phase modulator will add phase offset to the output of the phase accumulator just before the ROM lookup table. This will enhance the DDS system design by adding the capabilities to phase modulate the carrier output of the NCO. Figure 2 is a detailed block diagram of a typical NCO design showing the optional phase modulator.FIGURE 1: Typical DDS System.FIGURE 2: Typical NCO Design.To better understand the functions of the NCO design, first consider the basic NCO design which includes only a phase accumulator and a sinusoidal ROM lookup table. The function of these two blocks of the NCO design are best understood when compared to the graphical representation of Euler’s formula ej wt = cos( wt) + jsin( wt). T hegraphical representation of Euler’s formula, as shown in Figure 3, is a unit vector rotating around the center axis of the real and imaginary plane at a velocity of wrad/s. Plotting the imaginary component versus time projects a sine wave while plotting the real component versus time projects a cosine wave. The phase accumulator of the NCO is analogous, or could be considered, the generator of the angular velocity component wrad/s. The phase accumulator is loaded, synchronous to the reference sample clock, with an N bit frequency word.This frequency word is continuously accumulated with the last sampled phase value by an N bit adder. The output of the adder is sampled at the reference sample clock by an N bit register. When the accumulator reaches the N bit maximum value, the accumulator rolls over and continues. Plotting the sampled accumulator values versus time produces a saw tooth wave form as shown below in Figure 3. FIGURE 3 Euler’s Equation Represented GraphicallyThe sampled output of the phase accumulator is then used to address a ROM lookup table of sinusoidal magnitude values. This conversion of the sampled phase to a sinusoidal magnitude is analogous to the projection of the real or imaginary component in time. Since the number of bits used by the phase accumulator determines the granularity of the frequency adjustment steps, a typical phase accumulator size is 24 to 32 bits. Since the size of the sinusoidal ROMtable is directly proportional to the addressing range, not all 24 or 32 bits of the phase accumulator are used to address the ROM sinusoidal table. Only the upper Y bits of the phase accumulator are used to address the sinusoidal ROM table, where Y < N bits and Y is typically but not necessarily equal to D, and D is the number of output magnitude bits from the sinusoidal ROM table.Since an NCO outputs a carrier based on a digital representation of the phase and magnitude of the sinusoidal wave form, designers have complete control over frequency, phase, and even amplitude of the output carrier. By adding a phase port and a phase adder to the basic NCO design, the output carrier of the NCO can be M array phase modulated where M equals the number of phase port bits and where M is less than or equal to the Y number of bits used to address the sinusoidal ROM table. For system designs that require amplitude modulation such as QAM, a magnitude port can be added to adjust the sinusoidal ROM table output. Note that this port is not shown in Figure 2 and that this feature is not demonstrated in the sample QuickLogic FPGA design. Finally, frequency modulation is a given with the basic NCO design. The frequency port can directly adjust the carrier output frequency. Since frequency words are loaded into the DDS synchronous to the sample clock, frequency changes are phase continuous.Although DDS systems give the designer complete control ofcomplex modulation synthesis, the representation of sinusoidal phase and magnitude in a non-linear digital format introduces new design complexities. In sampling any continuous-time signal, one must consider the sampling theory and quantization error.To understand the effects of the sampling theory on a DDS system, it is best to look at the DDS synthesis processes in both the time and frequency domain. As stated above, the NCO generates a sinusoidal wave form by accumulating the phase at a specified rate and then uses the phase value to address a ROM table of sinusoidal amplitude values. Thus, the NCO is essentially taking a sinusoidal wave form and sampling it with the rising or falling edge of the NCO input reference sampling clock. Figure 4 shows the time and frequency domain of the NCO processing. Note that this representation does not assume quantization.Based on the loaded frequency word, the NCO produces a set of amplitude output values at a set period. The frequency domain representation of this sinusoid is an impulse function at the specified frequency. The NCO, however, outputs discrete digital samples of this sinusoid at the NCO reference clock rate. In the time domain, the NCO output is a function of the sampling clock edge strobes multiplied by the sinusoid wave form producing a train of impulses at the sinusoid amplitude. In the frequency domain, the sampling strobes of the reference clock produce a train of impulses at frequencies of K times theNCO clock frequency where K = ... - 1, 0, 1, 2 .... Since the sampling clock was multiplied by the sinusoid in the time domain, the frequency domain components of the sinusoid and the sampling clock need to be convolved to produce the frequency domain representation of the NCO output.The frequency domain results are the impulse function at the fundamental frequency of the sinusoid and the alias impulse functions occurring at K times the NCO clock frequency plus or minus the fundamental frequency. The fundamental and alias component occur at: K*Fclk - FoutK*Fclk + FoutWhere K = ... -1, 0 , 1, 2 ..... and K = 0 is the NCO sinusoid fundamental frequencyFout is the specified NCO sinusoid output frequencyFclk is the NCO reference clock frequencyFIGURE 4 NCO Output Representation Time and Frequency Domain The DAC of the DDS system takes the NCO output values and translates these values into analog voltages. Figure 4 shows the time and frequency domain representations of the DAC processing starting with the NCO output. The DAC output is a sample and hold circuit that takes the NCO digital amplitude words and converts the value into an analog voltage and holds the value for one sample clock period. The timedomain plot of the DAC processing is the convolution of the NCO sampled output values with a pulse of one sample clock period. The frequency domain plot of the sampling pulse is a sin(x)/x function with the first null at the sample clock frequency. Since the time domain was convolved, the frequency domain is multiplied. This multiplication dampens the NCO output with the sin(x)/x envelope. This attenuation at the DAC output can be calculated as follows and a sample output spectrum is shown in Figure 5:Atten(F) = 20log[(sin(pF/Fclk)/pF/Fclk)] Where F is the output frequency Fclk is the sample clock frequencyFIGURE 5: DAC Output Representation in Time and Frequency Domain Aside from the sampling theory, the quantization of the real values into digital form must also be considered in the performance analysis of a DDS system. The spurious response of a DDS system is primarily dictated by two quantization parameters. These parameters are the phase quantization by the phase accumulator and the magnitude quantization by the ROM sinusoidal table and the DAC.As mentioned above, only the upper Y bits of the phase accumulator are used to address the ROM lookup table. It should be noted, however, that using only the upper Y bits of the phase accumulator introduces a phase truncation. When a frequency word containing a non-zero value in the lower (N-Y-1:0) bits is loaded into the DDS system, the lowernon-zero bits will accumulate to the upper Y bits and cause a phase truncation. The frequency at which the phase truncation occurs can be calculated by the following:Ftrunc = FW(N-Y- 1:0)/2N-Y* Fclk.A phase truncation will periodically (at the Ftrunc rate) phase modulate the output carrier forward 2p/28 to compensate for frequency word granularity greater than 2Y. The phase jump caused by the accumulation of phase truncated bits produces spurs around the fundamental.These spurs are located plus and minus the truncation frequency from the fundamental frequency and the magnitude of the spurs will be - 20log(2Y)dBc. A sample output of a phase truncation spur is shown in Figure 5.In a typical NCO design, the ROM sinusoidal table will hold a ¼ sine wave (0 , p/2) of magnitude values. The ROM table is generated by taking all possible phase value addresses and map to a real magnitude sine value rounded to the nearest D bits. Thus, the maximum error output is ±- ½ LSB giving a worst case spur of -20log(2D)dBc.Like the NCO ROM table, a DAC quantizes the digital magnitude values. A DAC, however, outputs an analog voltage corresponding to the digital input value. When designing the NCO sinusoidal ROM table, one should take some empirical data on the DAC linearity to betterunderstand the interaction between the ROM table and the DAC. The quantization for a DAC is specified against an ideal linear plot of digital input versus analog output. Two linearity parameters, differential and integral linearity, are used to specify a DAC’s p erformance.Differential linearity is the output step size from bit to bit. A DAC must guarantee a differential linearity of a maximum 1 LSB. When an input code is increased, the DAC output must increase. If the DAC voltage does not increase versus an increase digital input value, the DAC is said to be missing codes. Thus, a 10 bit DAC that has a differential linearity of greater that 1 LSB is only accurate to 9 or less bits. The number of accurate output bits will specify the DDS spurious performance as -20log(2dl) where dl is the number differential linear bits..Integral linearity is a measure of the DAC’s overall linear performance versus an ideal linear straight line. The straight line plot can be either a “best straight line” where DC offsets are pos sible at both the min and max outputs of the DAC, or the straight line can cross the end points of the min and max output values. A DAC will tend to have a characteristic curve that is traversed over the output range. Depending on the shape and symmetry (symmetry about the half way point of the DAC output) of this curve, output harmonics of the DDS fundamental output frequency will be produced. As these harmonics approach andcross the Nyquist frequency of Fclk/2, the harmonics become under sampled and reflect back into the band of interest, 0 to Fclk/2. This problem is best illustrated by setting the NCO output to Fclk/4 plus a slight offset. The third harmonic will fall minus 3 folds the small offset from the fundamental and the second harmonic will cross the Nyquist frequency by 2 folds the small offset leaving a reflected image back in the band of interest A sample plot of this frequency setup is shown in Figure 5.Other DAC characteristic that will produce harmonic distortion is any disruption of the symmetry of the output wave form such as a different rise and fall time. These characteristics can typically be corrected by board components external to the DAC such as an RF transformer, board layout issues, attenuation pads etc.Given the complexities of the DDS system, engineers should consider implementing the design using separate devices for the numerically controlled oscillator, the digital to analog converter, and the low pass filter. This approach allows for signal observation at many points in the system, yet is compact enough to be practical as an end-solution. Alternatively, the discrete implementation can serve as a prototyping vehicle for a single-chip mixed signal ASIC.The author developed a version of the design using a Harris HI5721 evaluation board for the DAC. The NCO at the heart of the DDS design,and a random generator to test signal modulation, was implemented into about 65% of a QuickLogic field programmable gate array (FPGA). This FPGA, a QL16x24B 4000-gate device, was chosen for its high performance, ease-of-use, and powerful development tools.The NCO design included following:Developed in Verilog with the 8 bit CLA adder schematiccaptured and net listed to Verilog32 bit frequency word input32 phase accumulator pipelined over 8 bits8 bit phase moudulation word input8 bit sine ROM look-up tableThe design was described mostly in Verilog, with an 8 bit carry look ahead adder modified from QuickLogic’s macro library netlisted to Verilog. The whole design cycle was less than four days (two days to describe the design and a day and a half to prototype the hardware). Everything worked perfectly the first time, with the design running at an impressive 45MHz as predicted by the software simulation tools.Plots used in the article to illustrate DDS performance parameters were provided from the test configuration.Figure 6 below shows the external IO interface to the NCO design .The function of each signal is described in the following table.Signal Function TableFigure 6: The External IO InterfaceTop LevelThe top level of the NCO design instantiates the functional blocks of the NCO design and the PN generator block.PN GeneratorThis module is not part of the NCO design but is used to produce a sample random data pattern to modulate the carrier output. This module uses the PNCLK input to clock two Gold code 5 bit PN generators. The outputs of the PN generators are IDATA and QDATA outputs.The lower level block of this NCO design consist of a synchronous frequency word input register, a synchronous phase word input register, a 32 bit pipe lined phase accumulator, an 8 bit phase adder, and a sin lockup table. A detailed description of each of the NCO blocks and thePN generator are provided in the following sections.Load Frequency WordThe load frequency word block is a synchronizing loading circuit. The FREQWORD[31:0] input drives a the data input to the 32 bit fwreg register that is sampled on the rising edge of the FWWRN write strobe. The FWWRN strobe also drives the data input to a metastable flip flop fwwrnm that is used in conjunction with a synchronous register fwwrns to produce a FWWRN rising edge strobe. This rising edge strobe loadp1 is then piped for an additional 3 clock cycles producing the load strobes loadp2, loadp3, and loadp4. The load strobes are used to signal when to update the synchronous pipe line 8 bit registers pipefw1, pipefw2, pipefw3, and pipefw4 to the sampled frequency word content. The pipe line registers are concatenated to produce the 32 bit synchronous frequency word output SYNCFREQ[31:0] that is staggered to compensate for the 32 bit pipe lined phase adder.Phase Word AccumulatorThe phase accumulator block is a 32 bit accumulator that is pipe lined in 8 bit sections. This module instanciates a schematic captured carry lock ahead CLA adder that has a carry in and carry out port. The synchronous frequency word, staggered to match the pipe lined accumulator, is loaded into the B input of the CLA adders. The sum output of the CLA adders are registered in the pipe registered with theoutput tied back to the A input of the CLA adders. The carry output of the CLA adders is registered in the pipec registers with the output tied to the next most significant CLA adder carry input. The most significant sum output register pipe4 is assigned to the PHASE output port giving a phase value quantized to 8 bits. A digital sine and cosine value is also calculated from the pipe4 register and brought out of the chip as SIN and COS.Load Phase WordThe load phase word block is a synchronizing loading circuit. The PHASEWORD[7:0] input drives the data input to the 32 bit pwreg register that is sampled on the rising edge of the PWWRN write strobe. The PWWRN strobe also drives the data input to a metastable flip flop pwwrnm that is used in conjunction with a synchronous register pwwrns to produce a FWWRN rising edge strobe. This rising edge strobe load is used to signal when to update the synchronous phase word register phswd. The phswd register is assigned to the synchronous phase word output SYNCPHSWD[7:0].Phase ModulatorThe phase modulator block is used to phase offset the phase accumulator 8 bit quantized output with the synchronous phase word from the load phase word block. This module instantiates a CLA adder with the A input tied to the synchronous phase output and the B inputtied to the phase accumulator output. The sum output of the adder is registered in the mphsreg register and assigned to the MODPHASE output port. A modulated version of the sine and cosine values are calculated and brought out of the chip as MSIN and MCOS.Sine LockupThis module takes the modulated phase value form the phase modulator block and translated the quantized 8 bit value into a sine wave form amplitude value quantized to 8 bits. The translation from phase to amplitude is performed by a sine ROM table that in instantiated in this module. The ROM table is reduced to a ¼ of the symmetrical sine wave form and the MSB of the sine wave form is equivalent to the modulated phase module performs the calculations to reconstruct a complete period of the sine wave form f rom the ¼ representation of the ROM table and the MSB of the modulated phase input. To better understand the processing of this module, consider the following. The modulated phase value is a 0 to 2p value quantized to 8 bits 2p/28. The quantized value for p/2, p, 3p/2, and 2p are 0x3F, 0x7F, 0xBF, and 0xFF. The amplitude values for 0 to p/2 is stored in the ROM table. The amplitude values for p/2 to p are the ROM table output in the reverse order. The amplitude values for p to 3p/2 are the same output as the amplitude value from 0 to p/2 with the output from the ROM table inverted. Finally the amplitude value for 3p/2 to 2p are the same as for pto 3p/2 with the ROM table accessed in reverse.This module manages the address values to the ROM table and the amplitude outputs to form the complete period of the sine wave form. The first process of generating the sine wave function is the addressing of the ROM table such that phase angles p/2 to p and 3p/2 to 2p are addressed in the reverse order. Reverse addressing is accomplished by simply inverting the ROM table address input vector. The phase modulated address input is inverted when the MODPHASE[6] is one and is then registered in the phaseadd register. The phase address is used to address the ROM sine table with the output registered in the qwavesin_ff register. To construct the negative amplitude values of the sine wave form, the MSB of the modulate phase word input is registered twice in modphase_msb1_ff and modphase_msb2_ff, compensating for the two cycle latency of the phaseadd and qwavesin_ff registers. The delayed MSB bit is used to invert the ROM table output when one. The altered ROM table output and the invert of the delayed modulated phase word MSB are finally registered in by the dac_ff register and then assigned to the DACOUT output port.Sine ROM TableThis module is the sine wave form ROM table. This table converts the phase word input to a sine amplitude output. To conserve area, only ¼ of the symmetrical sine wave form is stored in the ROM. The sine valuesstored in this table are the 0 to p/2 unsigned values quantized to 8 bits. Thus, the ROM table requires a 6 bit phase address input and outputs a 7 bit amplitude output. The sinlup module processes the phase and amplitude values to produce a complete sine period.Dan Morelli has over 9 years of design and management experience. His areas of expertise include spread spectrum communications (involving GPS, TDRSS, and , PC chip set and system architecture, cell library development (for ECL devices) and ASIC development. He has been published and has multiple patents awarded and pending. Dan currently works for Accelent Systems Inc., an electronic design consulting company, where he is a founder and the VP of Engineering.数字频率合成器在探讨许多复杂的相位持续的调制技术中，对模拟电路中输出波形的操纵已经愈来愈困难。

基于DDS的信号发生器的设计的相关英文文献

基于DDS的信号发生器的设计的相关英文文献及翻译Direct Digital Synthesizer (DDS) is a type of frequency synthesizer used for creating arbitrary waveforms from a single, fixed-frequency reference clock. Applications of DDS include: signal generation, local oscillators in communication systems, function generators, mixers, modulators,sound synthesizers and as part of a digital phase-locked loop.直接数字频率合成（DDS）是一种用于产生任意波形从一个单一的，固定频率的参考时钟的频率合成器。

DDS的应用领域包括：信号的产生，在通信系统中，函数发生器，混频器，调制器，声音合成器和本地振荡器作为一个锁相环数字环路的一部分。

Figure 1 - Direct Digital Synthesizer block diagram图1 - 直接数字频率合成器框图A basic Direct Digital Synthesizer consists of a frequency reference (often a crystal or SAW oscillator), a numerically controlled oscillator (NCO) and a digital-to-analog converter (DAC) as shown in Figure 1.The reference provides a stable time base for the system and determines the frequency accuracy of the DDS. It provides the clock to the NCO which produces at its output a discrete-time, quantized version of the desired output waveform (often a sinusoid) whose period is controlled by the digital word contained in the Frequency Control Register. The sampled, digital waveform is converted to an analog waveform by the DAC. The output reconstruction filter rejects the spectral replicas produced by the zero-order hold inherent in the analog conversion process.A DDS has many advantages over its analog counterpart, the phase-locked loop (PLL), including much better frequency agility, improved phase noise, and precise control of the output phase across frequency switching transitions. Disadvantages include spurious due mainly to truncation effects in the NCO, crossing spurious resulting from high order (>1) Nyquist （尼奎斯特定理） images, and a higher noise floor at large frequency offsets due mainly to the Digital-to-analog converter.Because a DDS is a sampled system, in addition to the desired waveform at output frequency Fout, Nyquist images are also generated (the primaryimage is at Fclk -Fout, where Fclkis the reference clock frequency). In orderto reject these undesired images, a DDS is generally used in conjunction with an analog reconstruction lowpass filter as shown in Figure 1.The output frequency of a DDS is determined by the value stored in the frequency control register (FCR) (see Fig.1), which in turn controls the NCO's phase accumulator step size. Because the NCO operates in the discrete-time domain, it changes frequency instantaneously at the clock edge coincident with a change in the value stored in the FCR. The DDS output frequency settling time is determined mainly by the phase response of the reconstruction filter. An ideal reconstruction filter with a linear phase response (meaning the output is simply a delayed version of the input signal) would allow instantaneous frequency response at its output because a linear system can not create frequencies not present at its input.The superior close-in phase noise performance of a DDS stems from the fact that it is a feed-forward system. In a traditional phase locked loop (PLL), the frequency divider in the feedback path acts to multiply the phase noise of the reference oscillator and, within the PLL loop bandwidth, impresses this excess noise onto the VCO output. A DDS on the other hand, reduces the reference clock phase noise by the ratio f clk/f out，because its output is derived by fractional division of the clock. Reference clock jitter translates directly to the output, but this jitter is a smaller percentage of the output period (by the ratio above). Since the maximum output frequency is limited to f clk/2, the output phase noise at close-in offsets is always at least 6dB below the reference clock phase-noise.At offsets far removed from the carrier, the phase-noise floor of a DDS is determined by the power sum of the DAC quantization noise floor and the reference clock phase noise floor.一个DDS以上的锁相回路（PLL），其模拟对应，许多优势，包括更好的频率灵活性，提高了相位噪声，整个频率转换开关的输出相位的精确控制。

外文翻译-关于直接数字频率合成器

All About Direct Digital SynthesisBy Eva Murphy [eva.murphy@]Colm Slattery [colm.slattery@]What is Direct Digital Synthesis?Direct digital synthesis (DDS) is a method of producing an analog waveform—usually a sine wave—by generating a time-varying signal in digital form and then performing a digital-to-analog conversion. Because operations within a DDS device are primarily digital, it can offer fast switching between output frequencies, fine frequency resolution, and operation over a broad spectrum of frequencies. With advances in design and process technology, today’s DDS devices are very compact and draw little power.Why would one use a direct digital synthesizer (DDS)? Aren’t there other methods for easily generating frequencies?The ability to accurately produce and control waveforms of various frequencies and profiles has become a key requirement common to a number of industries. Whether providing agile sources of low-phase-noise variable-frequencies with good spurious performance for communications, or simply generating a frequency stimulus in industrial or biomedical test equipment applications, convenience, compactness, and low cost are important design considerations.Many possibilities for frequency generation are open to a designer, ranging from phase-locked-loop (PLL)-based techniques for very high-frequency synthesis, to dynamic programming of digital-to-analog converter (DAC) outputs to generate arbitrary waveforms at lower frequencies. But the DDS technique is rapidly gaining acceptance for solving frequency- (or waveform) generation requirements in both communications and industrial applications because single-chip IC devices can- 1 -generate programmable analog output waveforms simply and with high resolution and accuracy.Furthermore, the continual improvements in both process technolog y and design have resulted in cost and power consumption levels that were previously unthinkably low. For example, the AD9833, a DDS-based programmable waveform generator (Figure 1), operating at 5.5 V with a 25-MHz clock, consumes a maximum power of 30 milliwatts.Figure 1. The AD9833-a one-chip waveform generator.What are the main benefits of using a DDS?DDS devices like the AD9833 are programmed through a high speed serial peripheral-interface (SPI), and need only an external clock to generate simple sine waves. DDS devices are now available that can generate frequencies from less than 1 Hz up to 400 MHz (based on a 1-GHz clock). The benefits of their low power, low cost, and single small package, combined with their inherent excellent performance and the ability to digitally program (and re-program) the output waveform, make DDS devices an extremely attractive solution—preferable to less-flexible solutions comprising aggregations of discrete elements.What kind of outputs can I generate with a typical DDS device?- 2 -- 3 -DDS devices are not limited to purelysinusoidal outputs. Figure 2 shows thesquare-, triangular-, and sinusoidal outputsavailable from an AD9833.How does a DDS device create a sinewave?Here’s a breakdown of the internalcircuitry of a DDS device: its maincomponents are a phase accumulator, ameans of phase-to-amplitude conversion(often a sine look-up table), and a DAC.These blocks are represented in Figure 3.A DDS produces a sine wave at a givenfrequency. The frequency depends on two variables, the reference-clock frequency and the binar y number programmed into the frequency register (tuning word).The binary number in thefrequency register providesthe main input to the phaseaccumulator. If a sinelook-up table is used, the phase accumulator computesa phase (angle) address for the look-up table, which outputs the digital value of amplitude —corresponding to the sine of that phase angle —to the DAC. The DAC, in turn, converts that number to a corresponding value of analog voltage or current. To generate a fixed-frequency sine wave, a constant value (the phase increment —which is determined by the binary number) is added to the phase accumulator with eachFigure 2. Square-, triangular-, and sinusoidal outputs from a DDS.Figure 3. Components of a direct digital synthesizer.clock cycle. If the phase increment is large, the phase accumulator will step quicklythrough the sine look-up table and thus generate a high frequency sine wave. If thephase increment is small, the phase accumulator will take many more steps,accordingly generating a slower waveform.What do you mean by a complete DDS?The integration of a D/A converter and a DDS onto a single chip is commonlyknown as a complete DDS solution, a property common to all DDS devices fromADI.Let’s talk some more about the phase accumulator. How does it work?Continuous-time sinusoidal signals have a repetitive angular phase range of 0 to2 .The digital implementation is no different. The counter’s carry function allowsthe phase accumulator to act as a phase wheel in the DDS implementation.To understand this basic function, visualize the sine-wave oscillation as a vectorrotating around a phase circle (see Figure 4).Each designated point on the phase wheelcorresponds to the equivalent point on a cycleof a sine wave. As the vector rotates aroundthe wheel, visualize that the sine of the anglegenerates a corresponding output sine wave.One revolution of the vector around the phasewheel, at a constant speed, results in onecomplete cycle of the output sine wave. TheFigure 4. Digital phase wheel. phase accumulator provides the equallyspaced angular values accompanying the vector’s linear rotation around the phasewheel. The contents of the phase accumulator correspond to the points on the cycle ofthe output sine wave.- 4 -- 5 -The phase accumulator is actually a modulo- M counter that increments its stored number each time it receives a clock pulse. The magnitude of the increment is determined by the binary-coded input word (M). This word forms the phase step size between reference-clock updates; it effectively sets how many points to skip around the phase wheel. The larger the jump size, the faster the phase accumulator overflows and completes its equivalent of a sine-wave cycle. The number of discrete phase points contained in the wheel is determined by the resolution of the phase accumulator (n), which determines the tuning resolution of the DDS. For an n = 28-bit phase accumulator, an M value of 0000...0001 would result in the phase accumulator overflowing after 28 reference-clock cycles (increments). If the M value is changed to 0111...1111, the phase accumulator will overflow after only 2 reference-clock cycles (the minimum required by Nyquist). This relationship is found in the basic tuning equation for DDS architecture:n C out f M f 2⨯= where:fOUT = output frequency of the DDSM = binary tuning wordfC = internal reference clock frequency (system clock)n = length of the phase accumulator, in bitsChanges to the value of M result in immediate and phase-continuous changes in the output frequency. No loop settling time is incurred as in the case of a phase-locked loop.As the output frequency is increased, the number of samples per cycle decreases. Since sampling theory dictates that at least two samples per cycle are required to reconstruct the output waveform, the maximum fundamental output frequency of aDDS is fC/2. However, for practical applications, the output frequency is limited to somewhat less than that, improving the quality of the reconstructed waveform and permitting filtering on the output.When generating a constant frequency, the output of the phase accumulator increases linearly, so the analog waveform it generates is inherently a ramp.Then how is that linear output translated into a sine wave?A phase -to - amplitude lookup table is used to convert the phase-accumulator’s instantaneous output value (28 bits for AD9833)—with unneeded less-significant bits eliminated by truncation—into the sine-wave amplitude information that is presented to the (10 -bit) D/A converter.The DDS architecture exploitsthe symmetrical nature of a sinewave and utilizes mapping logicto synthesize a complete sinewave from one-quarter-cycle ofFigure 5. Signal flow through the DDS architecture. data from the phase accumulator.The phase-to- amplitude lookup table generates the remaining data by reading forward then back through the lookup table. This is shown pictorially in Figure 5. What are popular uses for DDS?Applications currently using DDS-based waveform generation fall into two principal categories: Designers of communications systems requiring agile (i.e., immediately responding) frequency sources with excellent phase noise and low spurious performance often choose DDS for its combination of spectral performance and frequency-tuning resolution. Such applications include using a DDS for modulation, as a reference for a PLL to enhance overall frequency tunability, as a local oscillator (LO), or even for direct RF transmission.- 6 -Alternatively, many industrial and biomedical applications use a DDS as a programmable waveform generator. Because a DDS is digitally programmable, the phase and frequency of a waveform can be easily adjusted without the need to change the external components that would normally need to be changed when using traditional analog-programmed waveform generators. DDS permits simple adjustments of frequency in real time to locate resonant frequencies or compensate for temperature drift. Suchapplications include using a DDS in adjustable frequency sources to measure impedance (for example in an impedance-based sensor), to generate pulse-wave modulated signals for micro-actuation, or to examine attenuation in LANs or telephone cables.What do you consider to be the key advantages of DDS to designers of real-world equipment and systems?Today’s cost- competitive, high - performance, functionally integrated DDS ICs are becoming common in both communication systems and sensor applications. The advantages that make them attractive to design engineers include:• digitally controlled micro-hertz frequency-tuning and sub-degree phase-tuning capability,• extremely fast hopping speed in tuning output frequency (or phase); phase - continuous frequency hops with no overshoot/undershoot or analog-related loop settling-time anomalies,• the digital architecture of DDS eliminates the need for the manual tuning and tweaking related to component aging and temperature drift in analog synthesizer solutions, and• the digital control interface of the DDS architecture facilitates an environment where systems can be remotely controlled and optimized with high resolution under processor control.- 7 -What are the key performance specs of a DDS based system?Phase noise, jitter, and spurious-free dynamic range (SFDR).Phase noise is a measure (dBc/Hz) of the short-term frequency instability of the oscillator. It is measured as the single-sideband noise resulting from changes in frequency (in decibels below the amplitude at the operating frequency of the oscillator using a 1-Hz bandwidth) at two or more frequency displacements from the operating frequency of the oscillator. This measurement has particular application to performance in the analog communications industry.Do DDS devices have good phase noise?Noise in a sampled system depends on many factors. Reference-clock jitter can be seen as phase noise on the fundamental signal in a DDS system; and phase truncation may introduce an error level into the system, depending on the code word chosen. For a ratio that can be exactly expressed by a truncated binary-coded word, there is no truncation error. For ratios requiring more bits than are available, the resulting phase noise truncation error results in spurs in a spectral plot. Their magnitudes and distribution depends on the code word chosen. The DAC also contributes to noise in the system.DAC quantization or linearity errorswill result in both noise andharmonics. Figure 9 shows a phasenoise plot for a typical DDSdevice—in this case an AD9834.How can I evaluate your DDSdevices?All DDS devices have an evaluation board available for Figure 9. Typical output phase noise plotfor the AD9834. Output frequency is 2 MHz and M clock is 50 MHz.- 8 -purchase. They come with dedicated software, allowing the user to test/evaluate the part easily within minutes of receiving the board. A technical note accompanying each evaluation board contains schematic information and shows best recommended board-design and layout practice.- 9 -西北工业大学明德学院本科毕业设计论文关于直接数字频率合成器1.什么是直接数字频率合成器？直接数字频率合成器（DDS）是一种通过产生一个以数字形式时变的信号，然后执行由数字至模拟转换的方法。

直接数字频率合成技术(DDS)

DDS直接数字频率合成技术
2, 采用分立IC电路系统实现,一般有CPU, RAM, ROM, D/A, CPLD, 模拟滤波器等组成
3, CPLD,FPGA实现
•用QuartusII采用原理图输入来完成顶层设计。 •相位累加器调用lmp_add_sub加减法器或用HDL实现 •波形存储器（ROM）通过调用lpm_rom元件实现，其LPM_FILE 的值*.mif是一个存放波形幅值的文件。注意，利用波形幅值的奇、偶对称特性，最多可以节省3/4的资源。 •频率控制字与频率之间的转换可以调用乘除法模块实现 •波形存储器设计主要考虑的问题是其容量的大小，这是非常可观的。
统输出一个正弦波。
▪输出正弦波周期
T0
Tc 2N M
▪输出正弦波频率
fout
M
fc 2N
DDS直接数字频率合成技术
▪M与输出fout和fC之间的关系
M ( fout 2N ) fc
0 M 2N 1
▪DDS的最小分辨率通常用频率增量来表示频率合成器的分辨率
fout
M
fc 2N
M=1
f m in
DDS直接数字频率合成技术
直接数字频率合成技术 (DDS)
DDS直接数字频率合成技术
DDS或DDFS 是 Direct Digital Frequency Synthesis 的简称
1971年，由J.Tierney 和C.M.Tader 等人ቤተ መጻሕፍቲ ባይዱ “A Digital Frequency Synthesizer”一文中首次提出了DDS的概念。
12
超宽的相对宽带
超高的捷变速率（可实现跳频）
超细的分辨率
相位的连续性
输出波形灵活

直接数字式频率合成器DDS

/dzdgdq/jsqy/40028.shtml/view/229432.htm?fr=ala0_1/view/38405.htm?fr=ala0_1_1直接数字式频率合成器DDS2010-04-25 18:06直接数字频率合成技术（Direct DigitalFrequencySynthesis，即DDFS，一般简称DDS）是从相位概念出发直接合成所需波形的一种新的频率合成技术。

DDS的工作原理是以数控振荡器的方式，产生频率、相位可控制的正弦波（SineWave）。

电路一般包括基准时钟、频率累加器、相位累加器、幅度／相位转换电路、D／A转换器和低通滤波器（LPF）。

其中，频率累加器对输入信号进行累加运算，产生频率控制数据（Frequency Data或相位步进量Phase Increment）。

相位累加器由N位全加器和N位累加寄存器级联而成，对代表频率的二进制码进行累加运算，是典型的反馈电路，产生累加结果Y。

幅度／相位转换电路实质是一个波形存储器（WaveformMemory），以供查表使用。

读出的数据送入D／A转换器和低通滤波器。

具体工作过程如下：每来一个时钟脉冲Fclk，N位加法器将频率控制数据X与累加寄存器输出的累加相位数据相加，把相加后的结果Y送至累加寄存器的输入端。

累加寄存器一方面将在上一时钟周期作用后所产生的新的相位数据反馈到加法器的输入端，以使加法器在下一时钟的作用下继续与频率控制数据X相加；另一方面，将这个值作为取样地址值送入幅度／相位转换电路（即波形存储器），幅度／相位转换电路根据这个地址值输出相应的波形数据。

最后，经数／模转换（D／AConverter）和低通滤波器（LowPass Filter）将波形数据转换成所需要的模拟波形。

相位累加器在基准时钟的作用下，进行线性相位累加，当相位累加器累加满量时就会产生一次溢出，这样就完成了一个周期，这个周期也就是DDS合成信号的一个频率周期。

直接数字频率合成器DDS

1. 直接数字频率合成器DDS直接数字频率合成器DDS 是Direct Digital Synthesizer 的缩写，它是通信系统中常用到的部件。

用DDS 还可以作为很有用的信号源，与模拟式的频率锁相环PLL 相比，它有许多优点，其中以下两条最为突出：（1）频率切换迅速由于不存在滤波环路，所以可以在极短的时钟周期内改变频率。

（2）频率稳定度高由于采用了晶体振荡器作为时钟源，因此极高的频率稳定度。

2. 数字式波形生成的基础知识存储器与波形数据如果一个存储器有n 条地址线，则这个存储器的存储空间为2n。

存储器中数据与波形的关系如图1所示。

假设在2n个存储单元内存放了一个周期的正弦波数据，则每个单元内的数据就表示正弦值的大小，这种存储器称为波形数据存储器。

图1表明了存储单元与正弦波形的对应关系。

如果重复地从0~2n -1单元读出波形数据存储器中的数据，在波形存储器的输出端就会得到周期的正弦序列；如果将周期的正弦序列输入到D/A 转换器，则会在D/A 转换器的输出端得到连续的正弦电压。

输出的正弦序列（或连续的正弦电压）的周期是由什么决定呢？它是由读出数据的时钟频率决定的。

如图2所示，设CLK 为加于波形存储器的时钟，该时钟的周期为T0，则其频率为fclk=1/T0。

显然，时钟频率越高，读取波形存储器内一个周期的数据所用的时间就越短，因而从D/A 转换器得到的正弦信号的频率就越高。

波形发生器的系统组成如图3所示为波形发生器的系统组成，其中，时钟fclk 加于二进制计数器，生成波形数据存储器所需的地址信号，地址信号的产生频率正比于时钟频率。

计数器的输出在0~2n -1之间周而复始地变化，从而使波形存储器输出周期的正弦序列，D/A 转换器则输出连续的模拟正弦电压波形。

图4所示给出了一周期的正弦波形与时钟周期的关系。

从图中可以得到fclk/f=2n ，这样一个重要关图1 存储器中的数据与波形的关系T0=1/fclk图2 时序逻辑电路的时钟形图3 波形发生器的系统组成系。

直接数字频率合成

电路板
三者性能比较
在频率合成（FS）技术发展的历史中，直接模拟合成技术是早期使用的一种较为广泛的技术。直接模拟合成利用倍频（乘法）、分频（除法）、混频（加减法）和滤波技术，从一个或多个高稳定度和精确度的参考频率源产生所需的频率。该方法的优点是频率转换时间短（小于100ns），载频相位噪声好等。但缺点是实现设备体积大、功耗大且易产生过多的杂散分量，频谱纯度不高，合成的正弦波的幅度、相位等参数难以控制。因此，直接模拟合成已逐渐不再使用。
目前使用最为广泛的频率合成技术就是锁相环（PLL）合成技术。该技术利用锁相环完成对参考频率源的加、减、乘、除运算，从而得到预期的频率。锁相技术具有良好的窄带跟踪特性，可以根据需要选择频率信号。相对于直接模拟频率合成而言，锁相环具有频谱纯度高，能有效抑制杂散分量且结构简单、易于集成等特点。但是，锁相环存在高分辨率和快速转换速度之间的矛盾，故而一般用于大步进频率合成技术中。
典型应用
频率变化灵敏的时钟发生器
灵敏的高频合成器
可编程的“小数N倍分频”合成器
预祝大家学有所成！谢谢！
基本原理
简易结构框图
完整结构框图
工作模式
控制寄存器
控制流程

1)给系统上电,由微控制器向AD9852发出复位信号,此信号需要至少保持10个参考时钟周期的高电平。 (2)设置S/P SELECT,选择相应的接口模式。 (3) 写控制字,设置外部时钟更新、工作模式、倍频指数等，发出外部更新时钟。 (4)写频率控制字,然后发出外部更新时钟,更新AD9852内部控制寄存器。
DDS的性能分析
5、输出波形的灵活性只要在DDS内部加上相应
控制如调频控制FM、调相控制PM和调幅控制 AM，即可以方便灵活地实现调频、调相和调幅功能，产生FSK、PSK、ASK和MSK等信号。另外，只要在DDS的波形存储器存放不同波形数据，就可以实现各种波形输出，如三角波、锯齿波和矩形波甚至是任意的波形。当DDS的波形存储器分别存放正弦和余弦函数表时，既可得到正交的两路输出。

直接数字频率合成器

直接数字频率合成器一、设计要求及说明设计一个频率及相位均可控制的具有正弦和余弦输出的直接数字频率合成器（Direct Digital Frequency Synthesizer 简称DDFS或DDS）.DDS是一种基于全数字技术，从相位概念出发直接合成所需波形的一种频率合成技术。

具体地说，从相位出发，用不同的相位，给出不同的电压幅度，最后平滑出需要的频率..DDS是一种新型的频率合成技术。

具有相对带宽大、频率转换时间短、分辨率高、相位连续性好等优点，很容易实现频率、相位和幅度的数控调制，广泛应用于通讯领域.(1)基本要求1)利用QuartusII软件和SmartSOPC实验箱实现DDS的设计；2)DDS中的波形存储器模块用Altera公司的Cyclone系列FPGA芯片中的RAM实现，RAM结构配置成212×10类型；3)具体参数要求：频率控制字K取4位；基准频率fc=1MHz,由实验板上的系统时钟分频得到,系统具有清零和保持的功能；4)利用实验箱上的D/A转换器件将ROM输出的数字信号转换为模拟信号，能够通过示波器观察到正弦波形,能够同时输出正余弦两路正交信号;5)通过开关（实验箱上的Ki）输入DDS的频率和相位控制字，并能用示波器观察加以验证；(2)提高要求1)扩大频率控制和相位控制的范围，并在数码管上分别显示频率控制字K及其对应生成的频率；2)设计能输出多种波形（三角波、锯齿波、方波等）的多功能波形发生器；二、方案论证DDS组成与工作原理图:(1)频率与之语调节电路K被称为频率控制字，也叫相位增量。

DDS方程为：f0=f c K/2N,f0为输出频率，f c为时钟频率。

当K=1时，DDS输出最低频率为f c/2N，而DDS的最大输出频率由Nyquist采样定理决定，即f c//2，也就是说K的最大值为2N-1。

因此，只要N足够大，DDS可以得到很细的频率间隔。

要改变DDS的输出频率，只要改变频率控制字K即可。

dds 芯片

dds 芯片DDS芯片，全称为直接数字频率合成器（Direct Digital Synthesizer），是一种能够直接生成高精度数字频率信号的数字电路。

其原理是通过数字信号处理技术，将参考时钟信号分频后，经过相位累加器进行相位计算，再通过查表读取幅度数据，最后通过数字模拟转换器（DAC）将数字信号转换成模拟信号输出。

DDS芯片的主要功能是用来产生各种复杂的波形信号，包括正弦波、方波、三角波等。

由于采用数字技术，在频率调整和生成各种模拟信号方面具有极高的灵活性和精度。

DDS芯片的输出频率范围广，可达数十千兆赫兹，频率分辨率也很高，可达数百、数千万分之一赫兹，因此被广泛应用于通信、雷达、仪器仪表、声音合成等领域。

DDS芯片的工作原理如下：首先，参考时钟信号会经过一个分频器，将其分频得到一个较低的频率信号，称为相量累加频率。

然后，将相量累加频率输入给相位累加器，相位累加器不断累加输入的相量累加频率，以得到相位信息。

最后，将相位信息输入给振荡器的控制输入端，控制振荡器输出信号的相位。

同时，通过振荡器输出的信号经过一个查表器，查表器根据输入的相位信息找到对应的幅度信息，然后通过DAC将数字信号转换为模拟信号输出。

DDS芯片的优点是具有高精度、快速调频、稳定性好等特点。

与传统的频率合成器相比，DDS芯片由于采用数字技术，可以直接生成所需频率的信号，无需通过频率分频器和相位累加器等模拟电路的串联，导致频率合成精度较高，频率稳定性好，而传统的电路调整频率时需要更换电子元器件并重新进行调试。

通过DDS芯片，可以生成各种复杂的波形信号，不仅可以产生常见的正弦波、方波、三角波等基本信号，还可以通过在查表中输入任意的幅度值来产生各种自定义波形。

这使得DDS芯片在声音合成、信号调制、激励信号产生等领域有广泛应用。

同时，由于DDS芯片具有高精度和可调性能，也被用于频率敏感的仪表设备和通信设备中。

综上所述，DDS芯片是一种能够直接生成高精度数字频率信号的数字电路。

直接数字合成英文文献翻译

直接数字合成函数发生器设计的影响函数发生器已经存在了很长一段时间。

假以时日，这些工具已经积累了一长串的功能。

开始只是几个旋钮设置的振幅和频率的正弦输出，函数发生器现在提供更宽的频率范围内，校准的输出电平，各种波形，调制模式，计算机接口，和在某些情况下，任意函数。

添加到函数发生器的许多功能复杂的设计，并增加了他们的成本。

有机会熟悉的函数发生器使用直接数字合成（DDS）进行大刀阔斧的重新设计。

DDS的频率分辨率和提供卓越的允许直接执行频率，相位和幅度调制。

这是“上涨”函数发生器的功能，现在都在一个干净的，根本的办法处理DDS。

直接数字频率合成许多的DDS的概念中示出的方式，产生一个正弦波。

下图显示了一个简单的DDS函数发生器的框图。

正弦函数被存储在一个RAM表。

由DAC数字正弦RAM的输出被转换为一个模拟正弦波。

出现在DAC输出通过一个低通滤波器，提供一个干净的正弦波输出过滤的步骤。

正弦波的频率依赖于地址RAM表被改变的速率。

地址由添加一个常量，存储在的相位增量寄存器（PIR），相位累加器。

一般，相加的速率是恒定的，并且通过改变在PIR的数目被改变的频率。

频率分辨率取决于在PIR的比特的数目。

如果PIR，加法器，和相位累加器的支持48位增加，那么分数频率分辨率是其中的一部分在247，或约1×1014。

这意味着一个48位的DDS发生器可以提供比1μHz分辨率的10 MHz输出。

有一些细节需要加以解决，以了解DDS在此应用程序。

关于采样率，RAM大小，分辨率DAC，滤波器的特性，和频谱纯度的输出必须回答的问题。

简单的DDS函数发生器下面的曲线图中示出了低通滤波器的传递函数。

正如我们已经看到的那样，必须通过过滤器的最高频率，我们希望生成（FMAX），但必须从它的阻带FS-FMAX。

陡峭的滚降滤波器的阻带衰减高是很难建立。

在这种权衡时，会出现一个合理的妥协FMAX= FS/ 3。

这使得过滤器的一个倍频程过渡频带。

直接数字频率合成技术及其接口电路设计

直接数字频率合成技术及其接口电路设计第一章概述随着科技的不断进步，频率合成技术在现代化信号系统设计中扮演着越来越重要的角色。

其中，数字频率合成技术具有显著的优势，广泛应用于无线电通信、雷达制导、导航定位等领域。

本文将重点介绍直接数字频率合成技术以及其接口电路设计。

第二章直接数字频率合成技术直接数字频率合成（Direct Digital Synthesis，DDS）是一种数字信号处理方式，可以通过程序控制生成高精度的周期信号。

DDS技术的基本原理是将一个相位累积器与一个查表器相结合，通过不断地自增相位值，并将相位值作为查表器的地址，从而在输出端实现期望频率的产生。

DDS技术可以通过改变相位累积器的增量来改变输出频率，并且频率调整速度非常快。

相比于传统的类比频率合成技术，DDS 技术的频率稳定性更高，而且能够灵活地实现各种复杂的调制方式。

由于DDS技术具有诸多优势，因此在现代化无线电通信、雷达制导、导航定位等应用领域表现出极大的优势。

第三章直接数字频率合成接口电路设计直接数字频率合成器作为一种数字信号处理器件，需要与外部输入输出信号进行交互，因此需要设计相应的接口电路。

DDS接口电路主要包括数字控制单元、时钟源、数字信号滤波器、DAC 等部分。

其中，数字控制单元负责输入频率、相位信息，生成相应的控制信号，并将这些信号传送给DDS芯片。

时钟源则向DDS芯片提供稳定的时钟信号。

数字信号滤波器用于抑制DDS芯片输出波形上的杂散谐波，确保输出信号的质量。

最后，DAC将DDS芯片输出的数字信号转换成模拟信号，输出到外部电路中。

第四章相关应用案例直接数字频率合成器在无线电通信、雷达制导、导航定位等领域中有着广泛的应用。

下面简要介绍一些相关的应用案例。

1.无线电通信：DDS技术在无线电通信领域中被广泛应用。

例如，在输入频率为100MHz，输出频率为100.5MHz的情况下，DDS芯片可以通过改变相位累积器的增量来产生相应的频率。

频率合成器

基于FPGA的直接数字频率合成技术设计直接数字频率合成（ＤｉｒｅｃｔＤｉｇｉｔａｌＦｒａｑｕｅｎｃｙＳｙｎ-ｔｈｅｓｉｓ即ＤＤＦＳ，一般简称ＤＤＳ）是从相位概念出发直接合成所需波形的一种新的频率合成技术。

它在相对带宽、频率转换时间、相位连续性、正交输出、高分辨率以及集成化等一系列性能指标方面已远远超过了传统频率合成技术。

当累加器的Ｎ很大时，最低输出频率可达Ｈｚ、ｍＨｚ甚至μＨｚ。

也就是说：ＤＤＳ的最低合成频率接近于零频。

如果ｆｃ为５０ＭＨｚ, 那么当Ｎ为４８位时，其分辨率可达１７９ｎＨｚ。

转换时间最快可达１０ｎｓ的量级，这都是传统频率合成所不能比拟的。

但它的不足之处是最高工作频率会受限、噪声和杂波不够理想。

本设计采用ＡＬＴＥＲＡ公司的ＦＰＧＡ芯片ＥＰ１Ｋ３０ＴＣ－１４４来实现ＤＤＳ技术。

ＥＰ１Ｋ３０芯片属ＡＬＴＥＲＡ公司的ＡＣＥＸ系列，该系列是ＡＬＴＥＲＡ公司着眼于通信、音频处理及类似场合应用而推出的ＦＰＧＡ器件系列芯片，它采用０．２２／０．１８微米混合工艺，密度从１００００门到１０００００门。

所有ＡＣＥＸ系列器件均兼容６４ｂｉｔ、６６ＭＨｚ的ＰＣＩ，并支持锁相环电路。

ＡＣＥＸ１Ｋ采用查找表（ＬＵＴ）和ＥＡＢ（嵌入式阵列块）相结合的结构，可用来实现存储器、专用逻辑功能和通用逻辑功能，每个ＥＢＡ能提供４０９６比特的存储空间，每个ＬＥ包含４个输入ＬＵＴ、一个可编程的触发器、进位链和一个层叠链。

合理运用进位链能够提高系统运行速度。

ＥＰ１Ｋ３０ＴＣ－１４４的最大系统门数为１１９０００，它有１７２８个逻辑宏单元数和５个嵌入式阵列块，最大可提供２ｋＢ的ＲＯＭ／ＲＡＭ位，因而可完全满足ＤＤＳ设计的要求。

１ＤＤＳ的实现过程图１为ＤＤＳ系统的基本原理图，图中的相位累加器由Ｎ位全加器和Ｎ位累加寄存器级联而成，可对频率控制字的２进制码进行累加运算，是典型的反馈电路，产生的累加结果的高Ｍ位作为ＲＯＭ查找表的取样地址值，而此查找表中储存了一个周期的正弦波幅度值。

直接数字频率合成

设计实例
N位
频率 M 控制字
累加器
相位寄存器
fc
频率控制字M 控制DDS输出正（余）弦波的频率
时钟源
相位控制字
加法器
正(余)弦查找表
相位控制字控制DDS输出正（余）弦波的相位
DAC
LPF
输出频率 fout
设计实例
N位
频率 M 控制字
累加器
相位寄存器
fc
相位控制字
加法器
正(余)弦查找表
设计实例
直接数字频率合成
1971年，学者J．Tierncy、 C.M.Rader和提出了以全数字技术、从相位概念出发直接合成所需波形的一种新的频率合成原理。
随着技术和器件水平的提高，一种新的频率合成技术——直接数字频率合成（DDS, Direct Digital Synthesis）得到了飞速的发展。 DDS技术是一种把一系列数字形式的信号通过DAC转换成模拟形式的信号的合成技术。
设计实例
CLK FRE Q[9..0 ] P HASE[9..0]
T[9 ..0]
LP M_DIRECTI ON＝ "ADD"
LP M_PIP ELI NE＝
累加器
LP M_REP RESENTATION＝ "UNSIGNE D"
LP M_WIDTH＝ 10
LP M_ADD_SUB
ci n d ataa
DAC
LPF
输出频率 fout
时钟源
波形参数：
Tout=(2N/M)Tc fout=(M/2N)fc 当M=2N-1时， foutmax=f c/2。
设计实例
34 DDS电路的波形仿真结果