On-line Detection of Short Circuits in Digital Devices and Systems

On-line Detection of Short Circuits in Digital Devices and Systems
Adam Kristof
Silesian University of Technology in Gliwice, Poland
a.kristof@
Abstract
Presented method of on-line detection of overloads and short circuits in digital devices and systems is based on inexp ensive overload detectors built into integrated circuits. A p rototyp e 0.8 µm CMOS ASIC successfully verifies this method.
Summary
P CB/MCM interconnections (physical wires connecting integrated circuits in electronic devices) are traditionally tested in off-line mode only. Unfortunately, some poten-tially dangerous interconnections' faults, as short circuits,can arise while a device is operating. Therefore, the following idea has born, which enables early detection of this kind of faults and can prevent from expensive damages. Short circuits can be on-line detected if all output ports in digital integrated circuits have built-in overload detectors. The overload detectors built into output ports of digital integrated circuits have been already presented in [1]. A simplified schematic diagram of an example bi-directional I/O port with the built-in
synchronous overload detector is shown in Fig. 1.
Figure 1: Overload detector built into a bi-directional I/O port.
Dedicated SEn (sensing enable) control signal masks tran-sient overloads during data change, and enables overload detection when output data on I/O pins have stabilised. In synchronous devices this signal can be easily derived from clock signal, see [1]. The overload signals ~F from all detectors in an integrated circuit are connected to and summed on a common ~F rail. The common ~F signal may be used internally (if required) and led outside the circuit as a general overload/short-circuit warning signal (OVL in Fig. 2).
While this idea might be expected to be expensive, in fact it is not. An experimental prototype ASIC, Fig. 2, which was designed and fabricated in AMS CXQ-08 silicon technology [2], can serve as the proof. Each overload detector built into a 3-state output port, (port selected from the CXQ-08 I/O ports library [2]), appeared to occupy only as little as 2% of the total I/O port area. Including a dedicated OVL port, which leads out the overload warning signal, the total overheads of implementing the complete architecture of built-in overload detectors appea-red to be only about 1.3% fraction of a 5 [mm 2] area of the prototype chip. For larger chips and for more advanced technologies the overheads are expected to be even smal-ler. Moreover, once designed a complete library of I/O ports with built-in overload detectors makes the imple-mentation process very easy. Exp erimental results : short circuits were signalled in less then 25 [ns] after the falling edge of CLK (~SEn)
signal following a fault insertion.
Figure 2: Experimental ASIC - a block diagram.
References
[1] A. Kristof: CMOS Output Ports with On-line Overload
Detection for Synchronous Digital ICs , proceedings of 3rd DDECS Workshop, pp. 74-80, Slovakia, Apr. 2000 [2]AMS 0.8 Micron Double-Metal CMOS Standard Cells
5.0V Databook, "/data books/cxb50/index.html", "/databoo ks/cxb50/index.html"
Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW’02) 0-7695-1641-6/02 $17.00 © 2002
IEEE。