Negative linear compressibility in confined dilatating systems
NASATM-2005-213530 Failure Models and Criteria for FRP Under In-Plane or Three-Dimensional
Failure Models and Criteria for FRP Under In-Plane or Three-Dimensional Stress States Including Shear Non-Linearity
Silvestre T. Pinho Imperial College, London, UK Carlos G. Dávila NASA Langley Research Center, Hampton, Virginia Pedro P. Camanho University of Porto, Porto, Portugal Lorenzo Iannucci Imperial College, London, UK Paul Robinson Imperial College, London, UK
February 2005
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LF356NNOPB,LF356M,LF356H,LF156H,LF256H,LF356MX, 规格书,Datasheet 资料
capability
Applications
n Precision high speed integrators n Fast D/A and A/D converters n High impedance buffers n Wideband, low noise, low drift amplifiers
LF155/LF156/LF256/LF257/LF355/LF356/LF357 JFET Input Operational Amplifiers
December 2001
LF155/LF156/LF256/LF257/LF355/LF356/LF357
JFET Input Operational Amplifiers
1.5
12 5 12
LF257/ LF357 (AV=5)
1.5
50 20 12
Units µs
V/µs MHz
Simplified Schematic
*3pF in LF357 series.
BI-FET™, BI-FET II™ are trademarks of National Semiconductor Corporation.
300˚C
300˚C
Dual-In-Line Package
Soldering (10 sec.)
260˚C
260˚C
260˚C
Small Outline Package
Vapor Phase (60 sec.)
铸造用英语词汇
材料成型工艺基础部分0 绪论金属材料:metal material (MR)高分子材料:high-molecular material陶瓷材料:ceramic material复合材料:composition material成形工艺:formation technology1 铸造铸造工艺:casting technique铸件:foundry goods (casting)机器零件:machine part毛坯:blank力学性能:mechanical property砂型铸造:sand casting process型砂:foundry sand1.1 铸件成形理论基础合金:alloy铸造性能:casting property工艺性能:processing property收缩性:constringency偏析性:aliquation氧化性:oxidizability吸气性:inspiratory铸件结构:casting structure使用性能:service performance浇不足:misrun冷隔:cold shut夹渣:cinder inclusion粘砂:sand fusion缺陷:flaw, defect, falling流动性:flowing power铸型:cast (foundry mold)蓄热系数:thermal storage capacity 浇注:pouring凝固:freezing收缩性:constringency逐层凝固:layer-by-layer freezing 糊状凝固:mushy freezing结晶:crystal缩孔:shrinkage void缩松:shrinkage porosity顺序凝固:progressive solidification 冷铁:iron chill补缩:feeding等温线法:constant temperature line method 内接圆法:inscribed circle method铸造应力:casting stress变形:deforming裂纹:crack机械应力:mechanical stress热应力:heat stress相变应力:transformation stress气孔:blow hole铸铁:ingot铸钢:cast steel非铁合金:nonferrous alloy灰铸铁:gray cast-iorn孕育处理:inoculation球墨铸铁:spheroidal球化处理:sheroidisation可锻铸铁:ductile cast iron石墨:graphite蠕墨铸铁:vermicular cast iron热处理:heat processing铝合金:Al-alloy熔炼:fusion metallurgy铜合金:copper alloy氢脆:hydrogen brittleness1.2 铸造方法(casting method)手工造型:hand moulding机器造型:machine moulding金属型:metal mold casting金属模:permanent mould压力铸造:press casting熔模铸造:investment moulding蜡膜:cere离心铸造:centrifugal casting低压铸造:casting under low pressure 差压铸造:counter-pressure casting 陶瓷型铸造:shaw process1.3 铸造工艺设计浇注位置:pouring position分型面:mould joint活块:loose piece起模:patter drawing型芯:core型芯撑:chaplet工艺参数:processing parameter下芯:core setting合型:mould assembly冒口:casting head尺寸公差:dimensional tolerance尺寸公差带:tolerance zone机械加工余量:machining allowance 铸孔:core hole非标准:nonstandard label收缩率:rate of contraction线收缩:linear contraction体收缩:volume contraction起模斜度:pattern draft铸造圆角:curving of castings芯头:core register芯头间隙:clearance芯座:core print seat分型线:joint line分模线:die parting line1.4 铸造结构工艺性加强筋:rib reinforcement撒砂:stuccoing内腔:entocoele2 金属塑性加工塑性加工:plastic working塑性:plastic property锻造:forge work冲压:punching轧制:rolling拉拔:drawing挤压:extruding细化晶粒:grain refinement 热锻:hit-forging温锻:warm forging2.1 金属塑性加工理论基础塑性变形:plastic yield加工硬化:work-hardening 韧性:ductility回复温度:return temperature 再结晶:recrystallize再结晶退火:full annealing 冷变形:cold deformation热变性:heat denaturation锻造比:forging ratio镦粗:upset拔长:pull out纤维组织:fibrous tissue锻造性能:forging property可锻性:forgeability变形抗力:resistance of deformation化学成分:chemical constitution热脆性:hot brittleness冷脆性:cold-shortness变形速度:deformation velocity应力状态:stress condition变形温度:deformation temperature过热:overheating过烧:burning脱碳:carbon elimination始锻温度:initiation forging temperature 终锻温度:final forging temperature 2.2 金属塑性加工方法自由锻:flat-die hammer冲孔:jetting弯曲:bend弯曲半径:bending radius切割:cut扭转:twist rotation错移:offsetting锻接:percussion基本工序:basic process辅助工序:auxiliary process精整工序:finishing process模锻:contour forging锻模:forging die胎膜锻:fetal membrane forging剪床:shearing machine冲床:backing-out punch冲裁:blanking弹性变形:elastic distortion塑性变形:plastic yield剪切变形:shearing deformation最小弯曲半径:minimum bending radius 曲率:angularity弯裂:rupture回弹:rebound辊轧:roll forming辊锻:roll forging斜轧:oblique rolling横轧:transverse rolling辗压:tamping drum挤压:extruding拉拔:draft2.3 塑性加工工艺设计工艺规程:process specification锻件图:forging drawing敷料:dressing锻件余量:forging allowance锻件公差:forging tolerance工夹具:clamping apparatus加热设备:firing equipment加热规范:heating schedule冷却规范:cooling schedule后续处理:after treatment分模面:die parting face冲孔连皮:punching the wad模锻斜度:draft angle圆角半径:radius of corner圆饼类锻件:circumcresent cake-like forging 长轴类锻件:long axis-like forging2.4 锻件结构工艺性锥体:cone斜面:cant空间曲线:curve in space粗糙度:degree of roughness2.5 冲压件结构工艺性3 焊接焊接:welding铆接:riverting熔焊:fusion welding压焊:press welding钎焊:braze welding3.1 焊接理论基础冶金:metallurgy电弧焊:arc welding气焊:acetylene welding电渣焊:electro-slag welding 高能束焊:high energy welding 电子焊:electronic welding激光焊:laser welding等离子焊:plasma welding电弧:electric arc阳极区:anode region阴极区:negative polarity弧柱区:arc stream正接法:electrode negative method反接法:opposition method脱氧剂:deoxidizing agent焊缝:welded seam焊缝区:weld zone熔合区:fusion area热影响区:heat-affected zone脆性断裂:brittle fracture过热区:overheated zone正火区:normalized zone相变区:phase change zone焊接应力:welding stress收缩变形:contraction distortion角变形:angular deformation弯曲变形:bend deformation扭曲变形:warping deformation波浪变形:wave transformation反变形法:reversible deformation method 刚性固定法:rigid fixing method预热:warming-up缓冷:slow cool焊后热处理:postweld heat treatment矫形处理:shape-righting3.2 焊接方法埋弧焊:hidden arc welding气体保护焊:gas shielded arc welding氩弧焊:argon welding熔化极氩弧焊:consumable electrode argon welding 钨极氩弧焊:argon tungsten-arc welding二氧化碳气体保护焊:CO2 gas shielded arc welding 碳弧焊:carbon arc welding碳弧气刨:carbon arc air gouging电渣焊:electro-slag welding高能焊:high grade energy welding等离子弧切割:plasma arc cutting (PAC)堆焊:bead weld电阻焊:resistance welding电焊:electric welding缝焊:seam welding压焊:press welding多点凸焊:multiple projection welding对焊:welding neck摩擦焊:friction welding扩散焊:diffusion welding硬钎料:brazing alloy软钎料:soft solder3.3 常用金属材料的焊接焊接性:weldability焊接方法:welding method 焊接材料:welding material 焊条:electrode焊剂:flux material碳素钢:carbon steel低碳钢:low carbon steel中碳钢:medium carbon steel 高碳钢:high carbon steel低合金钢:lean alloy steel不锈钢:non-corrosive steel 有色金属:nonferrous metal 3.4 焊接工艺设计型材:sectional bar药皮:coating焊丝:soldering wire连续焊缝:continuous weld断续焊缝:intermittent weld应力集中:stress concentration焊接接头:soldered joint坡口:groove对接:abutting joint搭接:lap joint角接:corner joint4 粉末冶金(power metallurgy)粉末冶金成品:finished power metallurgical product 铁氧体:ferrite硬质合金:sintered-carbide高熔点金属:high-melting metal陶瓷:ceramic4.1 粉末冶金工艺理论基础压坯:pressed compact扩散:diffusion烧结:agglomeration固溶:solid solubility化合:combination4.2 粉末冶金的工艺流程制备:preparation预处理:anticipation还原法:reduction method电解法:electrolytic method雾化法:atomization粒度:grain size松装密度:loose density流动性:flowing power压缩性:compressibility筛分:screen separation混合:compounding制粒:pelletization过烧:superburning欠烧:underburnt5 金属复合成型技术自蔓延焊接:SHS welding热等静压:HIP准热等静压:PHIP5.1 液态成型技术与固态成型技术的复合高压铸造:high-pressure casting电磁泵:magnetic-pump压射成型:injection molding柱塞:plunger piston冲头:drift pin凝固法:freezing method挤压法:extrusion method转向节:knuckle pivot制动器:arresting gear5.2 金属半凝固、半熔融成型技术凝固:freezing半熔融:semi-vitreous触变铸造:thixotropy casting触变锻造:thixotropy forging注射成型:injection molding5.3 其他金属成型新技术快速凝固:flash set非晶态:amorphous溢流法:press over system喷射沉积:ejecting deposit爆炸复合法:explosion cladding method 扩散焊接:diffusion welding挤压:extruding轧制:roll down6 非金属材料成型技术6.1 高分子材料成型技术高分子材料:non-metal material 耐腐蚀:resistant material绝缘:insulation老化:ageing耐热性:heat-durability粘弹性:viscoelasticity塑料:plastic material橡胶:rubber合成纤维:synthetic fibre涂料:covering material粘结剂:agglomerant粘度:viscosity热塑性塑料:thermoplastic plastics 热固性塑料:thermosetting plastic 通用塑料:general-purpose plastics 工程塑料:engineering plastic薄膜:thin film增强塑料:reinforced plastics浇注塑料:pouring plastics注射塑料:injiection plastics挤出塑料:extrusion plastics吹塑塑料:blowing plastics模压塑料:die pressing plastics聚合物:ploymer semiconductor吸湿性:hygroscopic cargo定向作用:directional action生胶:green glue stock填料:carrier丁苯橡胶:SBR顺丁橡胶:BR氯丁橡胶:CR丁腈橡胶:NBR硅橡胶:Q聚氨酯橡胶:U压延:calender硫化:sulfuration胶粘剂:adhesive胶接:glue joint刹车片:brake block零件修复:parts renewal蜂窝夹层:honeycomb core material 6.2 工业陶瓷制品的成型技术干燥:drying润滑剂:anti-friction结合剂:binder热压铸:hot injiection moulding 6.3 非金属材料成型技术的新进展热压烧结:hot pressed sintering7 复合材料的成型技术复合材料:composite material树脂:resin7.1 金属复合材料的成型技术硼纤维:boron fiber钛合金:titanium alloy碳纤维:carbon filter等离子喷涂:plasma spraying浸渍法:immersion method锭坯:ingot blank7.2 聚合物基复合材料的成型技术晶须:whisker缠绕成形:enwind forming湿法缠绕:wet method enwind 7.3 陶瓷复合材料成型技术溶胶-凝胶法:sol-gel method化学气相沉积:chemical vapor deposition (CVD) 原位:in situ8 材料成型方法的选择粉末冶金:powder metallurgy工程塑料:engineering plastics工程陶瓷:engineering ceramics。
惠普彩色激光打印机 Pro M454 和惠普彩色激光多功能一体机 Pro M479 维修手册说明书
Table -1 Revision history Revision number 1
Revision date 6/2019
Revision notes HP LaserJet Pro M454 HP LaserJet Pro MFP M479 Repair manual initial release
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Find information about the following topics ● Service manuals ● Service advisories ● Up-to-date control panel message (CPMD) troubleshooting ● Install and configure ● Printer specifications ● Solutions for printer issues and emerging issues ● Remove and replace part instructions and videos ● Warranty and regulatory information
TPA2010D1YZFR,TPA2010D1YZFR,TPA2010D1YZFR,TPA2010D1YEFR,TPA2010D1YEFT, 规格书,Datasheet 资料
FEATURES APPLICATIONSSEE ALSODESCRIPTIONAPPLICATION CIRCUIT9-BALLWAFER CHIP SCALE YZF , YEF PACKAGES TPA2010D1 DIMENSIONS Note: Pin A1 is marked with a “0”for Pb-free (YZF) and a “1”for SnPb (YEF).TPA2010D1SLOS417C–OCTOBER 2003–REVISED SEPTEMBER 20072.5-W MONO FILTER-FREE CLASS-D AUDIO POWER AMPLIFIER•Wireless or Cellular Handsets and PDAs •Maximum Battery Life and Minimum Heat •Personal Navigation Devices –Efficiency With an 8-ΩSpeaker:•General Portable Audio Devices –88%at 400mW •Linear Vibrator Drivers–80%at 100mW– 2.8-mA Quiescent Current –0.5-μA Shutdown Current•TPA2032D1,TPA2033D1,TPA2034D1•Only Three External Components–Optimized PWM Output Stage Eliminates LC Output FilterThe TPA2010D1(sometimes referred to as –Internally Generated 250-kHz Switching TPA2010)is a 2.5-W high efficiency filter-free class-D Frequency Eliminates Capacitor and audio power amplifier (class-D amp)in a 1,45mm ×1,45mm wafer chip scale package (WCSP)that Resistorrequires only three external components.–Improved PSRR (–75dB)and Wide Supply Voltage (2.5V to 5.5V)Eliminates Need for Features like 88%efficiency,–75-dB PSRR,a Voltage Regulatorimproved RF-rectification immunity,and 8mm 2total PCB area make the TPA2010D1(TPA2010)class-D –Fully Differential Design Reduces RF amp ideal for cellular handsets.A fast start-up time of Rectification and Eliminates Bypass 1ms with minimal pop makes the TPA2010D1Capacitor(TPA2010)ideal for PDA applications.–Improved CMRR Eliminates Two Input In cellular handsets,the earpiece,speaker phone,Coupling Capacitorsand melody ringer can each be driven by the •Wafer Chip Scale Packaging (WCSP)TPA2010D1.The TPA2010D1allows independent –NanoFree™Lead-Free (YZF)gain while summing signals from seperate sources,and has a low 36μV noise floor,A-weighted.–NanoStar™SnPb (YEF)Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.NanoFree,NanoStar are trademarks of Texas Instruments.PRODUCTION DATA information is current as of publication date.Copyright ©2003–2007,Texas Instruments IncorporatedProducts conform to specifications per the terms of the Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.ABSOLUTE MAXIMUM RATINGSRECOMMENDED OPERATING CONDITIONSPACKAGE DISSIPATION RATINGSTPA2010D1SLOS417C–OCTOBER 2003–REVISED SEPTEMBER 2007These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.T APACKAGEPART NUMBER SYMBOL Wafer chip scale package (YEF)TPA2010D1YEF (1)AJZ –40°C to 85°CWafer chip scale packaging –Lead free (YZF)TPA2010D1YZF(1)AKO(1)The YEF and YZF packages are only available taped and reeled.To order add the suffix R to the end of the part number for a reel of 3000,or add the suffix T to the end of the part number for a reel of 250(e.g.TPA2010D1YEFR).over operating free-air temperature range unless otherwise noted (1)TPA2010D1In active mode –0.3V to 6V V DD Supply voltage In SHUTDOWN mode–0.3V to 7V V I Input voltage–0.3V to V DD +0.3V Continuous total power dissipation See Dissipation Rating TableT A Operating free-air temperature –40°C to 85°C T J Operating junction temperature –40°C to 150°C T stgStorage temperature–65°C to 150°CYZF 260°C Lead temperature 1,6mm (1/16inch)from case for 10secondsYEF235°C(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.MINNOMMAX UNIT V DD Supply voltage 2.5 5.5V V IH High-level input voltage SHUTDOWN 1.3V DD V V IL Low-level input voltage SHUTDOWN 00.35V R I Input resistorGain ≤20V/V (26dB)15k ΩV IC Common mode input voltage range V DD =2.5V,5.5V,CMRR ≤–49dB0.5V DD –0.8V T AOperating free-air temperature–4085°CT A ≤25°C T A =70°C T A =85°C PACKAGEDERATING FACTOR (1)POWER RATINGPOWER RATINGPOWER RATINGYEF 7.8mW/°C 780mW 429mW 312mW YZF 7.8mW/°C780mW429mW312mW(1)Derating factor measure with High K board.2Submit Documentation FeedbackCopyright ©2003–2007,Texas Instruments IncorporatedProduct Folder Link(s):TPA2010D1ELECTRICAL CHARACTERISTICSOPERATING CHARACTERISTICSTPA2010D1SLOS417C–OCTOBER 2003–REVISED SEPTEMBER 2007T A =25°C (unless otherwise noted)T A =25°C,Gain =2V/V,R L =8Ω(unless otherwise noted)PARAMETERTEST CONDITIONSMINTYP MAX UNITV DD =5V2.5THD +N =10%,f =1kHz,R L =4ΩV DD =3.6V 1.3W V DD =2.5V 0.52V DD =5V2.08THD +N =1%,f =1kHz,R L =4ΩV DD =3.6V 1.06W V DD =2.5V 0.42P OOutput powerV DD =5V 1.45THD +N =10%,f =1kHz,R L =8ΩV DD =3.6V 0.73W V DD =2.5V 0.33V DD =5V1.19THD +N =1%,f =1kHz,R L =8ΩV DD =3.6V 0.59W V DD =2.5V0.26V DD =5V,P O =1W,R L =8Ω,f =1kHz 0.18%Total harmonic distortion plus THD+NV DD =3.6V,P O =0.5W,R L =8Ω,f =1kHz 0.19%noiseV DD =2.5V,P O =200mW,R L =8Ω,f =1kHz0.20%V DD =3.6V,Inputs ac-grounded f =217Hz,k SVR Supply ripple rejection ratio –67dB with C i =2μFV (RIPPLE)=200mV pp SNR Signal-to-noise ratio V DD =5V,P O =1W,R L =8Ω97dB No weighting 48V DD =3.6V,f =20Hz to 20kHz,V n Output voltage noise μV RMS Inputs ac-grounded with C i =2μF A weighting 36CMRR Common mode rejection ratio V DD =3.6V,V IC =1V ppf =217Hz–63dB Z IInput impedance142150158k ΩStart-up time from shutdownV DD =3.6V1ms Copyright ©2003–2007,Texas Instruments Incorporated Submit Documentation Feedback3Product Folder Link(s):TPA2010D1 FUNCTIONAL BLOCK DIAGRAMV DDV O-V O+GNDNotes:* T otal gain =150 kΩR I2 xTPA2010D1SLOS417C–OCTOBER2003–REVISED SEPTEMBER2007Terminal FunctionsTERMINALI/O DESCRIPTIONNAME YEF,YZFIN–C1I Negative differential inputIN+A1I Positive differential inputV DD B1I Power supplyV O+C3O Positive BTL outputGND A2,B3I High-current groundV O-A3O Negative BTL outputSHUTDOWN C2I Shutdown terminal(active low logic)PVDD B2I Power supply4Submit Documentation Feedback Copyright©2003–2007,Texas Instruments IncorporatedProduct Folder Link(s):TPA2010D1TYPICAL CHARACTERISTICSTABLE OF GRAPHSTEST SET-UP FOR GRAPHSNotes:(1) C I was Shorted for any Common-Mode input voltage measurement(2) A 33-µH inductor was placed in series with the load resistor to emulate a small speaker for efficiency measurements.(3) The 30-kHz low-pass filter is required even if the analyzer has an internal low-pass filter. An RC low pass filter (100 Ω, 47 nF) is used on each output for the data sheet graphs.TPA2010D1SLOS417C–OCTOBER 2003–REVISED SEPTEMBER 2007FIGUREEfficiencyvs Output power 1,2P D Power dissipation vs Output power 3,4Supply current vs Output power 5,6I (Q)Quiescent current vs Supply voltage 7I (SD)Shutdown current vs Shutdown voltage 8vs Supply voltage 9P OOutput powervs Load resistance 10,11vs Output power12,13THD+N Total harmonic distortion plus noise vs Frequency14,15,16,17vs Common-mode input voltage 18K SVRSupply voltage rejection ratio vs Frequency 19,20,21vs Time 22GSM power supply rejectionvs Frequency23K SVR Supply voltage rejection ratio vs Common-mode input voltage 24vs Frequency25CMRRCommon-mode rejection ratiovs Common-mode input voltage26Copyright ©2003–2007,Texas Instruments Incorporated Submit Documentation Feedback5Product Folder Link(s):TPA2010D1P O − Output Power − WE f f i c i e n c y − %P O − Output Power − W E f f i c i e n c y − %− P o w e r D i s s i p a t i o n − WP D P O − Output Power − W− S u p p l y C u r r e n t − m AP O − Output Power − WI D D − P o w e r D i s s i p a t i o n − WP D P O− Output Power − W − S u p p l y C u r r e n t − m AP O − Output Power − WI D DShutdown Voltage − V− S h u t d o w n C u r r e n t − I (S D )Aµ0.511.522.5348121620242832R L − Load Resistance − Ω− O u t p u t P o w e r − WP O − S u p p l y C u r r e n t − m AI D D V DD − Supply Voltage − VTPA2010D1SLOS417C–OCTOBER 2003–REVISED SEPTEMBER 2007EFFICIENCYEFFICIENCYPOWER DISSIPATIONvsvsvsOUTPUT POWEROUTPUT POWEROUTPUT POWERFigure 1.Figure 2.Figure 3.POWER DISSIPATIONSUPPLY CURRENTSUPPLY CURRENTvsvsvsOUTPUT POWEROUTPUT POWERFigure 4.Figure 5.Figure 6.SUPPLY CURRENTSUPPLY CURRENTOUTPUT POWERvsvsvsSUPPLY VOLTAGESHUTDOWN VOLTAGELOAD RESISTANCEFigure 7.Figure 8.Figure 9.6Submit Documentation FeedbackCopyright ©2003–2007,Texas Instruments IncorporatedProduct Folder Link(s):TPA2010D1R L − Load Resistance − Ω− O u t p u t P o w e r − WP O 00.511.522.52.53 3.54 4.55V CC − Supply Voltage − V− O u t p u t P o w e r − WP O3P O − Output Power − WT H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %P O − Output Power − WT H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %0.005100.010.020.050.10.20.5125f − Frequency − HzT H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %f − Frequency − HzT H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %f − Frequency − HzT H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %0.01100.020.050.10.20.5125f − Frequency − HzT H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %V IC − Common Mode Input Voltage − VT H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %TPA2010D1SLOS417C–OCTOBER 2003–REVISED SEPTEMBER 2007TOTAL HARMONIC DISTORTION +OUTPUT POWEROUTPUT POWERNOISE vsvsvsLOAD RESISTANCESUPPLY VOLTAGEOUTPUT POWERFigure 10.Figure 11.Figure 12.TOTAL HARMONIC DISTORTION +TOTAL HARMONIC DISTORTION +TOTAL HARMONIC DISTORTION +NOISE NOISE NOISE vsvsvsFREQUENCYFREQUENCYFigure 13.Figure 14.Figure 15.TOTAL HARMONIC DISTORTION +TOTAL HARMONIC DISTORTION +TOTAL HARMONIC DISTORTION +NOISE NOISE NOISE vsvsvsFREQUENCYFREQUENCYCOMMON MODE INPUT VOLTAGEFigure 16.Figure 17.Figure 18.Copyright ©2003–2007,Texas Instruments Incorporated Submit Documentation Feedback7Product Folder Link(s):TPA2010D1f − Frequency − HzS o p p l y R i p p l e R e j e c t i o n R a t i o − d Bf − Frequency − HzS o p p l y R i p p l e R e j e c t i o n R a t i o − d Bf − Frequency − HzS o p p l y R i p p l e R e j e c t i o n R a t i o − d BC1 − High 3.6 V C1 − Amp 512 mVC1 − Duty 12%t − Time − 2 ms/divV DD200 mV/divV OUT20 mV/divf − Frequency − Hz− O u t p u t V o l t a g e − d B VV O − S u p p l y V o l t a g e − d B VV D DV IC − Common Mode Input Voltage − VC M R R − C o m m o n M o d e R e j e c t i o n R a t i o − d Bf − Frequency − HzC M R R − C o m m o n M o d e R e j e c t i o n R a t i o − d BDC Common Mode Voltage − V S o p p l y R i p p l e R e j e c t i o n R a t i o − d BTPA2010D1SLOS417C–OCTOBER 2003–REVISED SEPTEMBER 2007SUPPLY RIPPLE REJECTION RATIOSUPPLY RIPPLE REJECTION RATIOSUPPLY RIPPLE REJECTION RATIOvsvsvsFigure 19.Figure 20.GSM POWER SUPPLY REJECTIONGSM POWER SUPPLY REJECTIONvs vsTIMEFREQUENCYFigure 22.Figure 23.SUPPLY RIPPLE REJECTION RATIOCOMMON-MODE REJECTION RATIOCOMMON-MODE REJECTION RATIOvsvsvsDC COMMON MODE VOLTAGEFREQUENCYFigure 24.Figure 25.Figure 26.8Submit Documentation FeedbackCopyright ©2003–2007,Texas Instruments IncorporatedProduct Folder Link(s):TPA2010D1APPLICATION INFORMATION FULLY DIFFERENTIAL AMPLIFIERAdvantages of Fully DIfferential AmplifiersCOMPONENT SELECTIONInput Resistors(R I)Gain+2x150k WR I ǒVVǓ(1)TPA2010D1SLOS417C–OCTOBER2003–REVISED SEPTEMBER2007The TPA2010D1is a fully differential amplifier with differential inputs and outputs.The fully differential amplifier consists of a differential amplifier and a common-mode amplifier.The differential amplifier ensures that the amplifier outputs a differential voltage on the output that is equal to the differential input times the gain.The common-mode feedback ensures that the common-mode voltage at the output is biased around V DD/2regardless of the common-mode voltage at the input.The fully differential TPA2010D1can still be used with a single-ended input;however,the TPA2010D1should be used with differential inputs when in a noisy environment,like a wireless handset,to ensure maximum noise rejection.•Input-coupling capacitors not required:–The fully differential amplifier allows the inputs to be biased at voltage other than mid-supply.For example, if a codec has a midsupply lower than the midsupply of the TPA2010D1,the common-mode feedback circuit will adjust,and the TPA2010D1outputs will still be biased at midsupply of the TPA2010D1.The inputs of the TPA2010D1can be biased from0.5V to V DD–0.8V.If the inputs are biased outside of that range,input-coupling capacitors are required.•Midsupply bypass capacitor,C(BYPASS),not required:–The fully differential amplifier does not require a bypass capacitor.This is because any shift in the midsupply affects both positive and negative channels equally and cancels at the differential output.•Better RF-immunity:–GSM handsets save power by turning on and shutting off the RF transmitter at a rate of217Hz.The transmitted signal is picked-up on input and output traces.The fully differential amplifier cancels the signal much better than the typical audio amplifier.Figure27shows the TPA2010D1typical schematic with differential inputs and Figure28shows the TPA2010D1 with differential inputs and input capacitors,and Figure29shows the TPA2010D1with single-ended inputs. Differential inputs should be used whenever the single-ended inputs are much more susceptible to noise.Table1.Typical Component ValuesREF DES VALUE EIA SIZE MANUFACTURER PART NUMBERR I150kΩ(±0.5%)0402Panasonic ERJ2RHD154VC S1μF(+22%,–80%)0402Murata GRP155F50J105ZC I(1) 3.3nF(±10%)0201Murata GRP033B10J332K(1)C I is only needed for single-ended input or if V ICM is not between0.5V and V DD–0.8V.C I=3.3nF(with R I=150kΩ)gives a high-pass corner frequency of321Hz.The input resistors(R I)set the gain of the amplifier according to Equation1.Resistor matching is very important in fully differential amplifiers.The balance of the output on the reference voltage depends on matched ratios of the resistors.CMRR,PSRR,and cancellation of the second harmonic distortion diminish if resistor mismatch occurs.Therefore,it is recommended to use1%tolerance resistors or better to keep the performance optimized.Matching is more important than overall tolerance.Resistor arrays with 1%matching can be used with a tolerance greater than1%.Place the input resistors very close to the TPA2010D1to limit noise injection on the high-impedance nodes.For optimal performance the gain should be set to2V/V or lower.Lower gain allows the TPA2010D1to operate at its best,and keeps a high voltage at the input making the inputs less susceptible to noise.Copyright©2003–2007,Texas Instruments Incorporated Submit Documentation Feedback9Product Folder Link(s):TPA2010D1 Decoupling Capacitor(C S)Input Capacitors(C I)f c+1ǒ2p RI C I Ǔ(2)C I+1ǒ2p RI f c Ǔ(3)TPA2010D1SLOS417C–OCTOBER2003–REVISED SEPTEMBER2007The TPA2010D1is a high-performance class-D audio amplifier that requires adequate power supply decoupling to ensure the efficiency is high and total harmonic distortion(THD)is low.For higher frequency transients, spikes,or digital hash on the line,a good low equivalent-series-resistance(ESR)ceramic capacitor,typically1μF,placed as close as possible to the device V DD lead works best.Placing this decoupling capacitor close to the TPA2010D1is very important for the efficiency of the class-D amplifier,because any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency.For filtering lower-frequency noise signals,a10μF or greater capacitor placed near the audio power amplifier would also help,but it is not required in most applications because of the high PSRR of this device.The TPA2010D1does not require input coupling capacitors if the design uses a differential source that is biased from0.5V to V DD–0.8V(shown in Figure27).If the input signal is not biased within the recommended common-mode input range,if needing input as a high pass filter(shown in Figure28),or if using a single-ended source(shown in Figure29),input coupling capacitors are required.The input capacitors and input resistors form a high-pass filter with the corner frequency,f c,determined in Equation2.The value of the input capacitor is important to consider as it directly affects the bass(low frequency) performance of the circuit.Speakers in wireless phones cannot usually respond well to low frequencies,so the corner frequency can be set to block low frequencies in this application.Equation3is reconfigured to solve for the input coupling capacitance.If the corner frequency is within the audio band,the capacitors should have a tolerance of10%or better, because any mismatch in capacitance causes an impedance mismatch at the corner frequency and below.For a flat low-frequency response,use large input coupling capacitors(1μF).However,in a GSM phone the ground signal is fluctuating at217Hz,but the signal from the codec does not have the same217Hz fluctuation. The difference between the two signals is amplified,sent to the speaker,and heard as a217Hz hum.Figure27.Typical TPA2010D1Application Schematic With Differential Input for a Wireless Phone10Submit Documentation Feedback Copyright©2003–2007,Texas Instruments IncorporatedProduct Folder Link(s):TPA2010D1SUMMING INPUT SIGNALS WITH THE TPA2010D1 Summing Two Differential Input SignalsGain1+V OV I1+2x150k WR I1ǒVVǓ(4)Gain2+V OV I2+2x150k WR I2ǒVVǓ(5)TPA2010D1SLOS417C–OCTOBER2003–REVISED SEPTEMBER2007Figure28.TPA2010D1Application Schematic With Differential Input and Input CapacitorsFigure29.TPA2010D1Application Schematic With Single-Ended InputMost wireless phones or PDAs need to sum signals at the audio power amplifier or just have two signal sources that need separate gain.The TPA2010D1makes it easy to sum signals or use separate signal sources with different gains.Many phones now use the same speaker for the earpiece and ringer,where the wireless phone would require a much lower gain for the phone earpiece than for the ringer.PDAs and phones that have stereo headphones require summing of the right and left channels to output the stereo signal to the mono speaker.Two extra resistors are needed for summing differential signals(a total of5components).The gain for each input source can be set independently(see Equation4and Equation5,and Figure30).If summing left and right inputs with a gain of1V/V,use R I1=R I2=300kΩ.Copyright©2003–2007,Texas Instruments Incorporated Submit Documentation Feedback11Product Folder Link(s):TPA2010D1Summing a Differential Input Signal and a Single-Ended Input SignalGain 1+VO V I1+2x 150k WR I1ǒV V Ǔ(6)Gain 2+VO V I2+2x 150k WR I2ǒV V Ǔ(7)C I2+1ǒ2p R I2f c2Ǔ(8)TPA2010D1SLOS417C–OCTOBER 2003–REVISED SEPTEMBER 2007If summing a ring tone and a phone signal,set the ring-tone gain to Gain 2=2V/V,and the phone gain to gain 1=0.1V/V.The resistor values would be...R I1=3M Ω,and =R I2=150k Ω.Figure 30.Application Schematic With TPA2010D1Summing Two Differential InputsFigure 31shows how to sum a differential input signal and a single-ended input signal.Ground noise can couple IN+with this method.It is better to use differential inputs.The corner frequency of the single-ended input is set by C I2,shown in Equation 8.To assure that each input is balanced,the single-ended input must be driven by a low-impedance if the input is not in useIf summing a ring tone and a phone signal,the phone signal should use a differential input signal while the ringtone might be limited to a single-ended signal.Phone gain is set at gain 1=0.1V/V,and the ring-tone gain is set to gain 2=2V/V,the resistor values would be…R I1=3M Ω,and =R I2=150k Ω.The high pass corner frequency of the single-ended input is set by C I2.If the desired corner frequency is less than 20Hz...12Submit Documentation FeedbackCopyright ©2003–2007,Texas Instruments IncorporatedProduct Folder Link(s):TPA2010D1CI2u1ǒ2p 150k W 20Hz Ǔ(9)CI2u 53nF(10)R Summing Two Single-Ended Input SignalsGain 1+VO V I1+2x 150k WR I1ǒV V Ǔ(11)Gain 2+VO V I2+2x 150k WR I2ǒV V Ǔ(12)C I1+1ǒ2p R I1fc1Ǔ(13)C I2+1ǒ2p R I2fc2Ǔ(14)C P +C I1)C I2(15)R P+R I1RI2ǒR I1)R I2Ǔ(16)TPA2010D1SLOS417C–OCTOBER 2003–REVISED SEPTEMBER 2007Figure 31.Application Schematic With TPA2010D1Summing Differential Input and Single-Ended InputSignals Four resistors and three capacitors are needed for summing single-ended input signals.The gain and corner frequencies (f c1and f c2)for each input source can be set independently (see Equation 11through Equation 14,and Figure 32).Resistor,R P ,and capacitor,C P ,are needed on the IN+the IN–single-ended inputs must be driven by low impedance sources even if one of the inputs is not outputting an ac signal.Copyright ©2003–2007,Texas Instruments Incorporated Submit Documentation Feedback13Product Folder Link(s):TPA2010D1BOARD LAYOUTCopperTrace WidthSolder Mask Thickness SolderPad WidthSolder MaskOpeningCopper TraceThicknessTPA2010D1SLOS417C–OCTOBER2003–REVISED SEPTEMBER2007Figure32.Application Schematic With TPA2010D1Summing Two Single-Ended InputsIn making the pad size for the WCSP balls,it is recommended that the layout use nonsolder mask defined (NSMD)land.With this method,the solder mask opening is made larger than the desired land area,and the opening size is defined by the copper pad width.Figure33and Table2show the appropriate diameters for a WCSP layout.The TPA2010D1evaluation in the next section as a layout example.nd Pattern Dimensions14Submit Documentation Feedback Copyright©2003–2007,Texas Instruments IncorporatedProduct Folder Link(s):TPA2010D1Component Location Trace WidthTPA2010D1SLOS417C–OCTOBER2003–REVISED SEPTEMBER2007 nd Pattern DimensionsSOLDER PAD SOLDER MASK COPPER STENCIL STENCIL COPPER PADDEFINITIONS OPENING THICKNESS OPENING THICKNESS Nonsolder mask275μm375μm1oz max(32μm)275μm x275μm Sq.125μm thick defined(NSMD)(+0.0,–25μm)(+0.0,–25μm)(rounded corners)NOTES:1.Circuit traces from NSMD defined PWB lands should be75μm to100μm wide in the exposed area insidethe solder mask opening.Wider trace widths reduce device stand off and impact reliability.2.Recommend solder paste is Type3or Type4.3.Best reilability results are achieved when the PWB laminate glass transition temperature is above theoperating the range of the intended application.4.For a PWB using a Ni/Au surface finish,the gold thickness should be less0.5μm to avoid a reduction inthermal fatigue performance.5.Solder mask thickness should be less than20μm on top of the copper circuit pattern.6.Best solder stencil preformance is achieved using laser cut stencils with electro e of chemicallyetched stencils results in inferior solder paste volume control.7.Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentionalcomponent movement due to solder wetting forces.Place all the external components very close to the TPA2010D1.The input resistors need to be very close to the TPA2010D1input pins so noise does not couple on the high impedance nodes between the input resistors and the input amplifier of the TPA2010D1.Placing the decoupling capacitor,CS,close to the TPA2010D1is important for the efficiency of the class-D amplifier.Any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency.Recommended trace width at the solder balls is75μm to100μm to prevent solder wicking onto wider PCB traces.Figure34shows the layout of the TPA2010D1evaluation module(EVM).For high current pins(V DD,GND V O+,and V O–)of the TPA2010D1,use100-μm trace widths at the solder balls and at least500-μm PCB traces to ensure proper performance and output power for the device.For input pins(IN–,IN+,and SHUTDOWN)of the TPA2010D1,use75-μm to100-μm trace widths at the solder balls.IN–and IN+pins need to run side-by-side to maximize common-mode noise cancellation.Placing input resistors,R IN,as close to the TPA2010D1as possible is recommended.Copyright©2003–2007,Texas Instruments Incorporated Submit Documentation Feedback15Product Folder Link(s):TPA2010D1375 m m(+0, -25 m m)275 m m(+0, -25 m m)Circular Solder Mask Opening75 m m100 m m100 m m100 m m100 m m100 m m75 m m75 m mEFFICIENCY AND THERMAL INFORMATIONq JA +1Derating Factor +10.0078+128.2°C ńW(17)T A Max +T J Max *q JA P Dmax +150*128.2(0.4)+98.72°C (18)ELIMINATING THE OUTPUT FILTER WITH THE TPA2010D1TPA2010D1SLOS417C–OCTOBER 2003–REVISED SEPTEMBER 2007Figure 34.Close Up of TPA2010D1Land Pattern From TPA2010D1EVMThe maximum ambient temperature depends on the heat-sinking ability of the PCB system.The derating factor for the YEF and YEZ packages are shown in the dissipation rating table.Converting this to θJA :Given θJA of 128.2°C/W,the maximum allowable junction temperature of 150°C,and the maximum internal dissipation of 0.4W (2.25W,4-Ωload,5-V supply,from Figure 3),the maximum ambient temperature can be calculated with the following equation.Equation 18shows that the calculated maximum ambient temperature is 98.72°C at maximum power dissipationand 4-Ωa load,see Figure 3.The TPA2010D1is designed with thermal protection that turns the device off when the junction 165°C ~190°C to prevent damage to the IC.Also,using speakers more resistive than 4-Ωdramatically increases the thermal performance by reducing the output current and increasing the efficiency of the amplifier.This section focuses on why the user can eliminate the output filter with the TPA2010D1.16Submit Documentation FeedbackCopyright ©2003–2007,Texas Instruments IncorporatedProduct Folder Link(s):TPA2010D1。
化工热力学--纯流体的容量性质第 --第三章普遍化关联式和偏心因子3.6-1
3-6 Generalized Correlations and the Acentric Factor…....introduction
Such generalized correlations represent a great improvement over the ideal-gas law. The basic presumption ( 假想 ) is that the compressibility factor (and certain other thermodynamic properties) of any gas is determined by its reduced temperature and pressure.
the vapor pressure of a material
approximately linear in ( 与…成线性关
系 ) the reciprocal of absolute
temperature,
we may write
log10
P sat r
a
b Tr
Where
P sat r
is
1 Tr
Thus a is the negative slope of the reducedvapor pressure curve when log10Prsat vs. 1/Tr
is represented by a straight line.
3-6 ……………………………………………………… Acentric Factor
Z
1
BP RT
1
BPc RTc
Pr Tr
负泊松比结构研究进展
负泊松比结构研究进展摘要:在我们日常生活中,所遇见的材料大部分为正泊松比材料,即材料在拉伸时横向收缩,压缩时横向膨胀。
而负泊松比材料恰恰与此相反,具体表现为材料在拉伸时纵向膨胀,压缩时纵向收缩。
这种特性使得负泊松比材料在很多领域的应用中优于传统材料,也正因为这个原因,负泊松比材料成为热门的研究领域,例如纺织工业、航空航海航天、国防军事、生物医疗等。
研究表明,负泊松比效应通常是由于材料内部的结构(几何设置)和它在承受应力时所经历的变形机制之间的合作效应而产生的。
本文主要介绍了几种常见的负泊松比结构,例如重入凹角结构、手性/反手性结构、旋转刚体结构,希望能为负泊松比材料的发展研究添砖加瓦。
关键词:负泊松比;结构;变形机制;介绍1 泊松比的概念泊松比,即结构垂直于荷载方向的应变与荷载方向应变的比值,是一个无量纲常数,也是材料的一个基本属性。
泊松比的概念最先由法国科学家Simeon-Denis Poisson (1781~1840)提出,并以他的名字命名,具体表达式如下:(1)其中,ν表示泊松比,表示垂直于加载方向的应变,表示加载方向的应变。
2 负泊松比结构的种类即使材料本身也没有负泊松比行为,但通过设计的结构,我们可以得到负泊松比。
一些结构已被证明表现出辅助性行为,在过去的几十年里,机械超材料的研究进展迅速。
目前发现的负泊松比结构中,常见的有重入凹角结构、手性/反手性结构、旋转刚体结构等。
重入指的是“向内”或具有负角度(角度大于180°)的结构,重入凹角结构一般是由斜肋和连接的链铰组成的桁架结构构成的。
重入凹角结构主要包括重入四边形结构、曲线重入四边形结构、重入六边形结构等。
重入凹角结构的产生机理是沿着水平方向轴向拉伸结构时,斜肋将向水平方向旋转,这导致了结构的横向膨胀,从而导致整体结构负泊松比的产生。
重入凹角结构设计最开始由Lakes[1]等于1987年提出,随后人们按照他的思路设计出更多的重入凹角结构,例如Shen[2]等于2014年利用3D打印技术打印出一系列简单几何形状结构。
科技英语补充材料
Additional useful expressionsflashover 闪络, 飞弧,跳火line voltage 线[间]电压overhead ground wire 避雷线,架空线路impulse wave 冲击波surge voltage 冲击电压wave front 波阵面,波前,冲击波头corona loss 电晕损失line insulator 线路绝缘子nominal value 标称值lightning arrester 避雷针,避雷器,避雷装置incoming line 进线spark gap 火花隙,火花放电器,避雷器insulation Co-ordination 绝缘配合Arcing Horn 角形避雷器sparkover voltage 跳火电压,火花放电电压de-energization 断开,去能,失励applied voltage 外加电压negative polarity 负极性impulse withstand level 耐冲击水平overhead shielding wire 架空屏蔽线steep-front wave 陡前沿波,前陡波,雷电波gap length 气隙长度gap adjustment 间隙调整non-linear-resistor-type arrester 非线性电阻器型避雷器BIL 1. (basic impulse level) 基本脉冲电平 2. (basic impulse insulation level) 冲击绝缘标准,标准冲击绝缘 3. (basic insulation level) 绝缘基本冲击耐压水平power-flow 功率潮流;电力潮流follow current 跟踪电流;继(电)流;残余电流breakdown 击穿,导通,开启构词法1. –ility 性adaptability 适应性capability 能力,本领compatibility 形容性,一致性compressibility 可压缩性2. –meter 计,表,仪voltmeter 电压表,伏特计photometer 光度计spectrometer 分光仪interferometer 干涉仪3. –fold 加上数词,表示“~倍的”、“~重的”。
ACT8846_DS_PrA_3JUL12_P
I2C Serial Interface Interrupt Controller
SYSTEM MANAGEMENT
Reset Interface and Sequencing Controller
Innovative PowerTM Active-Semi Confidential―Do Not Copy or Distribute
ActivePMUTM is a trademarks of Active-Semi. I2CTM is a trademark of NXP.
-1-
Copyright © 2012 Active-Semi, Inc.
Power on Reset Soft / Hard Reset Watchdog Supervision Multiple Sleep Modes
Thermal Management Subsystem
APPLICATIONS
Tablet PC Mobile Internet Devices (MID) E-books Personal Navigation Devices Smart Phones
®
ACT8846
Pr A, 3-Jul-12
TABLE OF CONTENTS
General Information ............................................................................................................................
三相电源监测传感器系列产品说明书
2C D C 251 054 F 0t 08ᕅ ᕄ ᕃᕉᕇᕆ ᕈ ᕊCM-MPN.522C D C 251055 F 0t 08ᕅ ᕄ ᕃᕉᕇᕆ ᕈ ᕊCM-MPN.622C D C 251 056 F 0t08ᕅ ᕄ ᕃᕉᕇᕆ ᕈ ᕊCM-MPN.72Multifunctional three-phase monitoring relaysCM-MPN.52, CM-MPN.62 and CM-MPN.72Data sheetApplicationThe CM-MPN.x2 are multifunctional monitoring relays for three-phase mains. They monitor the phase parameters phase sequence, phase failure, over- and undervoltage and phase unbalance.The threshold values for over- and undervoltage and phase unbalance are adjustable.Order dataOrder data - AccessoriesFeaturesMonitoring of three-phase mains for phase sequence (can be switched off), phase failure, over- andu ndervoltage as well as phase unbalance Automatic phase sequence correction configurableThreshold values for phase unbalance, over- and undervoltage are adjustable as absolute values Tripping delay can be adjusted or switched off by means of a logarithmic scale ON-delayed or OFF-delayed tripping delay selectable Powered by the measuring circuit True RMS measuring principle1x2 or 2x1 c/o (SPDT) contact configurable 3 LEDs for status indicationApprovalsA UL 508, CAN/CSA C22.2 No.14(only CM-MPN.52 und CM-MPN.62)C GLD GOST K CB scheme ECCCMarksa CE bC-TickR/T: yellow LED - relay status, timingF1: red LED - fault message F2: red LED - fault messageAdjustment of the trippingd elay t V Adjustment of the thresholdvalue for overvoltage6 Adjustment of the threshold value for undervoltage7 Adjustment of the threshold value for phase unbalance 8 Function selection(see DIP switch functions) / Marker labelOperating modeConfiguration of the devices is made by means of setting elements accessible on the front of the unit and signalling is made by means of front-face LEDs.Adjustment potentiometerThreshold valuesBy means of three separate potentiometers with direct reading scales, the threshold values for over- and undervoltage as well as for phase unbalance can be a djusted within the measuring range.Tripping delay t VThe tripping delay t V can be adjusted within a range of 0.1-30 s by means of a potentiometer with logaritmic scale. By turning to the left stop, the tripping delay can be switched off.DIP switches2C D C 252 041 F 0b 08LEDs1) Possible misadjustments of the front-face operating controls:Overlapping of the threshold values: An overlapping of the threshold values is given, if the threshold value foro vervoltage is set to a smaller value than the threshold value for u ndervoltage.DIP switch 3 = OFF and DIP switch 4 = ON: Automatic phase sequence c orrection is activated and selected operating mode is 1x2 c/o (SPDT) contactsDIP switch 2 and 4 = ON: Phase sequence detection is deactivated and the automatic phase sequence correction is activedFunction diagram legendG Control supply voltage not applied / Output contact open / LED off B Control supply voltage applied / Output contact closed / LED glowingPhase sequence and phase failure monitoringApplying control supply voltage begins the fixed start-up delay t S . When t S is complete and all phases are present with correct voltage, the output relays energize and the yellow LED R/T glows. Phase sequence monitoringIf phase sequence monitoring is activated, the output relays de- e nergize as soon as a phase sequence error occurs. The fault is displayed by alternated flashing of the LEDs F1 and F2. The output relays re- energize automatically as soon as the phase sequence is correct again. Phase failure monitoringThe output relays de-energize instantaneous if a phase failure o ccurs. The fault is indicated by lightning of LED F1 and flashing of LED F2. The output relays re-energize automatically as soon as the voltage returns to the tolerance range.25-2625-28L1, L2, L315-1615-182C D C 252 094 F 0207F1: red LED F2: red LED R/T: yellow LEDMeasuring valuet s = start-up delay fixed 200 msFunction descriptions/diagramsOver- and undervoltage monitoring 1x2 c/o (SPDT) contactsjApplying control supply voltage begins the fixed start-up delay t S . When t S is complete and all phases are present with correct voltage and with correct phase sequence, the output relays energize and the yellow LED R/T glows.Type of tripping delay = ON-delay AIf the voltage to be monitored exceeds or falls below the set threshold value, the output relays de-energize after the set tripping delay t V is complete. The LED R/T flashes during timing and turns off as soon as the output relays de-energize.The output relays re-energize automatically as soon as the voltage returns to the tolerance range, taking into account a fixed hysteresis of 5 %. The LED R/T glows.L1, L2, L315-1615-18> U > U - 5 %< U + 5 %< U25-2625-282C D C 252 090 F 0207F1: red LED F2: red LED R/T: yellow LEDMeasuring valuet s = start-up delay fixed 200 ms t v = adjustable tripping delayType of tripping delay = OFF-delay BIf the voltage to be monitored exceeds or falls below the set threshold value, the output relays de-energize instantaneously and the LED R/T turns off.As soon as the voltage returns to the t olerance range, taking into account a fixed hysteresis of 5 %, the output relays re-energize a utomatically after the set tripping delay t V is complete. The LED R/T flashes d uring timing and turns steady when timing is c omplete.25-2625-28L1, L2, L315-1615-18> U> U - 5 %< U + 5 %< U2C D C 252 091 F 0207F1: red LED F2: red LED R/T: yellow LEDMeasuring valuet s = start-up delay fixed 200 ms t v = adjustable tripping delayOver- and undervoltage monitoring 2x1 c/o (SPDT) contactiApplying control supply voltage begins the fixed start-up delay t S . When t S is complete and all phases are present with correct v oltage and with correct phase sequence, the output relays energize. The yellow LED R/T glows as long as at least one output relay is e nergized.Type of tripping delay = ON-delay AIf the voltage to be monitored exceeds or falls below the set threshold value, output relay R1 (overvoltage) or output relay R2 (undervoltage) de-energizes after the set tripping delay t V is c omplete. The LED R/T flashes during timing.The corresponding output relay re-energizes automatically as soon as the voltage returns to the tolerance range, taking into a ccount a fixed hysteresis of 5 %.L1, L2, L315-1615-1825-2625-28> U> U - 5 %< U + 5 %< U2C D C 252 006 F 0207F1: red LED F2: red LED R/T: yellow LEDMeasuring valuet s = start-up delay fixed 200 ms t v = adjustable tripping delayType of tripping delay = OFF-delay BIf the voltage to be monitored exceeds or falls below the set threshold value, output relay R1 (overvoltage) or output relay R2 (undervoltage) de-energizes instantaneously.As soon as the voltage returns to the tolerance range, taking into a ccount a fixed hysteresis of 5 %, the corresponding output relay re-energizes automatically after the set tripping delay t V is complete. The LED R/T flashes during timing.L1, L2, L315-1615-1825-2625-28> U > U - 5 %< U + 5 %< U2C D C 252 007 F 0207F1: red LED F2: red LED R/T: yellow LEDMeasuring valuet s = start-up delay fixed 200 ms t v = adjustable tripping delayPhase unbalance monitoringApplying control supply voltage begins the fixed start-up delay t S . When t S is complete and all phases are present with correct voltage and with correct phase sequence, the output relays energize and the yellow LED R/T glows.Type of tripping delay = ON-delay AIf the voltage to be monitored exceeds or falls below the set phase unbalance threshold value, the output relays de-energize after the set tripping delay t V is c omplete. The LED R/T flashes during timing and turns off as soon as the output relays de-energize.The output relays re-energize automatically as soon as the voltage r eturns to the tolerance range, taking into account a fixed hysteresis of 20 %. The LED R/T glows.L1, L2, L315-1615-1825-2625-282C D C 252 092 F 0207F1: red LED F2: red LED R/T: yellow LEDMeasuring valueUnbalanceUnbalance - HysteresisUnbalance + HysteresisUnbalancet s = start-up delay fixed 200 ms t v = adjustable tripping delayType of tripping delay = OFF-delay BIf the voltage to be monitored exceeds or falls below the set phase unbalance threshold value, the output relays de-energize i nstantaneously and the LED R/T turns off.As soon as the voltage r eturns to the t olerance range, taking into account a fixed hysteresis of 20 %, the output relays re-energize automatically a fter the set tripping delay t V is c omplete. The LED R/T flashes d uring timing and turns steady when timing is c omplete.25-2625-28L1, L2, L315-1615-182C D C 252 093 F 0207F1: red LED F2: red LED R/T: yellow LEDMeasuring valueUnbalanceUnbalance - HysteresisUnbalance + HysteresisUnbalancet s = start-up delay fixed 200 ms t v = adjustable tripping delayAutomatic phase sequence correctionThis function can be selected only if phase sequence monitoring is activated k (DIP switch 3 = ON) and operating mode 2x1 c/o (SPDT) contact j is selected (DIP switch 2 = OFF).Applying control supply voltage begins the fixed start-up delay t S1. When t S1 is complete and all phases are present with correct voltage, output relay R1 energizes. Output relay R2 energizes when the fixed start-up delay t S2 is complete and all phases are present with correct phase sequence. Output relay R2 remainsde-energized if the phase sequence is incorrect.If the voltage to be monitored exceeds or falls below the set threshold values for phase unbalance, over- or undervoltage or if a phase failure occurs, output relay R1 de-energizes and the LEDs F1 and F2 indicate the fault.Output relay R2 is responsive only to a false phase sequence. In conjunction with a reversing contactor combination, this enables an automatic correction of the rotation direction. See circuit diagrams.L1, L2, L315-1615-1825-2625-282C D C 252 085 F 0207F1: red LED F2: red LED R/T: yellow LEDMeasuring valuet S1 = start-up delay of R1 fixed 250 ms t S2 = start-up delay of R2 fixed 200 ms2C D C 252 086 F 0b 072C D C 252 087 F 0b 07Control circuit diagram (K1 = CM-MPN.x2)Power circuit diagramConnection diagramL1L228261525L3L3151618262825L2L116182C D C 252 038 F 0b 08L1, L2, L3 Control supply voltage = measuring voltage 15-16/18 Output contacts -25-26/28 closed-circuit principleCM-MPN.52, CM-MPN.62, CM-MPN.72Data at T a = 25 °C and rated values, unless otherwise indicatedData at T a = 25 °C and rated values, unless otherwise indicated1)Closed-circuit principle: Output relay(s) de-energize(s) if measured value exceeds or falls below the adjusted threshold value1112Technical diagramsLoad limit curvesAC load (resistive)2C D C 252 194 F 0205DC load (resistive)2C D C 252 193F 0205Derating factor Fat inductive AC load2C D C 252 192 F 0205Switching current [A]S w i t c h i n g c y c l e s2C D C 252 148 F 0206Dimensionsin mm2C D C 252 032 F 000313Further documentationYou can find the documentation online at /lowvoltage R Control Products R Electronic Relays and ControlsDimensions - Accessoriesin mm2C D C 252 009 F 00102C D C 252 010 F 0010ADP .02 - Adapter for screw mountingMAR.02 - Marker label2C D C 252 009 F 0010COV .02 - Sealable transparent coverABB STOTZ-KONTAKT GmbHP. O. Box 10 16 8069006 Heidelberg, Germany Phone: +49 (0) 6221 7 01-0Fax: +49 (0) 6221 7 01-13 25E-mail:*****************.comYou can find the address of your local sales organisation on theABB home page/contacts-> Low Voltage Products and Systems Contact usNote:We reserve the right to make technical changes or modify the contents of this document without prior notice. With regard to purchase orders, the agreed particulars shall prevail. ABB AG does not accept any responsibility whatsoever for potential errors or possible lack of information in this document.We reserve all rights in this document and in the subject matter and illustrations contained therein. Any reproduction, disclosure to third parties or utilization of its contents – in whole or in parts – is forbidden without prior written consent of ABB AG. Copyright© 2010 ABBAll rights reserved D o c u m e n t n u m b e r . 2 C D C 1 1 2 1 2 8 D 0 2 0 1 ( 0 7 / 1 0 )。
ADC10154CIWM资料
ADC10154/ADC1015810-Bit Plus Sign 4µs ADCs with 4-or 8-Channel MUX,Track/Hold and ReferenceGeneral DescriptionThe ADC10154and ADC10158are CMOS 10-bit plus sign successive approximation A/D converters with versatile ana-log input multiplexers,track/hold function and a 2.5V band-gap reference.The 4-channel or 8-channel multiplex-ers can be software configured for single-ended,differential or pseudo-differential modes of operation.The input track/hold is implemented using a capacitive array and sampled-data comparator.Resolution can be programmed to be 8-bit,8-bit plus sign,10-bit or 10-bit plus sign.Lower-resolution conversions can be performed faster.The variable resolution output data word is read in two bytes,and can be formatted left justified or right justified,high byte first.Applicationsn Process control n Instrumentation n Test equipmentFeaturesn 4-or 8-channel configurable multiplexer n Analog input track/hold functionn 0V to 5V analog input range with single +5V power supplyn −5V to +5V analog input voltage range with ±5V suppliesn Fully tested in unipolar (single +5V supply)and bipolar (dual ±5V supplies)operationn Programmable resolution/speed and output data format n Ratiometric or Absolute voltage reference operation n No zero or full scale adjustment required n No missing codes over temperature n Easy microprocessor interfaceKey Specificationsn Resolution10-bit plus sign n Integral linearity error±1LSB (max)n Unipolar power dissipation33mW (max)n Conversion time (10-bit +sign) 4.4µs (max)n Conversion time (8-bit)3.2µs (max)n Sampling rate (10-bit +sign)166kHz n Sampling rate (8-bit)207kHznBand-gap reference2.5V ±2.0%(max)ADC10158Simplified Block DiagramTRI-STATE ®is a registered trademark of National Semiconductor Corporation.DS011225-1November 1999ADC10154/ADC1015810-Bit Plus Sign 4µs ADCs with 4-or 8-Channel MUX,Track/Hold and Reference©1999National Semiconductor Corporation Connection DiagramsPin DescriptionsAV +This is the positive analog supply.This pin should be bypassed with a 0.1µF ceramic ca-pacitor and a 10µF tantalum capacitor to the system analog ground.DV +This is the positive digital supply.This supply pin also needs to be bypassed with 0.1µF ce-ramic and 10µF tantalum capacitors to the system digital ground.AV +and DV +should be bypassed separately and tied to same power supply.DGND This is the digital ground.All logic levels are re-ferred to this ground.V −This is the negative analog supply.For unipolar operation this pin may be tied to the system analog ground or to a negative supply source.It should not go above DGND by more than 50mV.When bipolar operation is required,the voltage on this pin will limit the analog input’s negative voltage level.In bipolar operation this supply pin needs to be bypassed with 0.1µF ceramic and 10µF tantalum capacitors to the system analog ground.V REF +,V REF −These are the positive and negative reference inputs.The voltage difference between V REF +and V REF −will set the analog input voltage span.V REF OutThis is the internal band-gap voltage reference output.For proper operation of the voltage ref-erence,this pin needs to be bypassed with a 330µF tantalum or electrolytic capacitor.CSThis is the chip select input.When a logic low is applied to this pin the WR and RD pins are enabled.RDThis is the read control input.When a logic low is applied to this pin the digital outputs are en-abled and the INT output is reset high.WRThis is the write control input.The rising edge of the signal applied to this pin selects the mul-tiplexer channel and initiates a conversion.INTThis is the interrupt output.A logic low at this output indicates the completion of a conver-sion.CLK This is the clock input.The clock frequency di-rectly controls the duration of the conversiontime (for example,in the 10-bit bipolar mode t C =22/f CLK )and the acquisition time (t A =6/f CLK ).DB0(MA0)–DB7(L/R)These are the digital data inputs/outputs.DB0is the least significant bit of the digital outputword;DB7is the most significant bit in the digi-tal output word (see the Output Data Configu-ration table).MA0through MA4are the digital inputs for the multiplexer channel selection (see the Multiplexer Addressing tables).U/S (Unsigned/Signed),8/10,(8/10-bit resolution)and L/R (Left/Right justification)are the digital input bits that set the A/D’s output word format and resolution (see the Output Data Configura-tion table).The conversion time is modified by the chosen resolution (see Electrical AC Char-acteristics table).The lower the resolution,the faster the conversion will be.CH0–CH7These are the analog input multiplexer chan-nels.They can be configured as single-ended inputs,differential input pairs,or pseudo-differential inputs (see the Multiplexer Addressing tables for the input polarity assignments).Dual-in-Line and SO PackagesDS011225-2Top ViewOrder Number ADC10154NS Package Number M24BDual-in-Line and SO Packages 2Absolute Maximum Ratings(Notes1,3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Positive Supply Voltage(V+=AV+=DV+) 6.5V Negative Supply Voltage(V−)−6.5V Total Supply Voltage(V+−V−)13V Total Reference Voltage(V REF+−V REF−) 6.6V Voltage at Inputs andOutputs V−−0.3V to V++0.3V Input Current at Any Pin(Note4)±5mA Package Input Current(Note4)±20mA Package Dissipation atT A=25˚C(Note5)500mW ESD Susceptibility(Note6)2000V Soldering InformationN Packages(10Sec)260˚C J Packages(10Sec)300˚C SO Package(Note7):Vapor Phase(60Sec)215˚C Infrared(15Sec)220˚C Storage TemperatureCeramic DIP PackagesPlastic DIP and SO Packages−65˚C to+150˚C−40˚C to+150˚C Operating Ratings(Notes2,3)Temperature Range T MIN≤T A≤T MAX ADC10154CIWM,ADC10158CIN,ADC10158CIWM−40˚C≤T A≤+85˚C Positive SupplyVoltage(V+=AV+=DV+) 4.5V DC to5.5V DC Unipolar NegativeSupply Voltage(V−)DGND Bipolar NegativeSupply Voltage(V−)−4.5V to−5.5V V+−V−11V V REF+AV++0.05V DC to V−−0.05V DC V REF−AV++0.05V DC to V−−0.05V DC V REF(V REF+−V REF−)0.5V DC to V+Electrical CharacteristicsThe following specifications apply for V+=AV+=DV+=+5.0V DC,V REF+=5.000V DC,V REF−=GND,V−=GND for unipo-lar operation or V−=−5.0V DC for bipolar operation,and f CLK=5.0MHz unless otherwise specified.Boldface limits apply for T A=T J=T MIN to T MAX;all other limits T A=T J=25˚C.(Notes8,9,12)Symbol Parameter Conditions Typical(Note10)CIN and CIWM Units(Limit) SuffixesLimits(Note11)UNIPOLAR CONVERTER AND MULTIPLEXER STATIC CHARACTERISTICSResolution10+Sign BitsUnipolar Integral V REF+=2.5V±0.5LSBLinearity Error V REF+=5.0V±1LSB(Max)Unipolar Full-Scale Error V REF+=2.5V±0.5LSBV REF+=5.0V±1.5LSB(Max) Unipolar Offset Error V REF+=2.5V±1LSBV REF+=5.0V±2LSB(Max) Unipolar Total Unadjusted V REF+=2.5V±1.5LSBError(Note13)V REF+=5.0V±2.5LSB(Max)Unipolar Power Supply V+=+5V±10%Sensitivity V REF+=4.5VOffset Error±0.25±1LSB(Max)Full-Scale Error±0.25±1LSB(Max) Integral Linearity Error±0.25LSBBIPOLAR CONVERTER AND MULTIPLEXER STATIC CHARACTERISTICSResolution10+Sign BitsBipolar Integral V REF+=5.0V±1LSB(Max)Linearity ErrorBipolar Full-Scale Error V REF+=5.0V±1.25LSB(Max)ADC10154/ADC101583Electrical Characteristics(Continued)The following specifications apply for V +=AV +=DV +=+5.0V DC ,V REF +=5.000V DC ,V REF −=GND,V −=GND for unipo-lar operation or V −=−5.0V DC for bipolar operation,and f CLK =5.0MHz unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =25˚C.(Notes 8,9,12)SymbolParameterConditionsTypical (Note 10)CIN and CIWMUnits (Limit)Suffixes Limits (Note 11)BIPOLAR CONVERTER AND MULTIPLEXER STATIC CHARACTERISTICSBipolar Negative Full-Scale V REF +=5.0VError with Positive-Full ±1.25LSB (Max)Scale Adjusted Bipolar Offset Error V REF +=5.0V ±2.5LSB (Max)Bipolar Total Unadjusted V REF +=5.0V±3LSB (Max)Error (Note 13)Bipolar Power Supply SensitivityOffset Error V +=+5V ±10%±0.5±2.5LSB (Max)Full-Scale Error V REF +=4.5V ±0.5±1.5LSB (Max)Integral Linearity Error±0.25LSB Offset Error V −=−5V ±10%±0.25±0.75LSB (Max)Full-Scale Error V REF +=4.5V±0.25±0.75LSB (Max)Integral Linearity Error±0.25LSBUNIPOLAR AND BIPOLAR CONVERTER AND MULTIPLEXER STATIC CHARACTERISTICSMissing Codes 0DC Common Mode V IN +=V IN −Error (Note 14)=V IN whereBipolar +5.0V ≥V IN ≥−5.0V ±0.25±0.75LSB (Max)Unipolar+5.0V ≥V IN ≥0V ±0.25±0.5LSB (Max)R REF Reference Input Resistance 7 4.5k Ω(Max)9.5k Ω(Max)C REF Reference Input Capacitance 70pF V AI Analog Input Voltage (V ++0.05)V (Max)(V −−0.05)V (Min)C AIAnalog Input Capacitance 30pF Off Channel Leakage On Channel =5V−400−1000nA (Max)Current Off Channel =0V (Note 15)On Channel =0V 4001000nA (Max)Off Channel =5VElectrical CharacteristicsThe following specifications apply for V +=AV +=DV +=+5.0V DC ,V REF +=5.000V DC ,V REF −=GND,V −=GND for unipolar operation or V −=−5.0V DC for bipolar operation,and f CLK =5.0MHz unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =25˚C.(Notes 8,9,12)SymbolParameterConditionsTypical Limits (Note 11)Units (Limit)(Note 10)DYNAMIC CONVERTER AND MULTIPLEXER CHARACTERISTICS S/(N+D)Unipolar Signal-to-Noise+f IN =10kHz,V IN =4.85V p–p60dB Distortion Ratio f IN =150kHz,V IN =4.85V p-p 58dB S/(N+D)Bipolar Signal-to-Noise+f IN =10kHz,V IN =±4.85V60dB Distortion Ratiof IN =150kHz,V IN =±4.85V58dBA D C 10154/A D C 10158 4Electrical Characteristics(Continued)The following specifications apply for V +=AV +=DV +=+5.0V DC ,V REF +=5.000V DC ,V REF −=GND,V −=GND for unipolar operation or V −=−5.0V DC for bipolar operation,and f CLK =5.0MHz unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =25˚C.(Notes 8,9,12)SymbolParameterConditionsTypical Limits (Note 11)Units (Limit)(Note 10)DYNAMIC CONVERTER AND MULTIPLEXER CHARACTERISTICS−3dB Unipolar Full V IN =4.85V p–p200kHz Power Bandwidth −3dB Bipolar Full V IN =±4.85V200kHzPower BandwidthREFERENCE CHARACTERISTICS (Unipolar Operation V −=GND Only)VREFOut Reference Output Voltage 2.5±1% 2.5±2%V (Max)∆V REF /∆t VREFOut Temperature Coefficient 40ppm/˚C ∆V REF /∆I LLoad Regulation Sourcing 0mA ≤I L ≤+4mA 0.0030.1%/mA (Max)Sinking0mA ≥I L ≥−1mA 0.20.6%/mA (Max)Line Regulation4.5V ≤V +≤5.5V 0.56mV (Max)I SCShort Circuit Current VREFOut =0V1425mA (Max)∆V REF /∆t Long-Term Stability 200ppm/1kHrt SU Start-Up TimeC L =330µF 20msDIGITAL AND DC CHARACTERISTICSV IN(1)Logical “1”Input Voltage V +=5.5V2.0V (Min)V IN(0)Logical “0”Input Voltage V +=4.5V 0.8V (Max)I IN(1)Logical “1”Input Current V IN =5.0V 0.005 2.5µA (Max)I IN(0)Logical “0”Input Current V IN =0V −0.005−2.5µA (Max)V OUT(1)Logical “1”Output VoltageV +=4.5V:I OUT =−360µA 2.4V (Min)I OUT =−10µA4.25V (Min)V OUT(0)Logical “0”Output Voltage V +=4.5V 0.4V (Max)I OUT =1.6mA I OUT TRI-STATE ®Output Current V OUT =0V−0.01−3µA (Max)V OUT =5V 0.013µA (Max)+I SC Output Short Circuit Source Current V OUT =0V −40−10mA (Min)−I SC Output Short Circuit V OUT =DV +3010mA (Min)Sink CurrentDI+Digital Supply Current CS =HIGH0.752mA (Max)CS =HIGH,f CLK =0Hz 0.15mA (Max)AI +Analog Supply Current CS =HIGH3 4.5mA (Max)CS =HIGH,f CLK =0Hz 3mA (Max)I−Negative Supply Current CS =HIGH3.54.5mA (Max)CS =HIGH,f CLK =0Hz 3.5mA (Max)I REFReference Input CurrentV REF +=5V0.71.1mA (Max)ADC10154/ADC101585Electrical CharacteristicsThe following specifications apply for V +=AV +=DV +=+5.0V DC ,V REF +=5.000V DC ,V REF −=GND,V −=GND for unipolar operation or V −=−5.0V DC for bipolar operation,and f CLK =5.0MHz unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =25˚C.(Note 16)SymbolParameterConditionsTypical Limits (Note 11)Units (Limit)(Note 10)AC CHARACTERISTICS f CLKClock Frequency 8 5.0MHz (Max)10kHz (Min)Clock Duty Cycle20%(Min)80%(Max)t CConversion 8-Bit Unipolar Mode161/f CLK Timef CLK=5.0MHz3.2µs (Max)8-Bit Bipolar Mode181/f CLK f CLK =5.0MHz3.6µs (Max)10-Bit Unipolar Mode201/f CLK f CLK =5.0MHz4.0µs (Max)10-Bit Bipolar Mode221/f CLK f CLK =5.0MHz4.4µs (Max)t A Acquisition Time61/f CLK f CLK =5.0MHz1.2µs t CR Delay between Falling Edge of 05ns (Min)CS and Falling Edge of RD t RC Delay betwee Rising Edge 05ns (Min)RD and Rising Edge of CS t CW Delay between Falling Edge 05ns (Min)of CS and Falling Edge of WR t WC Delay between Rising Edge 05ns (Min)of WR and Rising Edge of CS t RW Delay between Falling Edge 05ns (Min)of RD and Falling Edge of WR t W(WR)WR Pulse Width2550ns (Min)t WS WR High to CLK ÷2Low Set-Up Time 5ns (Max)t DS Data Set-Up Time 615ns (Max)t DH Data Hold Time 05ns (Max)t WR Delay from Rising Edge 05ns (Min)of WR to Rising Edge RD t ACC Access Time (Delay from Falling C L =100pF2545ns (Max)Edge of RD to Output Data Valid)t WI ,t RI Delay from Falling Edge C L =100pF2540ns (Max)of WR or RD to Reset of INT t INTL Delay from Falling Edge of CLK ÷2to Falling Edge of INT40ns t 1H ,t 0H TRI-STATE Control (Delay from C L =10pF,R L =1k Ω2035ns (Max)Rising Edge of RD to Hi-Z State)t RR Delay between Successive 2550ns (Min)RD Pulsest PDelay between Last Rising Edge of RD and the Next Falling 2050ns (Min)Edge of WRC IN Capacitance of Logic Inputs 5pF C OUTCapacitance of Logic Outputs5pFNote 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.A D C 10154/A D C 10158 6Electrical Characteristics(Continued)Note 2:Operating Ratings indicate conditions for which the device is functional,but do not guarantee specific performance limits.For guaranteed specifications and test conditions,see the Electrical Characteristics.The guaranteed specifications apply only for the test conditions listed.Some performance characteristics may de-grade when the device is not operated under the listed test conditions.Note 3:All voltages are measured with respect to GND,unless otherwise specified.Note 4:When the input voltage (V IN )at any pin exceeds the power supplies (V IN <V −or V IN >AV +or DV +),the current at that pin should be limited to 5mA.The 20mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5mA to four.Note 5:The maximum power dissipation must be derated at elevated temperatures and is dictated by T Jmax ,θJA and the ambient temperature,T A .The maximum allowable power dissipation at any temperature is P D =(T Jmax −T A )/θJA or the number given in the Absolute Maximum Ratings,whichever is lower.For this device,T Jmax =150˚C.The typical thermal resistance (θJA )of these parts when board mounted follow:ADC10154with BIN and CIN suffixes 65˚C/W,ADC10154with BIJ,CIJ and CMJ suffixes 49˚C/W,ADC10154with BIWM and CIWM suffixes 72˚C/W,ADC10158with BIN and CIN suffixes 59˚C/W,ADC10158with BIJ,CIJ,and CMJ suffixes 46˚C/W,ADC10158with BIWM and CIWM suffixes 68˚C/W.Note 6:Human body model,100pF capacitor discharged through a 1.5k Ωresistor.Note 7:See AN-450“Surface Mounting Methods and Their Effect on Product Reliability”or the section titled “Surface Mount”found in any post-1986National Semi-conductor Linear Data Book for other methods of soldering surface mount devices.Note 8:Two on-chip diodes are tied to each analog input as shown below.They will forward-conduct for analog input voltages one diode drop below V −supply or one diode drop greater than V +supply.Be careful during testing at low V +levels (4.5V),as high level analog inputs (5V)can cause an input diode to conduct,es-pecially at elevated temperatures,which will cause errors for analog inputs near full-scale.The specification allows 50mV forward bias of either diode;this means that as long as the analog V IN does not exceed the supply voltage by more than 50mV,the output code will be correct.Exceeding this range on an unselected chan-nel will corrupt the reading of a selected channel.This means that if AV +and DV +are minimum (4.5V DC )and V −is a maximum (−4.5V DC )full scale must be ≤±4.55V DC .Note 9:A diode exists between AV +and DV +as shown below.Note 10:Typicals are at T J =T A =25˚C and represent most likely parametric norm.Note 11:Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).Note 12:One LSB is referenced to 10bits of resolution.Note 13:Total unadjusted error includes offset,full-scale,linearity,multiplexer,and hold step errors.Note 14:For DC Common Mode Error the only specification that is measured is offset error.Note 15:Channel leakage current is measured after the channel selection.Note 16:All the timing specifications are tested at the TTL logic levels,V IL =0.8V for a falling edge and V IH =2.0V for a rising.DS011225-4DS011225-5To guarantee accuracy,it is required that the AV +and DV +be connected together to a power supply with separate bypass filter at each V +pin.ADC10154/ADC101587Electrical Characteristics(Continued)Ordering InformationIndustrial −40˚C ≤T A ≤85˚C Package ADC10154CIWM M24B ADC10158CIN N28B ADC10158CIWMM28BDS011225-6FIGURE 1.Transfer CharacteristicDS011225-7FIGURE 2.Simplified Error Curve vs Output CodeA D C 10154/A D C 10158 8Typical Converter Performance CharacteristicsTotal Positive SupplyCurrent(DI++AI+)vs TemperatureDS011225-27Total Positive PowerSupply Current(DI++AI+)vs Clock FrequencyDS011225-28Offset Errorvs TemperatureDS011225-29Offset Error vsReference VoltageDS011225-30Linearity Errorvs TemperatureDS011225-31Linearity Error vsReference VoltageDS011225-32Linearity Error vsClock FrequencyDS011225-33Spectral Response with50kHz Sine WaveDS011225-3410-Bit UnsignedSignal-to-Noise+THD Ratiovs Input Signal LevelDS011225-35ADC10154/ADC101589Typical Reference Performance CharacteristicsLeakage Current Test CircuitLoad RegulationDS011225-36Line Regulation (3Typical Parts)DS011225-37Output Drift vs Temperature (3Typical Parts)DS011225-38AvailableOutput Current vs Supply VoltageDS011225-39DS011225-10A D C 10154/A D C 10158 10TRI-STATE Test Circuits and WaveformsTiming DiagramsDS011225-11DS011225-12DS011225-13DS011225-14DS011225-15DIAGRAM 1.Starting a Conversion with New MUX Channel and Output ConfigurationADC10154/ADC1015811Timing Diagrams(Continued)DS011225-16DIAGRAM 2.Starting a Conversion without Changing the MUX Channel or Output ConfigurationDS011225-17DIAGRAM 3.Reading the Conversion ResultA D C 10154/A D C 10158 12Multiplexer Addressing and Output Data Configuration TablesTABLE1.ADC10154and ADC10158Output Data ConfigurationOutput Data Format Control Input Data Bus Output AssignmentResolution Data8/10U/S L/R DB7DB6DB5DB4DB3DB2DB1DB010-Bits+Sign Right-Justified L L L Sign Sign Sign Sign Sign Sign MSB9First Byte Read8765432LSB Second Byte Read10-Bits+Sign Left-Justified L L H Sign MSB987654First Byte Read32LSB L L L L L Second Byte Read10-Bits Right-Justified L H L L L L L L L MSB9First Byte Read8765432LSB Second Byte Read10-Bits Left-Justified L H H MSB9876543First Byte Read2LSB L L L L L L Second Byte Read8-Bits+Sign Right-Justified H L L Sign Sign Sign Sign Sign Sign Sign Sign First Byte ReadMSB765432LSB Second Byte Read8-Bits+Sign Left-Justified H L H Sign MSB765432First Byte ReadLSB L L L L L L L Second Byte Read8-Bits Right-Justified H H L L L L L L L L L First Byte ReadMSB765432LSB Second Byte Read8-Bits Left-Justified H H H MSB765432LSB First Byte ReadL L L L L L L L Second Byte ReadTABLE2.ADC10158Multiplexer AddressingMUX Address CS WR RD Channel Number MUXModeMA4MA3MA2MA1MA0CH0CH1CH2CH3CH4CH5CH6CH7V REF−X L L L L L H+−X L L L H L H−+X L L H L L H+−X L L H H L L H−+DifferentialX L H L L L H+−X L H L H L H−+X L H H L L H+−X L H H H L H−+L H L L L L H+−L H L L H L H+−L H L H L L H+−L H L H H L L H+−Single-EndedL H H L L L H+−L H H L H L H+−L H H H L L H+−L H H H H L H+−H H L L L L H+−H H L L H L H+−H H L H L L H+−H H L H H L L H+−Pseudo-DifferentialH H H L L L H+−H H H L H L H+−H H H H L L H+−X X X X X L L L Previous Channel ConfigurationADC10154/ADC1015813Multiplexer Addressing and Output Data Configuration Tables(Continued)TABLE 3.ADC10154Multiplexer AddressingMUX AddressCS WR RDChannel Number MUX Mode MA4MA3MA2MA1MA0CH0CH1CH2CH3V REF−X X L L L L H +−X X L L H L LH −+DifferentialX X L H L L H +−X X L H H L H −+X L H L L L H +−X L H L H L L H +−Single-EndedX L H H L L H +−X L H H H L H +−X H H L L L H +−X H H L H L L H +−Pseudo-DifferentialX H H H L L H +−XXXXXLL LPrevious Channel ConfigurationA D C 10154/A D C 10158 14Detailed Block DiagramD S 011225-18ADC10154/ADC10158151.0Functional DescriptionThe ADC10154and ADC10158use successive approxima-tion to digitize an analog input voltage.Additional logic has been incorporated in the devices to allow for the programma-bility of the resolution,conversion time and digital output for-mat.A capacitive array and a resistive ladder structure are used in the DAC portion of the A/D converters.The structure of the DAC allows a very simple switching scheme to provide a very versatile analog input multiplexer.Also,inherent in this structure is a sample/hold.A 2.5V CMOS band-gap ref-erence is also provided on the ADC10154and ADC10158.1.1DIGITAL INTERFACEThe ADC10154and ADC10158have eight digital outputs (DB0–DB8)and can be easily interfaced to an 8-bit data bus.Taking CS and WR low simultaneously will strobe the data word on the data-bus into the input latch.This word will be decoded to determine the multiplexer channel selection,the A/D conversion resolution and the output data format.The following table shows the input word data-bit assign-ment.DB0through DB4are assigned to the multiplexer address data bits zero through four (MA0–MA4).Tables 2,3describe the multiplexer address assignment.DB5selects unsigned or signed (U/S)operation.DB6selects 8-or 10-bit resolu-tion.DB7selects left or right justification of the output data.Refer to Table 1for the effect the Control Input Data has on the digital output word.The conversion process is started by the rising edge of WR,which sets the “start conversion”bit inside the ADC.If this bit is set,the converter will start acquiring the input voltage on the next falling edge of the internal CLK ÷2signal.The acqui-sition period is 3CLK ÷2periods,or 6CLK periods.Immedi-ately after the acquisition period the input signal is held and the actual conversion begins.The number of clocks required for a conversion is given in the following table:Conversion Type CLK ÷2CLK CyclesCycles (N)8-Bit 8168-Bit +Sign 91810-Bit 102010-Bit +Sign1122Since the CLK ÷2signal is internal to the ADC,it is initially impossible to know which falling edge of CLK corresponds to the falling edge of CLK ÷2.For the first conversion,the rising edge of WR should occur at least t WS ns before any falling edge of CLK.If this edge happens to be on the rising edge of CLK ÷2,this will add 2CLK cycles to the total conversion time.The phase of the CLK ÷2signal can be determined at the end of the first conversion,when INT goes low.INT al-ways goes low on the falling edge of the CLK ÷2signal.From the first falling edge of INT onward,every other falling edge of CLK will correspond to the falling edge of CLK ÷2.With the phase of CLK ÷2now known,the conversion time can be minimized by taking WR high at least t WS ns before the fall-ing edge of CLK ÷2.Upon completion of the conversion,INT goes low to signal the A/D conversion result is ready to be read.Taking CS and RD low will enable the digital output buffer and put byte 1of the conversion result on DB0through DB7.The falling edge of RD resets the INT output high.Taking CS and RD low a second time will put byte 2of the conversion result on DB7–DB0.Table 1defines the DB0–DB7assignment for dif-ferent Control Input Data.The second read does not have to be completed before a new conversion is started.Taking CS,WR and RD low simultaneously will start a con-version without changing the multiplexer channel assign-ment or output configuration and resolution.The timing dia-gram in Figure 3shows the sequence of events that implement this function.Refer to Diagrams 1,2,and 3in the Timing Diagrams section for the timing constraints that must be met.DS011225-44DS011225-19FIGURE 3.Starting a Conversion without Updating the Channel Configuration,Resolution,or Data FormatA D C 10154/A D C 10158 161.0Functional Description(Continued)Digital Interface Hints:•Reads and writes can be completely asynchronous to CLK.•In addition to the timing indicated in Diagrams1–3,CS can be tied low permanently or taken low for entire con-versions,eliminating all the CS guardbands(t CR,t RC, t CW,t WC).•If CS is used as shown in Diagrams1–-3,the CS guard-bands(t CR,t RC,t CW,t WC)between CS and the RD and WR signals can safely be ignored as long as the follow-ing two conditions are met:1)When initiating a write,CS and WR must be simulta-neously low for at least t W(WR)ns(see Diagram1).The “start”conversion”bit will be set on the rising edge of WR or CS,whichever is first.2)When reading data,understand that data will not be validuntil t ACC ns after both CS and RD go low.The output data will enter TRI-STATE t1H ns or t0H ns after either CS or RD goes high(see Diagrams2and3).1.2ARCHITECTUREBefore a conversion is started,during the analog input sam-pling period,the sampled data comparator is zeroed.As the comparator is being zeroed the channel assigned to be the positive input is connected to the A/D’s input capacitor.(See the Digital Interface section for a description of the assign-ment procedure.)This charges the input32C capacitor of the DAC to the positive analog input voltage.The switches shown in the DAC portion of the detailed block diagram are set for this zeroing/acquisition period.The voltage at the in-put and output of the comparator are at equilibrium at this point in time.When the conversion is started the comparator feedback switches are opened and the32C input capacitor is then switched to the assigned negative input voltage. When the comparator feedback switch opens a fixed amount of charge is trapped on the common plates of the capacitors. The voltage at the input of the comparator moves away from equilibrium when the32C capacitor is switched to the as-signed negative input voltage,causing the output of the com-parator to go high(“1”)or low(“0”).The SAR next goes through an algorithm,controlled by the output state of the comparator,that redistributes the charge on the capacitor ar-ray by switching the voltage on one side of the capacitors in the array.The objective of the SAR algorithm is to return the voltage at the input of the comparator as close as possible to equilibrium.The switch position information at the completion of the suc-cessive approximation routine is a direct representation ofthe digital output.This information is then manipulated by theDigital Output decoder to the programmed format.The refor-matted data is then available to be strobed onto the data bus(DB0–DB7)via the digital output buffers by taking CS andRD low.2.0Applications Information2.1MULTIPLEXER CONFIGURATIONThe design of these converters utilizes a sampled-data com-parator structure which allows a differential analog input tobe converted by the successive approximation routine.The actual voltage converted is always the difference be-tween an assigned“+”input terminal and a“−”input terminal.The polarity of each input terminal or pair of input terminalsbeing converted indicates which line the converter expectsto be the most positive.If the assigned“+”input is less thanthe“−”input the converter responds with an all zeros outputcode when configured for unsigned operation.When config-ured for signed operation the A/D responds with the appro-priate output digital code.A unique input multiplexing scheme has been utilized to pro-vide multiple analog channels.The input channels can besoftware configured into three modes:differential,single-ended,or pseudo-differential.Figure4shows thethree modes using the4-channel MUX of the ADC10154.The eight inputs of the ADC10158can also be configured inany of the three modes.The single-ended mode hasCH0–CH3assigned as the positive input with the negativeinput being the V REF−of the device.In the differential mode,the ADC10154channel inputs are grouped in pairs,CH0with CH1and CH2with CH3.The polarity assignment ofeach channel in the pair is interchangeable.Finally,in thepseudo-differential mode CH0–CH2are positive inputs re-ferred to CH3which is now a pseudo-ground.Thispseudo-ground input can be set to any potential within the in-put common-mode range of the converter.The analog signalconditioning required in transducer-based data acquisitionsystems is significantly simplified with this type of input flex-ibility.One converter package can now handleground-referred inputs and true differential inputs as well assignals referred to a specific voltage.The analog input voltages for each channel can range from50mV below V−(typically ground for unipolar operation or−5V for bipolar operation)to50mV above V+=DV+=AV+(typically5V)without degrading conversion accuracy.If thevoltage on an unselected channel exceeds these limits itmay corrupt the reading of the selected channel.ADC10154/ADC1015817。
MB96696管脚资料
z Source Clock Timers
Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer, 17-bit Sub clock timer)
z Hardware Watchdog Timer
Hardware watchdog timer is active after reset Window function of Watchdog Timer is used to select the lower window limit of the watchdog interval
FUJITSU SEMICONDUCTOR DATA SHEET
DS704-00011-0v01-E
16-bit Proprietary Microcontroller
CMOS
F MC-16FX MB96690 Series
MB96F696*
DESCRIPTION
MB96690 series is based on FUJITSU’s advanced 16FX architecture (16-bit with instruction pipeline for RISC-like performance). The CPU uses the same instruction set as the established 16LX series - thus allowing for easy migration of 16LX Software to the new 16FX products. 16FX improvements compared to the previous generation include significantly improved performance even at the same operation frequency, reduced power consumption and faster start-up time. For high processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 32MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction cycle time of 31.2ns going together with excellent EMI behavior. The emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows selecting suitable operation frequencies for peripheral resources independent of the CPU speed. *: These devices are under development and specification is preliminary. These products under development may change its specification without notice. Note: F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
NI ELVIS II系列产品规格说明说明书
Arbitrary Waveform Generator/Analog Output
Number of channels.........................2
DAC resolution................................16 bits
DNL.................................................±1 LSB
Maximum working voltage for analog inputs (signal + common mode) ................ ±11 V of AIGND
CMRR (DC to 60 Hz) ..................... 90 dB
Source..............................................AI<0..15>, ScopeCH0, ScopeCH1
Small signal bandwidth (–3 dB)......1.2 MHz
Input FIFO size................................4095 samples
Scanlist memory ..............................4095 entries
Data B signal stream, programmed I/O
TL431A TL431B 系列规格书推荐
Figure 1. Symbol
Reference (R) Cathode (K) 2.4 k 3.28 k 20 pF 7.2 k 150 4.0 k 10 k
Programmable Output Voltage to 36 V Voltage Reference Tolerance: ±0.4%, Typ @ 25°C (TL431B) Low Dynamic Output Impedance, 0.22 W Typical Sink Current Capability of 1.0 mA to 100 mA Equivalent Full−Range Temperature Coefficient of 50 ppm/°C Typical Temperature Compensated for Operation over Full Rated Operating Temperature Range Low Output Noise Voltage NCV/SCV Prefixes for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. This device contains latch−up protection and exceeds ±100 mA per JEDEC standard JESD78.
61毛细管流变仪 共138页
v
Measured pressure
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Pl
FULLY DEVELOPED
FLOW REGION
Pw
L
ENTRANCE LENGTH
Entrance pressure drop
+
2R Shear pressure drop
0
0
Z
L
small ram extruder
Pressure drop through a capillary/slit die
• Single point test (generates one number)
• Defined by standards (ISO1133)
• Simple • Cheap • Easy to use
MFI die (2.095mm diameter)
Melt Flow Indexer (MFI)
•Shear viscosity is only one part of Rheology.
•It is the dominant effect for pressure in extruders, injection moulding machines and dies.
Typical process shear rates
Capillary rheometry
Long die: shear
Short die: extension
3 Shear viscosity
• 完全发展区剪切应力的计算
2rL Pr2
Pr
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PR
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3 Shear viscosity
西门子QBE2x03-P...压力传感器使用说明书
A6V10432494_en--_dPressure SensorsQBE2003-P… QBE2103-P…for neutral and slightly aggressive liquids and gases• High-precision measuring• Measuring range 0 to 60 bar relative• Supply voltage AC 24 V / DC 12...33 V o r DC 7…33 V • DC 0 ...10 V or DC 4…20 mA output signal• Measurement unaffected by changes in temperature • High temperature stability• Connection: external thread G ½", inside thread M5• Maintenance free thanks to outstanding long-term stability • High overload resistance•Robust and compact construction1909P 012/6 UseThe pressure sensors are suitable for the measurement of relative pressure in HVAC plant, particularly in hydraulic and pneumatic systems using liquid or gaseous media (steam applications).Type summary*) These types do not have M5 inside threads.Ordering and deliveryWhen ordering a pressure sensor, please provide quantity, type reference, order number and product name.Any accessories required must be ordered separately.Accessories**) Cannot be used with types QBE2003-P10, QBE2003-P16, QBE2003-P25, QBE2103-P10, QBE2103-P16, and QBE2103-P25. These types do not have M5 inside threads.Example3/6Mode of operationThe pressure sensors operate on the piezo-resistive measuring principle. The ceramic or stainless steel diaphram*) (thick-film hybrid technology) acquires the pressurethrough direct contact with the medium. The measurement is converted electronically into a linear output signal of DC 0...10 V or DC 4…20 mA.*) Applies to QBE2003-P10, QBE2003-P16, QBE2003-P25, QBE2103-P10, QBE2103-P16, and QBE2103-P25Mechanical designThe pressure sensor consists of: • Sensor hood with DIN EN 175301-803-A plug-in connection • Piezo-resistive measuring element integrated in the stainless steel case • Pressure connection external thread G ½" and inside thread M5*) for use withaccessory AQB2001**)• Plug DIN EN 175301-803-A (plugged in) No changes or adjustments are possible.*) The following types do not have M5 inside threads:QBE2003-P10, QBE2003-P16, QBE2003-P25, QBE2103-P10, QBE2103-P16, and QBE2103-P25 **) Cannot be used on types QBE2003-P10, QBE2003-P16, QBE2003-P25, QBE2103-P10, QBE2103-P16, and QBE2103-P25. A solution on the construction side using the ½" threaded connection is possible.Mounting notesMounting Instructions are enclosed with the sensor. For further information aboutmounting location and mounting position refer to the sensor mounting user's manual at the BT download center: /bt/download .Appropriate measures must be taken to ensure a leak-proof fitting.To provide for test measurements without leakage of the medium, it is strongly recommended that an appropriate test adapter and shutoff device be fitted.The tapping point should be at the side, near the bottom of the pipe. Do not measure the pressure from the top of the pipe (where it may be affected by airlocks) or the bottom (where it may be affected by dirt).Always purge the system. 1909Z 03The tapping point should be at the top so that no condensate reaches the sensor.1909Z 04Ensure suitable constructions measures are undertaken to avoid pressure shocks in the plant; pressure shocks may damage the pressure sensor's diaphragm.In the event that pressure shocks are unavoidable, a panel screw (M5) may be able to weaken the effect. Contact in this case your nearest Siemens branch office.DisposalThe device is considered electrical and electronic equipment for disposal in terms of the applicable European Directive and may not be disposed of as domestic garbage.• Dispose of the device via the channels provided for this purpose. • Comply with all local and currently applicable laws and regulations.Pressure measurement with liquidsPressure measurement with condensing gasesImportant noteTechnical dataElectrical interface Power supplySupply voltage (QBE2003…)Current consumptionSupply voltage (QBE2103…)Current consumption Protection by extra low voltage (SELV, PELV) AC 24 V ±15%, 50...60 Hz or DC 12...33 V <7 mA, < 0.5 VADC 7…33 V<23 mA, < 0.7 VAExternal supply line protection Fuse slow max. 10 AorCircuit breaker max. 13 ACharacteristic B, C, D according to EN 60898orPower source with current limitation of max. 10 AOutput signal QBE2003…Output sig nal QBE2103…DC 0 ...10 V, load >10 kΩ, < 100 nF, 3-wireDC 4…20 mA, R Load ≤ Ohm 2-wireInsulation voltage 500VShort circuit proof, protected against reversepolarityAny connection Functional data Application range Refer to "Type summary"Measuring accuracy FS = Full scale Characteristic curve 1)ResolutionTemperature responseLong-term stability (as per IEC EN60770-1)±0.3 % FS0.1 % FS<±0.2 % FS/10 °C (-15…85°C)<±0.25 % FS1) typical; max. 0.5 % FS (including zero point, end value, linearity, hysteresis, and reproducibility)Dynamic response Response time: <2 ms, typical 1 msLoad change: < 100 HzNominal pressure Relative pressure as in "Type summary"(measurement of difference from ambient pressure) Max. admissible pressure/ Rupture pressure 3 x scale end value of measuring range0…1 to 0…4 bar2.5 x scale end value of measuring range0...6 to 0...60 barMediaAdmissible temperature of mediumNeutral and slightly corrosive liquids and gases(suited for use with oil-contacting media)−15...+125 °CMaintenance Maintenance-freeMounting position OptionalProtection Protection standard IP 65 to EN 60529Protection class III according to EN 60730Connections Electric connection Plug DIN EN 175301-803-A,Cable diameter 6-8 mmScrewed fitting External thread G ½", inside thread M5*)Environmental conditionsTemperatureHumidity O p e r a t i o n−30...+85 °CInsensitive to CondensationStorage−50...+100 °CInsensitive toCondensationOperating voltage – 7 V0,02 A4/65/6Directives and standardsProduct standardEN 61326-1Electrical equipment for measurement, control and laboratory use. EMC requirements. General requirementsMaterials Pressure connection Stainless steel 1.4404 / AISI 316L Plug housingPolyarylamide 50 % GF VOMaterials and media contact Press.connection Stainless steel 1.4404 / AISI 316LMeas.elem.**) Ceramics Al2O3 (96 %) Stainless steelSealantFPMle Conformity EU Conformity (CE)8000078214 ***) RCM ConformityCE1T1909en_C1 ***) Weight Including packaging0,171 kg*) The following types do not have M5 inside threads.QBE2003-P10, QBE2003-P16, QBE2003-P25, QBE2103-P10, QBE2103-P16, and QBE2103-P25 **) Stainless steel for types QBE2003-P10, QBE2003-P16, QBE2003-P25, QBE2103-P10, QBE2103-P16, and QBE2103-P25***) The documents can be downloaded from /bt/download .Internal diagramQBE2003…QBE2103…6/6 DimensionsQBE2003-P… QBE2103-P…*) The following types do not have M5 interior threads: QBE2003-P10 QBE2003-P16 QBE2003-P25 QBE2103-P10 QBE2103-P16 QBE2103-P25。
DAC088S085资料
September 2007 DAC088S0858-Bit Micro Power OCTAL Digital-to-Analog Converter with Rail-to-Rail OutputsGeneral DescriptionThe DAC088S085 is a full-featured, general purpose OCTAL8-bit voltage-output digital-to-analog converter (DAC) thatcan operate from a single +2.7V to +5.5V supply and con-sumes 1.95 mW at 3V and 4.85 mW at 5V. The DAC088S085is packaged in a 16-lead LLP package and a 16-lead TSSOPpackage. The LLP package makes the DAC088S085 thesmallest OCTAL DAC in its class. The on-chip output ampli-fiers allow rail-to-rail output swing and the three wire serialinterface operates at clock rates up to 40 MHz over the entiresupply voltage range. Competitive devices are limited to 25MHz clock rates at supply voltages in the 2.7V to 3.6V range.The serial interface is compatible with standard SPI™, QSPI,MICROWIRE and DSP interfaces. The DAC088S085 also of-fers daisy chain operation where an unlimited number ofDAC088S085s can be updated simultaneously using a singleserial interface.There are two references for the DAC088S085. One refer-ence input serves channels A through D while the otherreference serves channels E through H. Each reference canbe set independently between 0.5V and VA , providing thewidest possible output dynamic range. The DAC088S085 has a 16-bit input shift register that controls the mode of operation, the power-down condition, and the DAC channels' register/ output value. All eight DAC outputs can be updated simulta-neously or individually.A power-on reset circuit ensures that the DAC outputs power up to zero volts and remain there until there is a valid write to the device. The power-down feature of the DAC088S085 al-lows each DAC to be independently powered with three dif-ferent termination options. With all the DAC channels powered down, power consumption reduces to less than 0.3µW at 3V and less than 1 µW at 5V. The low power consump-tion and small packages of the DAC088S085 make it an excellent choice for use in battery operated equipment.The DAC088S085 is one of a family of pin compatible DACs, including the 10-bit DAC108S085 and the 12-bit DAC128S085. All three parts are offered with the same pinout, allowing system designers to select a resolution ap-propriate for their application without redesigning their printed circuit board. The DAC088S085 operates over the extended industrial temperature range of −40°C to +125°C.Features■Guaranteed Monotonicity■Low Power Operation■Rail-to-Rail Voltage Output■Daisy Chain Capability■Power-on Reset to 0V■Simultaneous Output Updating■Individual Channel Power Down Capability■Wide power supply range (+2.7V to +5.5V)■Dual Reference Voltages with range of 0.5V to V A■Operating Temperature Range of −40°C to +125°C■Industry's Smallest PackageKey Specifications■Resolution8 bits ■INL±0.5 LSB (max)■DNL+0.15 / −0.1 LSB (max)■Settling Time 4.5 µs (max)■Zero Code Error+15 mV (max)■Full-Scale Error−0.75 %FSR (max)■Supply Power■—Normal 1.95 mW (3V) / 4.85 mW (5V) typ —Power Down0.3 µW (3V) / 1 µW (5V) typ Applications■Battery-Powered Instruments■Digital Gain and Offset Adjustment■Programmable Voltage & Current Sources■Programmable Attenuators■Voltage Reference for ADCs■Sensor Supply Voltage■Range DetectorsOrdering InformationOrder Numbers Temperature Range Package Top MarkDAC088S085CISQ−40°C ≤ T A≤ +125°C16-Lead LLPDAC088S085CISQX−40°C ≤ T A≤ +125°C LLP Tape-and-ReelDAC088S085CIMT−40°C ≤ T A≤ +125°C16-Lead TSSOP X82CDAC088S085CIMTX−40°C ≤ T A≤ +125°C TSSOP Tape-and-Reel X82CDAC088S085EB Evaluation Board - BOTHSPI™ is a trademark of Motorola, Inc.© 2007 National Semiconductor DAC088S085 8-Bit Micro Power OCTAL Digital-to-Analog Converter with Rail-to-Rail OutputsBlock Diagram30031303 2D A C 088S 085Pin Configuration3003130130031302Pin DescriptionsLLPPin No.TSSOPPin No.Symbol Type Description13V OUTA Analog Output Channel A Analog Output Voltage.24V OUTB Analog Output Channel B Analog Output Voltage.35V OUTC Analog Output Channel C Analog Output Voltage.46V OUTD Analog Output Channel D Analog Output Voltage.57V A Supply Power supply input. Must be decoupled to GND.68V REF1Analog InputUnbuffered reference voltage shared by Channels A, B, C, and D.Must be decoupled to GND.79V REF2Analog InputUnbuffered reference voltage shared by Channels E, F, G, and H.Must be decoupled to GND.810GND Ground Ground reference for all on-chip circuitry.911V OUTH Analog Output Channel H Analog Output Voltage.1012V OUTG Analog Output Channel G Analog Output Voltage.1113V OUTF Analog Output Channel F Analog Output Voltage.1214V OUTE Analog Output Channel E Analog Output Voltage.1315SYNC Digital InputFrame Synchronization Input. When this pin goes low, data iswritten into the DAC's input shift register on the falling edges ofSCLK. After the 16th falling edge of SCLK, a rising edge of SYNCcauses the DAC to be updated. If SYNC is brought high before the15th falling edge of SCLK, the rising edge of SYNC acts as aninterrupt and the write sequence is ignored by the DAC.1416SCLK Digital InputSerial Clock Input. Data is clocked into the input shift register onthe falling edges of this pin.151D IN Digital InputSerial Data Input. Data is clocked into the 16-bit shift register onthe falling edges of SCLK after the fall of SYNC.162D OUT Digital OutputSerial Data Output. DOUTis utilized in daisy chain operation and isconnected directly to a DINpin on another DAC088S085. Data isnot available at DOUTunless SYNC remains low for more than 16SCLK cycles.17PAD(LLP only)GroundExposed die attach pad can be connected to ground or left floating.Soldering the pad to the PCB offers optimal thermal performanceand enhances package self-alignment during reflow.DAC088S085Absolute Maximum Ratings (Notes 1, 2)If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.Supply Voltage, V A6.5VVoltage on any Input Pin−0.3V to 6.5VInput Current at Any Pin (Note 3)10 mA Package Input Current (Note 3)30 mA Power Consumption at T A = 25°C See (Note 4)ESD Susceptibility (Note 5) Human Body Model Machine ModelCharge Device Mode 2500V 250V 1000V Junction Temperature +150°CStorage Temperature−65°C to +150°COperating Ratings (Notes 1, 2)Operating Temperature Range −40°C ≤ T A ≤ +125°CSupply Voltage, V A+2.7V to 5.5V Reference Voltage, V REF1,2+0.5V to V ADigital Input Voltage (Note 7)0.0V to 5.5VOutput Load0 to 1500 pF SCLK FrequencyUp to 40 MHzPackage Thermal ResistancesPackage θJA 16-Lead LLP 38°C/W 16-Lead TSSOP130°C/WSo l dering process must comp l y with Nationa l Semiconductor's Reflow Temperature Profile specifications.Refer to /packaging. (Note 6)Electrical CharacteristicsThe following specifications apply for V A = +2.7V to +5.5V, V REF1 = V REF2 = V A , C L = 200 pF to GND, f SCLK = 30 MHz, input code range 3 to 252. Boldface limits apply for T MIN ≤ T A ≤ T MAX and all other limits are at T A = 25°C, unless otherwise specified.SymbolParameterConditionsTypicalLimits (Note 8)Units (Limits)STATIC PERFORMANCEResolution 8Bits (min) Monotonicity 8Bits (min)INL Integral Non-Linearity ±0.12±0.5LSB (max)DNL Differential Non-Linearity +0.03+0.15LSB (max)−0.02−0.1LSB (min)ZE Zero Code Error I OUT = 0+5+15mV (max)FSE Full-Scale Error I OUT = 0−0.1−0.75% FSR (max)GE Gain Error−0.2−1.0% FSR (max)ZCED Zero Code Error Drift −20µV/°C TC GEGain Error Tempco−1.0ppm/°COUTPUT CHARACTERISTICSOutput Voltage Range 0V REF1,2V (min)V (max)I OZHigh-Impedance Output Leakage Current (Note 9)±1µA (max)ZCOZero Code OutputV A = 3V, I OUT = 200 µA10 mV V A = 3V, I OUT = 1 mA 45 mV V A = 5V, I OUT = 200 µA 8 mV V A = 5V, I OUT = 1 mA 34 mV FSOFull Scale OutputV A = 3V, I OUT = 200 µA2.984 V V A = 3V, I OUT = 1 mA 2.933 V V A = 5V, I OUT = 200 µA 4.987 V V A = 5V, I OUT = 1 mA4.955 V I OSOutput Short Circuit Current (source) (Note 10)V A = 3V, V OUT = 0V,Input Code = FFh −50 mA V A = 5V, V OUT = 0V,Input Code = FFh−60mA 4D A C 088S 085Symbol Parameter Conditions TypicalLimits(Note 8)Units(Limits)I OS Output Short Circuit Current (sink)(Note 10)VA= 3V, VOUT= 3V,Input Code = 00h50mAVA= 5V, VOUT= 5V,Input Code = 00h70mAI O Continuous Output Current perchannel (Note 9)TA= 105°C10mA (max)TA= 125°C 6.5mA (max)C L Maximum Load CapacitanceRL= ∞1500pFRL= 2kΩ1500pFZOUTDC Output Impedance8ΩREFERENCE INPUT CHARACTERISTICSVREF1,2Input Range Minimum0.5 2.7V (min) Input Range Maximum V A V (max) Input Impedance30kΩLOGIC INPUT CHARACTERISTICSIINInput Current (Note 9)±1µA (max)V IL Input Low VoltageVA= 2.7V to 3.6V 1.00.6V (max)VA= 4.5V to 5.5V 1.10.8V (max)V IH Input High VoltageVA= 2.7V to 3.6V 1.4 2.1V (min)VA= 4.5V to 5.5V 2.0 2.4V (min)CINInput Capacitance (Note 9)3pF (max) POWER REQUIREMENTSV A Supply Voltage Minimum 2.7V (min) Supply Voltage Maximum 5.5V (max)I N Normal Supply Current for supplypin VAfSCLK= 30 MHz,output unloadedVA= 2.7Vto 3.6V460575µA (max)VA= 4.5Vto 5.5V650840µA (max)Normal Supply Current for VREF1orVREF2fSCLK= 30 MHz,output unloadedVA= 2.7Vto 3.6V95135µA (max)VA= 4.5Vto 5.5V160225µA (max)I ST Static Supply Current for supply pinVAfSCLK= 0,output unloadedVA= 2.7Vto 3.6V370µAVA= 4.5Vto 5.5V440µAStatic Supply Current for VREF1orVREF2fSCLK= 0,output unloadedVA= 2.7Vto 3.6V95µAVA= 4.5Vto 5.5V160µAI PD Total Power Down Supply Currentfor all PD Modes(Note 9)fSCLK= 30 MHz, SYNC =VAand DIN= 0V after PDmode loadedVA= 2.7Vto 3.6V0.2 1.5µA (max)VA= 4.5Vto 5.5V0.5 3.0µA (max)fSCLK= 0, SYNC = VAandDIN= 0V after PD modeloadedVA= 2.7Vto 3.6V0.1 1.0µA (max)VA= 4.5Vto 5.5V0.2 2.0µA (max)DAC088S085Symbol Parameter ConditionsTypical Limits (Note 8)Units (Limits)P NTotal Power Consumption (output unloaded)f SCLK = 30 MHz output unloadedV A = 2.7V to 3.6V 1.95 3.0mW (max)V A = 4.5V to 5.5V 4.857.1mW (max)f SCLK = 0output unloadedV A = 2.7V to 3.6V 1.68 mW V A = 4.5V to 5.5V3.80 mW P PDTotal Power Consumption in all PD Modes,(Note 9)f SCLK = 30 MHz, SYNC =V A and D IN = 0V after PDmode loadedV A= 2.7Vto 3.6V0.6 5.4µW (max)V A = 4.5Vto 5.5V2.516.5µW (max)f SCLK = 0, SYNC = V A and D IN = 0V after PD modeloadedV A= 2.7Vto 3.6V0.3 3.6µW (max)V A = 4.5Vto 5.5V111µW (max)A.C. and Timing CharacteristicsThe following specifications apply for V A = +2.7V to +5.5V, V REF1,2 = V A , C L = 200 pF to GND, f SCLK = 30 MHz, input code range 3 to 252. Boldface limits apply for T MIN ≤ T A ≤ T MAX and all other limits are at T A = 25°C, unless otherwise specified.Symbol ParameterConductionsTypical Limits (Note 8)Units (Limits)f SCLK SCLK Frequency4030MHz (max)t s Output Voltage Settling Time (Note 9)40h to C0h code change R L = 2k Ω, C L = 200 pF 3 4.5µs (max)SR Output Slew Rate1 V/µs GI Glitch Impulse Code change from 80h to 7Fh 40 nV-sec DF Digital Feedthrough 0.5 nV-sec DC Digital Crosstalk 0.5 nV-sec CROSS DAC-to-DAC Crosstalk1 nV-sec MBW Multiplying Bandwidth V REF1,2 = 2.5V ± 2Vpp 360 kHz ONSD Output Noise Spectral Density DAC Code = 80h, 10kHz 40 nV/sqrt(Hz)ON Output Noise BW = 30kHz 14 µV t WU Wake-Up Time V A = 3V 3 µsec V A = 5V 20 µsec 1/f SCLK SCLK Cycle Time 2533ns (min)t CH SCLK High time 710ns (min)t CL SCLK Low Time710ns (min)t SS SYNC Set-up Time prior to SCLK Falling Edge310ns (min) 1 / f SCLK - 3ns (max)t DS Data Set-Up Time prior to SCLK Falling Edge1.02.5ns (min)t DH Data Hold Time after SCLK Falling Edge1.02.5ns (min)t SH SYNC Hold Time after the 16th fallingedge of SCLK03ns (min) 1 / f SCLK - 3ns (max)t SYNCSYNC High Time515ns (min) 6D A C 088S 085Note 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.Note 2:All voltages are measured with respect to GND = 0V, unless otherwise specified.Note 3:When the input voltage at any pin exceeds 5.5V or is less than GND, the current at that pin should be limited to 10 mA. The 30 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to three.Note 4:The absolute maximum junction temperature (T J max) for this device is 150°C. The maximum allowable power dissipation is dictated by T J max, the junction-to-ambient thermal resistance (θJA ), and the ambient temperature (T A ), and can be calculated using the formula P D MAX = (T J max − T A ) / θJA . The values for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed). Such conditions should always be avoided.Note 5:Human body model is 100 pF capacitor discharged through a 1.5 k Ω resistor. Machine model is 220 pF discharged through 0 Ω. Charge device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.Note 6:Reflow temperature profiles are different for lead-free packages.Note 7:The inputs are protected as shown below. Input voltage magnitudes up to 5.5V, regardless of V A , will not cause errors in the conversion result. For example, if V A is 3V, the digital input pins can be driven with a 5V logic device.30031304Note 8:Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level).Note 9:This parameter is guaranteed by design and/or characterization and is not tested in production.Note 10:This parameter does not represent a condition which the DAC can sustain continuously. See the continuous output current specification for the maximum DAC output current per channel.Timing Diagrams30031306FIGURE 1. Serial Timing DiagramDAC088S085Specification DefinitionsDIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB,which is V REF / 256 = V A / 256.DAC-to-DAC CROSSTALK is the glitch impulse transferred to a DAC output in response to a full-scale change in the out-put of another DAC.DIGITAL CROSSTALK is the glitch impulse transferred to a DAC output at mid-scale in response to a full-scale change in the input register of another DAC.DIGITAL FEEDTHROUGH is a measure of the energy inject-ed into the analog output of the DAC from the digital inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the data bus.FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (FFh) loaded into the DAC and the value of V A x 255 / 256.GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and Full-Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error.GLITCH IMPULSE is the energy injected into the analog out-put when the input code to the DAC register changes. It is specified as the area of the glitch in nanovolt-seconds.INTEGRAL NON-LINEARITY (INL) is a measure of the de-viation of each individual code from a straight line through the input to output transfer function. The deviation of any given code from this straight line is measured from the center of that code value. The end point method is used. INL for this product is specified over a limited range, per the Electrical Tables.LEAST SIGNIFICANT BIT (LSB) is the bit that has the small-est value or weight of all bits in a word. This value isLSB = V REF / 2nwhere V REF is the supply voltage for this product, and "n" is the DAC resolution in bits, which is 8 for the DAC088S085.MAXIMUM LOAD CAPACITANCE is the maximum capaci-tance that can be driven by the DAC with output stability maintained.MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when the input code increases.MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is 1/2 of V A .MULTIPLYING BANDWIDTH is the frequency at which the output amplitude falls 3dB below the input sine wave on V REF1,2 with the DAC code at full-scale.NOISE SPECTRAL DENSITY is the internally generated ran-dom noise. It is measured by loading the DAC to mid-scale and measuring the noise at the output.POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from the power supply. The difference between the supply and output cur-rents is the power consumed by the device without a load.SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is updated.TOTAL HARMONIC DISTORTION PLUS NOISE (THD+N)is the ratio of the harmonics plus the noise present at the out-put of the DACs to the rms level of an ideal sine wave applied to V REF1,2 with the DAC code at mid-scale.WAKE-UP TIME is the time for the output to exit power-down mode. This is the time from the rising edge of SYNC to when the output voltage deviates from the power-down voltage of 0V.ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 00h has been entered.Transfer Characteristic30031305FIGURE 2. Input / Output Transfer Characteristic 8D A C 088S 085Typical Performance Characteristics VA = +2.7V to +5.5V, VREF1,2= VA, fSCLK= 30 MHz, TA= 25°C,unless otherwise statedINL vs Code30031352DNL vs Code30031355INL/DNL vs VREF30031357INL/DNL vs fSCLK30031324INL/DNL vs VA30031322INL/DNL vs Temperature30031327DAC088S085Zero Code Error vs. V A30031330Zero Code Error vs. V REF30031331Zero Code Error vs. f SCLK30031334Zero Code Error vs. Temperature30031336Full-Scale Error vs. V A 30031337Full-Scale Error vs. V REF30031332 10D A C 088S 085Full-Scale Error vs. fSCLK30031333Full-Scale Error vs. Temperature30031339I VA vs. VA30031344IVAvs. Temperature30031345I VREF vs. VREF30031325IVREFvs. Temperature30031335DAC088S085Settling Time30031328Glitch Response30031346Wake-Up Time 30031351DAC-to-DAC Crosstalk30031338Power-On Reset 30031347Multiplying Bandwidth30031350D A C 088S 0851.0 Functional Description1.1 DAC ARCHITECTUREThe DAC088S085 is fabricated on a CMOS process with an architecture that consists of switches and resistor strings that are followed by an output buffer. The reference voltages are externally applied at V REF1 for DAC channels A through D and V REF2 for DAC channels E through H.For simplicity, a single resistor string is shown in Figure 3.This string consists of 256 equal valued resistors with a switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register determines which switch is closed, connecting the proper node to the amplifier. The input coding is straight binary with an ideal output voltage of:V OUTA,B,C,D = V REF1 x (D / 256)V OUTE,F,G,H = V REF2 x (D / 256)where D is the decimal equivalent of the binary code that is loaded into the DAC register. D can take on any value be-tween 0 and 255. This configuration guarantees that the DAC is monotonic.30031307FIGURE 3. DAC Resistor StringSince all eight DAC channels of the DAC088S085 can be controlled independently, each channel consists of a DAC register and a 8-bit DAC. Figure 4 is a simple block diagram of an individual channel in the DAC088S085. Depending on the mode of operation, data written into a DAC register causes the 8-bit DAC output to be updated or an additional command is required to update the DAC output. Further description of the modes of operation can be found in the Serial Interface description.30031369FIGURE 4. Single Channel Block Diagram1.2 OUTPUT AMPLIFIERSThe output amplifiers are rail-to-rail, providing an output volt-age range of 0V to V A when the reference is V A . All amplifiers,even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0V and V A , in this case). For this reason, linearity is specified over less than the full output range of the DAC. However, if the reference is less than V A ,there is only a loss in linearity in the lowest codes.The output amplifiers are capable of driving a load of 2 k Ω in parallel with 1500 pF to ground or to V A . The zero-code and full-scale outputs for given load currents are available in the Electrical Characteristics Table.1.3 REFERENCE VOLTAGEThe DAC088S085 uses dual external references, V REF1 and V REF2, that are shared by channels A, B, C, D and channels E, F, G, H respectively. The reference pins are not buffered and have an input impedance of 30 k Ω. It is recommended that V REF1 and V REF2 be driven by voltage sources with low output impedance. The reference voltage range is 0.5V to V A , providing the widest possible output dynamic range.1.4 SERIAL INTERFACEThe three-wire interface is compatible with SPI, QSPI and MICROWIRE, as well as most DSPs and operates at clock rates up to 40 MHz. A valid serial frame contains 16 falling edges of SCLK. See the Timing Diagram for information on a write sequence.A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the D IN line is clocked into the 16-bit serial input register on the falling edges of SCLK. To avoid mis-clocking data into the shift register, it is critical that SYNC not be brought low on a falling edge of SCLK (see minimum and maximum setup times for SYNC in the Timing Characteristics and Figure 5). On the 16th falling edge of SCLK, the last data bit is clocked into the register. The write sequence is concluded by bringing the SYNC line high. Once SYNC is high, the programmed function (a change in the DAC channel address, mode of operation and/or register contents)is executed. To avoid mis-clocking data into the shift register,it is critical that SYNC be brought high between the 16th and 17th falling edges of SCLK (see minimum and maximum hold times for SYNC in the Timing Characteristics and Figure 5).30031365FIGURE 5. CS Setup and Hold TimesIf SYNC is brought high before the 15th falling edge of SCLK,the write sequence is aborted and the data that has been shifted into the input register is discarded. If SYNC is held low beyond the 17th falling edge of SCLK, the serial data pre-sented at D IN will begin to be output on D OUT . More informa-tion on this mode of operation can be found in the Daisy Chain Section. In either case, SYNC must be brought high for the minimum specified time before the next write sequence is ini-tiated with a falling edge of SYNC.Since the D IN buffer draws more current when it is high, it should be idled low between write sequences to minimize power consumption. On the other hand, SYNC should beDAC088S085idled high to avoid the activation of daisy chain operation where D OUT is active.1.5 DAISY CHAIN OPERATIONDaisy chain operation allows communication with any number of DAC088S085s using a single serial interface. As long as the correct number of data bits are input in a write sequence (multiple of sixteen bits), a rising edge of SYNC will properly update all DACs in the system.To support multiple devices in a daisy chain configuration,SCLK and SYNC are shared across all DAC088S085s and D OUT of the first DAC in the chain is connected to D IN of the second. Figure 6 shows three DAC088S085s connected in daisy chain fashion. Similar to a single channel write se-quence, the conversion for a daisy chain operation begins on a falling edge of SYNC and ends on a rising edge of SYNC.A valid write sequence for n devices in a chain requires n times 16 falling edges to shift the entire input data stream through the chain. Daisy chain operation is guaranteed for a maximum SCLK speed of 30MHz.30031367FIGURE 6. Daisy Chain ConfigurationThe serial data output pin, D OUT , is available on the DAC088S085 to allow daisy-chaining of multiple DAC088S085 devices in a system. In a write sequence,D OUT remains low for the first fourteen falling edges of SCLK before going high on the fifteenth falling edge. Subsequently,the next sixteen falling edges of SCLK will output the first six-teen data bits entered into D IN . Figure 7 shows the timing of three DAC088S085s in Figure 6. In this instance, It takes forty-eight falling edges of SCLK followed by a rising edge of SYNC to load all three DAC088S085s with the appropriate register data. On the rising edge of SYNC, the programmed function is executed in each DAC088S085 simultaneously.30031368FIGURE 7. Daisy Chain Timing Diagram1.6 SERIAL INPUT REGISTERThe DAC088S085 has two modes of operation plus a few special command operations. The two modes of operation are Write Register Mode (WRM) and Write Through Mode (WTM). For the rest of this document, these modes will be referred to as WRM and WTM. The special command oper-ations are separate from WRM and WTM because they can be called upon regardless of the current mode of operation.The mode of operation is controlled by the first four bits of the control register, DB15 through DB12. See Table 1 for a de-tailed summary.TABLE 1. Write Register and Write Through ModesDB[15:12]DB[11:0]Description of Mode1 0 0 0X X X X X X X X X X X X WRM: The registers of each DAC Channel can be written to without causing their outputs to change.1 0 0 1X X X X X X X X X X X XWTM: Writing data to a channel's register causes the DAC output to change.D A C 088S 085。
ADC12130CIWM资料
ADC12130/ADC12132/ADC12138Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/HoldGeneral DescriptionThe ADC12130,ADC12132and ADC12138are 12-bit plus sign successive approximation A/D converters with serial I/O and configurable input multiplexer.The ADC12132and ADC12138have a 2and an 8channel multiplexer,respec-tively.The differential multiplexer outputs and A/D inputs are available on the MUXOUT1,MUXOUT2,A/DIN1and A/DIN2pins.The ADC12130has a two channel multiplexer with the multiplexer outputs and A/D inputs internally connected.The ADC12130family is tested with a 5MHz clock.On request,these A/Ds go through a self calibration process that adjusts linearity,zero and full-scale errors to typically less than ±1LSB each.The analog inputs can be configured to operate in various combinations of single-ended,differential,or pseudo-differential modes.A fully differential unipolar analog input range (0V to +5V)can be accommodated with a single +5V supply.In the differential modes,valid outputs are ob-tained even when the negative inputs are greater than the positive because of the 12-bit plus sign output data format.The serial I/O is configured to comply with the NSC MI-CROWIRE ™.For voltage references,see the LM4040or LM4041.Featuresn Serial I/O (MICROWIRE,SPI and QSPI Compatible)n 2or 8channel differential or single-ended multiplexer n Analog input sample/hold function n Power down moden Programmable acquisition timen Variable digital output word length and format n No zero or full scale adjustment requiredn0V to 5V analog input range with single 5V power supplyKey Specificationsn Resolution:12-bit plus signn 12-bit plus sign conversion time:8.8µs (max)n 12-bit plus sign throughput time:14µs (max)n Integral linearity error:±2LSB (max)n Single supply: 3.3V or 5V ±10%nPower consumption —3.3V 15mW (max)—3.3V power down 40µW (typ)—5V 33mW (max)—5V power down 100µW (typ)Applicationsn Pen-based computers n Digitizersn Global positioning systemsADC12138Simplified Block DiagramTRI-STATE ®is a registered trademark of National Semiconductor Corporation.COPS ™microcontrollers,HPC ™and MICROWIRE ™are trademarks of National Semiconductor Corporation.DS012079-1March 2000ADC12130/ADC12132/ADC12138Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold©2000National Semiconductor Corporation Ordering InformationIndustrial Temperature Range−40˚C ≤T A ≤+85˚C NS Package Number ADC12130CIN N16E,Dual-In-Line ADC12130CIWM M16B,Wide Body SOADC12132CIMSA MSA20,SSOP ADC12138CIN N28B,Dual-In-LineADC12138CIWM M28B ADC12138CIMSAMSA28,SSOPConnection Diagrams16-Pin Dual-In-Line and Wide Body SO PackagesDS012079-2Top View20-Pin SSOP PackageDS012079-47Top View28-Pin Dual-In-Line,SSOP and Wide Body SO PackagesDS012079-3Top ViewA D C 12130/A D C 12132/A D C 12138 2Pin DescriptionsCCLK The clock applied to this input controls the su-cessive approximation conversion time intervaland the acquisition time.The rise and fall timesof the clock edges should not exceed1µs. SCLK This is the serial data clock input.The clock applied to this input controls the rate at whichthe serial data exchange occurs.The risingedge loads the information on the DI pin intothe multiplexer address and mode select shiftregister.This address controls which channelof the analog input multiplexer(MUX)is se-lected and the mode of operation for the A/D.With CS low,the falling edge of SCLK shiftsthe data resulting from the previous ADC con-version out on DO,with the exception of thefirst bit of data.When CS is low continuously,the first bit of the data is clocked out on the ris-ing edge of EOC(end of conversion).WhenCS is toggled,the falling edge of CS alwaysclocks out the first bit of data.CS should bebrought low when SCLK is low.The rise andfall times of the clock edges should not exceed1µs.DI This is the serial data input pin.The data ap-plied to this pin is shifted by the rising edge ofSCLK into the multiplexer address and modeselect register.Table2through Table4showthe assignment of the multiplexer address andthe mode select data.DO The data output pin.This pin is an active push/ pull output when CS is low.When CS is high,this output is TRI-STATE.The A/D conversionresult(DB0–DB12)and converter status dataare clocked out by the falling edge of SCLK onthis pin.The word length and format of this re-sult can vary(see Table1).The word lengthand format are controlled by the data shiftedinto the multiplexer address and mode selectregister(see Table4).EOC This pin is an active push/pull output and indi-cates the status of the ADC12130/2/8.Whenlow,it signals that the A/D is busy with a con-version,auto-calibration,auto-zero or powerdown cycle.The rising edge of EOC signalsthe end of one of these cycles.CS This is the chip select pin.When a logic low is applied to this pin,the rising edge of SCLKshifts the data on DI into the address register.This low also brings DO out of TRI-STATE.With CS low,the falling edge of SCLK shiftsthe data resulting from the previous ADC con-version out on DO,with the exception of thefirst bit of data.When CS is low continuously,the first bit of the data is clocked out on the ris-ing edge of EOC(end of conversion).WhenCS is toggled,the falling edge of CS alwaysclocks out the first bit of data.CS should bebrought low when SCLK is low.The fallingedge of CS resets a conversion in progressand starts the sequence for a new conversion.When CS is brought back low during a conver-sion,that conversion is prematurely termi-nated.The data in the output latches may becorrupted.Therefore,when CS is brought backlow during a conversion in progress the dataoutput at that time should be ignored.CS mayalso be left continuously low.In this case it isimperative that the correct number of SCLKpulses be applied to the ADC in order to re-main synchronous.After the ADC supplypower is applied it expects to see13clockpulses for each I/O sequence.The number ofclock pulses the ADC expects is the same asthe digital output word length.This word lengthcan be modified by the data shifted in on theDO pin.Table4details the data required.DOR This is the data output ready pin.This pin is anactive push/pull output.It is low when the con-version result is being shifted out and goeshigh to signal that all the data has been shiftedout.CONV A logic low is required on this pin to programany mode or change the ADC’s configurationas listed in the Mode Programming Table(Table4)such as12-bit conversion,Auto Cal,Auto Zero etc.When this pin is high the ADC isplaced in the read data only mode.While in theread data only mode,bringing CS low andpulsing SCLK will only clock out on DO anydata stored in the ADCs output shift register.The data on DI will be neglected.A new con-version will not be started and the ADC will re-main in the mode and/or configuration previ-ously programmed.Read data only cannot beperformed while a conversion,Auto-Cal orAuto-Zero are in progress.PD This is the power down pin.When PD is highthe A/D is powered down;when PD is low theA/D is powered up.The A/D takes a maximumof700µs to power up after the command isgiven.CH0–CH7These are the analog inputs of the MUX.Achannel input is selected by the address infor-mation at the DI pin,which is loaded on the ris-ing edge of SCLK into the address register(see Table2and Table3).The voltage applied to these inputs should notexceed V A+or go below GND.Exceeding thisrange on an unselected channel will corruptthe reading of a selected channel.COM This pin is another analog input pin.It is usedas a pseudo ground when the analog multi-plexer is single-ended.MUXOUT1,MUXOUT2These are the multiplexer outputpins.A/DIN1,A/DIN2These are the converter input pins.MUXOUT1is usually tied to A/DIN1.MUXOUT2is usuallytied to A/DIN2.If external circuitry is placed be-tween MUXOUT1and A/DIN1,or MUXOUT2and A/DIN2it may be necessary to protectthese pins.The voltage at these pins shouldnot exceed V A+or go below AGND(see Figure5).V REF+This is the positive analog voltage referenceinput.In order to maintain accuracy,the volt-age range of V REF(V REF=V REF+−V REF−)isADC12130/ADC12132/ADC121383Pin Descriptions(Continued)1V DC to 5.0V DC and the voltage at V REF +cannot exceed V A +.See Figure 6for recom-mended bypassing.V REF −The negative voltage reference input.In order to maintain accuracy,the voltage at this pin must not go below GND or exceed V A +.(See Figure 6).V A +,V D +These are the analog and digital power supply pins.V A +and V D +are not connected together on the chip.These pins should be tied to the same power supply and bypassed separately (see Figure 6).The operating voltage range of V A +and V D +is 3.0V DC to 5.5V DC .DGND This is the digital ground pin (see Figure 6).AGNDThis is the analog ground pin (see Figure 6).A D C 12130/A D C 12132/A D C 12138 4Absolute Maximum Ratings (Notes 1,2)If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.Positive Supply Voltage (V +=V A +=V D +)6.5VVoltage at Inputs and Outputs except CH0–CH7and COM −0.3V to V ++0.3V Voltage at Analog Inputs CH0–CH7and COM GND −5V to V ++5V|V A +−V D +|300mV Input Current at Any Pin (Note 3)±30mA Package Input Current (Note 3)±120mAPackage Dissipation at T A =25˚C (Note 4)500mWESD Susceptability (Note 5)Human Body Model 1500V Soldering InformationN Packages (10seconds)260˚C SO Package (Note 6):Vapor Phase (60seconds)215˚C Infrared (15seconds)220˚CStorage Temperature −65˚C to +150˚COperating Ratings (Notes 1,2)Operating Temperature RangeT MIN ≤T A ≤T MAXADC12130CIN,ADC12130CIWM,ADC12132CIMSA,ADC12138CIMSA,ADC12138CIN,ADC12138CIWM −40˚C ≤T A ≤+85˚CSupply Voltage (V +=V A +=V D +)+3.0V to +5.5V|V A +−V D +|≤100mV V REF +0V to V A +V REF −0V to V REF +V REF (V REF +−V REF −)1V to V A +V REF Common Mode Voltage Range0.1V A +to 0.6V A +A/DIN1,A/DIN2,MUXOUT1and MUXOUT2Voltage Range 0V to V A +A/D IN Common Mode Voltage Range0V to V A +Converter Electrical CharacteristicsThe following specifications apply for (V +=V A +=V D +=+5V,V REF +=+4.096V,and fully differential input with fixed 2.048V common-mode voltage)or (V +=V A +=V D +=3.3V,V REF +=2.5V and fully-differential input with fixed 1.250Vcommon-mode voltage),V REF −=0V,12-bit +sign conversion mode,source impedance for analog inputs,V REF −and V REF +≤25Ω,f CK =f SK =5MHz,and 10(t CK )acquisition time unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =25˚C.(Notes 7,8,9)SymbolParameterConditionsTypical (Note 10)Limits Units (Limits)(Note 11)STATIC CONVERTER CHARACTERISTICSResolution12+signBits (min)+ILE Positive Integral Linearity Error After Auto-Cal (Notes 12,18)±1/2±2LSB (max)−ILE Negative Integral Linearity Error After Auto-Cal (Notes 12,18)±1/2±2LSB (max)DNLDifferential Non-Linearity After Auto-Cal±1.5LSB (max)Positive Full-Scale Error After Auto-Cal (Notes 12,18)±1/2±3.0LSB (max)Negative Full-Scale Error After Auto-Cal (Notes 12,18)±1/2±3.0LSB (max)Offset ErrorAfter Auto-Cal (Notes 5,18)±1/2±2LSB (max)V IN (+)=V IN (−)=2.048VDC Common Mode ErrorAfter Auto-Cal (Note 15)±2LSB (max)TUETotal Unadjusted ErrorAfter Auto-Cal ±1LSB(Notes 12,13,14)ADC12130/ADC12132/ADC121385Converter Electrical CharacteristicsThe following specifications apply for (V +=V A +=V D +=+5V,V REF +=+4.096V,and fully differential input with fixed 2.048V common-mode voltage)or (V +=V A +=V D +=3.3V,V REF +=+2.5V and fully-differential input with fixed 1.250Vcommon-mode voltage),V REF −=0V,12-bit +sign conversion mode,source impedance for analog inputs,V REF −and V REF +≤25Ω,f CK =f SK =5MHz,and 10(t CK )acquisition time unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =25˚C.(Notes 7,8,9)(Continued)SymbolParameterConditionsTypical (Note 10)Limits Units (Limits)(Note 11)STATIC CONVERTER CHARACTERISTICS (Continued)Multiplexer Channel to Channel ±0.05LSBMatchingPower Supply SensitivityV +=+5V ±10%V REF =+4.096VOffset Error ±0.5LSB +Full-Scale Error ±0.5LSB −Full-Scale Error±0.5LSB +Integral Linearity Error ±0.5LSB −Integral Linearity Error±0.5LSBUNIPOLAR DYNAMIC CONVERTER CHARACTERISTICS S/(N+D)Signal-to-Noise Plus f IN =1kHz,V IN =5V PP ,V REF +=5.0V 69.4dB Distortion Ratiof IN =20kHz,V IN =5V PP ,V REF +=5.0V 68.3dB f IN =40kHz,V IN =5V PP ,V REF +=5.0V 65.7dB −3dB Full Power BandwidthV IN =5V PP ,where S/(N+D)drops 3dB 31kHzDIFFERENTIAL DYNAMIC CONVERTER CHARACTERISTICSS/(N+D)Signal-to-Noise Plus f IN =1kHz,V IN =±5V,V REF +=5.0V 77.0dB Distortion Ratiof IN =20kHz,V IN =±5V,V REF +=5.0V 73.9dB f IN =40kHz,V IN =±5V,V REF +=5.0V 67.0dB −3dB Full Power BandwidthV IN =±5V,where S/(N+D)drops 3dB40kHzElectrical CharacteristicsThe following specifications apply for (V +=V A +=V D +=+5V,V REF +=+4.096V,and fully differential input with fixed 2.048V common-mode voltage)or (V +=V A +=V D +=+3.3V,V REF +=2.5V and fully-differential input with fixed 1.250Vcommon-mode voltage),V REF −=0V,12-bit +sign conversion mode,source impedance for analog inputs,V REF −and V REF +≤25Ω,f CK =f SK =5MHz,and 10(t CK )acquisition time unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =25˚C.(Notes 7,8,9)SymbolParameterConditionsTypical Limits Units (Note 10)(Note 11)(Limits)REFERENCE INPUT,ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS C REF Reference Input Capacitance 85pF C A/DA/DIN1and A/DIN2Analog Input 75pF CapacitanceA/DIN1and A/DIN2Analog Input V IN =+5.0V or ±0.1µALeakage CurrentV IN =0VCH0–CH7and COM Input VoltageGND −0.05VV A ++0.05C CH CH0–CH7and COM Input Capacitance10pF C MUXOUTMUX Output Capacitance 20pF Off Channel Leakage (Note 16)On Channel =5V and −0.01µA CH0–CH7and COM PinsOff Channel =0V On Channel =0V and 0.01µAOff Channel =5VA D C 12130/A D C 12132/A D C 12138 6Electrical Characteristics(Continued)The following specifications apply for(V+=V A+=V D+=+5V,V REF+=+4.096V,and fully differential input with fixed2.048V common-mode voltage)or(V+=V A+=V D+=+3.3V,V REF+=2.5V and fully-differential input with fixed1.250Vcommon-mode voltage),V REF−=0V,12-bit+sign conversion mode,source impedance for analog inputs,V REF−and V REF+≤25Ω,f CK=f SK=5MHz,and10(t CK)acquisition time unless otherwise specified.Boldface limits apply for T A=T J=T MIN to T MAX;all other limits T A=T J=25˚C.(Notes7,8,9)Symbol Parameter Conditions Typical Limits Units(Note10)(Note11)(Limits) REFERENCE INPUT,ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICSOn Channel Leakage(Note16)On Channel=5V and0.01µACH0–CH7and COM Pins Off Channel=0VOn Channel=0V and−0.01µAOff Channel=5VMUXOUT1and MUXOUT2V MUXOUT=5.0V or0.01µALeakage Current V MUXOUT=0VR ON MUX On Resistance V IN=2.5V and8501900Ω(max)V MUXOUT=2.4VR ON Matching Channel to Channel V IN=2.5V and5%V MUXOUT=2.4VChannel to Channel Crosstalk V IN=5V PP,f IN=40kHz−72dBMUX Bandwidth90kHz DC and Logic Electrical CharacteristicsThe following specifications apply for(V+=V A+=V D+=+5V,V REF+=+4.096V,and fully-differential input with fixed2.048V common-mode voltage)or(V+=V A+=V D+=+3.3V,V REF+=+2.5V and fully-differential input with fixed1.250Vcommon-mode voltage),V REF−=0V,12-bit+sign conversion mode,source impedance for analog inputs,V REF−and V REF+≤25Ω,f CK=f SK=5MHz,and10(t CK)acquisition time unless otherwise specified.Boldface limits apply for T A=T J=T MIN to T MAX;all other limits T A=T J=25˚C.(Notes7,8,9)Symbol Parameter Conditions Typical(Note10)V+=V A+=V+=V A+=Units(Limits) V D+=3.3V V D+=5VLimits Limits(Note11)(Note11)CCLK,CS,CONV,DI,PD AND SCLK INPUT CHARACTERISTICSV IN(1)Logical“1”InputVoltageV A+=V D+=V++10% 2.0 2.0V(min)V IN(0)Logical“0”InputVoltageV A+=V D+=V+−10%0.80.8V(max)I IN(1)Logical“1”InputCurrentV IN=V+0.005 1.0 1.0µA(max)I IN(0)Logical“0”InputCurrentV IN=0V−0.005−1.0−1.0µA(min) DO,EOC AND DOR DIGITAL OUTPUT CHARACTERISTICSV OUT(1)Logical“1”V A+=V D+=V+−10%,Output Voltage I OUT=−360µA 2.4 2.4V(min)V A+=V D+=V+−10%, 2.9 4.25V(min)I OUT=−10µAV OUT(0)Logical“0”V A+=V D+=V+−10%Output Voltage I OUT=1.6mA0.40.4V(max) I OUT TRI-STATE V OUT=0V−0.1−3.0−3.0µA(max)Output Current V OUT=V+−0.1 3.0 3.0+I SC Output ShortCircuit SourceCurrent V OUT=0V−14mAADC12130/ADC12132/ADC121387DC and Logic Electrical Characteristics(Continued)The following specifications apply for (V +=V A +=V D +=+5V,V REF +=+4.096V,and fully-differential input with fixed 2.048V common-mode voltage)or (V +=V A +=V D +=+3.3V,V REF +=+2.5V and fully-differential input with fixed 1.250Vcommon-mode voltage),V REF −=0V,12-bit +sign conversion mode,source impedance for analog inputs,V REF −and V REF +≤25Ω,f CK =f SK =5MHz,and 10(t CK )acquisition time unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =25˚C.(Notes 7,8,9)SymbolParameterConditionsTypical (Note 10)V +=V A +=V +=V A +=Units (Limits)V D +=3.3V V D +=5V Limits Limits (Note 11)(Note 11)DO,EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS −I SCOutput Short Circuit Sink Current V OUT =V D +16mAPOWER SUPPLY CHARACTERISTICS I D +Digital Supply 1.52.5mA (max)CurrentCS =HIGH,Powered Down,CCLK on 600µA CS =HIGH,Powered Down,CCLK off20µA I A +Positive Analog 3.04.0mA (max)Supply CurrentCS =HIGH,Powered Down,CCLK on 10µA CS =HIGH,Powered Down,CCLK off0.1µAI REFReference Input CurrentCS =HIGH,Powered Down,CCLK on 70µA CS =HIGH,Powered Down,CCLK off0.1µAAC Electrical CharacteristicsThe following specifications apply for (V +=V A +=V D +=+5V,V REF +=+4.096V,and fully-differential input with fixed 2.048V common-mode voltage)or (V +=V A +=V D +=+3.3V,V REF +=+2.5V and fully-differential input with fixed 1.250Vcommon-mode voltage),V REF −=0V,12-bit +sign conversion mode,source impedance for analog inputs,V REF −and V REF +≤25Ω,f CK =f SK =5MHz,and 10(t CK )acquisition time unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =25˚C.(Note 17)SymbolParameterConditionsTypical Limits Units (Note 10)(Note 11)(Limits)f CK Conversion Clock 105MHz (max)(CCLK)Frequency 1MHz (min)f SKSerial Data Clock 105MHz (max)SCLK Frequency 0Hz (min)Conversion Clock 40%(min)Duty Cycle 60%(max)Serial Data Clock 40%(min)Duty Cycle60%(max)t CConversion Time12-Bit +Sign or 12-Bit44(t CK )44(t CK )(max)8.8µs (max)A D C 12130/A D C 12132/A D C 12138 8AC Electrical Characteristics(Continued)The following specifications apply for(V+=V A+=V D+=+5V,V REF+=+4.096V,and fully-differential input with fixed2.048V common-mode voltage)or(V+=V A+=V D+=+3.3V,V REF+=+2.5V and fully-differential input with fixed1.250Vcommon-mode voltage),V REF−=0V,12-bit+sign conversion mode,source impedance for analog inputs,V REF−and V REF+≤25Ω,f CK=f SK=5MHz,and10(t CK)acquisition time unless otherwise specified.Boldface limits apply for T A=T J=T MIN to T MAX;all other limits T A=T J=25˚C.(Note17)Symbol Parameter Conditions Typical Limits Units(Note 10)(Note11)(Limits)t A Acquisition Time6Cycles Programmed6(t CK)6(t CK)(min) (Note19)7(t CK)(max)1.2µs(min)1.4µs(max)10Cycles Programmed10(t CK)10(t CK)(min)11(t CK)(max)2.0µs(min)2.2µs(max)18Cycles Programmed18(t CK)18(t CK)(min)19(t CK)(max)3.6µs(min)3.8µs(max)34Cycles Programmed34(t CK)34(t CK)(min)35(t CK)(max)6.8µs(min)7.0µs(max)t CAL Self-Calibration Time4944(t CK)4944(t CK)(max)988.8µs(max)t AZ Auto-Zero Time76(t CK)76(t CK)(max)15.2µs(max)t SYNC Self-Calibration or2(t CK)2(t CK)(min) Auto-Zero Synchronization3(t CK)(max)Time from DOR0.40µs(min)0.60µs(max)t DOR DOR High Time when CS is Low9(t SK)9(t SK)(max) Continuously for Read Data and SoftwarePower Up/Down1.8µs(max)t CONV CONV Valid Data Time8(t SK)8(t SK)(max)1.6µs(max)AC Electrical CharacteristicsThe following specifications apply for(V+=V A+=V D+=+5V,V REF+=+4.096V,and fully-differential input with fixed2.048V common-mode voltage)or(V+=V A+=V D+=+3.3V,V REF+=+2.5V and fully-differential input with fixed1.250Vcommon-mode voltage),V REF−=0V,12-bit+sign conversion mode,source impedance for analog inputs,V REF−and V REF+≤25Ω,f CK=f SK=5MHz,and10(t CK)acquisition time unless otherwise specified.Boldface limits apply for T A=T J=T MIN to T MAX;all other limits T A=T J=25˚C.(Note17)(Continued)Symbol Parameter Conditions Typical Limits Units(Note10)(Note11)(Limits)t HPU Hardware Power-Up Time,Time from500700µs(max) PD Falling Edge to EOC Rising Edget SPU Software Power-Up Time,Time fromSerial Data Clock Falling Edge to500700µs(max)EOC Rising Edget ACC Access Time Delay from2560ns(max) CS Falling Edge to DO Data ValidADC12130/ADC12132/ADC121389AC Electrical Characteristics(Continued)The following specifications apply for (V +=V A +=V D +=+5V,V REF +=+4.096V,and fully-differential input with fixed 2.048V common-mode voltage)or (V +=V A +=V D +=+3.3V,V REF +=+2.5V and fully-differential input with fixed 1.250Vcommon-mode voltage),V REF −=0V,12-bit +sign conversion mode,source impedance for analog inputs,V REF −and V REF +≤25Ω,f CK =f SK =5MHz,and 10(t CK )acquisition time unless otherwise specified.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =25˚C.(Note 17)(Continued)Symbol ParameterConditionsTypical Limits Units (Note 10)(Note 11)(Limits)t SET-UP Set-Up Time of CS Falling Edge to 50ns (min)Serial Data Clock Rising Edge t DELAY Delay from SCLK Falling 05ns (min)Edge to CS Falling Edge t 1H ,t 0H Delay from CS Rising Edge to R L =3k,C L =100pF70100ns (max)DO TRI-STATE ®t HDI DI Hold Time from Serial Data 515ns (min)Clock Rising Edget SDI DI Set-Up Time from Serial Data 510ns (min)Clock Rising Edget HDO DO Hold Time from Serial Data R L =3k,C L =100pF3565ns (max)Clock Falling Edge5ns (min)t DDO Delay from Serial Data Clock 5090ns (max)Falling Edge to DO Data Valid t RDO DO Rise Time,TRI-STATE to High R L =3k,C L =100pF1040ns (max)DO Rise Time,Low to High 1040ns (max)t FDO DO Fall Time,TRI-STATE to Low R L =3k,C L =100pF 1540ns (max)DO Fall Time,High to Low 1540ns (max)t CD Delay from CS Falling Edge 4580ns (max)to DOR Falling Edget SD Delay from Serial Data Clock Falling 4580ns (max)Edge to DOR Rising Edge C IN Capacitance of Logic Inputs 10pF C OUTCapacitance of Logic Outputs20pFNote 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the device is func-tional,but do not guarantee specific performance limits.For guaranteed specifications and test conditions,see the Electrical Characteristics.The guaranteed speci-fications apply only for the test conditions listed.Some performance characteristics may degrade when the device is not operated under the listed test conditions.Note 2:All voltages are measured with respect to GND,unless otherwise specified.Note 3:When the input voltage (V IN )at any pin exceeds the power supplies (V IN <GND or V IN >V A +or V D +),the current at that pin should be limited to 30mA.The 120mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30mA to four.Note 4:The maximum power dissipation must be derated at elevated temperatures and is dictated by T J max,θJA and the ambient temperature,T A .The maximum allowable power dissipation at any temperature is P D =(T J max −T A )/θJA or the number given in the Absolute Maximum Ratings,whichever is lower.For this device,T J max =150˚C.The typical thermal resistance (θJA )of these parts when board mounted follow:ThermalPart Number ResistanceθJA ADC12130CIN 53˚C/W ADC12130CIWM 70˚C/W ADC12132CIMSA 134˚C/W ADC12138CIN 40˚C/W ADC12138CIWM 50˚C/W ADC12138CIMSA125˚C/WNote 5:The human body model is a 100pF capacitor discharged through a 1.5k Ωresistor into each pin.Note 6:See AN450“Surface Mounting Methods and Their Effect on Product Reliability”or the section titled “Surface Mount”found in any post 1986National Semi-conductor Linear Data Book for other methods of soldering surface mount devices.A D C 12130/A D C 12132/A D C 12138 10AC Electrical Characteristics(Continued)Note 7:Two on-chip diodes are tied to each analog input through a series resistor as shown below.Input voltage magnitude up to 5V above V A +or 5V below GND will not damage this device.However,errors in the A/D conversion can occur (if these diodes are forward biased by more than 50mV)if the input voltage magnitude of selected or unselected analog input go above V A +or below GND by more than 50mV.As an example,if V A +is 4.5V DC ,full-scale input voltage must be ≤4.55V DC to ensure accurate conversions.Note 8:To guarantee accuracy,it is required that the V A +and V D +be connected together to the same power supply with separate bypass capacitors at each V +pin.Note 9:With the test condition for V REF (V REF +−V REF −)given as +4.096V,the 12-bit LSB is 1.0mV.For V REF =2.5V,the 12-bit LSB is 610µV.Note 10:Typicals are at T J =T A =25˚C and represent most likely parametric norm.Note 11:Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).Note 12:Positive integral linearity error is defined as the deviation of the analog value,expressed in LSBs,from the straight line that passes through positive full-scale and zero.For negative integral linearity error,the straight line passes through negative full-scale and zero (see Figure 2and Figure 3).Note 13:Zero error is a measure of the deviation from the mid-scale voltage (a code of zero),expressed in LSB.It is the average value of the code transitions be-tween −1to 0and 0to +1(see Figure 4).Note 14:Total unadjusted error includes offset,full-scale,linearity and multiplexer errors.Note 15:The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.Note 16:Channel leakage current is measured after the channel selection.Note 17:Timing specifications are tested at the TTL logic levels,V OL =0.4V for a falling edge and V OL =2.4V for a rising edge.TRI-STATE output voltage is forced to 1.4V.Note 18:The ADC12130family’s self-calibration technique ensures linearity and offset errors as specified,but noise inherent in the self-calibration process will re-sult in a maximum repeatability uncertainty of 0.2LSB.Note 19:If SCLK and CCLK are driven from the same clock source,then t A is 6,10,18or 34clock periods minimum and maximum.Note 20:The “12-Bit Conversion of Offset”and “12-Bit Conversion of Full-Scale”modes are intended to test the functionality of the device.Therefore,the output data from these modes are not an indication of the accuracy of a conversion result.DS012079-4DS012079-5FIGURE 1.Transfer CharacteristicADC12130/ADC12132/ADC12138。
VQD1000-TF2Z545EN 4口气阀系列说明书
Instruction Manual 4 Port Solenoid ValveSeries VQD1000The intended use of this valve is to control the movement of an actuator.1 Safety InstructionsThese safety instructions are intended to prevent hazardous situations and/or equipment damage. These instructions indicate the level of potential hazard with the labels of “Caution,” “Warning” or “Danger.” They are all important notes for safety and must be followed in addition to International Standards (ISO/IEC) *1), and other safety regulations. *1)ISO 4414: Pneumatic fluid power - General rules relating to systems. ISO 4413: Hydraulic fluid power - General rules relating to systems.IEC 60204-1: Safety of machinery - Electrical equipment of machines. (Part 1: General requirements)ISO 10218-1: Robots and robotic devices - Safety requirements for industrial robots - Part 1: Robots.• Refer to product catalogue, Operation Manual and Handling Precautions for SMC Products for additional information. • Keep this manual in a safe place for future reference.CautionCaution indicates a hazard with a low level of risk which, if not avoided, could result in minor or moderate injury.WarningWarning indicates a hazard with a medium level of riskwhich, if not avoided, could result in death or serious injury.DangerDanger indicates a hazard with a high level of risk which, ifnot avoided, will result in death or serious injury.Warning• Always ensure compliance with relevant safety laws and standards.• All work must be carried out in a safe manner by a qualified person in compliance with applicable national regulations.• If this equipment is used in a manner not specified by the manufacturer, the protection provided by the equipment may be impaired.Caution• The product is provided for use in manufacturing industries only. Do not use in residential premises.2 Specifications2.1 Valve specifications TypeStandard single Large-flow single Large- flow latchingFluid Air Operating pressure range [MPa] 0 (Vacuum: -101.2 kPa) to 0.7 Ambient and fluid temperature [°C] -10 to 50 (no freezing) Flow characteristics Refer to catalogue Response time [ms] Refer to catalogue Duty cycle Contact SMC Min. operating frequency 1 cycle / 30 days Max. operating frequency [Hz] Contact SMC Manual override Non-locking push type Locking Lubrication Not required Impact / Vibration resistance [m/s 2]Note 1)150/30 Enclosure (based on IEC60529) IP402 Specifications - continuedMounting orientation Unrestricted WeightRefer to catalogueTable 1.Note 1) Impact resistance: No malfunction occurred when it was tested with a droptester in the axial direction and at right angles to the main valve and armature; in both energized and de-energised states and for every time in each condition. (Values at the initial period).Vibration resistance: No malfunction occurred in a one-sweep test between 45 and 2000 Hz. Tests are performed at both energized and de-energized states in the axial direction and at right angles to the main valve and armature. (Values at the initial period).2.2 Solenoid specifications Type Standard single Large-flow single Large-flowlatchingCoil rated voltage [VDC] 12, 24 24 Electrical entry L/M plug connector Coil insulation class Class B or equivalentAllowable voltage fluctuation-10% to +10% of rated voltage Power consumption [W] Note 1) 2 3.2 (Inrush) 1 (Holding)2Surge voltage suppressor Varistor Diode Varistor Indicator light LEDTable 2.Note 1) Refer to catalogue for energy saving type power waveform.2.3 Pneumatic symbolSingle type Latching typeFigure 1. Pneumatic symbol2.4 Special productsWarningSpecial products (-X) might have specifications different from those shown in this section. Contact SMC for specific drawings.3 Installation3.1 InstallationWarning• Do not install the product unless the safety instructions have been read and understood. 3.2 EnvironmentWarning• Do not use in an environment where corrosive gases, chemicals, salt water or steam are present.• Do not use in an explosive atmosphere.• Do not expose to direct sunlight. Use a suitable protective cover.• Do not install in a location subject to vibration or impact in excess of the product’s specifications .• Do not mount in a location exposed to radiant heat that would result in temperatures in excess of the product’s specifications. 3.3 PipingCaution• Before connecting piping make sure to clean up chips, cutting oil, dust etc.• When installing piping or fittings, ensure sealant material does not enter inside the port. When using seal tape, leave 1 thread exposed on the end of the pipe/fitting.• Tighten fittings to the specified tightening torque. Port Thread Tightening torque [N·m]1(P), 3(R) M5 1 to 1.5 2(B), 4(A)P(1), R(3) (Manifold)1/83 to 5Table 4.3 Installation - continued3.4 LubricationCaution• SMC products have been lubricated for life at manufacture, and do not require lubrication in service.• If a lubricant is used in the system, refer to catalogue for details. 3.5 Air supplyWarning• Use clean air. If the compressed air supply includes chemicals, synthetic materials (including organic solvents), salinity, corrosive gas etc., it can lead to damage or malfunction.Caution• Install an air filter upstream of the valve. Select an air filter with afiltration size of 5 μm or smaller. 3.6 Manual overrideWarning• Regardless of an electric signal for the valve, the manual override is used for switching the main valve. Since connected equipment will operate when the manual override is activated, confirm that conditions are safe prior to activation.• Locked manual overrides might prevent the valve responding to being electrically de-energised or cause unexpected movement in the equipment.• Refer to the catalogue for details of manual override operation. 3.7 MountingCaution• Ensure gaskets are in good condition, not deformed and are dust and debris free.• When mounting valves ensure gaskets are present, aligned and securely in place and tighten the mounting screws to a torque of 0.18 to 0.25 N∙m.• When piping and mounting valves, clamp the body part in place to avoid applying force to the coil. If you apply force over 120 N to coil, connection pins deform, which may cause malfunction. (Latching: 50N or more).Figure 2.3.8 Electrical circuitsCautionFigure 3. Single type (Standard: 2W)Figure 4. Single type (Large flow: 3.2 W)Effective energizing time for the energy saving type is between 15 to 25 ms at 24 VDC. Refer to catalogue for electrical power waveform.3 Installation - continuedFigure 5. Latching solenoid typeFigure 6. Positive commonFigure 7. Negative common3.9 Electrical connectorsCautionFigure 8. How to use plug connectorPull lead wire with gently, otherwise it may cause contact failure ordisconnection.Refer to catalogue for guidance on how to use plug connector. 3.10 Residual voltageCaution• If a varistor voltage suppressor is used, the suppressor arrests the back EMF voltage from the coil to a level in proportion to the rated voltage.• Ensure the transient voltage is within the specification of the host controller.• Contact SMC for the varistor residual voltage.• In the case of a diode, the residual voltage is approximately 1 V.• Valve response time is dependent on surge suppression method selected.ORIGINAL INSTRUCTIONSFittingCoilPin BodyLEDSOL.Red (+/-)Black (-/+)V a r i s t o rRed (+)Black (-)E n e r g y s a v i n g I CDiode SOL.SOL.LEDA (-) SetC (+) COMV a r i s t o rS i m u l t a n e o u s e n e r g i s a t i o n p r o t e c t i o n c i r c u i tB (-) ResetS i m u l t a n e o u s e n e r g i s a t i o n p r o t e c t i o n c i r c u i tS i m u l t a n e o u s e n e r g i s a t i o n p r o t e c t i o n c i r c u i tBlack (-) A-ONRed (+) COMWhite (-) B-ONRed (+) A-ONBlack (-) COMWhite (+) B-ONSOL.SOL.CoverGroove PinConnectorLeverLeverConnectorL plug connector M plug connector Base mounted Body ported Base mounted Body ported AC3 Installation - continued3.11 Countermeasure for surge voltageCaution•At times of sudden interruption of the power supply, the energy stored in a large inductive device may cause non-polar type valves in a de-energised state to switch.•When installing a breaker circuit to isolate the power, consider a valve with polarity (with polarity protection diode), or install a surge absorption diode across the output of the breaker.3.12 Extended period of continuous energizationWarning•If a valve will be continuously energized for an extended period of time, or is mounted in a control panel, the temperature of the valve will increase due to the heat generated by the coil assembly. This will likely adversely affect the performance of the valve and any nearby peripheral equipment. Therefore, if the valve is to be energized for periods of longer than 30 minutes at a time or if during the hours of operation the energized period per day is longer than the de-energized period, we advise using a direct operated continuous duty type valve such as the VK series or the VT series, or consider use of the latching type for which continuous energization is not required.•Coil temperature may get high due to ambient temperature or energizing duration. Do not touch the valve by hand directly. When there is such a dangerous case to be touched by hands directly, install a protective cover.•The latching type should not be energized over 30 seconds. Ensure the de-energised period is longer than the energised time (both A andB should be turned off.) before the next operation.3.13 Effect of back pressure when using a manifoldWarningUse caution when valves are used on a manifold, because an actuator may malfunction due to back-pressure.3.14 Latching typeCaution•Use in a circuit that does not have simultaneous energization of A-ON and B-ON signals.•The minimum energization time required for self-holding is 50 ms. •Although there is no problem for normal operations and environments. please consult SMC when operating in an environment with vibration (10G or more) or strong magnetic fields.•When there is the magnetic body at the valve side, it may cause malfunction. Allow a space over 10 mm between the valve and magnetic body.•Even though this valve is held on to B-ON position (passage: P → B), it may switch to the set position during transportation or due to impact when mounting valves, etc. Therefore, check the initial position by means of power supply or manual override prior to use.Energisation Passage Light colourA-ON (Set) A(-) C(+)Black RedP→A(B→R)RedB-ON (Reset) B(-) C(+)White RedP→B(A→R)GreenTable 5.Note) For positive common.4 How to OrderRefer to catalogue for ‘How to Order’.5 Outline DimensionsRefer to catalogue for outline dimensions.6 Maintenance6.1 General maintenanceCaution•Not following proper maintenance procedures could cause the product to malfunction and lead to equipment damage.•If handled improperly, compressed air can be dangerous. •Maintenance of pneumatic systems should be performed only by qualified personnel. 6 Maintenance - continued•Before performing maintenance, turn off the power supply and be sureto cut off the supply pressure. Confirm that the air is released toatmosphere.•After installation and maintenance, apply operating pressure andpower to the equipment and perform appropriate functional andleakage tests to make sure the equipment is installed correctly.•If any electrical connections are disturbed during maintenance, ensurethey are reconnected correctly and safety checks are carried out asrequired to ensure continued compliance with applicable nationalregulations.•Do not make any modification to the product.•Do not disassemble the product, unless required by installation ormaintenance instructions.6.2 MountingCautionRefer to 3.7 Mounting for guidance on how to mount valve to base.6.3 Maintainable partsCautionRefer to catalogue for how to order manifold accessories, sub-plates orelectrical connector assemblies.7 Limitations of Use7.1 Limited warranty and disclaimer/compliance requirementsCautionRefer to Handling Precautions for SMC Products.7.2 Effect of energy loss on valve switchingWarningSingle type Latching type Note)Air supply present,electrical supply cutValve spoolreturns to OFFposition by springforce.Valve spool holds position untilreset signal is sent (B-ON), spoolthen returns to OFF position byspring force.Electrical supplypresent, air supply cutValve operation is not dependent on presence of airsupply. Spool position/movement is unaffected byloss of air supply.Note) Refer to 3.14 and catalogue for Latching type operation guidance.7.3 Holding of pressureWarningSince valves are subject to air leakage, they cannot be used forapplications such as holding pressure (including vacuum) in a system.7.4 Cannot be used as an emergency shut-off valveWarningThis product is not designed for safety applications such as anemergency shut-off valve. If the valves are used in this type of system,other reliable safety assurance measures should be adopted.7.5 Leakage voltageCautionEnsure that any leakage voltage caused by the leakage current when theswitching element is OFF causes ≤ 2% of the rated voltage across thevalve.7.6 Low temperature operationCautionUnless otherwise indicated in the specifications for each valve, operationis possible to -10˚C, but appropriate measures should be taken to avoidsolidification or freezing of drainage and moisture, etc.7 Limitations of Use - continued7.7 Vacuum applications and use as a 3 port valve.Caution•Use a VQD(1/2)(2/3/5)1(V/W) valve for vacuum applications.•Connect the vacuum source to the 3(R) port.•Refer to catalogue for diagram.•Air pressure cannot be applied to the 3(R) port.•When used as a 3 port valve, conversion from N.O. to N.C. and viceversa is possible by plugging either port 4(A) or 2(B).•The valve cannot be used as a 2 port valve.8 Product DisposalThis product shall not be disposed of as municipal waste. Check yourlocal regulations and guidelines to dispose this product correctly, in orderto reduce the impact on human health and the environment.9 ContactsRefer to or www.smc.eu for your localdistributor/importer.URL : https:// (Global) https:// www.smc.eu (Europe)SMC Corporation, 4-14-1, Sotokanda, Chiyoda-ku, Tokyo 101-0021, JapanSpecifications are subject to change without prior notice from the manufacturer.© 2022SMC Corporation All Rights Reserved.Template DKP50047-F-085M。
锂离子电池容量衰减机理和副反应-翻译(个人翻译的外文文献)
锂离子电池容量衰减机理和副反应-翻译(个人翻译的外文文献)Capacity Fade Mechanisms and Side Reactions inLithium-Ion Batteries锂离子电池容量衰减机机理和副反应Pankaj Arorat and Ralph E. White*作者:Pankaj Arorat and Ralph E. White*Center For Electrochemical Engineering, Department of Chemical Engineering, University of South Carolina,Columbia, South Carolina 29208, USA美国,南卡罗来纳,年哥伦比亚29208,南卡罗来纳大学,化学工程系,中心电化学工程ABSTRACT 摘要The capacity of a lithium-ion battery decreases 锂离子电池容量随着循环during cycling. This capacity loss or fade occurs due to 衰减。
容量损失或者衰减的发several different mechanisms which are due to or are 生主要是由于以下几种反应机associated with unwanted side reactions that occur in these 理,这些机理起因于或者关联batteries. These reactions occur during overcharge or 于一些我们不希望发生在电池overdischarge and cause electrolyte decomposition, passive 里的副反应。
这些反应发生在filmformation, active material dissolution, and other 过充或者过放中,导致了电解phenomena. These capacity loss mechanisms are not 液分解、钝化膜的形成、活性included in the present lithium-ion battery mathematical 物质溶解和其他现象形成。
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a r X i v :c o n d -m a t /0601258v 1 [c o n d -m a t .s t a t -m e c h ] 12 J a n 2006Negative linear compressibility in confined dilatating systems E.V.Vakarin a ,Yurko Dudab ,J.P.Badiali a a UMR 7575LECA ENSCP-UPMC,11rue P.et M.Curie,75231Cedex 05,Paris,France b Programa de Ingenier ´ia Molecular,Instituto Mexicano del Petr´o leo,07730D.F.,M´e xico Abstract The role of a matrix response to a fluid insertion is analyzed in terms of a perturbation theory and Monte Carlo simulations applied to a hard sphere fluid in a slit of fluctuating density-dependent width.It is demon-strated that a coupling of the fluid-slit repulsion,spatial confinement and the matrix dilatation acts as an effective fluid-fluid attraction,inducing a pseudo-critical state with divergent linear compressibility and non-critical density fluctuations.An appropriate combination of the dilatation rate,fluid density and the slit size leads to the fluid states with negative linear compressibility.It is shown that the switching from positive to negative compressibility is accompanied by an abrupt change in the packing mecha-nism.I.INTRODUCTION Compounds with a negative linear (or surface)compressibility have recently attractedan interest 1–3because of their specific properties (stretch-induced densification and aux-etic behavior),which might have promising applications.In the case of pure materials only ”rare”crystal phases exhibit these effects,while for composite structures 4it seems to be rather common.Recent experimental studies on insertion into organic 5and non-organic 6matrices reveal the negative compressibility effects due to the host-guest coupling.Con-ceptually similar escape transition 7occurs when a polymer chain is compressed betweentwo pistons.Charge separation in confinedfluids has also been accompanied8with the negative compressibility.These examples suggest that the insertion systems with confine-ment and swelling(dilatation)should exhibit this generic effect at appropriate conditions. In particular,two-particle systems confined to two-dimensionalfinite-size boxes of differ-ent geometry have been studied9–11in this context.It has been found that the isotherms exhibit a van der Waals-type(vdW)instability(loop)as the box size passes through a critical value.The instability has been associated with a prototype of a liquid-gas or a liquid-solid transition in many-body systems.A quite similar instability appears in two-dimensional granular media12,whose effective temperature decreases with the density, leading to a phase separation.Similar features have been detected13in hard discs confined to a narrow channel.Nevertheless,the non-monotonic behavior has been attributed to a sharp change in the accessible phase space,without any connection to collective effects typical for the conventional phase transitions.It is well-known,however,that a liquid-gas transition infinite systems14manifests itself through the negative compressibility states due to the surface effects.Thus,it is quite interesting tofind out if such a loop could exist in three-dimensional many-body systems and what is the physics behind.In particular,we focus on a proto-type of an insertion system.One of the key features of such systems is a host dilatation (or contraction)upon a guest accommodation.This is evident from experiments with high-porosity materials,like aerogels15,16.Upon adsorption such matrices change in vol-ume and their pore size distribution depends on the adsorbate pressure(or density).This effect is not exclusive to relatively soft gel-like matrices,it is quite common for carbon nanotubes17and various intercalation compounds18–20.In anisotropic cases(yered compounds)one deals with a competition of two effects.An increase of the lateral dimen-sion(stretching)at constant number of particles tends to decrease the guest density.This usually induces a transversal shrink,leading to a densification in this direction.Since we have a composite host-guest system,the shrink does not obey the linear elasticity rules and,depending on the shrink intensity,one might expect the negative compressibility. In particular,it has been shown20that a nonlinear increase of the host size with theguest concentration may induce a liquid-gas coexistence for the guestfluid even if the bulk liquid phase does not exist(e.g.a hard-spherefluid).This means that the negative compressibility states were indeed present,but they were unstable under the conditions imposed.Therefore,the objective of this paper is tofind the conditions at which a coupling of the host dilatation and the guest confinement can stabilize the negative compressibility states. For this purpose we start with a quite simple model-the hard spheres,adsorbed in a softly-repulsing planar slit with a density-dependent width.The model contains all the relevant features:confinement,dilatation and spatial anisotropy.The latter is important because it offers a possibility of observing negative linear and positive tangential compressibilities, preserving the overall thermodynamic stability.On the other hand,in the absence of the dilatation(fixed slit width),the model is phenomenologically simple21,22.In particular, there is no a liquid-vapor transition(both in the bulk and in confined geometries).Such that the new aspects are not masked by the internal complexity.The system is analyzed by means of Monte Carlo(MC)simulation and afirst-order perturbation theory23–25. Qualitative reliability of this approach has been tested in application to the liquid-vapor coexistence24and phase separation25in confined geometries.II.MODELConsider N hard spheres of diameterσ=1in a planar slit with the surface area S. The slit itself is a part of a hosting system,whose coupling to the guest species changes the slit geometry.Therefore,the slit width h is notfixed,itfluctuates according to the fluid density(see below).For any h the total Hamiltonian isH=H ff+H fw,(1) where H ff is the hard sphere Hamiltonian,H fw is the slit potentialH fw=ANi=1 1(h−z i)k ;1/2≤z i≤h−1/2.(2)We do not take into account a short-rangedfluid-wall attraction,responsible for the surface adsorption or layering effects.The inverse-power shape for H fw is chosen as a generic form of a soft repulsion,with k controlling the softness.For technical purposes we are working with k=3.Moreover,our results are qualitatively insensitive to a particular choice of k.It should be noted that we do not discuss an adsorption mechanism or the equilibrium between the pore and the bulkfluids.In our case N isfixed and we focus on the pressure variation due to the changes in the slit geometry.III.PERTURBATION THEORYIn practice the evolution of the matrix morphology is much slower than thefluid equilibration process.Then for a given width h we can calculate thefluid thermodynamics conditional to h.A.Conditional equation of state and insertion isothermAt any pore width h the free energy can be represented asβF(h)=βF0(h)−ln e−βH f w 0(3)where F0(h)is the free energy of a reference system,and ... 0is the average over the reference state.Taking a spatially confined hard sphere system(the one with A=0)as a reference,we consider afirst order perturbation23–25for the conditional free energyβF(h)=βF0(h)+βSρ(h) i dz i H fw(4) whereβ=1/(kT)andρ(h)is the pore density in the”slab”approximationNρ(h)=in the excluded volume approximation,while the perturbation contribution is NΨ(h), such that the total conditional free energy isβF(h)=−N ln 1−bρ(h)(1−2h)2(7) Tangential P t(h)and normal P n(h)pressures can be found asP t(h)=−1∂S β,N;P n(h)=−1∂hβ,N.(8)This leads toβP t(h)=ρ(h)1−bρ(h)+16A∗N(2h−1)3.(9)where A∗=βA.Equation(5)allows us to eliminate the surface density N/S in the favor ofρ(h)and we obtain the following equation of stateβP n(h)=ρ(h)(2h−1)3(10)Therefore,for afixed h,our result is clear and simple.The tangential pressure has the bulk form,with the bulk density being replaced by the pore density.As a consequence of thefirst-order perturbative approach,P t(h)does not depend on the slit-fluid interaction. As we will see later,the simulation results demonstrate that this dependence is indeed quite weak.If necessary this effect can be reproduced theoretically taking into account the second-order perturbation term.The normal pressure increases due to the repulsion A∗and decreases with increasing pore width h,such that P n(h)=P t(h)as h→∞.Recall that we are dealing with afixed N.The insertion process can be considered in the same framework.Just instead of the pressure components one would calculate the system response to increasing N–the insertion isothermβµ(h)= ∂βF(h)1−bρ(h) +bρ(h)B.Dilatation effectAs is discussed above,the pore dilatation can be taken into account,assuming that the width h is density-dependent.Real insertion materials are usually rather complex (multicomponent and heterogeneous).For that reason one usually deals with a distribu-tion of pore sizes or with an average size.In this context we assume that h is known only statistically and the probability distribution f(h|ρ)is conditional26,27to the guest density ρ,which should be selfconsistently found fromρ= dhf(h|ρ)ρ(h).(12) Then,taking our results for P n(h)and P t(h),we can focus on the equation of state averaged over the widthfluctuations.P i= dhf(h|ρ)P i(h);i=n,t.(13) This,however,requires a knowledge on the distribution f(h|ρ).Even without resorting to a concrete form for f(h|ρ),it is clear that the matrix reaction can be manifested as a change in the distribution width or/and the mean value.One of the simplest forms reflecting at least one of these features is aδ-like distribution,ignoring a non-zero width.f(h|ρ)=δ[h−h(ρ)](14)whereδ(x)is the Diracδ-function and the mean pore width h(ρ)is density-dependent.h(ρ)=h0(1+tanh[∆(ρ−ρ0)]+tanh[∆ρ0])(15)This form mimics a non-Vegard behavior,typical for layered intercalation compounds20. At low densities(ρ<<ρ0)the dilatation is weak.The most intensive response is at ρ≈ρ0,and then the pore reaches a saturation,corresponding to its mechanical stability limit.Here∆is the matrix response constant or dilatation rate,controlling the slope nearρ≈ρ0.From eq.(12)the average density is found to beρ=Nh(ρ)−1(16)Changing the surface density N/S we vary the average pore densityρ.This allows us to eliminate N/S in the favor ofρin all thermodynamic bining eqs(10)and (13)we obtainβP n=ρ(2h(ρ)−1)3;(17)It is convenient to introduce the compressibility functionχn=1∂P n=1∂ρ∂ρ1−bρ+4A∗h0ρ2(19)Therefore,we have an interplay of several effects–the packing(first term),thefluid-matrix interaction(linear in density),and the matrix reaction(quadratic term).It is seen that a coupling of thefluid-slit repulsion(A),spatial confinement(h0)and the matrix response(∆)acts as an effective infinite-rangefluid-fluid attraction(but just in one direction).Introducing a dimensionless temperature T∗=1/(4A∗),and solving∂P n∂ρ2=0(20) wefind the”critical”parametersρc=1∆b;T∗c=1bh0∆2(21)at which the normal compressibilityχn diverges.It is seen that a physically meaningful (with T∗c>0)pseudo-criticality appears only at∆>b/2.In other words,the matrixreaction∆should dominate the packing effects.In addition,T∗c decreases with increasing pore width h0.It is well known that for bulk systems the vdW loop appearing at T∗<T∗c is un-physical and one usually invokes the Maxwell construction,determining the liquid-vapor coexistence.As we will see below,in our case the loop is a physically justified effect.It appears as a competition between the packing,which tends to increase the pressure with increasingρand the slit dilatation,decreasing P n with increasingρ.As a result the states with negative linear compressibility are stabilized.Note that this behavior is not sensitive to the particular form(15)of h(ρ).Moreover,the dilatation rate∆is essential,while the dilatation magnitude h(ρ)−h0plays only a marginal role.As it should be,this effect disappears in the bulk limit h0→∞or in the case of insensitive matrices∆→0.In order to be more accurate in comparison to the MC data the reference part is replaced by the Carnahan-Starling formβP n=ρ1+η+η2−η3(2h(ρ)−1)3;η=πρ/6.(22)This allows us to avoid the unphysical behavior at high densities.IV.SIMULATIONIn order to verify the existence of the loop predicted by the perturbation theory as well as to get more insight into the phenomenon the MC simulation of the model has been carried out.We applied the canonical NVT MC simulations of a confined hard sphere fluid to calculate the density profiles and pressure components.The simulation cell was parallelepiped in shape,with parallel walls at surface separation h,and surface area S=L x×L y.The periodic boundary conditions were applied to the X and Y directions of the simulation box;the box length in the Z direction isfixed by the pore width.For a given pore width the adsorbedfluid density is chosen according to the Eq.(5).There was constant number of particles,N=1000,and a desiredfluid density has been get by adjusting the value of area,S.We repeated our simulation runs with bigger numberof particles,N=1500and3000,but no significant differences were found.The density profiles,ρ(z),were calculated in the usual way by counting the number of particles,N i in the slabs of thickness d z=0.05parallel to the plane XY by usingρ(z)=N i/v,where v is the slab volume v=d z×L x×L y.The definition of Irving and Kirkwood28has been used to calculate the components of the pressure.The normal component of the pressure for thefluid-fluid interaction isβP n(z)=ρ(z)−βdrz2ijz ij)Θ(z j−zdr=−δ(r−1)(24)The Diracδfunction in our simulation was approximated asδ(r−1)=Θ(r−1)−Θ(r−1−Λ)V i j>i1|r ij|Θ(z−z i z ij) (26)The wall-fluid interaction is a function of z and affects only P n while the tangential component remains the same.The normal pressure in this case isβP W n(z)=βP W1n (z)+βP W2n(z)(27)whereβP W1n (z)andβP W2n(z)are thefluid-wall contributions from surfaces located atz W1=0.5and z W2=h−0.5,respectively.These contributions are defined asβP W1n (z)=−βdz|z i−z W1|Θ(z i−z)Θ(z−z W1) (28)βP W2n (z)=−βdz|z W2−z i|Θ(z W2−z)Θ(z−z i) (29)These definitions of the pressure tensor treat the wall-particle interaction as a contri-bution to the intermolecular forces in a system consisting of thefluid and solid,rather than as an externalfield acting on thefluid.Thus the normal component of the pressure tensor must be independent of z as a condition of mechanical equilibrium and for a sys-tem containing bulkfluid must be equal to the pressure at the bulk density.Tangential components should approach the bulk pressure for sufficiently large h.In this work we have taken parameterΛequal to0.001,0.002,and0.003to make the extrapolation.The average normal component,includes thefluid-fluid andfluid-wall con-tributions given by equations(26)and(27).Each simulation runs5×105MC cycles,with thefirst half for the system to reach equilibrium whereas the second half for evaluating the ensemble averages.V.RESULTSIn agreement with our theoretical prediction,the simulation results confirm that the negative compressibility states(the loop)appear only if the slit reaction∆reaches some threshold value∆∗which involves a combination of h0,ρ0and A.The variation of the average densityρdue to the dilatation should dominate its variation,induced by the changes in the surface density N/S.Pressure as a function of the average pore density is plotted in Figure1.It is seen that the normal component P n develops the loop with increasing pore-fluid repulsion A.The simulation results confirm that this feature is not an artefact of our theoretical approximations.As expected25,the perturbation theory systematically underestimates the magnitude of thefluid-wall repulsion,A,(overestimates the temperature T∗)at which this effect takes place.The tangential component P t is much less sensitive to the slit dilatation.This is coherent with our theoretical estimation.Interestingly,that P t can be reasonablyfitted by the expression for P n taken at much lower A(see the insets).Therefore,we expect that at sufficiently strong repulsion(low temperatures)P t could also be non-monotonic.This would correspond to afluid-solid transformation,which is not considered here.The loop becomes more pronounced with increasing dilatation rate ∆.Since only one pressure component exhibits this behavior,there is no rational basis to suspect a vdW instability(of liquid-vapor type).Moreover,we are dealing with rather wide pores(h0=10)in order to avoid the narrow channel effects13.This makes us to search for an alternative explanation.With this purpose we have analyzed thefluid structure at different densities.The density profiles are presented in Figure2.It is obvious that the system does not exhibit strong density oscillations.It is worth noting,that our perturbation theory results are obtained in the’slab’approximation,eq.(5),which does not take them into account.On the other hand,analysis of the density profiles indicates a sudden change of the packing regime in the negative compressibility region(in between the points A and B,marked in the Figure1(b)).Thefluidfilm becomes more dilute with decreasing(e.g.due to a lateral stretching)density up to the point B withρ=0.32.This process goes uniformly in the middle of thefilm and at the periphery.Passing fromρ=0.32toρ=0.29does not change the middle density,while the rarefaction takes place only near the slit walls. Upon reachingρ=0.25thefilm suddenly densifies in the middle.This corresponds to the inflection point in Figure1(b).Up to the point A withρ=0.2thefilm dilutes only at its periphery.Then we return to the usual uniform dilution with further decrease in the density.Therefore,there is a clear correlation between the negative compressibility states and the packing mechanism.In order to study the redistribution of thefluid density we have calculated the average densityΓ(z)in slabs of different thickness zΓ(z)= z0ρ(t)dt(30) The obtained results are presented in Figure3.As seen,Γ(z)exhibits the same loop as the normal pressure does.Going towards the middle of the pore makes this effect more pronounced.Such similarity permits us to conclude that thefluid-wall soft repulsion(coupled to the dilatation∆)is a main reason of thefluid reordering inside the pore,and as a consequence the states with negative compressibility can occur.This is clearly seen from eq.(22),that gives a monotonic isotherm as A→0or∆→0.It is interesting to mention that a similar trend has been described recently in the studies of mineral clays swelling30,ly,Smith et al.31reported the simulation results of hydrated Na-smectites with variable layer charge.They found that the tendency to swell increases with increasing layer charge(increasing repulsion),which is consistent with our conclusions.VI.CONCLUSIONWe have found that a coupling of thefluid-slit repulsion,spatial confinement and the slit dilatation acts as an anisotropicfluid-fluid attraction,inducing negative linear com-pressibility states.These states are shown to be related to an abrupt change in the packing regime,including a local densification in the middle with decreasing surface density.This resembles the stretch-densification effects1,2in negative compressibility materials.In the context of our model the mechanism is the following.Stretching in the lateral direction decreases the surface N/S and the poreρdensities.This leads to a transversal shrink h(ρ)at the rate∆.This stabilizes the negative transversal compressibility when the rate passes some threshould value.This mechanism is quite different from that explored in the low-dimensional systems9–11,13,where the loops appeared essentially due to the small-size effects restricting the phase space accessibility when the box length became comparable with the particle size.As a result,the vdW feature is found11to be very sensitive to the box geometry(rectangular or spherical).In our case we deal with a three-dimensional system where the particles can exchange their positions almost freely(10≤h(ρ)/σ≤30), although the phase space is somewhat restricted by the slit-fluid repulsion.Nevertheless, our model shares some of the low-dimensional features9–11,13and we recover the usual monotonic behavior in the bulk limit h0→∞.Since the tangential pressure component does not exhibit this effect,the system doesnot undergo a phase transition(at least in its traditional sense).This is confirmed by the absence of strong densityfluctuations(in both directions).On the other hand,the loop appears in the direction,along which our system isfinite(finite h)and,therefore,the negative compressibility can be considered as afinite-size effect14,vanishing in the bulk limit.Nevertheless,an inclusion of an attractivefluid-fluid interaction would result23,24 in the pore condensation.In this respect it would be quite interesting to analyze how the above stretch-densification coexists with the true critical behavior.The role of more isotropic geometries(e.g.spherical pores)as well as that of a non-zero distribution width (f(h|ρ))and the potential softness k could also be discussed.Another interesting point is to describe the sorption behavior,that is,changingρby varying N atfixed S.In this way we can mimic a”dosen”adsorption29or the equilibrium with an infinite bulk reservoir. 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