ECE-C 471 Introduction to VLSI Design Baris Taskin Bossone 413F

ECE-C471Introduction to VLSI Design Syllabus Baris Taskin Lecture:Mon10:00am-12:00pm Bossone413F Lab:Fri11:00am-1:00pm
Course Information
Course Title:Introduction to VLSI Design
Course Type:Undergraduate–Senior
Credits:3credits
Duration:Fall Quarter
Meeting Times:Lectures:Once a week for2hours
Laboratory:Once a week for2hours
Prerequisites
This course is intended for senior-level ECE undergraduate students.
Knowledge of digital logic design(ECE200)and introductory eletronics(ECE-L301-302) is required.Previous exposure to transistors and semiconductor devices would be useful,but not required.These introductory topics will be discussed in early stages of the course to provide necessary technical background to all students from EE and CE.
Course Description
This is an introductory course in thefield of Very Large Scale Integration(VLSI)circuit and systems design.Systematic understanding,design and analysis of VLSI integrated circuits will be covered.This course will focus exclusively on digital CMOS VLSI systems design,although some issues in mixed-signal mode will also be addressed.
The course will begin with a review of CMOS transistor operation and semiconductor man-ufacturing process.Logic design with CMOS transistors and circuit families will be described. Specifically,layout,design rules,and circuit simulation will be addressed.
Course objectives include:
•To learn the basic concepts of modern VLSI circuit design by studying logic design,physical structure and fabrication of semiconductor devices,
•To analyze the electrical and design characteristics of transistors and gates,
•To observe the integration of these devices into complicated high-performance systems,•To understand the role of computer-aided design(CAD)tools in automating the designflow and providing improved productivity in VLSI systems design,
•To understand the relationship between semiconductor technology,transistors and architec-ture,addressing all levels of hierarchy in VLSI system designflow.
1
Course Structure
Laboratory:Once a week for2hours,five(5)assignments
Exam(s):One(1)final examination.
Homework(s):Two(2)homeworks will be assigned.
Project(s):None
This is a senior level undergraduate level class and the evaluation criteria is established accord-ingly.The evaluation process will encompass the monitoring of not the quality of individual work but also participation in group projects and lectures.Thefinal grade will be calculated as follows:
Final→30%
Homework(s)→30%
Lab assignment(s)→40%
Total100%
Textbook
Following is a list of suggested textbooks for this course,starting with the required textbook by J.M.Rabaey,A.Chandrakasan and B.Nikolic.The additional textbooks1through3provide much additional information and can be quite useful.
Required Textbook:J.M.Rabaey,A.Chandrakasan and B.Nikolic,Digital Integrated Cir-
cuits,Prentice Hall,2003,ISBN:0130909963.
Additional Reading: 1.John P.Uyemura,Introduction to VLSI Circuits and Systems:A
Design Perspective Prentice-Hall,Inc.,2002.
2.N.H.Weste and D.Harris,CMOS VLSI Design:A Circuits and
Systems Perspective,Addison-Wesley,2nd ed.,2004.
3.S.M.Kang and Y.Leblebici,CMOS Digital Integrated Circuits Anal-
ysis&Design,McGraw-Hill Inc.,2002.
Laboratory
Weekly design and simulation assignments using Cadence CAD tools.Specifically,Cadence Virtuoso tool for layout,Analog Artist using simulators Spice and Spectre for simulation and Diva for DRC will be used.
Weekly assignments will include:
•CMOS Inverter
•CMOS NAND and NOR gates
•XOR and MUX gates
•Learning about data paths:A simple combinational circuit(i.e.2-bit adder)
2
Tentative Schedule
Week Lecture Lab
1Introduction to VLSI Systems
2CMOS Fabrication
3HSPICE Simulation SPICE assignment 4Layout Design:Rules,Models,CAD CMOS inverter design 5Interconnect Wires HW#1
6Static CMOS Inverter:Speed,Power,Area,Scaling CMOS NAND and NOR 7Layout Techniques for Complex Gates CMOS XOR and MUX 8Power Consumption
9Combinational Logic1:Standard Cells,Circuit Families2-bit Adder
10Combinational Logic2:Low Power CMOS
11Sequential Logic1:Registers,Clock,Timing HW#2
12Sequential Logic2:Clock,Timing
Final Examination(Date TBA)
3。