基于FPGA的LM75A温度传感器(VHDL).

1．编写的程序（一）功能模块：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;--实体--entity at24c08 isport(clk : in std_logic; --时钟信号rst : in std_logic; --复位信号scl : out std_logic; --i2c时钟线sda : inout std_logic; --i2c数据线urv_1 : in std_logic; --上限值1urv_2 : in std_logic; --上限值2sel : out std_logic_vector(3 downto 0);seg : out std_logic_vector(7 downto 0);beep : out std_logic --蜂鸣器输出信号线);end at24c08;--结构体--architecture arch_at24c08 of at24c08 issignal clk_sslow : std_logic;signal counter : std_logic_vector(23 downto 0);signal readdata_reg_buf : std_logic_vector(15 downto 0);signal readdata_ten : integer range 0 to 24564;signal readdata_std : std_logic_vector(15 downto 0);signal qian : std_logic_vector(3 downto 0);signal bai : std_logic_vector(3 downto 0);signal shi : std_logic_vector(3 downto 0);signal ge : std_logic_vector(3 downto 0);signal qian_0 : integer range 0 to 10;signal bai_0 : integer range 0 to 10;signal shi_0 : integer range 0 to 10;signal ge_0 : integer range 0 to 10;--数码管部分信号signal sel_0 : std_logic_vector(3 downto 0);signal seg_0 : std_logic_vector(7 downto 0);signal count : std_logic_vector(13 downto 0);signal clk_slow : std_logic;signal scan_num : std_logic_vector(1 downto 0);signal seg_data_buf : std_logic_vector(3 downto 0);--i2c部分信号signal sda_buf : std_logic; --i2c输入/输出数据寄存器signal link : std_logic; --sda输入输出方向寄存器signal readdata_reg : std_logic_vector(15 downto 0);--i2c读回的数据寄存器signal sda_0 : std_logic; --与sda端口连接信号signal scl_0 : std_logic; --与scl端口连接信号--按键消抖部分信号signal delay_cnt : std_logic_vector(19 downto 0); --消抖延时计数器signal start_delay : std_logic; --按键延时开始--分频部分信号signal clk_div : std_logic_vector(12 downto 0); --分频计数器，5000分频，10khz--蜂鸣器部分信号signal beep_en : std_logic; --蜂鸣器使能信号signal beep_buf : std_logic; --与beep端口连接的信号--时钟部分信号signal level_high : std_logic; --高电平中间值，1249 signal level_low : std_logic; --低电平中间值，3749 signal level_hig_edge : std_logic; --上升沿，4999signal level_low_edge : std_logic; --下降沿，2499--状态机部分信号signal main_state : std_logic_vector(1 downto 0); --状态机主状态signal i2c_state : std_logic_vector(2 downto 0); --i2c状态signal i2c_per_state : std_logic_vector(3 downto 0); --i2c每一步状态--分频部分常量constant div_parameter : std_logic_vector(12 downto 0):="1001110001000";--分频系数，500--状态机部分常量--操作状态常量constant read_init : std_logic_vector(2 downto 0) :="000";--EEPORM 初始化constant read_high : std_logic_vector(2 downto 0) :="001";--读高位数据状态constant read_low : std_logic_vector(2 downto 0) :="010";--读低位数据状态--i2c每一步状态常量constant start : std_logic_vector(3 downto 0) :="0000";--开始位constant first : std_logic_vector(3 downto 0) :="0001";--数据第一位constant second : std_logic_vector(3 downto 0) :="0010";--数据第二位constant third : std_logic_vector(3 downto 0) :="0011";--数据第三位constant fourth : std_logic_vector(3 downto 0) :="0100";--数据第四位constant fifth : std_logic_vector(3 downto 0) :="0101";--数据第五位constant sixth : std_logic_vector(3 downto 0) :="0110";--数据第六位constant seventh : std_logic_vector(3 downto 0) :="0111";--数据第七位constant eighth : std_logic_vector(3 downto 0) :="1000";--数据第八位constant ack : std_logic_vector(3 downto 0) :="1001";--应答位constant stop : std_logic_vector(3 downto 0) :="1010";--停止位--结构体开始beginscl <= scl_0;seg <= seg_0;sda_0 <= sda_buf when (link)='1' else 'Z';sda <= sda_0;sel <= sel_0;beep <= beep_buf;--按键消抖key : process(clk,rst)beginif(not rst='1') thendelay_cnt <= (others => '0');elsif (clk'event and clk='1') thenif start_delay='1' thenif(delay_cnt /= "11110100001001000000") then --20ms延时delay_cnt <= delay_cnt+'1';elsedelay_cnt <= (others => '0');end if;end if;end if;end process key;--分频部分div : process(rst,clk)beginif(not rst='1') thenclk_div <= "0000000000000";level_high <= '0';level_low <= '0';level_hig_edge <= '0';level_low_edge <= '0';elsif(clk'event and clk='1') thenif(clk_div /= div_parameter-'1') then clk_div <= clk_div+'1';elseclk_div <= "0000000000000";end if;if(level_high='1') thenlevel_high <= '0';elseif(clk_div="10011100001") thenlevel_high <= '1';end if;end if;if(level_low_edge='1') thenlevel_low_edge <= '0';elseif(clk_div="100111000011") thenlevel_low_edge <= '1';end if;end if;if(level_low='1') thenlevel_low <= '0';elseif(clk_div="111010100101") thenlevel_low <= '1';end if;end if;if(level_hig_edge='1') thenlevel_hig_edge <= '0';elseif(clk_div="1001110000111") thenlevel_hig_edge <= '1';end if;end if;end if;end process div;--EEPROM操作部分state : process(clk,rst)beginif(not rst='1') thenstart_delay <= '0';scl_0 <= '1';sda_buf <= '1';link <= '0';readdata_reg <= "0000000000000000";main_state <= "00";i2c_state <= read_init;i2c_per_state <= start;elsif(clk'event and clk='1') thencase main_state is--初始化EEPROMwhen "00" =>--等待读写要求scl_0 <= '1';sda_buf <= '1';link <= '0';i2c_state <= read_init;i2c_per_state <= start;main_state <= "10";--读取EEPRO数据when "10" =>if(level_hig_edge='1') thenscl_0 <= '1';elseif(level_low_edge='1') thenscl_0 <= '0';end if;end if;case i2c_state iswhen read_init => --读命令地址case i2c_per_state iswhen start =>if(level_high='1') thensda_buf <= '0';link <= '1';end if;if((level_low and link)='1') thenlink <= '1';sda_buf <= '1';i2c_per_state <= first;end if;when first =>if(level_low='1') thensda_buf <= '0';i2c_per_state <= second;end if;when second =>if(level_low='1') thensda_buf <= '0';link <= '1';i2c_per_state <= third;end if;when third =>if(level_low='1') thensda_buf <= '1';link <= '1';i2c_per_state <= fourth;end if;when fourth =>if(level_low='1') thensda_buf <= '0';link <= '1';i2c_per_state <= fifth;end if;when fifth =>if(level_low='1') thensda_buf <= '0';link <= '1';i2c_per_state <= sixth;end if;when sixth =>if(level_low='1') thensda_buf <= '0';i2c_per_state <= seventh;end if;when seventh =>if(level_low='1') thensda_buf <= '1';link <= '1';i2c_per_state <= eighth;end if;when eighth =>if(level_low='1') thenlink <= '0';i2c_per_state <= ack;end if;when ack =>if(level_hig_edge='1') thensda_buf <= sda;end if;if(level_high='1') thenif(sda_buf='1') thenmain_state <= "00";end if;end if;if(level_low='1') thenlink <= '0';i2c_state <= read_high;i2c_per_state <= first;end if;when others => null;end case;when read_high => --读回数据case i2c_per_state iswhen first =>if(level_hig_edge='1') thensda_buf <= sda;end if;if(level_high='1') thenreaddata_reg(15 downto 9) <= readdata_reg(14 downto 8);readdata_reg(8) <= sda;end if;if(level_low='1') theni2c_per_state <= second;end if;when second =>if(level_hig_edge='1') thensda_buf <= sda;end if;if(level_high='1') thenreaddata_reg(15 downto 9) <= readdata_reg(14 downto 8);readdata_reg(8) <= sda;end if;if(level_low='1') theni2c_per_state <= third;end if;when third =>if(level_hig_edge='1') thensda_buf <= sda;end if;if(level_high='1') thenreaddata_reg(15 downto 9) <= readdata_reg(14 downto 8);readdata_reg(8) <= sda;end if;if(level_low='1') theni2c_per_state <= fourth;end if;when fourth =>if(level_hig_edge='1') thensda_buf <= sda;end if;if(level_high='1') thenreaddata_reg(15 downto 9) <= readdata_reg(14 downto 8);readdata_reg(8) <= sda;end if;if(level_low='1') theni2c_per_state <= fifth;end if;when fifth =>if(level_hig_edge='1') thensda_buf <= sda;end if;if(level_high='1') thenreaddata_reg(15 downto 9) <= readdata_reg(14 downto 8);readdata_reg(8) <= sda;end if;if(level_low='1') theni2c_per_state <= sixth;end if;when sixth =>if(level_hig_edge='1') thensda_buf <= sda;end if;if(level_high='1') thenreaddata_reg(15 downto 9) <= readdata_reg(14 downto 8);readdata_reg(8) <= sda;end if;if(level_low='1') theni2c_per_state <= seventh;end if;when seventh =>if(level_hig_edge='1') thensda_buf <= sda;end if;if(level_high='1') thenreaddata_reg(15 downto 9) <= readdata_reg(14 downto 8);readdata_reg(8) <= sda;end if;if(level_low='1') theni2c_per_state <= eighth;end if;when eighth =>if(level_hig_edge='1') thensda_buf <= sda;end if;if(level_high='1') thenreaddata_reg(15 downto 9) <= readdata_reg(14 downto 8);readdata_reg(8) <= sda;end if;if(level_low='1') theni2c_per_state <= ack;end if;when ack =>if(level_high='1') thenlink <= '1';sda_buf <= '0';i2c_per_state <= first;i2c_state <= read_low;end if;when others => null;end case;when read_low =>case i2c_per_state iswhen first =>if(level_hig_edge='1') thenlink <= '0';sda_buf <= sda;end if;if(level_high='1') thenreaddata_reg(7 downto 1) <= readdata_reg(6 downto 0);readdata_reg(0) <= sda;end if;if(level_low='1') theni2c_per_state <= second;end if;when second =>if(level_hig_edge='1') thenlink <= '0';sda_buf <= sda;end if;if(level_high='1') thenreaddata_reg(7 downto 1) <= readdata_reg(6 downto 0);readdata_reg(0) <= sda;end if;if(level_low='1') theni2c_per_state <= third;end if;when third =>if(level_hig_edge='1') thenlink <= '0';sda_buf <= sda;end if;if(level_high='1') thenreaddata_reg(7 downto 1) <= readdata_reg(6 downto 0);readdata_reg(0) <= sda;end if;if(level_low='1') theni2c_per_state <= fourth;end if;when fourth =>if(level_hig_edge='1') thenlink <= '0';sda_buf <= sda;end if;if(level_high='1') thenreaddata_reg(7 downto 1) <= readdata_reg(6 downto 0);readdata_reg(0) <= sda;end if;if(level_low='1') theni2c_per_state <= fifth;end if;when fifth =>if(level_hig_edge='1') thenlink <= '0';sda_buf <= sda;end if;if(level_high='1') thenreaddata_reg(7 downto 1) <= readdata_reg(6 downto 0);readdata_reg(0) <= sda;end if;if(level_low='1') theni2c_per_state <= sixth;end if;when sixth =>if(level_hig_edge='1') thenlink <= '0';sda_buf <= sda;end if;if(level_high='1') thenreaddata_reg(7 downto 1) <= readdata_reg(6 downto 0);readdata_reg(0) <= sda;end if;if(level_low='1') theni2c_per_state <= seventh;end if;when seventh =>if(level_hig_edge='1') thenlink <= '0';sda_buf <= sda;end if;if(level_high='1') thenreaddata_reg(7 downto 1) <= readdata_reg(6 downto 0);readdata_reg(0) <= sda;end if;if(level_low='1') theni2c_per_state <= eighth;end if;when eighth =>if(level_hig_edge='1') thenlink <= '0';sda_buf <= sda;end if;if(level_high='1') thenreaddata_reg(7 downto 1) <= readdata_reg(6 downto 0);readdata_reg(0) <= sda;end if;if(level_low='1') theni2c_per_state <= ack;end if;when ack =>if(level_high='1') thenlink <= '1';sda_buf <= '1'; --非应答位-- i2c_per_state <= stop;end if;if(level_low='1') thenlink <= '1';sda_buf <= '0';i2c_per_state <= stop;end if;when stop =>if(level_high='1') thenlink <= '1';sda_buf <= '1'; --停止位end if;if(level_low='1') thenmain_state <= "00";end if;when others => null;end case;when others => null;end case;when others => null;end case;end if;end process state;--数据处理部分anly1 : process(readdata_reg_buf)beginreaddata_ten <= conv_integer(readdata_reg_buf)*12;qian_0 <= readdata_ten/1000;bai_0 <= (readdata_ten/100) rem 10;shi_0 <= (readdata_ten/10) rem 10;ge_0 <= readdata_ten rem 10;end process anly1;anly2 : process(qian_0,bai_0,shi_0,ge_0)beginqian <= conv_std_logic_vector(qian_0,4);bai <= conv_std_logic_vector(bai_0,4);shi <= conv_std_logic_vector(shi_0,4);ge <= conv_std_logic_vector(ge_0,4);end process anly2;--数码管显示部分scan : process(rst,clk)beginif(not rst='1') thencount <= (others => '0');clk_slow <= '0';elsif(clk'event and clk='1') thenif(count="11111011011111") thencount <= (others => '0');clk_slow <= not clk_slow;elsecount <= count + '1';end if;end if;end process scan;seg1 : process(clk_slow,rst)beginif(not rst='1') thenscan_num <= "00";elsif(clk_slow'event and clk_slow='1') thenif(scan_num="11") thenscan_num <= "00";elsescan_num <= scan_num + '1';end if;end if;end process seg1;seg2 : process(seg_data_buf)begincase seg_data_buf iswhen "1111" => seg_0 <= "10001110";when "1110" => seg_0 <= "10000110"; when "1101" => seg_0 <= "10100001";when "1100" => seg_0 <= "11000110";when "1011" => seg_0 <= "10000011";when "1010" => seg_0 <= "10011000";when "1001" => seg_0 <= "10010000";when "1000" => seg_0 <= "10000000"; when "0111" => seg_0 <= "11111000"; when "0110" => seg_0 <= "10000010"; when "0101" => seg_0 <= "10010010"; when "0100" => seg_0 <= "10011001"; when "0011" => seg_0 <= "10110000"; when "0010" => seg_0 <= "10100100"; when "0001" => seg_0 <= "11111001"; when "0000" => seg_0 <= "11000000"; when others => seg_0 <= "11111111";end case;end process seg2;seg0 : process(scan_num)begincase scan_num iswhen "00" =>sel_0 <= "1110";seg_data_buf <= ge;when "01" =>sel_0 <= "1101";seg_data_buf <= shi;when "10" =>sel_0 <= "1011";seg_data_buf <= bai;when "11" =>sel_0 <= "0111";seg_data_buf <= qian;when others => null;end case;end process seg0;--数据缓存部分ss : process(clk,rst)beginif(not rst='1') thenclk_sslow <= '0';counter <= (others => '0');elsif(clk'event and clk='1') thenif(counter /= "111111111111111111111110") then counter <= counter + '1';elsecounter <= (others => '0');clk_sslow <= not clk_sslow;end if;end if;end process ss;buf : process(clk_sslow)beginif(clk_sslow'event and clk_sslow='1') thenreaddata_reg_buf <= readdata_reg;elsereaddata_reg_buf <= readdata_reg_buf;end if;end process buf;--蜂鸣器报警部分bep : process(clk,rst)variable count : integer range 0 to 50000; --1KHz方波beginif(not rst='1') thencount := 0;beep_en <= '0';elsif(clk'event and clk='1') thenif(beep_en='1') thencount := count+1;if(count>50000) thencount := 0;beep_buf <= not beep_buf;end if;elseif(not urv_1='1') thenif(readdata_reg>"0000000000000011") thenbeep_en <= '1';end if;elsif(not urv_2='1') thenif(readdata_reg>"1111111111100000") thenbeep_en <= '1';end if;end if;end if;end if;end process bep;end arch_at24c08;（二）测试模块：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity tb is--null;end tb;architecture behv_tb of tb iscomponent at24c08port(clk : in std_logic; --时钟信号rst : in std_logic; --复位信号scl : out std_logic; --i2c时钟线sda : inout std_logic; --i2c数据线urv_1 : in std_logic; --上限值1urv_2 : in std_logic; --上限值2sel : out std_logic_vector(3 downto 0);seg : out std_logic_vector(7 downto 0);beep : out std_logic --蜂鸣器输出信号线);end component;constant clockperiod : time := 20ns;signal clk_tb : std_logic := '0';signal rst_tb : std_logic;signal scl_tb : std_logic;signal sda_tb : std_logic;signal urv_1_tb : std_logic;signal urv_2_tb : std_logic;signal sel_tb : std_logic_vector(3 downto 0);signal seg_tb : std_logic_vector(7 downto 0);signal beep_tb : std_logic;beginmyuit : at24c08 port map(clk => clk_tb,rst => rst_tb,scl => scl_tb,sda => sda_tb,urv_1 => urv_1_tb,urv_2 => urv_2_tb,sel => sel_tb,seg => seg_tb,beep => beep_tb);process(clk_tb)beginclk_tb <= not clk_tb after clockperiod/2;end process;rst_tb <= ‘0',‘1' after 1000ns;end behv_tb;。