CDCLVC1112PW;中文规格书,Datasheet资料
VCS1026中文资料
622.080MHz VCSO FEATURES• Industry Standard 5x7mm SMTFootprint• +3.3 Vdc Supply Voltage• -40°C to 85°C Temp. Range• LVPECL differential outputs• ± 50ppm Absolute Pull Range (APR)• Output Enable/Disable Function• SAW resonator• Extremely Low Jitter• Tape & Reel Packaging• RoHS CompliantDESCRIPTIONSurface mount 5x7mm VCSO operating at3.3V supply with complementary LVPECLoutputs for use in datacom & telecomapplications.ELECTRICAL SPECIFICATIONSParameter Conditions&RemarksMinTypicalMaxUnit Operating ConditionsNominal Frequency f NOM- 622.080 - MHz Operating Temperature Range -40 - 85 °C Storage Temperature Range -55 - 125 °C Supply Voltage V CC; ±5% 3.135 3.300 3.465 VdcSupply Current I cc; Max. V CC; T A = 25°Cload = 50Ω to V CC – 2V- 60 70 mALoad output to V CC – 2V - 50 - ΩFrequency StabilityFrequency vs. Temperature ref to T A = 25°C; V C = constant +20 - -150 ppm Electronic Frequency ControlInput Impedance Z i50 100 - kΩControl Voltage Range V C ; positive monotonic transfer 0.3 - 3.0 Vdc Gain Transfer - 180 - ppm/V Absolute Pull Range APR; all causes (see note 1) ± 50 - - ppm Modulation Bandwidth -3dB ref. 100Hz - 50 - kHz Linearity Deviation from best linear fit - 2 10 % NOTE 1: Minimum guaranteed frequency shift (∆f/f NOM) under all conditions (temperature, aging, supply voltage, load) for 15 years at an average effective operating temperature of +55°C622.080MHz VCSO ELECTRICAL SPECIFICATIONS (Continued)Parameter Conditions&RemarksMinTypicalMaxUnit Output ParametersOutput Signal LVPECLV OL- -V CC-1.620AmplitudeV OH V CC-1.025 - -VdcRise/Fall Times 20% to 80% - 250 400 ps Duty Cycle @ 50% of output signal 45 50 55 % Start up time to reach 90% of final amplitude - - 10 ms100Hz - -85 -75 dBc/Hz1kHz - -110 -100 dBc/Hz10kHz - -140 -130 dBc/Hz100kHz - -143 -140 dBc/Hz Phase Noise1MHz - -143 -140 dBc/Hz12kHz to 20MHz (calculated from Phase Noise) - 0.16 0.3 psRMSPhase Jitter50kHz to 80MHz (calculated from Phase Noise) - 0.16 0.3 psRMSLVPECL OUTPUT WAVEFORM TEST CIRCUIT, LVPECL LOADOUTPUT ENABLE/DISABLE LOGICPad 2 Pad 4 Pad 5Low ”0” outputs disabled HI Z HI ZOpen outputs enabled Output Comp. OutputHigh ”1” outputs enabled Output Comp. Output622.080MHz VCSO622.080MHz VCSOMAXIMUM SOLDERING PROFILETemperature217°C 260°C (Absolute max temperature) Time60-150 sec 10 sec. maxNote: Part is not designed to be reflowed in an inverted position.MSL Level: 1This product is fully compliant to RoHS Directive 2002/95/EC。
1117-_datasheet线性电源LDO
LM1117/LM1117I800mA Low-Dropout Linear RegulatorGeneral DescriptionThe LM1117is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA of load current.It has the same pin-out as National Semiconductor’s industry standard LM317.The LM1117is available in an adjustable version,which can set the output voltage from 1.25V to 13.8V with only two external resistors.In addition,it is also available in five fixed voltages,1.8V,2.5V,2.85V,3.3V,and 5V.The LM1117offers current limiting and thermal shutdown.Its circuit includes a zener trimmed bandgap reference to as-sure output voltage accuracy to within ±1%.The LM1117series is available in LLP ,TO-263,SOT-223,TO-220,and TO-252D-PAK packages.A minimum of 10µF tantalum capacitor is required at the output to improve the transient response and stability.Featuresn Available in 1.8V,2.5V,2.85V,3.3V,5V,and Adjustable Versionsn Space Saving SOT-223and LLP Packages n Current Limiting and Thermal Protection n Output Current 800mA n Line Regulation 0.2%(Max)n Load Regulation 0.4%(Max)n Temperature Range —LM11170˚C to 125˚C —LM1117I −40˚C to 125˚CApplicationsn 2.85V Model for SCSI-2Active Termination n Post Regulator for Switching DC/DC Converter n High Efficiency Linear Regulators n Battery ChargernBattery Powered InstrumentationTypical ApplicationActive Terminator for SCSI-2Bus10091905Fixed Output Regulator10091928June 2004LM1117/LM1117I 800mA Low-Dropout Linear Regulator©2004National Semiconductor Corporation Ordering InformationPackage TemperatureRange Part Number Packaging MarkingTransport Media NSC Drawing 3-lead SOT-2230˚C to +125˚CLM1117MPX-ADJ N03A Tape and Reel MP04ALM1117MPX-1.8N12A Tape and Reel LM1117MPX-2.5N13A Tape and Reel LM1117MPX-2.85N04A Tape and Reel LM1117MPX-3.3N05A Tape and Reel LM1117MPX-5.0N06A Tape and Reel −40˚C to +125˚CLM1117IMPX-ADJ N03B Tape and Reel LM1117IMPX-3.3N05B Tape and Reel LM1117IMPX-5.0N06B Tape and Reel3-lead TO-2200˚C to +125˚CLM1117T-ADJ LM1117T-ADJ Rails T03B LM1117T-1.8LM1117T-1.8Rails LM1117T-2.5LM1117T-2.5Rails LM1117T-2.85LM1117T-2.85Rails LM1117T-3.3LM1117T-3.3Rails LM1117T-5.0LM1117T-5.0Rails 3-lead TO-2520˚C to +125˚CLM1117DTX-ADJ LM1117DT-ADJ Tape and Reel TD03B LM1117DTX-1.8LM1117DT-1.8Tape and Reel LM1117DTX-2.5LM1117DT-2.5Tape and Reel LM1117DTX-2.85LM1117DT-2.85Tape and Reel LM1117DTX-3.3LM1117DT-3.3Tape and Reel LM1117DTX-5.0LM1117DT-5.0Tape and Reel −40˚C to +125˚CLM1117IDTX-ADJ LM1117IDT-ADJ Tape and Reel LM1117IDTX-3.3LM1117IDT-3.3Tape and Reel LM1117IDTX-5.0LM1117IDT-5.0Tape and Reel 8-lead LLP0˚C to +125˚CLM1117LDX-ADJ 1117ADJ Tape and Reel LDC08A LM1117LDX-1.81117-18Tape and Reel LM1117LDX-2.51117-25Tape and Reel LM1117LDX-2.851117-28Tape and Reel LM1117LDX-3.31117-33Tape and Reel LM1117LDX-5.01117-50Tape and Reel −40˚C to 125˚CLM1117ILDX-ADJ 1117IAD Tape and Reel LM1117ILDX-3.31117I33Tape and Reel LM1117ILDX-5.01117I50Tape and Reel TO-2630˚C to +125˚CLM1117SX-ADJ LM1117SADJ Tape and Reel TS3B LM1117SX-2.85LM1117S2.85Tape and Reel LM1117SX-3.3LM1117S3.3Tape and Reel LM1117SX-5.0LM1117S5.0Tape and ReelL M 1117/L M 1117I 2Block Diagram10091901Connection DiagramsSOT-22310091904Top ViewTO-22010091902Top ViewTO-25210091938Top ViewTO-26310091944Top View10091945Side ViewLLP10091946When using the LLP packagePins2,3&4must be connected together andPins5,6&7must be connected togetherTop ViewLM1117/LM1117I3Absolute Maximum Ratings (Note 1)If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.Maximum Input Voltage (V IN to GND)20VPower Dissipation (Note 2)Internally LimitedJunction Temperature (T J )(Note 2)150˚CStorage Temperature Range -65˚C to 150˚CLead TemperatureTO-220(T)Package 260˚C,10sec SOT-223(IMP)Package 260˚C,4secESD Tolerance (Note 3)2000VOperating Ratings (Note 1)Input Voltage (V IN to GND)15VJunction Temperature Range (T J )(Note 2)LM11170˚C to 125˚C LM1117I−40˚C to 125˚CLM1117Electrical CharacteristicsTypicals and limits appearing in normal type apply for T J =25˚C.Limits appearing in Boldface type apply over the entire junc-tion temperature range for operation,0˚C to 125˚C.Symbol Parameter ConditionsMin (Note 5)Typ (Note 4)Max (Note 5)UnitsV REFReference VoltageLM1117-ADJI OUT =10mA,V IN -V OUT =2V,T J =25˚C 10mA ≤I OUT ≤800mA,1.4V ≤V IN -V OUT ≤10V1.2381.2251.2501.2501.2621.270V VV OUTOutput VoltageLM1117-1.8I OUT =10mA,V IN =3.8V,T J =25˚C 0≤I OUT ≤800mA,3.2V ≤V IN ≤10V 1.7821.746 1.8001.800 1.8181.854V V LM1117-2.5I OUT =10mA,V IN =4.5V,T J =25˚C 0≤I OUT ≤800mA,3.9V ≤V IN ≤10V 2.4752.450 2.5002.500 2.5252.550V V LM1117-2.85I OUT =10mA,V IN =4.85V,T J =25˚C 0≤I OUT ≤800mA,4.25V ≤V IN ≤10V 0≤I OUT ≤500mA,V IN =4.10V 2.8202.7902.790 2.8502.8502.850 2.8802.9102.910V V V LM1117-3.3I OUT =10mA,V IN =5V T J =25˚C 0≤I OUT ≤800mA,4.75V ≤V IN ≤10V 3.2673.235 3.3003.300 3.3333.365V V LM1117-5.0I OUT =10mA,V IN =7V,T J =25˚C 0≤I OUT ≤800mA,6.5V ≤V IN ≤12V4.9504.9005.0005.000 5.0505.100V V ∆V OUTLine Regulation (Note 6)LM1117-ADJI OUT =10mA,1.5V ≤V IN -V OUT ≤13.75V 0.0350.2%LM1117-1.8I OUT =0mA,3.2V ≤V IN ≤10V 16mV LM1117-2.5I OUT =0mA,3.9V ≤V IN ≤10V 16mVLM1117-2.85I OUT =0mA,4.25V ≤V IN ≤10V 16mV LM1117-3.3I OUT =0mA,4.75V ≤V IN ≤15V 16mV LM1117-5.0I OUT =0mA,6.5V ≤V IN ≤15V110mVL M 1117/L M 1117I 4LM1117Electrical Characteristics(Continued)Typicals and limits appearing in normal type apply for T J=25˚C.Limits appearing in Boldface type apply over the entire junc-tion temperature range for operation,0˚C to125˚C.Symbol Parameter ConditionsMin(Note5)Typ(Note4)Max(Note5)Units∆V OUT Load Regulation(Note6)LM1117-ADJV IN-V OUT=3V,10≤I OUT≤800mA0.20.4% LM1117-1.8V IN=3.2V,0≤I OUT≤800mA110mVLM1117-2.5V IN=3.9V,0≤I OUT≤800mA110mVLM1117-2.85V IN=4.25V,0≤I OUT≤800mA110mV LM1117-3.3V IN=4.75V,0≤I OUT≤800mA110mV LM1117-5.0V IN=6.5V,0≤I OUT≤800mA115mVV IN-V OUT Dropout Voltage(Note7)I OUT=100mA 1.10 1.20V I OUT=500mA 1.15 1.25V I OUT=800mA 1.20 1.30VI LIMIT Current Limit V IN-V OUT=5V,T J=25˚C80012001500mAMinimum Load Current(Note8)LM1117-ADJV IN=15V 1.75mAQuiescent Current LM1117-1.8V IN≤15V510mALM1117-2.5V IN≤15V510mALM1117-2.85V IN≤10V510mALM1117-3.3V IN≤15V510mALM1117-5.0V IN≤15V510mA Thermal Regulation T A=25˚C,30ms Pulse0.010.1%/W Ripple Regulation f RIPPLE=120Hz,V IN-V OUT=3V V RIPPLE=1V PP6075dB Adjust Pin Current60120µAAdjust Pin Current Change 10≤I OUT≤800mA,1.4V≤V IN-V OUT≤10V0.25µATemperature Stability0.5% Long Term Stability T A=125˚C,1000Hrs0.3% RMS Output Noise(%of V OUT),10Hz≤f≤10kHz0.003%Thermal Resistance Junction-to-Case 3-Lead SOT-22315.0˚C/W 3-Lead TO-220 3.0˚C/W 3-Lead TO-25210˚C/WThermal Resistance Junction-to-Ambient (No air flow)3-Lead SOT-223(No heat sink)136˚C/W3-Lead TO-220(No heat sink)79˚C/W3-Lead TO-252(Note9)(No heat sink)92˚C/W3-Lead TO-26355˚C/W8-Lead LLP(Note10)40˚C/WLM1117/LM1117I5LM1117I Electrical CharacteristicsTypicals and limits appearing in normal type apply for T J =25˚C.Limits appearing in Boldface type apply over the entire junc-tion temperature range for operation,−40˚C to 125˚C.Symbol Parameter ConditionsMin (Note 5)Typ (Note 4)Max (Note 5)UnitsV REFReference VoltageLM1117I-ADJI OUT =10mA,V IN -V OUT =2V,T J =25˚C 10mA ≤I OUT ≤800mA,1.4V ≤V IN -V OUT ≤10V1.2381.2001.2501.2501.2621.290V VV OUTOutput VoltageLM1117I-3.3I OUT =10mA,V IN =5V,T J =25˚C 0≤I OUT ≤800mA,4.75V ≤V IN ≤10V 3.2673.168 3.3003.300 3.3333.432V V LM1117I-5.0I OUT =10mA,V IN =7V,T J =25˚C 0≤I OUT ≤800mA,6.5V ≤V IN ≤12V4.9504.8005.0005.000 5.0505.200V V ∆V OUTLine Regulation (Note 6)LM1117I-ADJI OUT =10mA,1.5V ≤V IN -V OUT ≤13.75V 0.0350.3%LM1117I-3.3I OUT =0mA,4.75V ≤V IN ≤15V 110mV LM1117I-5.0I OUT =0mA,6.5V ≤V IN ≤15V115mV ∆V OUTLoad Regulation (Note 6)LM1117I-ADJV IN -V OUT =3V,10≤I OUT ≤800mA 0.20.5%LM1117I-3.3V IN =4.75V,0≤I OUT ≤800mA 115mV LM1117I-5.0V IN =6.5V,0≤I OUT ≤800mA120mV V IN -V OUTDropout Voltage (Note 7)I OUT =100mA 1.10 1.30V I OUT =500mA 1.15 1.35V I OUT =800mA1.20 1.40V I LIMITCurrent Limit V IN -V OUT =5V,T J =25˚C 80012001500mA Minimum Load Current (Note 8)LM1117I-ADJ V IN =15V 1.75mA Quiescent CurrentLM1117I-3.3V IN ≤15V 515mA LM1117I-5.0V IN ≤15V515mA Thermal Regulation T A =25˚C,30ms Pulse0.010.1%/W Ripple Regulation f RIPPLE =120Hz,V IN -V OUT =3V V RIPPLE =1V PP6075dBAdjust Pin Current 60120µA Adjust Pin Current Change10≤I OUT ≤800mA,1.4V ≤V IN -V OUT ≤10V 0.210µA Temperature Stability 0.5%Long Term Stability T A =125˚C,1000Hrs0.3%RMS Output Noise (%of V OUT ),10Hz ≤f ≤10kHz 0.003%Thermal Resistance Junction-to-Case 3-Lead SOT-22315.0˚C/W 3-Lead TO-25210˚C/W Thermal Resistance Junction-to-Ambient No air flow)3-Lead SOT-223(No heat sink)136˚C/W 3-Lead TO-252(No heat sink)(Note 9)92˚C/W 8-Lead LLP(Note 10)40˚C/WNote 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the device is intended to be functional,but specific performance is not guaranteed.For guaranteed specifications and the test conditions,see the Electrical Characteristics.L M 1117/L M 1117I 6Note 2:The maximum power dissipation is a function of T J(max),θJA ,and T A .The maximum allowable power dissipation at any ambient temperature is P D =(T J(max)–T A )/θJA .All numbers apply for packages soldered directly into a PC board.Note 3:For testing purposes,ESD was applied using human body model,1.5k Ωin series with 100pF.Note 4:Typical Values represent the most likely parametric norm.Note 5:All limits are guaranteed by testing or statistical analysis.Note 6:Load and line regulation are measured at constant junction room temperature.Note 7:The dropout voltage is the input/output differential at which the circuit ceases to regulate against further reduction in input voltage.It is measured when the output voltage has dropped 100mV from the nominal value obtained at V IN =V OUT +1.5V.Note 8:The minimum output current required to maintain regulation.Note 9:Minimum pad size of 0.038in 2Note 10:Thermal Performance for the LLP was obtained using JESD51-7board with six vias and an ambient temperature of 22˚C.For information about improved thermal performance and power dissipation for the LLP ,refer to Application Note AN-1187.Typical Performance CharacteristicsDropout Voltage (V IN -VOUT )Short-Circuit Current1009192210091923Load Regulation LM1117-ADJ Ripple Rejection1009194310091906LM1117/LM1117I7Typical Performance Characteristics(Continued)LM1117-ADJ Ripple Rejection vs.CurrentTemperature Stability1009190710091925Adjust Pin Current LM1117-2.85Load Transient Response1009192610091908LM1117-5.0Load Transient Response LM1117-2.85Line Transient Response1009190910091910L M 1117/L M 1117I 8Typical Performance Characteristics(Continued) LM1117-5.0Line Transient Response10091911Application Note1.0External Capacitors/Stability1.1Input Bypass CapacitorAn input capacitor is recommended.A10µF tantalum on theinput is a suitable input bypassing for almost all applications.1.2Adjust Terminal Bypass CapacitorThe adjust terminal can be bypassed to ground with a by-pass capacitor(C ADJ)to improve ripple rejection.This by-pass capacitor prevents ripple from being amplified as theoutput voltage is increased.At any ripple frequency,theimpedance of the C ADJ should be less than R1to prevent theripple from being amplified:1/(2π*f RIPPLE*C ADJ)<R1The R1is the resistor between the output and the adjust pin.Its value is normally in the range of100-200Ω.For example,with R1=124Ωand f RIPPLE=120Hz,the C ADJ should be>11µF.1.3Output CapacitorThe output capacitor is critical in maintaining regulator sta-bility,and must meet the required conditions for both mini-mum amount of capacitance and ESR(Equivalent Series Resistance).The minimum output capacitance required by the LM1117is10µF,if a tantalum capacitor is used.Any increase of the output capacitance will merely improve the loop stability and transient response.The ESR of the output capacitor should range between0.3Ω-22Ω.In the case of the adjustable regulator,when the C ADJ is used,a larger output capacitance(22µf tantalum)is required.2.0Output VoltageThe LM1117adjustable version develops a1.25V reference voltage,V REF,between the output and the adjust terminal. As shown in Figure1,this voltage is applied across resistor R1to generate a constant current I1.The current I ADJ from the adjust terminal could introduce error to the output.But since it is very small(60µA)compared with the I1and very constant with line and load changes,the error can be ig-nored.The constant current I1then flows through the output set resistor R2and sets the output voltage to the desired level.For fixed voltage devices,R1and R2are integrated inside the devices.3.0Load RegulationThe LM1117regulates the voltage that appears between itsoutput and ground pins,or between its output and adjustpins.In some cases,line resistances can introduce errors tothe voltage across the load.To obtain the best load regula-tion,a few precautions are needed.Figure2,shows a typical application using a fixed outputregulator.The Rt1and Rt2are the line resistances.It isobvious that the V LOAD is less than the V OUT by the sum ofthe voltage drops along the line resistances.In this case,theload regulation seen at the R LOAD would be degraded fromthe data sheet specification.To improve this,the load shouldbe tied directly to the output terminal on the positive side anddirectly tied to the ground terminal on the negative side.10091917FIGURE1.Basic Adjustable RegulatorLM1117/LM1117I9Application Note(Continued)When the adjustable regulator is used (Figure 3),the best performance is obtained with the positive side of the resistor R1tied directly to the output terminal of the regulator rather than near the load.This eliminates line drops from appearing effectively in series with the reference and degrading regu-lation.For example,a 5V regulator with 0.05Ωresistance between the regulator and load will have a load regulation due to line resistance of 0.05Ωx I L .If R1(=125Ω)is con-nected near the load,the effective line resistance will be 0.05Ω(1+R2/R1)or in this case,it is 4times worse.In addition,the ground side of the resistor R2can be returned near the ground of the load to provide remote ground sens-ing and improve load regulation.4.0Protection DiodesUnder normal operation,the LM1117regulators do not need any protection diode.With the adjustable device,the internal resistance between the adjust and output terminals limits the current.No diode is needed to divert the current around the regulator even with capacitor on the adjust terminal.The adjust pin can take a transient signal of ±25V with respect to the output voltage without damaging the device.When a output capacitor is connected to a regulator and the input is shorted to ground,the output capacitor will discharge into the output of the regulator.The discharge current de-pends on the value of the capacitor,the output voltage of the regulator,and rate of decrease of V IN .In the LM1117regu-lators,the internal diode between the output and input pins can withstand microsecond surge currents of 10A to 20A.With an extremely large output capacitor (≥1000µF),and with input instantaneously shorted to ground,the regulator could be damaged.In this case,an external diode is recommended between the output and input pins to protect the regulator,as shown in Figure 4.5.0Heatsink RequirementsWhen an integrated circuit operates with an appreciable current,its junction temperature is elevated.It is important to quantify its thermal limits in order to achieve acceptable performance and reliability.This limit is determined by sum-ming the individual parts consisting of a series of tempera-ture rises from the semiconductor junction to the operating environment.A one-dimensional steady-state model of con-duction heat transfer is demonstrated in Figure 5.The heat generated at the device junction flows through the die to the die attach pad,through the lead frame to the surrounding case material,to the printed circuit board,and eventually to the ambient environment.Below is a list of variables that may affect the thermal resistance and in turn the need for a heatsink.R θJC (ComponentVariables)R θCA (ApplicationVariables)Leadframe Size &Material Mounting Pad Size,Material,&Location No.of Conduction Pins Placement of Mounting PadDie SizePCB Size &Material Die Attach Material Traces Length &Width Molding Compound Size and MaterialAdjacent Heat Sources Volume of Air Ambient Temperatue Shape of Mounting Pad10091918FIGURE 2.Typical Application using Fixed OutputRegulator 10091919FIGURE 3.Best Load Regulation using AdjustableOutput Regulator 10091915FIGURE 4.Regulator with Protection Diode L M 1117/L M 1117I10Application Note(Continued)The LM1117regulators have internal thermal shutdown to protect the device from over-heating.Under all possible operating conditions,the junction temperature of the LM1117must be within the range of 0˚C to 125˚C.A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of the application.To deter-mine if a heatsink is needed,the power dissipated by the regulator,P D ,must be calculated:I IN =I L +I GP D =(V IN -V OUT )I L +V IN I GFigure 6shows the voltages and currents which are present in the circuit.The next parameter which must be calculated is the maxi-mum allowable temperature rise,T R (max):T R (max)=T J (max)-T A (max)where T J (max)is the maximum allowable junction tempera-ture (125˚C),and T A (max)is the maximum ambient tem-perature which will be encountered in the application.Using the calculated values for T R (max)and P D ,the maxi-mum allowable value for the junction-to-ambient thermal resistance (θJA )can be calculated:θJA =T R (max)/P DIf the maximum allowable value for θJA is found to be ≥136˚C/W for SOT-223package or ≥79˚C/W for TO-220package or ≥92˚C/W for TO-252package,no heatsink is needed since the package alone will dissipate enough heat to satisfy these requirements.If the calculated value for θJA falls below these limits,a heatsink is required.As a design aid,Table 1shows the value of the θJA of SOT-223and TO-252for different heatsink area.The copper patterns that we used to measure these θJA s are shown at the end of the Application Notes Section.Figure 7and Figure 8reflects the same test results as what are in the Table 1Figure 9and Figure 10shows the maximum allowable power dissipation vs.ambient temperature for the SOT-223and TO-252device.Figures Figure 11and Figure 12shows the maximum allowable power dissipation vs.copper area (in 2)for the SOT-223and TO-252devices.Please see AN1028for power enhancement techniques to be used with SOT-223and TO-252packages.*Application Note AN-1187discusses improved thermal per-formance and power dissipation for the LLP .TABLE 1.θJA Different Heatsink AreaLayout Copper AreaThermal ResistanceTop Side (in 2)*Bottom Side (in 2)(θJA ,˚C/W)SOT-223(θJA ,˚C/W)TO-25210.0123013610320.0660*******.30846040.530755450.76069526106647700.211584800.49870900.689631000.8825711017957120.0660.06612589130.1750.175937210091937FIGURE 5.Cross-sectional view of Integrated Circuit Mounted on a printed circuit board.Note that the case temperature is measured at the point where the leadscontact with the mounting pad surface 10091916FIGURE 6.Power Dissipation DiagramLM1117/LM1117IApplication Note(Continued)TABLE 1.θJA Different Heatsink Area (Continued)Layout Copper AreaThermal Resistance140.2840.2848361150.3920.3927555160.50.57053*Tab of device attached to topside copperL M 1117/L M 1117IApplication Note(Continued)10091913 FIGURE7.θJA vs.1oz Copper Area for SOT-22310091934 FIGURE8.θJA vs.2oz Copper Area for TO-25210091912 FIGURE9.Maximum Allowable Power Dissipation vs.Ambient Temperature for SOT-22310091936FIGURE10.Maximum Allowable Power Dissipation vs.Ambient Temperature for TO-25210091914FIGURE11.Maximum Allowable Power Dissipation vs.1oz Copper Area for SOT-22310091935FIGURE12.Maximum Allowable Power Dissipation vs.2oz Copper Area for TO-252LM1117/LM1117IApplication Note(Continued)10091941FIGURE 13.Top View of the Thermal Test Pattern in Actual ScaleL M 1117/L M 1117IApplication Note(Continued)10091942FIGURE14.Bottom View of the Thermal Test Pattern in Actual Scale LM1117/LM1117ITypical Application Circuits10091930Adjusting Output of Fixed Regulators10091931Regulator with Reference100919291.25V to 10V Adjustable Regulator with ImprovedRipple Rejection100919275V Logic Regulator with Electronic Shutdown*L M 1117/L M 1117ITypical Application Circuits(Continued)10091932Battery Backed-Up Regulated Supply10091933Low Dropout Negative Supply LM1117/LM1117IPhysical Dimensionsinches (millimeters)unless otherwise noted3-Lead SOT-223NS Package Number MP04A3-Lead TO-220NS Package Number T03BL M 1117/L M 1117IPhysical Dimensions inches(millimeters)unless otherwise noted(Continued)3-Lead TO-263NS Package Number TS3B LM1117/LM1117IPhysical Dimensionsinches (millimeters)unless otherwise noted (Continued)3-Lead TO-252NS Package Number TD03B8-Lead LLPNS Package Number LDC08AL M 1117/L M 1117INotesLIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices orsystems which,(a)are intended for surgical implant into the body,or(b)support or sustain life,and whose failure to perform when properly used in accordance with instructions for use provided in the labeling,can be reasonably expected to result in a significant injury to the user.2.A critical component is any component of a lifesupport device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,or to affect its safety or effectiveness.BANNED SUBSTANCE COMPLIANCENational Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification(CSP-9-111C2)and the Banned Substances and Materials of Interest Specification (CSP-9-111S2)and contain no‘‘Banned Substances’’as defined in CSP-9-111S2.National Semiconductor Americas CustomerSupport CenterEmail:new.feedback@ Tel:1-800-272-9959National SemiconductorEurope Customer Support CenterFax:+49(0)180-5308586Email:europe.support@Deutsch Tel:+49(0)6995086208English Tel:+44(0)8702402171Français Tel:+33(0)141918790National SemiconductorAsia Pacific CustomerSupport CenterEmail:ap.support@National SemiconductorJapan Customer Support CenterFax:81-3-5639-7507Email:jpn.feedback@Tel:81-3-5639-7560 LM1117/LM1117I 800mA Low-Dropout Linear RegulatorNational does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.。
SC1112中文资料
V S µA mV V V V S S µA
VTTINTH DeltaTRACK VIN = 3.30V, IO = 0A
1.45
1.52 200
1.55
V mV
2001 Semtech Corp.
2
元器件交易网
SC1112
POWER MANAGEMENT Electrical Characteristics (Cont.)
500 500
AGP Gate Current
IsourceAGPgate IsinkAGPgate
5VSTBY = 4.75V, Vgate = 3.0V
500 500
ADJ Gate Current
IsourceADJgate IsinkADJgate
5VSTBY = 4.75V, Vgate = 3.0V
500 500
Load Regulation Line Regulation Gain (AOL)(2)
LOADREG LINEREG GAINLDO
VTTIN = 3.30V, IO = 0 to 2A VTTIN = 3.13V to 3.47V, Io = 2A LDOS Output to GATE
V mA
1.5 (Cdelay*SCTH)/ISC 16 650 1.450 1.060 1.330 22 700 1.500 1.085 1.350 (Cdelay*PGTH_1.2)/IPG (Cdelay*PGTH_1.5)/IPG 16 22 28 28 750 1.550 1.110 1.390
GND AGPGATE AGPSEN VTTGATE VTTSEN AGPSEL VTTSEL VTTIN
CDCLVP1212RHAT;CDCLVP1212RHAR;CDCLVP1212EVM;中文规格书,Datasheet资料
VVV V V V VCDCLVP1212 SCAS886B–AUGUST2009–REVISED AUGUST2011 12LVPECL Output,High-Performance Clock BufferCheck for Samples:CDCLVP1212FEATURES DESCRIPTIONThe CDCLVP1212is a highly versatile,low additive •2:12Differential Bufferjitter buffer that can generate12copies of LVPECL •Selectable Clock Inputs Through Control Pin clock outputs from one of two selectable LVPECL,•Universal Inputs Accept LVPECL,LVDS,and LVDS,or LVCMOS inputs for a variety of LVCMOS/LVTTL communication applications.It has a maximum clockfrequency up to2GHz.The CDCLVP1212features •12LVPECL Outputsan on-chip multiplexer(MUX)for selecting one of two •Maximum Clock Frequency:2GHz inputs that can be easily configured solely through a•Maximum Core Current Consumption:88mA control pin.The overall additive jitter performance isless than0.1ps,RMS from10kHz to20MHz,and •Very Low Additive Jitter:<100fs,rms in10-kHzoverall output skew is as low as25ps,making the to20-MHz Offset Rangedevice a perfect choice for use in demanding • 2.375-V to3.6-V Device Power Supply applications.•Maximum Propagation Delay:550psThe CDCLVP1212clock buffer distributes one of two •Maximum Output Skew:25ps selectable clock inputs(IN0,IN1)to12pairs of •LVPECL Reference Voltage,V AC_REF,Available differential LVPECL clock outputs(OUT0,OUT11)with minimum skew for clock distribution.The for Capacitive-Coupled InputsCDCLVP1212can accept two clock sources into an •Industrial Temperature Range:–40°C to+85°Cinput multiplexer.The inputs can be LVPECL,LVDS,•ESD Protection Exceeds2kV(HBM)or LVCMOS/LVTTL.•Available in6-mm×6-mm QFN-40(RHA)The CDCLVP1212is specifically designed for driving Package50-Ωtransmission lines.When driving the inputs insingle-ended mode,the LVPECL bias voltage APPLICATIONS(VAC_REF)should be applied to the unused negativeinput pin.However,for high-speed performance up to •Wireless Communications2GHz,differential mode is strongly recommended.•Telecommunications/NetworkingThe CDCLVP1212is packaged in a small40-pin,•Medical Imaging6-mm x6-mm QFN package and is characterized for •Test and Measurement Equipment operation from–40°C to+85°C.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.All trademarks are the property of their respective owners.PRODUCTION DATA information is current as of publication date.Copyright©2009–2011,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.CDCLVP1212SCAS886B–AUGUST2009–REVISED This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.AVAILABLE OPTIONS(1)T A PACKAGED DEVICES FEATURESCDCLVP1212RHAT40-pin QFN(RHA)package,small tape and reel –40°C to+85°CCDCLVP1212RHAR40-pin QFN(RHA)package,tape and reel(1)For the most current specifications and package information,see the Package Option Addendum located at the end of this data sheet orrefer to our web site at .ABSOLUTE MAXIMUM RATINGS(1)Over operating free-air temperature range(unless otherwise noted).CDCLVP1212UNITV CC Supply voltage range(2)–0.5to4.6VV IN Input voltage range(3)–0.5to V CC+0.5VV OUT Output voltage range(3)–0.5to V CC+0.5VI IN Input current20mAI OUT Output current50mAT A Specified free-air temperature range(no airflow)–40to+85°CT STG Storage temperature range–65to+150°CT J Maximum junction temperature+125°CESD Electrostatic discharge(HBM)2kV (1)Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.These are stress ratingsonly,and functional operation of the device at these or any other conditions beyond those indicated is not implied.Exposure toabsolute-maximum-rated conditions for extended periods may affect device reliability.(2)All supply voltages must be supplied simultaneously.(3)The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. RECOMMENDED OPERATING CONDITIONSOver operating free-air temperature range(unless otherwise noted).CDCLVP1212PARAMETER MIN TYP MAX UNITV CC Supply voltage 2.375 2.50/3.30 3.60VT A Ambient temperature–40+85°C PACKAGE DISSIPATION RATINGS(1)(2)VALUETEST4×4VIASPARAMETER CONDITIONS ON PAD UNIT0LFM36.1°C/WθJA Thermal resistance,junction-to-ambient150LFM30.2°C/W400LFM28.2°C/WθJP(3)Thermal resistance,junction-to-pad 3.58°C/W(1)The package thermal resistance is calculated in accordance with JESD51and JEDEC2S2P(high-K board).(2)Connected to GND with16thermal vias(0.3-mm diameter).(3)θJP(junction-to-pad)is used for the QFN package,because the primary heat flow is from the junction to the GND pad of the QFNpackage.2Submit Documentation Feedback Copyright©2009–2011,Texas Instruments IncorporatedProduct Folder Link(s):CDCLVP1212CDCLVP1212 SCAS886B–AUGUST2009–REVISED AUGUST2011ELECTRICAL CHARACTERISTICS:LVCMOS Input(1)At V CC=2.375V to3.6V and T A=–40°C to+85°C(unless otherwise noted).CDCLVP1212PARAMETER TEST CONDITIONS MIN TYP MAX UNITf IN Input frequency200MHzExternal threshold voltage applied toV th Input threshold voltage 1.1 1.8Vcomplementary inputV IH Input high voltage V th+0.1V CC VV IL Input low voltage0V th–0.1VI IH Input high current V CC=3.6V,V IH=3.6V40μAI IL Input low current V CC=3.6V,V IL=0V–40μAΔV/ΔT Input edge rate20%to80% 1.5V/nsI CAP Input capacitance5pF(1)Figure3and Figure4show dc test setup.ELECTRICAL CHARACTERISTICS:Differential Input(1)At V CC=2.375V to3.6V and T A=–40°C to+85°C(unless otherwise noted).CDCLVP1212PARAMETER TEST CONDITIONS MIN TYP MAX UNITf IN Input frequency Clock input2000MHzf IN≤1.5GHz0.1 1.5VV IN,DIFF,PP Differential input peak-peak voltage1.5GHz≤f IN≤2GHz0.2 1.5VV ICM Input common-mode level 1.0V CC–0.3VI IH Input high current V CC=3.6V,V IH=3.6V40μAI IL Input low current V CC=3.6V,V IL=0V–40μAΔV/ΔT Input edge rate20%to80% 1.5V/nsI CAP Input capacitance5pF(1)Figure5and Figure6show dc test setup.Figure7shows ac test setup.Copyright©2009–2011,Texas Instruments Incorporated Submit Documentation Feedback3Product Folder Link(s):CDCLVP1212CDCLVP1212SCAS886B–AUGUST2009–REVISED ELECTRICAL CHARACTERISTICS:LVPECL Output(1)At V CC=2.375V to2.625V and T A=–40°C to+85°C(unless otherwise noted).CDCLVP1212PARAMETER TEST CONDITIONS MIN TYP MAX UNITV OH Output high voltage V CC–1.26V CC–0.9VV OL Output low voltage V CC–1.7V CC–1.3VV OUT,DIFF,PP Differential output peak-peak voltage f IN≤2GHz0.5 1.35VV AC_REF Input bias voltage(2)I AC_REF=2mA V CC–1.6V CC–1.1VV IN,DIFF,PP=0.1V550pst PD Propagation delayV IN,DIFF,PP=0.3V550pst SK,PP Part-to-part skew150pst SK,O Output skew25psCrossing-point-to-crossing-point distortion,t SK,P Pulse skew(with50%duty cycle input)–5050psf OUT=100MHzf OUT=100MHz,V IN,SE=V CC,V th=1.25V,0.11ps,RMS10kHz to20MHzf OUT=100MHz,V IN,SE=0.9V,0.128ps,RMSV th=1.1V,10kHz to20MHzRandom additive jitter(with50%duty f OUT=2GHz,V IN,DIFF,PP=0.2V,t RJIT0.053ps,RMS cycle input)V ICM=1V,10kHz to20MHzf OUT=100MHz,V IN,DIFF,PP=0.15V,0.093ps,RMSV ICM=1V,10kHz to20MHzf OUT=100MHz,V IN,DIFF,PP=1V,0.092ps,RMSV ICM=1V,10kHz to20MHzt R/t F Output rise/fall time20%to80%200psI EE Supply internal current Outputs unterminated88mAI CC Output and internal supply current All outputs terminated,50Ωto V CC–2468mA(1)Figure8and Figure9show dc and ac test setup.(2)Internally generated bias voltage(V AC_REF)is for3.3-V operation only.It is recommended to apply externally generated bias voltage forV CC<3.0V.4Submit Documentation Feedback Copyright©2009–2011,Texas Instruments IncorporatedProduct Folder Link(s):CDCLVP1212CDCLVP1212 SCAS886B–AUGUST2009–REVISED AUGUST2011ELECTRICAL CHARACTERISTICS:LVPECL Output(1)At V CC=3.0V to3.6V and T A=–40°C to+85°C(unless otherwise noted).CDCLVP1212PARAMETER TEST CONDITIONS MIN TYP MAX UNITV OH Output high voltage V CC–1.26V CC–0.9VV OL Output low voltage V CC–1.7V CC–1.3VV OUT,DIFF,PP Differential output peak-peak voltage f IN≤2GHz0.65 1.35VV AC_REF Input bias voltage I AC_REF=2mA V CC–1.6V CC–1.1VV IN,DIFF,PP=0.1V550pst PD Propagation delayV IN,DIFF,PP=0.3V550pst SK,PP Part-to-part skew150pst SK,O Output skew25psCrossing-point-to-crossing-point distortion,t SK,P Pulse skew(with50%duty cycle input)–5050psf OUT=100MHzf OUT=100MHz,V IN,SE=V CC,V th=1.65V,0.101ps,RMS10kHz to20MHzf OUT=100MHz,V IN,SE=0.9V,0.130ps,RMSV th=1.1V,10kHz to20MHzRandom additive jitter(with50%duty f OUT=2GHz,V IN,DIFF,PP=0.2V,t RJIT0.069ps,RMS cycle input)V ICM=1V,10kHz to20MHzf OUT=100MHz,V IN,DIFF,PP=0.15V,0.094ps,RMSV ICM=1V,10kHz to20MHzf OUT=100MHz,V IN,DIFF,PP=1V,0.094ps,RMSV ICM=1V,10kHz to20MHzt R/t F Output rise/fall time20%to80%200psI EE Supply internal current Outputs unterminated88mAI CC Output and internal supply current All outputs terminated,50Ωto V CC–2468mA(1)Figure8and Figure9show dc and ac test setup.Copyright©2009–2011,Texas Instruments Incorporated Submit Documentation Feedback5Product Folder Link(s):CDCLVP1212CDCLVP1212Thermal Pad(1)12345678910I N _S E LI N P 1I N N 1N CV C CV C CV A C _R E FI N N 0I N P 0OUTN3OUTP3OUTN2OUTP2OUTN1OUTP1OUTN0OUTP0V CCV CC 20191817161514131211O U T P 7O U T P 5G N DO U T P 6O U T P 4O U T N 6O U T N 4O U T N 7O U T N 5G N D 30292827262524232221V CC OUTP8OUTN8OUTP9OUTN9OUTP10OUTN10OUTP11OUTN11V CC31323334353637383940N C CDCLVP1212SCAS886B –AUGUST 2009–REVISED AUGUST 2011PIN CONFIGURATIONRHA PACKAGEQFN-40(TOP VIEW)(1)Thermal pad must be soldered to ground.6Submit Documentation FeedbackCopyright ©2009–2011,Texas Instruments IncorporatedProduct Folder Link(s):CDCLVP1212CDCLVP1212 SCAS886B–AUGUST2009–REVISED AUGUST2011 PIN DESCRIPTIONSCDCLVP1212Pin DescriptionsTERMINAL TERMINAL PULL-UP/NAME NO.TYPE PULLDOWN DESCRIPTION5,6,11,20,V CC Power— 2.5-V/3.3-V supplies for the device31,40GND21,30Ground—Device groundsINP0,INN09,8Input—Differential input pair or single-ended input.Unused input pair can be left floating.Redundant differential input pair or single-ended input.Unused input pair can be INP1,INN12,3Input—left floating.OUTP11,38,39Output—Differential LVPECL output pair no.11.Unused output pair can be left floating.OUTN11OUTP10,36,37Output—Differential LVPECL output pair no.10.Unused output pair can be left floating.OUTN10OUTP9,34,35Output—Differential LVPECL output pair no.9.Unused output pair can be left floating.OUTN9OUTP8,32,33Output—Differential LVPECL output pair no.8.Unused output pair can be left floating.OUTN8OUTP7,28,29Output—Differential LVPECL output pair no.7.Unused output pair can be left floating.OUTN7OUTP6,26,27Output—Differential LVPECL output pair no.6.Unused output pair can be left floating.OUTN6OUTP5,24,25Output—Differential LVPECL output pair no.5.Unused output pair can be left floating.OUTN5OUTP4,22,23Output—Differential LVPECL output pair no.4.Unused output pair can be left floating.OUTN4OUTP3,18,19Output—Differential LVPECL output pair no.3.Unused output pair can be left floating.OUTN3OUTP2,16,17Output—Differential LVPECL output pair no.2.Unused output pair can be left floating.OUTN2OUTP1,14,15Output—Differential LVPECL output pair no.1.Unused output pair can be left floating.OUTN1OUTP012,13Output—Differential LVPECL output pair no.0.Unused output pair can be left floating.OUTN0PulldownIN_SEL1Input MUX select input for input choice(see Table2)(see Table1)Bias voltage output for capacitive coupled inputs.Do not use V AC_REF at V CC< V AC_REF7Output— 3.0V.If used,it is recommended to use a0.1-μF capacitor to GND on this pin.The output current is limited to2mA.NC4,10——Do not connectTable1.Pin CharacteristicsPARAMETER MIN TYP MAX UNITSR PULLDOWN Input pulldown resistor150kΩTable2.Input Selection TableIN_SEL ACTIVE CLOCK INPUT0INP0,INN01INP1,INN1Copyright©2009–2011,Texas Instruments Incorporated Submit Documentation Feedback7Product Folder Link(s):CDCLVP12120.20.40.60.81.01.21.41.62.01.8Frequency (GHz)1.00.90.80.70.60.50.4D i f f e r e n t i a l O u t p u t P e a k -t o -P e a k V o l t a g e (V)0.20.40.60.81.01.21.41.62.01.8Frequency (GHz)1.11.21.31.00.90.80.70.60.50.4D i f f e r e n t i a l O u t p u t P e a k -t o -P e a k V o l t a g e (V )CDCLVP1212SCAS886B –AUGUST 2009–REVISED AUGUST 2011TYPICAL CHARACTERISTICSAt T A =–40°C to +85°C (unless otherwise noted).DIFFERENTIAL OUTPUT PEAK-TO-PEAK VOLTAGEvs FREQUENCYFigure 1.DIFFERENTIAL OUTPUT PEAK-TO-PEAK VOLTAGEvs FREQUENCYFigure 2.8Submit Documentation FeedbackCopyright ©2009–2011,Texas Instruments IncorporatedProduct Folder Link(s):CDCLVP1212VV V thV IHmaxV ILmaxV IHminV ILminV IHV ILV th V V V GNDV CCV V CDCLVP1212SCAS886B –AUGUST 2009–REVISED AUGUST 2011TEST CONFIGURATIONSThis section describes the function of each block for the CDCLVP1212.Figure 3through Figure 9illustrate how the device should be set up for a variety of test configurations.Figure 3.DC-Coupled LVCMOS Input During Device TestFigure 4.V th Variation over LVCMOS LevelsFigure 5.DC-Coupled LVPECL Input During Device TestCopyright ©2009–2011,Texas Instruments Incorporated Submit Documentation Feedback9Product Folder Link(s):CDCLVP1212CDCLVP1212SCAS886B–AUGUST2009–REVISED Figure6.DC-Coupled LVDS Input During Device TestV VFigure7.AC-Coupled Differential Input to DeviceFigure8.LVPECL Output DC Configuration During Device TestFigure9.LVPECL Output AC Configuration During Device Test10Submit Documentation Feedback Copyright©2009–2011,Texas Instruments IncorporatedProduct Folder Link(s):CDCLVP1212分销商库存信息:TICDCLVP1212RHAT CDCLVP1212RHAR CDCLVP1212EVM。
AG6200-MCQ中文规格书
AG6200-MCQHDMI转VGA转换器中文数据表V1.3 QQ176490316 TEL136七023 2221变更历史PS:本中文规格书由第三方翻译软件自动翻译，权威信息请以原厂英文版规格书为准。
索引1.特点和功能描述 (2)管脚映射 (2)管脚说明 (3)2.电气特性 (4)直流规范 (5)交流规格 (6)3.包装和标记规范 (6)标记 (6)包装尺寸 (7)4.参考文献 (7)图片列表图1 HDMI到VGA桥接器的应用程序 (1)图2系统框图 (2)图3 48引脚映射 (2)表格列表表1引脚说明 (4)表2正常运行条件 (4)表3直流电源典型电源特性 (5)表4直流规范 (5)表5数字I/O规范 (5)表6 TMDS输入时间 (6)AG6200-MCQ特征将HDMI 1.4b转换为VGAAG6200支持高达1920x1200@60Hz的视频分辨率：AG6200支持热插拔检测内置晶体，无需外挂晶体。
内置5V至1.2V稳压器核心电压1.2V符合HDCP 1.4规范的片上HDCP引擎集成片上HDCP密钥AG6200支持2通道IIS音频接口AG6200支持1080i分辨率AG6200-MCQ封装（QQ176490316 TEL136********）AG6200-MCQ封装尺寸：48-pin QFN,6 mm x 6 mmAG6200-MCQ温度范围（0℃～+85℃）AG6200-MCQ应用电缆适配器扩展底座、扩展坞AG6200-MCQ概述Algoltek AG6200-MCQ芯片是一个HDMI（高清多媒体接口）到VGA桥接芯片。
它将HDMI信号转换为标准VGA信号它可以在适配器、智能电缆等设备中设计图1 HDMI到VGA网桥的应用1、AG6200-MCQ系统框图和功能描述图2系统框图AG6200-MCQ引脚映射图3 48引脚映射AG6200-MCQ管脚说明Tabl表1引脚说明2、AG6200-MCQ电气特性正常工作条件表2正常运行条件直流规范表3直流电源典型电源规格表4直流电源最大供电规范表5数字I/O规交流规格表6 TMDS输入时间3、AG6200-MCQ包装和标记规范AG6200-MCQ标记AG6200-MCQHDMI 转VGA 转换器 11 / 112020-02-08 AG6200-MCQ 包装尺寸QFN48 QFN48注1。
TPS2412PW中文资料
DEVICE TPS2412 TPS2413
ORDERING INFORMATION(1)
TEMPERATURE
PACKAGE (2)
ORDERING CODE
–40°C to 85°C
PW (TSSOP - 8)
TPS2412PW TPS2413PW
MARKING TPS2412 TPS2413
(1) Add an R suffix to the device type for tape and reel. (2) For the most current package and ordering information, see the Package Option Addendum at the end
Accurate voltage sensing and a programmable turn-off threshold allows operation to be tailored for a wide range of implementations and bus characteristics. The TPS2412/13 are lower pin count, feature reduced versions of the TPS2410/11.
VALUE –0.3 to 18
7.5 18 –0.3 to 30 –0.3 to 13 0.3 –0.3 to 7 Indefinite 2 500 Internally liited –65 to 150
UNIT V V V V V V V
kV V °C °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
HLW8110 HLW8112智能计量IC用户手册说明书
REV 1.191 / 68HLW8110/HLW8112用户手册REV 1.19REV 1.192 / 68智能计量IC1应用领域 ⏹ 智能家电设备 ⏹ 漏电检测设备 ⏹ 计量电表⏹ 计量插座 ⏹ WIFI 插座 ⏹ 充电桩 ⏹ PDU 设备 ⏹ LED 照明 ⏹ 交通路灯REV 1.193 / 682修订历史时间 修改记录版本 2018-03-16 初始版本 REV 1.00 2018-04-10 增加图表附录 REV 1.01 2018-05-25 增加协议资料 REV 1.02 2018-09-26 修改PIN 脚说明 REV 1.05 2018-09-28 重新排版 REV 1.06 2018-12-25 增加相角计算公式 REV 1.07 2019-02-13 修改字体REV 1.08 2019-02-18 更正输入通道信号输入范围值 REV 1.09 2019-02-20 增加B 通道比较器描述 REV 1.10 2019-05-21 电气特性参数修改REV 1.12 2019-10-03 增加UART 复位条件，删除uart 4800bps 设置选项 REV 1.16 2020-03-02 修改漏电检测电路 REV 1.17 2020-08-28 修订版本REV 1.18 2020-11-20 修改原理图，1K 和33NF 变更为100R 和330NF REV 1.19REV 1.194 / 68目录1 应用领域 .........................................................................................................................................2 2 修订历史 .........................................................................................................................................3 3 特性 ................................................................................................................................................. 74 概述 ................................................................................................................................................. 85 功能框图 ......................................................................................................................................... 8 6引脚配置和功能描述 (9)6.1 HLW8110芯片管脚描述 ............................................................................................................ 9 6.2 HLW8110典型应用 .................................................................................................................. 10 6.3 HLW8112芯片管脚描述 .......................................................................................................... 10 6.4HLW8112典型应用 (12)7电气特性 (12)7.1 推荐工作条件 ......................................................................................................................... 12 7.2 模拟特性 ................................................................................................................................. 13 7.3 数字特性 ................................................................................................................................. 14 7.4 极限额定值 ............................................................................................................................. 15 7.5可靠性 (15)8功能概述 (16)8.1 复位系统 ................................................................................................................................. 16 8.2 时钟系统 ................................................................................................................................. 17 8.3 模数转换 ................................................................................................................................. 17 8.4 通道切换 ................................................................................................................................. 18 8.5 有功功率 ................................................................................................................................. 18 8.6 有效值 ..................................................................................................................................... 19 8.7 视在功率和功率因素 ............................................................................................................. 20 8.8 能量计算 ................................................................................................................................. 20 8.9 过零检测、相角、电压频率测量 ......................................................................................... 21 8.10 峰值检测 ................................................................................................................................. 23 8.11 过流、过压、有功功率过载检测 ......................................................................................... 25 8.12 电压聚降检测 ......................................................................................................................... 27 8.13 均值信号 ................................................................................................................................. 29 8.14 瞬时信号和采样波形 ............................................................................................................. 30 8.15 温度传感器 ............................................................................................................................. 30 8.16比较器 (31)9寄存器说明 (32)REV 1.195 / 689.1.1 系统控制寄存器 ............................................................................................................. 34 9.1.2 计量控制寄存器 ............................................................................................................. 35 9.1.3 计量控制寄存器2 .......................................................................................................... 36 9.1.4 脉冲频率寄存器 ............................................................................................................. 37 9.1.5 无负载有功功率（潜动与启动）阈值寄存器PstartPA 、PstartPB ......................... 38 9.1.6 有功功率和视在功率增益校正寄存器 ......................................................................... 38 9.1.7 相位校正寄存器 .............................................................................. 错误！未定义书签。
CDCLVC1310RHBR;CDCLVC1310-EVM;中文规格书,Datasheet资料
CDCLVC1310 SCAS917B–JULY2011–REVISED FEBRUARY2012 Ten-Output Low-Jitter Low-Power Clock BufferCheck for Samples:CDCLVC1310FEATURES APPLICATIONS•High-Performance Crystal Buffer With Ultralow•Wireless and Wired Infrastructure Noise Floor of–169dBc/Hz•Networking and Data Communications •Additive Phase Noise/Jitter Performance Is•Medical Imaging25fs RMS(Typ.)•Portable Test and Measurement•Operates with3.3-V/2.5-V Core and•High-End A/V3.3-V/2.5-V/1.8-V/1.5-V Output Supply•Device inputs consist of primary,secondary DESCRIPTIONand crystal inputs and can be selected The CDCLVC1310is a highly versatile,low-jitter, manually(through pins)using the input MUX.low-power clock fanout buffer which can distribute to The primary and secondary inputs can accept ten low-jitter LVCMOS clock outputs from one of LVPECL,LVDS,HCSL,SSTL or LVCMOS three inputs,whose primary and secondary inputscan feature differential or single-ended signals and signals and crystal input.crystal input.Such a buffer is intended for use in a –Crystal Frequencies Supported Are Fromvariety of mobile and wired infrastructure,data 8MHz to50MHz communication,computing,low-power medical–Differential and Single-Ended Input imaging,and portable test and measurement Frequencies Supported Are up to200MHz applications.When the input is an illegal level,theoutput is at a defined state.The core can be set to •10Single-Ended LVCMOS Outputs.The2.5V or3.3V,and output can be set to1.5V,1.8V,outputs can operate at1.5-V,1.8-V,2.5-V or2.5V or3.3V.The CDCLVC1310can be easily3.3-V Power-Supply Voltage.configured through pin programming.The overall–LVCMOS Outputs Operate up to200MHz additive jitter performance is25fsRMS (typ).TheCDCLVC1310is packaged in a small32-pin5-mm×–Output Skew Is30ps(typ)5-mm QFN package.–Total Propagation Delay Is2ns(typ)–Synchronous and Glitch-Free OutputEnable Is Available•Offered in QFN-325-mm×5-mm Package WithIndustrial Temperature Range of–40°C to85°C•Crystal Input Can Be Overdriven WithLVCMOS Signal up to50MHzPlease be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Copyright©2011–2012,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.XTAL LVCMOSOEDifferential/LVCMOSIN_SEL0/IN_SEL1CDCLVC1310SCAS917B –JULY 2011–REVISED FEBRUARY 2012These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.BLOCK DIAGRAMFigure 1.High-Level Block Diagram of CDCLVC13102Submit Documentation FeedbackCopyright ©2011–2012,Texas Instruments IncorporatedProduct Folder Link(s):CDCLVC1310P0048-18CDCLVC1310RHB Package (Top View)Y9Y0G N DG N DVDDO O EY8I N _S E L 0GND I N _S E L 1Y7S E C _I N PVDDO S E C _I N NY6G N DY5G N DVDDOV D DY1X I NGND X O U TY2P R I _I N PVDDOP R I _I N NY3G N DY4G N DCDCLVC1310SCAS917B –JULY 2011–REVISED FEBRUARY 2012PINOUT DIAGRAMCopyright ©2011–2012,Texas Instruments Incorporated Submit Documentation Feedback3Product Folder Link(s):CDCLVC1310CDCLVC1310SCAS917B–JULY2011–REVISED PIN FUNCTIONSPINI/O TYPE DESCRIPTIONNAME NO(s)4,9,15,16,21,GND PWR Analog Power supply ground25,26,32IN_SEL0,30,29I Digital Input clock selection(pulldown of150kΩ)IN_SEL1OE31I Digital LVCMOS output enable(pulldown of150kΩ)Inverting differential primary reference input,internally biased to Vdd/2(pullup/pulldown PRI_INN14I Analogof150kΩ)PRI_INP13I Analog Non-inverting differential/single-ended primary reference input(pulldown of150kΩ)Inverting differential secondary reference input,internally biased to Vdd/2SEC_INN27I Analog(pullup/pulldown of150kΩ)SEC_INP28I Analog Non-inverting differential/single-ended secondary reference input(pulldown of150kΩ) VDD10PWR Analog Power supply pins2,6,19,VDDO PWR Analog I/O power supply pins23XIN11I Analog Crystal Oscillator Input or XTAL Bypass modeXOUT12I Analog Crystal Oscillator OutputY01O Analog LVCMOS output0Y13O Analog LVCMOS output1Y25O Analog LVCMOS output2Y37O Analog LVCMOS output3Y48O Analog LVCMOS output4Y517O Analog LVCMOS output5Y618O Analog LVCMOS output6Y720O Analog LVCMOS output7Y822O Analog LVCMOS output8Y924O Analog LVCMOS output9Table1.Input SelectionIN_SEL1IN_SEL0INPUT CHOSEN00PRI_IN01SEC_IN10XTAL/overdrive(1)11XTAL bypass(2)(1)This mode can be used to overdrive the XTAL oscillator with anLVCMOS input.For characteristics;see LVCMOS OUTPUTCHARACTERISTICS.(2)This mode is only XTAL bypass.For characteristics,see LVCMOSOUTPUT CHARACTERISTICS.Table2.INPUT/OUTPUT OPERATION(1)INPUT STATE OUTPUT STATEPRI_INx,SEC_INx open Logic LOWPRI_INP/SEC_INP=HIGH,Logic HIGHPRI_INN/SEC_INN=LOWPRI_INP/SEC_INP=LOW,Logic LOWPRI_INN/SEC_INN=HIGH(1)Device must have switching edge to obtain output states.4Submit Documentation Feedback Copyright©2011–2012,Texas Instruments IncorporatedProduct Folder Link(s):CDCLVC1310CDCLVC1310 SCAS917B–JULY2011–REVISED FEBRUARY2012Table3.OE FunctionOE Yx0High-impedance1EnabledABSOLUTE MAXIMUM RATINGS(1)over operating free-air temperature range(unless otherwise noted)VALUE UNIT VDD,VDDO Supply voltage range–0.5to4.6VV IN Input voltage range–0.5to VDD+0.5VV OUT Output voltage range–0.5to VDDO+0.5VI IN Input current±20VI OUT Output current±50VT stg Storage temperature range–65to150°CT J Junction temperature125°C(1)Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.These are stress ratingsonly,and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONSover operating free-air temperature range(unless otherwise noted)MIN NOM MAX UNIT3.135 3.3 3.4652.375 2.5 2.625VDDO Output supply voltage V1.6 1.821.35 1.5 1.653.135 3.3 3.465VDD Core supply voltage V2.375 2.5 2.625I OH High-level output current,LVCMOS–24mAI OL Low-level output current,LVCMOS24mAT A Ambient temperature–4085°CCopyright©2011–2012,Texas Instruments Incorporated Submit Documentation Feedback5Product Folder Link(s):CDCLVC1310CDCLVC1310SCAS917B–JULY2011–REVISED THERMAL INFORMATIONCDCLVC1310THERMAL METRIC(1)RHB UNIT32PINSθJA Junction-to-ambient thermal resistance(2)41.7°C/WθJCtop Junction-to-case(top)thermal resistance(3)34.1°C/WθJB Junction-to-board thermal resistance(4)14.4°C/WψJT Junction-to-top characterization parameter(5)0.9°C/WψJB Junction-to-board characterization parameter(6)14.4°C/WθJCbot Junction-to-case(bottom)thermal resistance(7) 6.2°C/W(1)For more information about traditional and new thermal metrics,see the IC Package Thermal Metrics application report,SPRA953.(2)The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard,high-K board,asspecified in JESD51-7,in an environment described in JESD51-2a.(3)The junction-to-case(top)thermal resistance is obtained by simulating a cold plate test on the package top.No specificJEDEC-standard test exists,but a close description can be found in the ANSI SEMI standard G30-88.(4)The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCBtemperature,as described in JESD51-8.(5)The junction-to-top characterization parameter,ψJT,estimates the junction temperature of a device in a real system and is extractedfrom the simulation data for obtainingθJA,using a procedure described in JESD51-2a(sections6and7).(6)The junction-to-board characterization parameter,ψJB,estimates the junction temperature of a device in a real system and is extractedfrom the simulation data for obtainingθJA,using a procedure described in JESD51-2a(sections6and7).(7)The junction-to-case(bottom)thermal resistance is obtained by simulating a cold plate test on the exposed(power)pad.No specificJEDEC standard test exists,but a close description can be found in the ANSI SEMI standard G30-88.INPUT CHARACTERISTICSover recommended ranges of supply voltage(VDDO≤VDD),load and ambient temperature(unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC Characteristic(OE,IN_SEL0,IN_SEL1,PRI_IN,SEC_IN)I IH Input high current VDD=3.465V,V IH=3.465V40µAI IL Input low current VDD=3.465V,V IL=0V–40µAΔV/ΔT Input edge rate20%–80%2V/nsR Pullup/down Pullup/down resistance150kΩC IN Input capacitance2pF Single-Ended DC Characteristic(PRI_INP,SEC_INP)(1)VDD=3.3V±5%2VDD+0.3V IH Input high voltage VVDD=2.5V±5% 1.6VDD+0.3VDD=3.3V±5%–0.3 1.3V IL Input low voltage VVDD=2.5V±5%–0.30.9Single-Ended DC Characteristic(OE,IN_SEL0,IN_SEL1)V IH Input high voltage0.7×VDD VV IL Input low voltage0.3×VDD V Differential DC Characteristic(PRI_IN,SEC_IN)V I,DIFF Differential input voltage swing(2)0.15 1.3VVDD–V ICM Input common-mode voltage(3)0.5V0.85AC Characteristic(PRI_IN,SEC_IN)f IN Input frequency DC200MHzidc Input duty cycle40%60%(1)PRI/SEC_INN biased to VDD/2(2)V IL should not be less than–0.3V(3)Input common-mode voltage is defined as V IH(see Figure19).6Submit Documentation Feedback Copyright©2011–2012,Texas Instruments IncorporatedProduct Folder Link(s):CDCLVC1310CDCLVC1310 SCAS917B–JULY2011–REVISED FEBRUARY2012CRYSTAL CHARACTERISTICSover recommended ranges of supply voltage,load and ambient temperature(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Equivalent series resistance(ESR)50ΩMaximum shunt capacitance7pF Drive level100µWCRYSTAL OSCILLATOR CHARACTERISTICSover recommended ranges of supply voltage,load and ambient temperature(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Mode of oscillation FundamentalFrequency850MHz Frequency in overdrive mode(1)50MHz Frequency in bypass mode(2)50MHzOn-chip load capacitance12pF(1)Input signal swing(max)=2V;input signal t r/t f(max)=10ns;functional,but ac parameters may not be met.(2)Input signal swing(max)=V DD;input signal t r/t f(max)=10ns;functional,but ac parameters may not be met.Copyright©2011–2012,Texas Instruments Incorporated Submit Documentation Feedback7Product Folder Link(s):CDCLVC1310CDCLVC1310SCAS917B–JULY2011–REVISED LVCMOS OUTPUT CHARACTERISTICSover recommended ranges of supply voltage(VDDO≤VDD),load(50Ωto VDDO/2),and ambient temperature(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITf OUT200MHzVDDO=3.135V 2.5VDDO=2.375V 1.8V OH Output high voltage VVDDO=1.6V 1.15VDDO=1.35V0.95VDDO=3.135V0.5VDDO=2.375V0.4V OL Output low voltage VVDDO=1.6V0.4VDDO=1.35V0.4VDDO=3.3V15VDDO=2.5V20R OUT Output impedanceΩVDDO=1.8V25VDDO=1.5V30t SLEW-RATE Output rise/fall slew rate20%to80%5V/nst SK Output skew3050pst SK,PP Part-to-part skew(1)2nst DELAY Propagation delay2nsSingle-ended input,VDD=3.3V,25VDDO=3.3VSingle-ended input,VDD=2.5V/3.3V,VDDO=1.5V/1.8V/2.5V,f IN/OUT30=125MHzt RJIT System-level additive jitter(2)f S,RMSDifferential input,VDD=3.3V,30VDDO=3.3VDifferential input,VDD=2.5V/3.3V,VDDO=1.5V/1.8V/2.5V,f IN/OUT=30125MHz10-kHz offset(3)–145100-kHz offset(3)–1561-MHz offset(3)–16310-MHz offset(3)–16420-MHz offset(3)–164NF Noise floor dBc/Hz10-kHz offset(4)–145100-kHz offset(4)–1551-MHz offset(4)–16010-MHz offset(4)–16120-MHz offset(4)–162odc Output duty cycle f IN/OUT=125MHz,idc=50%(5)45%55%t EN Output enable/disable time2CycleMUX ISOLATMUX isolation(6)125MHz55dBION(1)Part-to-part skew is calculated as the difference between the fastest and the slowest t pd across multiple devices.(2)Integration range:12kHz–20MHz;input source see Application Information(3)Single-ended input,f IN/OUT=125MHz,VDD=VDDO=3.3V(4)Differential input,f IN/OUT=125MHz,VDD=VDDO=3.3V(5)Stable V IH,V IL,and V CM(6)See Figure18.8Submit Documentation Feedback Copyright©2011–2012,Texas Instruments IncorporatedProduct Folder Link(s):CDCLVC1310CDCLVC1310 SCAS917B–JULY2011–REVISED FEBRUARY2012PHASE NOISE WITH XTAL(1)SELECTEDVDD=VDDO=2.5V/3.3V,f XTAL=25MHz,T A=25°C(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITIB=12kHz to5MHz,VDD=VDDO80=3.3VJrms RMS phase jitter ps rmsIB=12kHz to5MHz,VDD=VDDO115=2.5Vf offset=100Hz,VDD=VDDO=3.3–92Vf offset=1kHz,VDD=VDDO=3.3V–137f offset=10kHz,VDD=VDDO=3.3–163Vf offset=100kHz,VDD=VDDO=3.3–168Vf offset=1MHz,VDD=VDDO=3.3–168Vf offset=5MHz,VDD=VDDO=3.3–169VPN Phase noise(see Figure15)dBc/Hzf offset=100Hz,VDD=VDDO=2.5–91Vf offset=1kHz,VDD=VDDO=2.5V–136f offset=10kHz,VDD=VDDO=2.5–159Vf offset=100kHz,VDD=VDDO=2.5–164Vf offset=1MHz,VDD=VDDO=2.5–165Vf offset=5MHz,VDD=VDDO=2.5–165V(1)Crystal specification:C L=18pF;ESR=35Ω(max);C0=7pF;drive level=100µW(max)DEVICE CURRENT CONSUMPTIONover recommended ranges of supply voltage,load and ambient temperature(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OVERALL PARAMETERS FOR ALL VERSIONSOE=0V or V DD;Ref.input(PRI/SEC)=0V or V DD;14I O=0mA;V DD/V DDO=3.3VI DD Static device current(1)mAOE=0V or V DD;Ref.input(PRI/SEC)=0V or V DD;8I O=0mA;V DD/V DDO=2.5VI DD,XTAL Device current with XTAL input(1)20mAVDDO=3.465V;f=100MHz8.8VDDO=2.625V;f=100MHz7.7 Power dissipation capacitance perC PD pFoutput(2)VDDO=2V;f=100MHz7.3VDDO=1.65V;f=100MHz 6.9(1)I DD and I DD,XTAL is the current through V DD;outputs on or in the high-impedance state;no load.(2)This is the formula for the power dissipation calculation(see Power Consideration section)I DD,Total=I DD+I DD,Cload+I DD,dyn[mA]I DD,dyn=C PD×V DDO×f×n[mA]I DD,Cload=C load×V DDO×f×n[mA]n=Number of switching output pinsCopyright©2011–2012,Texas Instruments Incorporated Submit Documentation Feedback9Product Folder Link(s):CDCLVC1310R=50from measurement equipmentWCDCLVC1310SCAS917B –JULY 2011–REVISED FEBRUARY 2012TEST CONFIGURATIONSFigure 2through Figure 8illustrate how the device should be set up for a variety of test configurations.Figure 2.LVCMOS Output DC Configuration;Test Load CircuitFigure 3.LVCMOS Input DC Configuration During Device TestFigure 4.LVPECL Input Configuration During Device Test10Submit Documentation FeedbackCopyright ©2011–2012,Texas Instruments IncorporatedProduct Folder Link(s):CDCLVC1310分销商库存信息:TICDCLVC1310RHBR CDCLVC1310-EVM。
IRMCK311TR;中文规格书,Datasheet资料
Data Sheet No. PD60338IRMCK311 Dual Channel Sensorless Motor Control IC forAppliancesFeaturesMCE TM (Motion Control Engine) - Hardware based computation engine for high efficiency sinusoidal sensorless control of permanent magnet AC motor Integrated Power Factor Correction controlSupports both interior and surface permanent magnet motorsBuilt-in hardware peripheral for single shunt current feedback reconstructionNo external current or voltage sensing operational amplifier requiredDual channel three/two-phase Space Vector PWM Three-channel analog output (PWM)Embedded 8-bit high speed microcontroller (8051) for flexible I/O and man-machine controlJTAG programming port for emulation/debugger Two serial communication interface (UART)I2C/SPI serial interfaceWatchdog timer with independent analog clockThree general purpose timers/countersTwo special timers: periodic timer, capture timer Internal ‘One-Time Programmable’ (OTP) memory and internal RAM for final production usagePin compatible with IRMCF311 RAM version1.8V/3.3V CMOS Product SummaryMaximum crystal frequency 60 MHz Maximum internal clock (SYSCLK) frequency 128 MHz Maximum 8051 clock frequency 33 MHz Sensorless control computation time 11 μsec typ MCE TM computation data range 16 bit signed 8051 OTP Program memory 56K bytes MCE program and Data RAM 8K bytes GateKill latency (digital filtered) 2 μsec PWM carrier frequency counter 16 bits/ SYSCLK A/D input channels 6 A/D converter resolution 12 bits A/D converter conversion speed 2 μsec 8051 instruction execution speed 2 SYSCLK Analog output (PWM) resolution 8 bits UART baud rate (typ) 57.6K bps Number of I/O (max) 14 Package (lead-free) QFP64 Operating temperature -40°C ~ 85°CDescriptionIRMCK311 is a high performance OTP based motion control IC designed primarily for appliance applications. IRMCK311 is designed to achieve low cost and high performance control solutions for advanced inverterized appliance motor control. IRMCK311 contains two computation engines. One is Motion Control Engine (MCE TM) for sensorless control of permanent magnet motors; the other is an 8-bit high-speed microcontroller (8051). Both computation engines are integrated into one monolithic chip. The MCE TM contains a collection of control elements such as Proportional plus Integral, Vector rotator, Angle estimator, Multiply/Divide, Low loss SVPWM, Single Shunt IFB. The user can program a motion control algorithm by connecting these control elements using a graphic compiler. Key components of the sensorless control algorithms, such as the Angle Estimator, are provided as complete pre-defined control blocks implemented in hardware. A unique analog/digital circuit and algorithm to fully support single shunt current reconstruction is also provided. The 8051 microcontroller performs 2-cycle instruction execution (16MIPS at 33MHz). The MCE and 8051 microcontroller are connected via dual port RAM to process signal monitoring and command input. An advanced graphic compiler for the MCE TM is seamlessly integrated into the MATLAB/Simulink environment, while third party JTAG based emulator tools are supported for 8051 developments. IRMCK311 comes with a small QFP64 pin lead-free package.TABLE OF CONTENTS1 Overview (5)2 IRMCK311 Block Diagram and Main Functions (6)3 Pinout (8)4 Input/Output of IRMCK311 (9)4.1 8051 Peripheral Interface Group (10)4.2 Motion Peripheral Interface Group (10)4.3 Analog Interface Group (11)4.4 Power Interface Group (11)4.5 Test Interface (12)5 Application Connections (13)6 DC Characteristics (14)6.1 Absolute Maximum Ratings (14)6.2 System Clock Frequency and Power Consumption (14)6.3 Digital I/O DC Characteristics (15)6.4 PLL and Oscillator DC Characteristics (15)6.5 Analog I/O DC Characteristics (16)6.6 Under Voltage Lockout DC Characteristics (17)6.7 AREF Characteristics (17)7 AC Characteristics (18)7.1 PLL AC Characteristics (18)7.2 Analog to Digital Converter AC Characteristics (19)7.3 Op Amp AC Characteristics (19)7.4 SYNC to SVPWM and A/D Conversion AC Timing (20)7.5 GATEKILL to SVPWM AC Timing (21)7.6 Interrupt AC Timing (21)7.7 I2C AC Timing (22)7.8 SPI AC Timing (23)7.8.1 SPI Write AC timing (23)7.8.2 SPI Read AC Timing (24)7.9 UART AC Timing (25)7.10 CAPTURE Input AC Timing (26)7.11 JTAG AC Timing (27)7.12 OTP Programming Timing (28)8 I/O Structure (29)9 Pin List (32)Dimensions (35)10 Package11 Part Marking Information (36)Information (36)12 OrderingTABLE OF FIGURESFigure 1. Typical Application Block Diagram Using IRMCK311 (5)Figure 2. IRMCK311 Internal Block Diagram (6)Figure 3. IRMCK311 Pin Configuration (8)Figure 4. Input/Output of IRMCK311 (9)Figure 5. Application Connection of IRMCK311 (13)Figure 6. Clock Frequency vs. Power Consumption (14)Figure 7 Crystal oscillator circuit (18)Figure 8 Voltage droop of sample and hold (19)Figure 9 SYNC to SVPWM and A/D conversion AC Timing (20)Figure 10 GATEKILL to SVPWM AC Timing (21)Figure 11 Interrupt AC Timing (21)Figure 12 I2C AC Timing (22)Figure 13 SPI AC Timing (23)Figure 14 SPI Read AC Timing (24)Figure 15 UART AC Timing (25)Figure 16 CAPTURE Input AC Timing (26)Figure 17 JTAG AC Timing (27)Figure 18 OTP Programming Timing (28)Figure 19 All digital I/O except motor PWM output (29)Figure 20 RESET, GATEKILL I/O (29)Figure 21 Analog input (30)Figure 22 Analog operational amplifier output and AREF I/O structure (30)Figure 23 VPP programming pin I/O structure (30)Figure 24 VSS and AVSS pin structure (31)Figure 25 VDD1 and VDDCAP pin structure (31)Figure 26 XTAL0/XTAL1 pins structure (31)TABLE OF TABLESTable 1. Absolute Maximum Ratings (14)Table 2. System Clock Frequency (14)Table 3. Digital I/O DC Characteristics (15)Table 4. PLL DC Characteristics (15)Table 5. Analog I/O DC Characteristics (16)Table 6. UVcc DC Characteristics (17)Table 7. AREF DC Characteristics (17)Table 8. PLL AC Characteristics (18)Table 9. A/D Converter AC Characteristics (19)Table 10. Current Sensing OP Amp AC Characteristics (19)Table 11. SYNC AC Characteristics (20)Table 12. GATEKILL to SVPWM AC Timing (21)Table 13. Interrupt AC Timing (21)Table 14. I2C AC Timing (22)Table 15. SPI Write AC Timing (23)Table 16. SPI Read AC Timing (24)Table 17. UART AC Timing (25)Table 18. CAPTURE AC Timing (26)Table 19. JTAG AC Timing (27)Table 20. OTP Programming Timing (28)Table 21. Pin List (32)1 OverviewIRMCK311 is a new International Rectifier integrated circuit device primarily designed as a one-chip solution for complete inverter controlled appliance dual motor control applications. Unlike a traditional microcontroller or DSP, the IRMCK311 provides a built-in closed loop sensorless control algorithm using the unique Motion Control Engine (MCE TM) for permanent magnet motors. The MCE TM consists of a collection of control elements, motion peripherals, a dedicated motion control sequencer and dual port RAM to map internal signal nodes. IRMCK311 also employs a unique single shunt current reconstruction circuit to eliminate additional analog/digital circuitry and enables a direct shunt resistor interface to the IC. The sensorless control is the same for both motors with a single shunt current sensing capability. Motion control programming is achieved using a dedicated graphical compiler integrated into the MATLAB/Simulink TM development environment. Sequencing, user interface, host communication, and upper layer control tasks can be implemented in the 8051 high-speed 8-bit microcontroller. The 8051 microcontroller is equipped with a JTAG port to facilitate emulation and debugging tools. Figure 1 shows a typical application schematic using IRMCK311.IRMCK311 is intended for volume production purpose and contains 64K bytes of OTP (One Time Programming) ROM, which can be programmed through a JTAG port. For a development purpose use, IRMCF311 contains a 48k byte of RAM in place of program OTP to facilitate an application development work. Both IRMCF311 and IRMCK311 come in the same 64-pin QFP package with identical pin configuration to facilitate PC board layout and transition to mass productionFigure 1. Typical Application Block Diagram Using IRMCK3112 IRMCK311 Block Diagram and Main FunctionsM o t i o n C o n t r o l B u sFigure 2. IRMCK311 Internal Block DiagramIRMCK311 contains the following functions for sensorless AC motor control applications:• Motion Control Engine (MCE TM )o Proportional plus Integral block o Low pass filtero Differentiator and lag (high pass filter) o Ramp o Limito Angle estimate (sensorless control) o Inverse Clark transformation o Vector rotator o Bit latch o Peak detect o Transitiono Multiply-divide (signed and unsigned)o Divide (signed and unsigned)o Addero Subtractoro Comparatoro Countero Accumulatoro Switcho Shifto ATAN (arc tangent)o Function block (any curve fitting, nonlinear function)o16-bit wide Logic operations (AND, OR, XOR, NOT, NEGATE)o MCE TM program and data memory (6K byte). Note 1o MCE TM control sequencer• 8051 microcontrollero Three 16-bit timer/counterso16-bit periodic timero16-bit analog watchdog timero16-bit capture timero Up to 36 discrete I/Oso Eleven-channel 12-bit A/DFive buffered channels (0 – 1.2V input)One unbuffered channel (0 – 1.2V input)o JTAG port (4 pins)o Up to three channels of analog output (8-bit PWM)o Two UARTo I2C/SPI porto 64K byte Note 1program One-Time Programmable memoryo2K byte data RAM. Note 2Note 1: Total size of OTP memory is 64K byte, however MCE program occupiesmaximum 8K byte which will be loaded into internal RAM at a powerup/bootprocess. Therefore only 56K byte OTP memory area is usable for 8051microcontroller.Note 2: Total size of RAM is 8K byte including MCE program, MCE data, and 8051data. Different sizes can be allocated depending on applications.3 PinoutXTAL0XTAL1P1.1/RXD P1.2/TXDVDD1VSS VDD2P1.3/SYNC/SCKP1.4/CAPP 3.6/R X D 1P 3.7/T X D 1FPWMVL FPWMUL V S SV D D 2A V D DA V S SA I N 0A R E FP 2.7/A O P W M 1P 2.6/A O P W M 0CPWMUH CPWMVH CPWMWH CPWMUL CPWMVL CPWMWL CGATEKILL VDD1VSS I F B C OI F B C +I F B C -P L L V S SP L L V D DR E S E TN CT C KP 5.3/T D IP 5.2/T D OP 5.1/T M SS D A /C S 0S C L /S O -S I /V P PP 5.0/P F C G K I L LP F C P W M V S SFGATEKILL FPWMWL VAC-VAC+VACO IPFCO IPFC+IPFC-I F B F OI F B F +I F B F -P3.0/INT2/CS1C M E X TFPWMVH FPWMUHFPWMWH A I N 1P 3.2/I N T 0Figure 3. IRMCK311 Pin Configuration4 Input/Output of IRMCK311All I/O signals of IRMCK311 are shown in Figure 4. All I/O pins are 3.3V logic interface except A/D interface pins.Figure 4. Input/Output of IRMCK3114.1 8051 Peripheral Interface GroupUART InterfaceP1.1/RXD Input, Receive data to IRMCK311, can be configured as P1.1P1.2/TXD Output, Transmit data from IRMCK311, can be configured as P1.22nd channel Receive data to IRMCK311, can be configured as P3.6 P3.6/RXD1 Input,P3.7/TXD1 Output,2nd channel Transmit data from IRMCK311, can be configured as P3.7Discrete I/O InterfaceP1.3/SYNC/SCK Input/output port 1.3, can be configured as SYNC output or SPI clock P1.4/CAP Input/output port 1.4, can be configured as Capture Timer inputP3.0/INT2/CS1 Input/output port 3.0, can be configured as external interrupt 2 or SPIchip select 1P3.2/INT0 Input/output port 3.2, can be configured as external interrupt 0Analog Output InterfaceP2.6/AOPWM0 Input/output, can be configured as 8-bit PWM output 0 withprogrammable carrier frequencyP2.7/AOPWM1 Input/output, can be configured as 8-bit PWM output 1 withprogrammable carrier frequencyCrystal InterfaceXTAL0 Input, connected to crystalXTAL1 Output, connected to crystalReset InterfaceRESET Inout, system reset, needs to be pulled up to VDD1 but doesn’t requireexternal RC time constantI2C/SPI InterfaceSCL/SO-SI/VPP Output, I2C clock output, SPI SO-SII2C Data line, Chip Select 0 of SPISDA/CS0 Input/output,P3.0/INT2/CS1 Input/output port 3.0, can be configured as external interrupt 2 or SPIchip select 1P1.3/SYNC/SCK Input/output port 1.3, can be configured as SYNC output or SPI clock 4.2 Motion Peripheral Interface GroupPWMCPWMUH Output, motor 1 PWM phase U high side gate signalCPWMUL Output, motor 1 PWM phase U low side gate signalCPWMVH Output, motor 1 PWM phase V high side gate signalCPWMVL Output, motor 1 PWM phase V low side gate signalCPWMWH Output, motor 1 PWM phase W high side gate signalCPWMWL Output, motor 1 PWM phase W low side gate signalFPWMUH Output, motor 2 PWM phase U high side gate signalFPWMUL Output, motor 2 PWM phase U low side gate signal分销商库存信息: IRIRMCK311TR。
MIW1123中文资料
Dual OutputSingle OutputBlock DiagramMIW1100-Series power modules are low-profiledc-dc converters that operate over input voltage ranges of4.5-9VDC, 9-18VDC, 18-36VDC and 36-75VDC and provide precisely regulated output voltages of 5V, 12V, 15V, {12V and {15V.The -40] to +71] operating temperature range makes it ideal for data communication equipments, mobile battery driven equipments, distributed power systems, telecommunicationequipments, mixed analog/digital subsystems, process/machinecontrol equipments, computer peripheral systems and industrial robot systems.The modules have a maximum power rating of 3W and a typical full-load efficiency of 81%, continuous short circuit, 60mA output ripple, built-in filtering for both input and output minimizes the need for external filtering.y MTBF > 1,000,000 Hoursy EMI Complies With EN55022 Class A y Short Circuit Protectiony SMT Technologyy Industry Standard Pinout y I/O Isolation 500VDC y 2:1 Input Rangey High Efficiency up to 81%Key FeaturesSingle and Dual Outputs3 Watts 2 :1 Wide Input Range DC/DC ConvertersMIW1100 SeriesTOTAL POWER INT'L8177{10{100{15MIW11458177{12.5{125{12MIW114481772020015MIW114381772525012MIW1142771038160600548( 36 ~ 75 )MIW114181154{10{100{15MIW113581154{12.5{125{12MIW1134811542020015MIW1133811542525012MIW11327715516260600524( 18 ~ 36 )MIW113180313{10{100{15MIW112580313{12.5{125{12MIW1124803132020015MIW1123803132525012MIW112276302032960600512( 9 ~ 18 )MIW112174811{10{100{15MIW111574811{12.5{125{12MIW1114748112020015MIW1113748112525012MIW111270100408576060055( 4.5 ~ 9 )MIW1111% (Typ.)mA (Typ.)mA (Typ.)mA (Typ.)mA mA VDC VDC@Max. Load @No Load @Max. Load Min.Max.EfficiencyReflected Ripple Current Input CurrentOutput CurrentOutput VoltageInput VoltageModel NumberModel Selection GuideEN55022 Class AConducted EMIFree-Air Convection Cooling%95---Humidity ]+125-40Storage Temperature ]+90-40CaseOperating Temperature ]+71-40Ambient Operating Temperature Unit Max.Min.Conditions ParameterEnvironmental SpecificationsExceeding these values can damage the module. These are not continuous operating ratings.mW2,500---Internal Power Dissipation]260---Lead Temperature (1.5mm from case for 10 Sec.)VDC 100-0.748VDC Input ModelsVDC 50-0.724VDC Input ModelsVDC 25-0.712VDC Input Models VDC 11-0.75VDC Input Models Input Surge Voltage( 1000 mS )Unit Max.Min.ParameterNote :1. Specifications typical at Ta=+25], resistive load,nominal input voltage, rated output current unless otherwise noted.2. Transient recovery time is measured to within 1%error band for a step change in output load of 75%to 100%.3. Ripple & Noise measurement bandwidth is 0-20MHz.4. These power converters require a minimum output loading to maintain specified regulation.5. Operation under no-load conditions will not damage these devices; however they may not meet all listed specifications.6. All DC/DC converters should be externally fused at the front end for protection.7. Other input and output voltage may be available,please contact factory.8. Specifications subject to change without notice.Absolute Maximum RatingsMIW1100 SeriesK Hours------1000MIL-HDBK-217F @ 25], Ground BenignMTBFKHz ---300---Switching Frequency pF 500------100KHz,1VIsolation Capacitance M[------1000500VDC Isolation Resistance VDC ------550Flash Tested for 1 SecondIsolation Test Voltage VDC ------50060 SecondsIsolation Voltage Unit Max.Typ.Min.Conditions ParameterGeneral SpecificationsContinuousOutput Short Circuit%/]{0.02{0.01---Temperature Coefficient %{5{3---Transient Response Deviation uS 500300---25% Load Step Change Transient Recovery Time %------120Over Power Protection mV rms.15------Ripple & Noise (20MHz)mV P-P 100------Over Line,Load & Temp Ripple & Noise (20MHz)mV P-P 6045---Ripple & Noise (20MHz)%{0.5{0.2---Io=10% to 100%Load Regulation %{0.5{0.2---Vin=Min. to Max.Line Regulation %{2.0{0.5---Dual Output Balance LoadOutput Voltage Balance %{2.0{0.5---Output Voltage Accuracy Unit Max.Typ.Min.ConditionsParameterOutput SpecificationsPi FilterInput FiltermW 15001000---Short Circuit Input Power A 1------All ModelsReverse Polarity Input Current 3422---48V Input Models1711---24V Input Models 8.56.5---12V Input Models 43.5---5V Input Models Under Voltage Shortdown36241648V Input Models1812824V Input Models 974.512V Input Models VDC 4.543.55V Input Models Start VoltageUnitMax.Typ.Min.Model ParameterInput SpecificationsNote: # For each output .uF10001000200020002000Maximum Capacitive Load Unit {15V #{12V #15V 12V 5V Models by Vout Capacitive LoadMIW1100 Series135mA Slow - Blow Type350mA Slow - Blow Type700mA Slow - Blow Type1500mA Slow - Blow Type48V Input Models 24V Input Models 12V Input Models 5V Input Models Input Fuse Selection GuideInput Voltage Transient RatingMIW1100 SeriesMIW1100 SeriesTest ConfigurationsInput Reflected-Ripple Current Test SetupLin (4.7uH) and Cin (220uF, ESR < 1.0[ at 100 KHz) to simulate source impedance.Capacitor Cin, offsets possible battery impedance.Current ripple is measured at the input terminals of the module, measurement bandwidth is 0-500 KHz.Peak-to-Peak Output Noise Measurement TestUse a Cout 0.47uF ceramic capacitor.Scope measurement should be made by using a BNC socket, measurement bandwidth is 0-20 MHz. Position the load between 50 mm and 75 mm from the DC/DC Converter.Design & Feature ConsiderationsMaximum Capacitive LoadThe MIW1100 series has limitation of maximum connected capacitance at the output.The power module may be operated in current limiting mode during start-up, affecting the ramp-up and the startup time.For optimum performance we recommend 1000uF maximum capacitive load for dual outputs and 2000u F capacitive load for single outputs.The maximum capacitance can be found in the data .Overcurrent ProtectionTo provide protection in a fault (output overload) condition,the unit is equipped with internal current limiting circuitry and can endure current limiting for an unlimited duration. At the point of current-limit inception, the unit shifts from voltage control to current control. The unit operates normally once the output current is brought back into its specified range.Input Source ImpedanceThe power module should be connected to a low ac-impedance input source. Highly inductive source impedances can affect the stability of the power module.In applications where power is supplied over long lines and output loading is high, it may be necessary to use a capacitor at the input to ensure startup.Capacitor mounted close to the power module helps ensure stability of the unit, it is recommended to use a good quality low Equivalent Series Resistance (ESR < 1.0[ at 100KHz) capacitor of a 8.2uF for the 5V input devices, a 3.3uF for the 12V input devices and a 1.5uF for the 24V and 48V devices.A good quality low ESR capacitor placed as close as practicable across the load will give the best ripple and noise performance.To reduce output ripple, it is recommended to use 3.3uF capacitors at the output.MIW1100 SeriesMIW1100 Series Thermal ConsiderationsMany conditions affect the thermal performance of the power module, such as orientation, airflow over the module and board spacing. To avoid exceeding the maximum temperature rating of the components inside the power module, the case temperature must be kept below 90°C.The derating curves are determined from measurements obtained in an experimental apparatus.Units are encapsulated in a low thermal resistance molding compound which has excellent chemical resistance and electrical properties in high humidity environment and over a wide operating temperature range.The encapsulant and outer shell of the unit have UL94V-0 ratings. The leads are golden plated for better soldering.NC: No Connection+Vin+Vin24-Vout NC 23Common NC 22Common -Vout 15+Vout +Vout 14UL94V-0:Flammability-Vin -Vin 13-Vin -Vin 1212.4g :Weight +Vout +Vout 11Common -Vout 10Non-Conductive Black Plastic :Case Material Common NC 3-Vout NC 2 1.25*0.8*0.4 inches+Vin +Vin 131.8*20.3*10.2 mm :Case Size Dual OutputSingle OutputPin Physical CharacteristicsPin ConnectionsConnecting Pin PatternsTop View ( 2.54 mm / 0.1 inch grids )Mechanical DataMIW 1100 Series。
SFH 221;中文规格书,Datasheet资料
SFH 221Silizium-Differential-Fotodiode Silicon Differential PhotodiodeLead (Pb) Free Product - RoHS Compliant2007-04-031Wesentliche Merkmale•Speziell geeignet für Anwendungen im Bereich von 400 nm bis 1100 nm •Hohe Fotoempfindlichkeit•Hermetisch dichte Metallbauform (ähnlich TO-5), geeignet bis 125 °C 1)•Doppeldiode von extrem hoher Gleichmäβigkeit Anwendungen •Nachlaufsteuerungen •Kantenführung •Industrieelektronik•…Messen/Steuern/Regeln“1)Eine Abstimmung der Einsatzbedingungen mit dem Hersteller wird empfohlen bei T A > 85 °C1)For operating conditions of T A > 85 °C please contact us.Typ Type Bestellnummer Ordering Code SFH 221Q62702P0270Features•Especially suitable for applications from 400 nm to 1100 nm •High photosensitivity•Hermetically sealed metal package (similar to TO-5), suitable up to 125 °C 1)•Double diode with extremely high homogeneousness Applications •Follow-up controls •Edge drives•Industrial electronics•For control and drive circuitsGrenzwerte Maximum RatingsBezeichnung Parameter SymbolSymbolWertValueEinheitUnitBetriebs- und Lagertemperatur Operating and storage temperature range Top; T stg– 40 … + 125°CSperrspannung Reverse voltage VR10VIsolationsspannung gegen Gehäuse Insulation voltage vs. package VIS100VVerlustleistung, T A = 25 °C Total power dissipation Ptot50mWKennwerte (T A = 25 °C, Normlicht A, T = 2856 K) für jede Einzeldiode Characteristics (T A = 25 °C, standard light A, T = 2856 K) per single diodeBezeichnung Parameter SymbolSymbolWertValueEinheitUnitFotoempfindlichkeit, V R = 5 VSpectral sensitivityS24 (≥ 15)nA/IxWellenlänge der max. FotoempfindlichkeitWavelength of max. sensitivityλS max900nmSpektraler Bereich der FotoempfindlichkeitS = 10% von SmaxSpectral range of sensitivityS = 10% of Smaxλ400 … 1100nmBestrahlungsempfindliche FlächeRadiant sensitive areaA 1.54mm2Abmessung der bestrahlungsempfindlichen Fläche Dimensions of radiant sensitive area L×BL×W0.7 × 2.2mm²Halbwinkel Half angle ϕ± 55Graddeg.Dunkelstrom, V R = 10 V Dark current IR10 (≤ 100)nASpektrale Fotoempfindlichkeit, λ = 850 nm Spectral sensitivity Sλ0.55A/W2007-04-0322007-04-033Maximale Abweichung der Fotoempfindlichkeit vom MittelwertMax. deviation of the system spectral sensitivity from the averageΔS± 5%Quantenausbeute, λ = 850 nm Quantum yieldη0.80Electrons Photon Leerlaufspannung, E v = 1000 Ix Open-circuit voltageV O 330 (≥ 280)mV Kurzschlu βstrom, E v = 1000 Ix Short-circuit current I SC 24μA Isolationsstrom, V IS = 100 V Insulation currentI IS 0.1 (≤ 1)nA Anstiegs- und Abfallzeit des Fotostromes Rise and fall time of the photocurrentR L = 1 k Ω; V R = 5 V; λ = 850 nm; I p = 25 μA t r , t f500nsDurchla βspannung, I F = 40 mA, E = 0 Forward voltageV F 1.0V Kapazität, V R = 0 V, f = 1 MHz, E = 0 CapacitanceC 025pF Temperaturkoeffizient für V O Temperature coefficient of V O TC V – 2.6mV/K Temperaturkoeffizient für I SC Temperature coefficient of I SCTC I 0.18%/K Rauschäquivalente Strahlungsleistung Noise equivalent power V R = 10 V, λ = 850 nmNEP1.0 × 10–13Nachweisgrenze, V R = 10 V, λ = 850 nm Detection limitD*1.2 × 1012Kennwerte (T A = 25 °C, Normlicht A, T = 2856 K) für jede EinzeldiodeCharacteristics (T A = 25 °C, standard light A, T = 2856 K) per single diode (cont’d)Bezeichnung ParameterSymbol Symbol Wert Value Einheit Unit W Hz -----------cm Hz ×W--------------------------2007-04-034OPTO SEMICONDUCTORSRelative Spectral SensitivityDark CurrentDirectional Characteristics S Photocurrent I P = f (Ev ), VR = 5 V CapacitanceTotal Power Dissipation Dark CurrentMaßzeichnungPackage OutlinesMaße in mm (inch) / Dimensions in mm (inch).2007-04-035LötbedingungenSoldering ConditionsWellenlöten (TTW)(nach CECC 00802)TTW Soldering(acc. to CECC 00802)OSRAM Opto Semiconductors GmbHWernerwerkstrasse 2, D-93049 Regensburg© All Rights Reserved.The information describes the type of component and shall not be considered as assured characteristics.Terms of delivery and rights to change design reserved. Due to technical requirements components may contain dangerous substances. For information on the types in question please contact our Sales Organization.PackingPlease use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components 1 , may only be used in life-support devices or systems 2 with the express written approval of OSRAM OS.1 A critical component is a component usedin a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.2007-04-036分销商库存信息: OSRAMSFH 221。
SFH213;SFH 213 FA;中文规格书,Datasheet资料
SFH 213 SFH 213 FA
80
OHF01034
60
40
20
0 400 600 800 1000 nm 1200
λ
Photocurrent IP = f (Ee), VR = 5 V Open-Circuit Voltage VO = f (Ee) SFH 213 FA
Directional Characteristics Srel = f (ϕ)
Typ Type SFH 213 SFH 213 FA
Bestellnummer Ordering Code Q62702P0930 Q62702P1671
2007-04-02
1
/
Grenzwerte Maximum Ratings
Bezeichnung Parameter
7.8 (0.307) 7.5 (0.295)
SFH 213, SFH 213 FA
5.9 (0.232) 5.5 (0.217)
2.54 (0.100) spacing 0.8 (0.031) 0.5 (0.020) ø5.1 (0.201) ø4.8 (0.189)
1.8 (0.071)
1.2 (0.047)
Temperaturkoeffizient von ISC Temperature coefficient of ISC
Normlicht/standard light A λ = 870 nm
ISL88731CHRTZ-T;ISL88731CHRTZ;ISL88731CEVAL2Z;中文规格书,Datasheet资料
SMBus Level 2 Battery ChargerISL88731CThe ISL88731C is a highly integrated Lithium-ion battery charger controller, programmable over the SMBus system management bus (SMBus). The ISL88731C is intended to be used in a smart battery charger (SBC) within a smart battery system (SBS) that throttles the charge power such that the current from the AC-adapter is automatically limited. Highefficiency is achieved with a DC/DC synchronous-rectifier buck converter, equipped with diode emulation for enhanced light load efficiency and system bus boosting prevention. The ISL88731C charges one to four Lithium-ion series cells, and delivers up to 8A charge current. Integrated MOSFET drivers and bootstrap diode result in fewer components and smaller implementation area. Low offset current-sense amplifiers provide high accuracy with 10m Ω sense resistors. The ISL88731C provides 0.5% end-of-charge battery voltage accuracy.The ISL88731C provides a digital output that indicates the presence of the AC adapter as well as an analog output which indicates the adapter current within 4% accuracy.The ISL88731C is available in a small 5mmx5mm 28Ld Thin (0.8mm) QFN package. An evaluation kit is available to reduce design time. The ISL88731C is available in Pb-Free packages.Related Literature•See AN1404 for “ISL88731EVAL2Z and ISL88731CEVAL2Z Evaluation Boards Setup Procedure”Features•0.5% Battery Voltage Accuracy •3% Adapter Current Limit Accuracy •3% Charge Current Accuracy •SMBus 2-Wire Serial Interface •Battery Short Circuit Protection •Fast Response for Pulse-Charging •Fast System-Load Transient Response •Monitor Outputs-Adapter Current (3% Accuracy)-AC-Adapter Detection •11-Bit Battery Voltage Setting•6 Bit Charge Current/Adapter Current Setting •8A Maximum Battery Charger Current •11A Maximum Adapter Current •+8V to +26V Adapter Voltage Range •Pb-Free (RoHS Compliant)Applications•Notebook Computers •Tablet PCs•Portable Equipment with Rechargeable BatteriesFIGURE 1.TYPICAL CHARGING VOLTAGE AND CURRENTFIGURE 2.EFFICIENCY vs CHARGE CURRENT AND BATTERYVOLTAGECHARGE TIME (MINUTES)10.010.511.011.512.012.513.0020406080100120140160B A T T E R Y V O L T A G E0.00.51.01.52.02.53.03.5BATTERY CURRENTVCHG (V)ICHG (A)808590951000.01.02.03.04.05.06.07.08.0I OUT (A)E F F I C I E N C Y (%)8.4V BATTERY12.6V BATTERY 16.8V BATTERY 4.2V BATTERYFIGURE 3.FUNCTIONAL BLOCK DIAGRAMPHASEBOOT UGATE LGATEPGNDISL88731CCSSN CSSP CSOP CSON ACIN SCL VREFDCINSDA VDDSMBICM ICOMP VCOMP VCCACOK VDDP GNDAC ADAPTERTO BATTERYTO SYSTEMH O S TVFB RS1RS2AGNDPGNDAGNDFIGURE 4.TYPICAL APPLICATION CIRCUITPin ConfigurationISL88731C (28 LD TQFN)TOP VIEWC S S PC S S N V C CB O O TU G A T E P H A S E D C I N I C MS D AS C LV D D S M BG N DA C O KN CNC ACIN VREF ICOMPNC VCOMPNCVDDP LGATE PGND CSOP CSON NC VFB12345672120191817161528272625242322891011121314PDFunctional Pin DescriptionsPIN NUMBERSYMBOL DESCRIPTION2ACIN AC Adapter Detection Input. Connect to a resistor divider from the AC adapter output. Range zero to 5.5V.3VREF Reference Voltage output. Range 3.168V to 3.232V. It is internally compensated. Do not connect a decoupling capacitor.4ICOMP Compensation Point for the charging current and adapter current regulation Loop. Connect 0.01µF to GND. See “Voltage Control Loop” on page 21 for details on selecting the ICOMP capacitor. Range zero to 5.5V.6VCOMP Compensation Point for the voltage regulation loop. Connect 4.7k Ω in series with 0.01µF to GND. See “Voltage Control Loop” on page 21 for details on selecting VCOMP components. Range zero to 5.5V.8ICM Input Current Monitor Output. ICM voltage equals 20 x (V CSSP - V CSSN ). Range zero to 3V.9SDA SMBus Data I/O. Open-drain Output. Connect an external pull-up resistor according to SMBus specifications. Range zero to 5.5V.10SCL SMBus Clock Input. Connect an external pull-up resistor according to SMBus specifications. Range zero to 5.5V.11VDDSMB SMBus interface Supply Voltage Input. Bypass with a 0.1µF capacitor to GND. Range 3.3V to 5.5V.12GND Analog Ground. Connect directly to the backside paddle. Connect to the backside paddle and PGND at one point close to (under) the IC.13ACOK AC Detect Output. This open drain output is high impedance when ACIN is greater than 3.2V. The ACOK output remains low when the ISL88731C is powered down. Connect a 10k pull-up resistor from ACOK to VDDSMB. Range 3.3V to 5.5V.15VFB Feedback for the Battery Voltage. Range 1V to 19V.17CSON Charge Current-Sense Negative Input. Range 1V to 19V.18CSOP Charge Current-Sense Positive Input. Range 1V to 19V.19PGND Power Ground. Connect PGND to the source of the low side MOSFET and the negative side of capacitors to the charger output and the drain of the upper switching FET. Connect this area to the Backside paddle at one location very near (under) the IC.20LGATELow-Side Power MOSFET Driver Output. Connect to low-side N channel MOSFET. LGATE drives between VDDP and PGND. Range is -0.3V to 5.23V.21VDDPLinear Regulator Output. VDDP is the output of the 5.2V linear regulator supplied from DCIN. VDDP also directlysupplies the LGATE driver and the BOOT strap diode. Bypass with a 1µF ceramic capacitor from VDDP to PGND. Range is 5.0V to 5.23V.22DCIN Charger Bias Supply Input. Bypass DCIN with a 0.1µF capacitor to GND. Range 8V to +26V.23PHASE High-Side Power MOSFET Driver Source Connection. Connect to the source of the high-side N-Channel MOSFET. Range -2V to +26V.24UGATE High-Side Power MOSFET Driver Output. Connect to the high-side N-channel MOSFET gate. Range -2V to +33V.25BOOT High-Side Power MOSFET Driver Power-Supply Connection. Connect a 0.1µF capacitor from BOOT-to-PHASE. Range -2V to +33V.26VCC Power input for internal analog circuits. Connect a 4.7Ω resistor from VCC to VDDP and a 1µF ceramic capacitor from VCC to ground. Range 4V to 5.23V.27CSSN Input Current-Sense Negative Input. Range 8V to 26V.28CSSP Input Current-Sense Positive Input. Range 8V to 26V.PDConnect the backside paddle to GND. This pad has the lowest thermal resistance to the die. It should be connected to a large area of ground with 3 to 5 vias for good thermal performance. The recommended potential of the thermal pad is zero (0) Volts.1, 5, 7, 14, 16NCNo Connect. Pins are not connected internally.Ordering InformationPART NUMBER (Notes 1, 2, 3)PART MARKINGTEMP RANGE(°C)PACKAGE (Pb-Free)PKG.DWG. #ISL88731CHRTZ 88731C HRTZ -10 to +10028 Ld 5x5 TQFNL28.5x5BISL88731CEVAL2Z Evaluation BoardNOTES:1.Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.2.These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.3.For Moisture Sensitivity Level (MSL), please see device information page for ISL88731C . For more information on MSL please see tech brief TB363.Functional Pin Descriptions (Continued)PIN NUMBERSYMBOL DESCRIPTIONTable of ContentsAbsolute Maximum Ratings (6)Thermal Information (6)Electrical Specifications (6)SMBus Timing Specifications (8)Typical Operating Performance (9)Theory of Operation (11)Introduction (11)PWM Control (11)AC-Adapter Detection (11)Current Measurement (11)VDDP Regulator (11)VDDSMB Supply (11)Short Circuit Protection and 0V Battery Charging (11)Undervoltage Detect and Battery Trickle Charging (11)Over-Temperature Protection (12)Overvoltage Protection (12)The System Management Bus (12)General SMBus Architecture (12)Data Validity (12)START and STOP Conditions (12)Acknowledge (13)SMBus Transactions (13)Byte Format (13)ISL88731C and SMBus (13)Battery Charger Registers (14)Enabling and Disabling Charging (14)Setting Charge Voltage (14)Setting Charge Current (15)Setting Input-Current Limit (16)Charger Timeout (17)ISL88731C Data Byte Order..................................................17Writing to the Internal Registers.. (17)Reading from the Internal Registers (17)Application Information (17)Inductor Selection (17)Output Capacitor Selection (18)MOSFET Selection (18)Snubber Design (19)Input Capacitor Selection (19)Loop Compensation Design (19)Transconductance Amplifiers GMV, GMI and GMS (19)PWM Gain Fm (19)Charge Current Control Loop (20)Adapter Current Limit Control Loop (20)Voltage Control Loop (21)Output LC Filter Transfer Functions (21)Compensation Break Frequency Equations (22)PCB Layout Considerations (22)Power and Signal Layers Placement on the PCB (22)Component Placement (22)Signal Ground and Power Ground Connection (22)GND and VCC Pin (22)LGATE Pin (22)PGND Pin (22)PHASE Pin (23)UGATE Pin (23)BOOT Pin (23)CSOP, CSON, CSSP and CSSN Pins (23)DCIN Pin (23)Copper Size for the Phase Node (23)Identify the Power and Signal Ground (23)Clamping Capacitor for Switching MOSFET (23)Revision History (24)Products (24)Package Outline Drawing (25)Absolute Maximum Ratings Thermal InformationDCIN, CSSP, CSSN, CSOP, CSON, VFB . . . . . . . . . . . . . . . . . . .-0.3V to +28V CSSP-CSSN, CSOP-CSON, PGND-GND . . . . . . . . . . . . . . . . . . -0.3V to +0.3V PHASE to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to +30V BOOT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +33V BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V UGATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PHASE - 0.3V to BOOT + 0.3V LGATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PGND - 0.3V to VDDP + 0.3V ICOMP, VCOMP, VREF, to GND. . . . . . . . . . . . . . . . . . . . .-0.3V to VCC + 0.3V VDDSMB, SCL, SDA, ACIN, ACOK . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V VDDP, ICM, VCC to GND, VDDP to PGND . . . . . . . . . . . . . . . . . .-0.3V to +6V Thermal Resistance (Typical)θJA (°C/W)θJC (°C/W) 28 Ld TQFN Package (Notes 4, 5) . . . . . . . 38 6.5 Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below /pbfree/Pb-FreeReflow.aspCAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.NOTES:4.θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See TechBrief TB379.5.For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.Electrical Specifications DCIN = CSSP = CSSN = 18V, CSOP = CSON = 12V, VDDP = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, CVDDP=1µF, IVDDP = 0mA, T A = -10°C to +100°C. Boldface limits apply over the operating temperature range, -10°C to +100°C.PARAMETER CONDITIONSMIN(Note 7)TYPMAX(Note 7)UNITSCHARGE VOLTAGE REGULATIONBattery Full Charge Voltage and Accuracy ChargeVoltage = 0x41A016.71616.816.884V-0.50.5%ChargeVoltage = 0x313012.52912.59212.655V-0.50.5%ChargeVoltage = 0x20D08.3508.48.450V-0.60.6%ChargeVoltage = 0x1060 4.163 4.192 4.221V-0.70.7% Battery Undervoltage Lockout Trip Point forTrickle ChargeVFB rising 2.55 2.7 2.85VBattery Undervoltage Lockout Trip PointHysteresis100250400mV CHARGE CURRENT REGULATIONCSOP to CSON Full-ScaleCurrent-Sense Voltage78.2280.6483.06mVCharge Current and Accuracy RS2 = 10mΩ (see Figure4)ChargingCurrent = 0x1f80 7.8228.0648.306A -33%RS2 = 10mΩ (see Figure4) ChargingCurrent = 0x0f803.809 3.968 4.126A -44%RS2 = 10mΩ (see Figure4)ChargingCurrent = 0x008064128220mA Charge Current Gain Error Based on charge current = 128mA and 8.064A-1.6 1.4% CSOP/CSON Input Voltage Range019VBattery Quiescent CurrentAdapter present, not charging,I CSOP + I CSON + I PHASE + I CSSP + I CSSN + I FB V PHASE = V CSON = V CSOP = V DCIN = 19V, V ACIN = 5V135200µAAdapter AbsentI CSOP + I CSON + I PHASE + I CSSP + I CSSN + I FB V PHASE = V CSON = V CSOP = 19V, V DCIN = 0V-10.22µAAdapter Quiescent CurrentI DCIN + I CSSP + I CSSNVadapter = 8V to 26V, Vbattery 4V to 16.8V35mAINPUT CURRENT REGULATIONCSSP to CSSN Full-Scale Current-Sense VoltageCSSP = 19V106.7110113.3mV Input Current AccuracyRS1 = 10m Ω (see Figure 4)Adapter Current = 11004mA or 3584mA -33%RS1 = 10m Ω (see Figure 4)Adapter Current = 2048mA-55%Input Current Limit Gain Error Based on InputCurrent = 1024mA and 11004mA-1.5 1.5%Input Current Limit Offset -11mV CSSP/CSSN Input Voltage Range 826V ICM Gain V CSSP-CSSN = 110mV 20V/V ICM AccuracyV CSSP-CSSN = 110mV -2.5 2.5%V CSSP-CSSN = 55mV or 35mV -44%V CSSP-CSSN = 20mV-88%ICM Max Output CurrentV CSSP-CSSN = 0.1V500µASUPPLY AND LINEAR REGULATORDCIN, Input Voltage Range 826V VDDP Output Voltage 8.0V < V DCIN < 28V, no load 5.05.1 5.23V VDDP Load Regulation 0 < I VDDP < 30mA35100mV VDDSMB Range 2.7 5.5V VDDSMB UVLO Rising 2.4 2.5 2.6V VDDSMB UVLO Hysteresis 40100150mV VDDSMB Quiescent CurrentVDDP = SCL = SDA = 5.5V 2027µAV REFERENCEVREF Output Voltage0 < I VREF < 300µA3.1683.23.232VACOKACOK Sink Current V ACOK = 0.4V, ACIN = 1.5V 28mA ACOK Leakage CurrentV ACOK = 5.5V, ACIN = 3.7V1µAACINACIN rising Threshold 3.15 3.2 3.25V ACIN Threshold Hysteresis 406090mV ACIN Input Bias Current-11µAPARAMETERCONDITIONSMIN (Note 7)TYP MAX (Note 7)UNITSSWITCHING REGULATORFrequency330400440kHz BOOT Supply Current UGATE High170290400µA PHASE Input Bias Current V DCON = 28V, V CSON = V PHASE = 20V 02µA UGATE On-Resistance Low I UGATE = -100mA 0.9 1.6ΩUGATE On-Resistance High I UGATE = 10mA 1.4 2.5ΩLGATE On-Resistance High I LGATE = +10mA 1.4 2.5ΩLGATE On-Resistance Low I LGATE = -100mA0.9 1.6ΩDead TimeFalling UGATE to rising LGATE or falling LGATE to rising UGATE355080nsERROR AMPLIFIERSGMV Amplifier Transconductance 200250300µA/V GMI Amplifier Transconductance 405060µA/V GMS Amplifier Transconductance 405060µA/V GMI/GMS Saturation Current 152125µA GMV Saturation Current 101730µA ICOMP, VCOMP Clamp Voltage0.25V < V ICOMP, VCOMP < 3.5V200300400mVLOGIC LEVELSSDA/SCL Input Low Voltage VDDSMB = 2.7V to 5.5V 0.8V SDA/SCL Input High Voltage VDDSMB = 2.7V to 5.5V 2V SDA/SCL Input Bias Current VDDSMB = 2.7V to 5.5V -11µA SDA, Output Sink CurrentV SDA = 0.4V715mAPARAMETERCONDITIONSMIN (Note 7)TYPMAX (Note 7)UNITSSMBus Timing SpecificationsVDDSMB = 2.7V to 5.5V.PARAMETERSYMBOL CONDITIONSMIN TYPMAX UNITS SMBus Frequency FSMB 10100kHz Bus Free Timet BUF 4.7µs Start Condition Hold Time from SCL t HD:STA 4µs Start Condition Setup Time from SCL t SU:STA 4.7µs Stop Condition Setup Time from SCL t SU:STO 4µs SDA Hold Time from SCL t HD:DAT 300ns SDA Setup Time from SCL t SU:DAT 250ns SCL Low Timeout (Note 6)t TIMEOUT 222530ms SCL Low Period t LOW 4.7µs SCL High Periodt HIGH4µs Maximum Charging Period without an SMBus Write to ChargeVoltage or ChargeCurrent Register 140180220sNOTES:6.If SCL is low for longer than the specified time, the charger is disabled.7.Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested.Typical Operating PerformanceDCIN = 20V, 3S2P Li-Battery, T A = +25°C, unless otherwise noted.FIGURE 5.VDD LOAD REGULATION FIGURE 6.VREF LOAD REGULATIONFIGURE 7.ICM ACCURACY vs AC-ADAPTER CURRENT FIGURE 8.TYPICAL CHARGING VOLTAGE AND CURRENTFIGURE 9.CHARGE ENABLE FIGURE 10.CHARGE DISABLE4.854.904.955.005.055.105.15020406080100VDDP LOAD CURRENT (mA)V D D P (V )3.173.183.193.203.213.223.23050100150200I VREF (µA)V R E F (V )-1.0%-0.5%0.0%0.5%1.0%-15-10-5051015123567AC-ADAPTER CURRENT (A)I C M A C C U R A C Y (%)4810.010.511.011.512.012.513.0020406080100120140160TIME (MINUTES)B A T T E R Y V O L T A G E0.00.51.01.52.02.53.03.5BATTERY CURRENTVCHG (V)ICHG (A)VCOMP ICOMPINDUCTOR CURRENTCHARGE CURRENTVCOMPICOMP INDUCTOR CURRENTCHARGE CURRENTFIGURE 11.SWITCHING WAVEFORMS AT DIODE EMULATION FIGURE 12.SWITCHING WAVEFORMS IN CC MODEFIGURE 13.BATTERY REMOVAL FIGURE 14.BATTERY INSERTIONFIGURE 15.LOAD TRANSIENT RESPONSEFIGURE 16.EFFICIENCY vs CHARGE CURRENT AND BATTERYVOLTAGETypical Operating PerformanceDCIN = 20V, 3S2P Li-Battery, T A = +25°C, unless otherwise noted. (Continued)UGATELGATEINDUCTOR CURRENTPHASEUGATELGATEINDUCTOR CURRENTPHASECSON/V BATTERYBATTERY CURRENTBATTERY CURRENTCSON/V BATTERYSYSTEM LOAD BATTERY VOLTAGE CHARGE CURRENTADAPTER CURRENT808590951000.01.02.03.04.05.06.07.08.0I OUT (A)E F F I C I E N C Y (%)8.4V BATTERY12.6V BATTERY 16.8V BATTERY 4.2V BATTERY分销商库存信息:INTERSILISL88731CHRTZ-T ISL88731CHRTZ ISL88731CEVAL2Z。
CDCLVC1103PWR;CDCLVC1104PWR;CDCLVC1106PWR;CDCLVC1108PWR;CDCLVC1110PWR;中文规格书,Datasheet资料
1GGNDCLKIN Y1Y2VDDVDDY3Y4VDDGNDY0Y11Y5GNDY6Y7Y9VDD Y8GNDGND Y10VDDY0Y1Y2Y3YnCLKIN1G•••CDCLVC11xx SCAS895–MAY20103.3V and2.5V LVCMOS High-Performance Clock Buffer FamilyCheck for Samples:CDCLVC11xxFEATURES•Operating Temperature Range:–40°C to85°C •High-Performance1:2,1:3,1:4,1:6,1:8,1:10,•Available in8-,14-,16-,20-,24-Pin TSSOP 1:12LVCMOS Clock Buffer Family Package(all pin compatible)•Very Low Pin-to-Pin Skew<50psAPPLICATIONS•Very Low Additive Jitter<100fs•General Purpose Communication,Industrial •Supply Voltage:3.3V or2.5V and Consumer Applications•f max=250MHz for3.3Vf max=180MHz for2.5VDESCRIPTIONThe CDCLVC11xx is a modular,high-performance,low-skew,general purpose clock buffer family from Texas Instruments.The whole family is designed with a modular approach in mind.It is intended to round up TI's series of LVCMOS clock generators.There are7different fan-out variations,1:2to1:12,available.All of the devices are pin compatible to each other for easy handling.All family members share the same high performing characteristics like low additive jitter,low skew,and wide operating temperature range.The CDCLVC11xx supports an asynchronous output enable control(1G)which switches the outputs into a low state when1G is low.Also,versions with synchronized enable control for glitch free switching and three-state outputs are planned in future device options.The CDCLVC11xx operate in a2.5V and3.3V environment and are characterized for operation from–40°C to 85°C.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Copyright©2010,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.1G GND CLKIN Y 1Y 2VDD VDD Y 3Y 4VDDGND Y 0Y 5GND1G GND CLKIN Y 1Y 2VDD VDD Y 3Y 4VDD GND Y 0Y 5GND Y 6Y71G GND CLKIN Y1Y2VDD VDD Y3Y 4VDD GND Y 0Y5GND Y 6Y7Y 9VDD Y8GNDY 1NCVDD NC YY 1Y 2VDD Y 3Y Y 1Y 2VDDNC Y1G GND CLKIN Y1Y2VDD VDD Y3Y 4VDD GND Y 0Y11Y5GND Y 6Y7Y 9VDD Y8GND GND Y10VDDCDCLVC11xxSCAS895–MAY 2010These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.PACKAGE OPTIONSPIN FUNCTIONSLVCMOS CLOCK OUTPUTSUPPLY LVCMOS CLOCK OUTPUTGROUND CLOCK INPUTENABLEVOLTAGEDEVICES CLKIN 1G Y0,Y1,…Y11V DD GND CDCLVC1102123,864CDCLVC1103123,8,564CDCLVC1104123,8,5,764CDCLVC1106123,14,11,13,6,95,8,124,7,10CDCLVC1108123,16,13,15,6,11,8,95,10,144,7,12CDCLVC1110123,20,17,19,6,15,8,13,105,9,14,184,7,11,16CDCLVC1112123,24,21,23,6,19,8,17,16,10,14,125,9,13,18,224,7,11,15,20OUTPUT LOGIC TABLEINPUTSOUTPUTSCLKIN 1G Yn X L L L H L HHH2Submit Documentation FeedbackCopyright ©2010,Texas Instruments IncorporatedProduct Folder Link(s):CDCLVC11xxCDCLVC11xx SCAS895–MAY2010ABSOLUTE MAXIMUM RATINGS(1)over operating free-air temperature range(unless otherwise noted)VALUE/UNITV DD Supply voltage range–0.5V to4.6VV IN Input voltage range(2)–0.5V to V DD+0.5VV O Output voltage range(2)–0.5V to V DD+0.5VI IN Input current±20mAI O Continuous output current±50mAT J Maximum junction temperature125°CT ST Storage temperature range–65°C to150°C(1)Stresses beyond those listed under"absolute maximum ratings"may cause permanent damage to the device.These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under"recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)This value is limited to4.6V maximum.THERMAL INFORMATIONDCDLVC1102/03/04CDCLVC1106CDCLVC1108CDCLVC11010CDCLVC1112 THERMAL METRIC(1)PW PW PW PW PW UNITS8PINS14PINS16PINS20PINS24PINSq JA Junction-to-ambient thermal resistance(2)149.4112.6108.483.087.9°C/W q JC(top)Junction-to-case(top)thermal resistance(3)69.448.033.632.326.5(1)For more information about traditional and new thermal metrics,see the IC Package Thermal Metrics application report,SPRA953.(2)The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard,high-K board,asspecified in JESD51-7,in an environment described in JESD51-2a.(3)The junction-to-case(top)thermal resistance is obtained by simulating a cold plate test on the package top.No specificJEDEC-standard test exists,but a close description can be found in the ANSI SEMI standard G30-88.RECOMMENDED OPERATING CONDITIONSover operating free-air temperature range(unless otherwise noted)MIN NOM MAX UNIT3.3V supply 3.0 3.3 3.6V DD Supply voltage range V2.5V supply 2.3 2.5 2.7V DD=3.0V to3.6V V DD/2–600V IL Low-level input voltage mVV DD=2.3V to2.7V V DD/2–400V DD=3.0V to3.6V V DD/2+600V IH High-level input voltage mVV DD=2.3V to2.7V V DD/2+400V th Input threshold voltage V DD=2.3V to3.6V V DD/2mVt r/t f Input slew rate14V/nsV DD=3.0V to3.6V 1.8Minimum pulse width att w ns CLKIN V=2.3V to2.7V 2.75DDV DD=3.0V to3.6V DC250 LVCMOS clock Inputf CLK MHzFrequency V=2.3V to2.7V DC180DDT A Operating free-air temperature–4085°CCopyright©2010,Texas Instruments Incorporated Submit Documentation Feedback3Product Folder Link(s):CDCLVC11xxCDCLVC11xxSCAS895–DEVICE CHARACTERISTICSover recommended operating free-air temperature range(unless otherwise noted)PARAMETER CONDITION MIN TYP(1)MAX UNIT OVERALL PARAMETERS FOR ALL VERSIONS1G=V DD;CLKIN=0V or V DD;I O=0mA;V DD=3.6V610mAI DD Static device current(2)1G=V DD;CLKIN=0V or V DD;I O=0mA;V DD=2.7V36mAI PD Power down current1G=0V;CLKIN=0V or V DD;I O=0mA;V DD=3.6V or2.7V60µAV DD=3.3V;f=10MHz6pF Power dissipation capacitanceC PDper output(3)V=2.5V;f=10MHz 4.5pFDDInput leakage current at1G±8I I V I=0V or V DD,V DD=3.6V or2.7VµAInput leakage current at CLKIN±25V DD=3.3V45ΩR OUT Output impedanceV DD=2.5V60ΩV DD=3.0V to3.6V DC250MHz f OUT Output frequencyV DD=2.3V to2.7V DC180MHz OUTPUT PARAMETERS FOR V DD=3.3V±0.3VV DD=3V,I OH=–0.1mA 2.9V OH High-level output voltage V DD=3V,I OH=–8mA 2.5VV DD=3V,I OH=–12mA 2.2V DD=3V,I OL=0.1mA0.1V OL Low-level output voltage V DD=3V,I OL=8mA0.5VV DD=3V,I OL=12mA0.8t PLH,Propagation delay CLKIN to Yn0.8 2.0nst PHLt sk(o)Output skew Equal load of each output50pst r/t f Rise and fall time20%–80%(V OH-V OL)0.30.8nst DIS Output disable time1G to Yn6nst EN Output enable time1G to Yn6nsPulse skew;t sk(p)To be measured with input duty cycle of50%180ps t PLH(Yn)–t PHL(Yn)(4)t sk(pp)Part-to-part skew Under equal operating conditions for two parts0.5nst jitter Additive jitter rms12kHz…20MHz,f OUT=250MHz100fs(1)All typical values are at respective nominal V DD.For switching characteristics,outputs are terminated to50Ωto V DD/2(see Figure1).(2)For dynamic I DD over frequency see Figure8and Figure9.(3)This is the formula for the power dissipation calculation(see Figure8and the Power Consideration section).P tot=P stat+P dyn+P Cload[W]P stat=V DD×I DD[W]P dyn=C PD×V DD2׃[W]P Cload=C load×V DD2׃×n[W]n=Number of switching output pins(4)t sk(p)depends on output rise-and fall-time(t r/t f).The output duty-cycle can be calculated:odc=(t w(OUT)±t sk(p))/t period;t w(OUT)ispulse-width of output waveform and tperiod is1/f OUT.4Submit Documentation Feedback Copyright©2010,Texas Instruments IncorporatedProduct Folder Link(s):CDCLVC11xxCDCLVC11xx SCAS895–MAY2010DEVICE CHARACTERISTICS(continued)over recommended operating free-air temperature range(unless otherwise noted)PARAMETER CONDITION MIN TYP(1)MAX UNIT OUTPUT PARAMETERS FOR V DD=2.5V±0.2VV DD=2.3V,I OH=–0.1mA 2.2V OH High-level output voltage VV DD=2.3V,I OH=–8mA 1.7V DD=2.3V,I OL=0.1mA0.1V OL Low-level output voltage VV DD=2.3V,I OL=8mA0.5t PLH,Propagation delay CLKIN to Yn 1.0 2.6nst PHLt sk(o)Output skew Equal load of each output50pst r/t f Rise and fall time20%–80%reference point0.3 1.2nst DIS Output disable time1G to Yn10nst EN Output enable time1G to Yn10nsPulse skew;t sk(p)To be measured with input duty cycle of50%220ps t PLH(Yn)–t PHL(Yn)(5)t sk(pp)Part-to-part skew Under equal operating conditions for two parts 1.2nst jitter Additive jitter rms12kHz…20MHz,f OUT=180MHz350fs (5)t sk(p)depends on output rise-and fall-time(t r/t f).The output duty-cycle can be calculated:odc=(t w(OUT)±t sk(p))/t period;t w(OUT)ispulse-width of output waveform and tperiod is1/f OUT.Copyright©2010,Texas Instruments Incorporated Submit Documentation Feedback5Product Folder Link(s):CDCLVC11xxR=50Wfrom Measurement EquipmentV /2DDV = 3.3 V or 2.5 V1GYnY n+1Y nCDCLVC11xxSCAS895–MAY 2010PARAMETERS MEASUREMENT INFORMATIONFigure 1.Test Load CircuitFigure 2.Application Load With 50ΩLine TerminationFigure 3.Application Load With Series Line TerminationFigure 4.t DIS and t EN for Disable Low Figure 5.Output Skew t sk(o)6Submit Documentation FeedbackCopyright ©2010,Texas Instruments IncorporatedProduct Folder Link(s):CDCLVC11xxY nOL CLKINOLVY nCLKINNote:sk (p)PLH PHL CDCLVC11xxSCAS895–MAY 2010PARAMETERS MEASUREMENT INFORMATION (continued)Figure 6.Pulse Skew t sk(p)and Propagation DelayFigure 7.Rise/Fall Times t r /t ft PLH /t PHLTYPICAL CHARACTERISTICSPower ConsiderationThe following power consideration refers to the device-consumed power consumption only.The device power consumption is the sum of static power and dynamic power.The dynamic power usage consists of two components:1.Power used by the device as it switches states.2.Power required to charge any output load.The output load can be capacitive only or capacitive and resistive.The following formula and the power graphs in Figure 8and Figure 9can be used to obtain the power consumption of the device:P dev =P stat +n (P dyn +P Cload )P stat =V DD x I DDP dyn +P Cload =see Figure 8and Figure 9where:V DD =Supply voltage (3.3V or 2.5V)I DD =Static device current (typ 6mA for V DD =3.3V;typ 3mA for V DD =2.5V)n =Number of switching output pinsExample for Device Power Consumption for CDCLVC1104:4outputs are switching,f =120MHz,V DD =3.3V and C load =2pF per output:P dev =P stat +n (P dyn +P Cload )=19.8mW +40mW =59.8mW P stat =V DD x I DD =6mA x 3.3V =19.8mW n (P dyn +P Cload )=4x 10mW =40mWNOTEFor dimensioning the power supply,the total power consumption needs to be considered.The total power consumption is the sum of the device power consumption and the power consumption of the load.Copyright ©2010,Texas Instruments Incorporated Submit Documentation Feedback7Product Folder Link(s):CDCLVC11xx051015f - Clock Frequency - MHzD e v i c e P o w e r C o n s u m p t i o n - mWf - Clock Frequency - MHzD e v i c e P o w e r C o n s u m p t i o n - m W0123f - Clock Frequency - MHzI - D y n a m i c S u p p l y C u r r e n t - m Ad yn 012345f - Clock Frequency - MHzI - D y n a m i c S u p p l y C u r r e n t - m Ad y n CDCLVC11xxSCAS895–MAY 2010TYPICAL CHARACTERISTICS (continued)Figure 8.Device Power Consumption vs Clock FrequencyFigure 9.Device Power Consumption vs Clock Frequency(Load 50Ωinto V DD /2.2pF,8pF;Per Output)(Load 50Ωinto V DD /2.2pF,8pF;Per Output)Figure 10.Dynamic Supply Current vs Clock FrequencyFigure 11.Dynamic Supply Current vs Clock Frequency(C PD =6pF,No Load;Per Output)(C PD =4.5pF,No Load;Per Output)8Submit Documentation FeedbackCopyright ©2010,Texas Instruments IncorporatedProduct Folder Link(s):CDCLVC11xxPACKAG PACKAGING INFORMATIONOrderable Device Status (1)Package Type PackageDrawing Pins Package Qty Eco Plan (2)Lead/Ball FinishMSL PeaCDCLVC1102PW ACTIVE TSSOP PW8150Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1102PWR ACTIVE TSSOP PW82000Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1103PW ACTIVE TSSOP PW8150Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1103PWR ACTIVE TSSOP PW82000Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1104PW ACTIVE TSSOP PW8150Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1104PWR ACTIVE TSSOP PW82000Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1106PW ACTIVE TSSOP PW1490Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1106PWR ACTIVE TSSOP PW142000Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1108PW ACTIVE TSSOP PW1690Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1108PWR ACTIVE TSSOP PW162000Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1110PW ACTIVE TSSOP PW2070Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1110PWR ACTIVE TSSOP PW202000Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1112PW ACTIVE TSSOP PW2460Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1112PWR ACTIVE TSSOP PW242000Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.//PACKAG Array (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.tinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for alllead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable foPb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package,the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardin homogeneous material)(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TIprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate infcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical an TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for releasIn no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Cu分销商库存信息:TICDCLVC1103PWR CDCLVC1104PWR CDCLVC1106PWR CDCLVC1108PWR CDCLVC1110PWR CDCLVC1112PWR CDCLVC1104EVM CDCLVC1112EVM。
MC9S12_datasheet中文
目录 .................................................................................................................................................. I 第一章 PWM模块 ...........................................................................................................................1 第一节 PWM模块介绍 .........................................................................................................1 第二节 PWM寄存器简介 .......................................................................2 2.1 PWME寄存器 ........................................................................................................2 2.2 PWMPOL寄存器...................................................................................................2 2.3 PWMCLK寄存器 ..................................................................
CDCLVD1204RGTT;CDCLVD1204RGTR;CDCLVD1204EVM;中文规格书,Datasheet资料
Copyright © 2010, Texas Instruments Incorporated
/
CDCLVD1204
SCAS898A – MAY 2010 – REVISED JUNE 2010
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PIN DESCRIPTIONS
PIN
NAME
NO.
VCC
5
GND
1
INP0, INN0
6, 7
INP1, INN1
3, 4
VAC_REF
8
OUTP0, OUTN0 OUTP1, OUTN1 OUTP2, OUTN2 OUTP3, OUTN3
9, 10 11,12 13,14 15,16
IN_SEL
The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1204 is packaged in small 16-pin, 3-mm × 3-mm QFN package.
Compatible • Clock Frequency up to 800 MHz • 2.375 V–2.625 V Device Power Supply • LVDS Reference Voltage, VAC_REF, Available for
DC22.1111.111;DC22.2111.111;DC22.6111.111;DC22.4111.111;DC22.1121.111;中文规格书,Datasheet资料
- - - - differential mode _____ common mode
4A
6A
10 A
Medical version (M5)
1A
2A
4A
6A
10 A
Connectors
/
DC22
/pg06
Variants
Rated Current [A]
Terminal
Panel Thickness s
Material: Housing
1 - 10 A @ Ta 40 °C / 250 VAC; 50 Hz 1 - 10 A @ Ta 40 °C / 125 VAC; 60 Hz standard < 0.5 mA (250 V / 60 Hz) medical < 5 µA (250 V / 60 Hz) > 1.7 kVDC between L-N > 2.7 kVDC between L/N-PE Test voltage (2 sec) -25 °C to 85 °C 25/085/21 acc. to IEC 60068-1 from front side IP 40 acc. to IEC 60529 Suitable for appliances with protection class 1 acc. to IEC 61140 For PCB mounting ; Ground terminal: Quick connect terminals 6.3 x 0.8 mm angled to pin axis Screw: max 4 mm Mounting screw torque max 0.5 Nm Thermoplastic, black, UL 94V-0
LD1117中文资料
LD1117
符号
测试条件
Vin=3.8V,Iout=10mA, Tj=25℃（图 1） Vin=3.1V∼12V, Iout=1mA∼1A,（图 1） Vin=3.8V,Tj=25℃ （图 1） Vin=3.8V,Iout =1mA， ΔT=0℃∼125℃，图 1 VKA =VREF, ΔVin=3.3V∼8V，图 1 ΔIout =1mA∼800mA, Vin=3.3V，图 1 图1 Vin>8V，图 1 Iout=0.1A,图 1 Iout=0.5A,图 1 Iout=1A,图 1 1% 6%
Vin=3.2V,Iout=10mA, Tj=25℃（图 1） Vin=2.5V∼12V, Iout=1mA∼1A,（图 1） Vin=3.2V,Tj=25℃ （图 1） Vin=3.2V,Iout =1mA， ΔT=0℃∼125℃，图 1 VKA =VREF, ΔVin=2.7V∼8V，图 1 ΔIout =1mA∼800mA, Vin=2.7V，图 1 图1 Vin>8V，图 1 Iout=0.1A,图 1 Iout=0.5A,图 1 Iout=1A,图 1 1% 7.5%
赛 普 微 电 子 有 限 公 司
Super Microelectronics
低压差线性稳压器
基本特性： � 此稳压源输入最高电压 16V。 � 提供固定电压输出 1.2V、1.5V、1.8V、2.5V、3.3V、5V 和可调电压输出。 � 输出电压精度可控制在 1%范围内。 � 较宽输出电流范围 1mA ~ 1A 。 SOT-223 PKG � 非常好线性调整率和负载调整率。 � 低开启电压。 � 提供封装 SOT-223，TO-252。 应用范围：
1000
mA mV/℃
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1GGNDCLKIN Y1Y2VDDVDDY3Y4VDDGNDY0Y11Y5GNDY6Y7Y9VDD Y8GNDGND Y10VDDY0Y1Y2Y3YnCLKIN1G•••CDCLVC11xx SCAS895–MAY20103.3V and2.5V LVCMOS High-Performance Clock Buffer FamilyCheck for Samples:CDCLVC11xxFEATURES•Operating Temperature Range:–40°C to85°C •High-Performance1:2,1:3,1:4,1:6,1:8,1:10,•Available in8-,14-,16-,20-,24-Pin TSSOP 1:12LVCMOS Clock Buffer Family Package(all pin compatible)•Very Low Pin-to-Pin Skew<50psAPPLICATIONS•Very Low Additive Jitter<100fs•General Purpose Communication,Industrial •Supply Voltage:3.3V or2.5V and Consumer Applications•f max=250MHz for3.3Vf max=180MHz for2.5VDESCRIPTIONThe CDCLVC11xx is a modular,high-performance,low-skew,general purpose clock buffer family from Texas Instruments.The whole family is designed with a modular approach in mind.It is intended to round up TI's series of LVCMOS clock generators.There are7different fan-out variations,1:2to1:12,available.All of the devices are pin compatible to each other for easy handling.All family members share the same high performing characteristics like low additive jitter,low skew,and wide operating temperature range.The CDCLVC11xx supports an asynchronous output enable control(1G)which switches the outputs into a low state when1G is low.Also,versions with synchronized enable control for glitch free switching and three-state outputs are planned in future device options.The CDCLVC11xx operate in a2.5V and3.3V environment and are characterized for operation from–40°C to 85°C.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Copyright©2010,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.1G GND CLKIN Y 1Y 2VDD VDD Y 3Y 4VDDGND Y 0Y 5GND1G GND CLKIN Y 1Y 2VDD VDD Y 3Y 4VDD GND Y 0Y 5GND Y 6Y71G GND CLKIN Y1Y2VDD VDD Y3Y 4VDD GND Y 0Y5GND Y 6Y7Y 9VDD Y8GNDY 1NCVDD NC YY 1Y 2VDD Y 3Y Y 1Y 2VDDNC Y1G GND CLKIN Y1Y2VDD VDD Y3Y 4VDD GND Y 0Y11Y5GND Y 6Y7Y 9VDD Y8GND GND Y10VDDCDCLVC11xxSCAS895–MAY 2010These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.PACKAGE OPTIONSPIN FUNCTIONSLVCMOS CLOCK OUTPUTSUPPLY LVCMOS CLOCK OUTPUTGROUND CLOCK INPUTENABLEVOLTAGEDEVICES CLKIN 1G Y0,Y1,…Y11V DD GND CDCLVC1102123,864CDCLVC1103123,8,564CDCLVC1104123,8,5,764CDCLVC1106123,14,11,13,6,95,8,124,7,10CDCLVC1108123,16,13,15,6,11,8,95,10,144,7,12CDCLVC1110123,20,17,19,6,15,8,13,105,9,14,184,7,11,16CDCLVC1112123,24,21,23,6,19,8,17,16,10,14,125,9,13,18,224,7,11,15,20OUTPUT LOGIC TABLEINPUTSOUTPUTSCLKIN 1G Yn X L L L H L HHH2Submit Documentation FeedbackCopyright ©2010,Texas Instruments IncorporatedProduct Folder Link(s):CDCLVC11xxCDCLVC11xx SCAS895–MAY2010ABSOLUTE MAXIMUM RATINGS(1)over operating free-air temperature range(unless otherwise noted)VALUE/UNITV DD Supply voltage range–0.5V to4.6VV IN Input voltage range(2)–0.5V to V DD+0.5VV O Output voltage range(2)–0.5V to V DD+0.5VI IN Input current±20mAI O Continuous output current±50mAT J Maximum junction temperature125°CT ST Storage temperature range–65°C to150°C(1)Stresses beyond those listed under"absolute maximum ratings"may cause permanent damage to the device.These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under"recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)This value is limited to4.6V maximum.THERMAL INFORMATIONDCDLVC1102/03/04CDCLVC1106CDCLVC1108CDCLVC11010CDCLVC1112 THERMAL METRIC(1)PW PW PW PW PW UNITS8PINS14PINS16PINS20PINS24PINSq JA Junction-to-ambient thermal resistance(2)149.4112.6108.483.087.9°C/W q JC(top)Junction-to-case(top)thermal resistance(3)69.448.033.632.326.5(1)For more information about traditional and new thermal metrics,see the IC Package Thermal Metrics application report,SPRA953.(2)The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard,high-K board,asspecified in JESD51-7,in an environment described in JESD51-2a.(3)The junction-to-case(top)thermal resistance is obtained by simulating a cold plate test on the package top.No specificJEDEC-standard test exists,but a close description can be found in the ANSI SEMI standard G30-88.RECOMMENDED OPERATING CONDITIONSover operating free-air temperature range(unless otherwise noted)MIN NOM MAX UNIT3.3V supply 3.0 3.3 3.6V DD Supply voltage range V2.5V supply 2.3 2.5 2.7V DD=3.0V to3.6V V DD/2–600V IL Low-level input voltage mVV DD=2.3V to2.7V V DD/2–400V DD=3.0V to3.6V V DD/2+600V IH High-level input voltage mVV DD=2.3V to2.7V V DD/2+400V th Input threshold voltage V DD=2.3V to3.6V V DD/2mVt r/t f Input slew rate14V/nsV DD=3.0V to3.6V 1.8Minimum pulse width att w ns CLKIN V=2.3V to2.7V 2.75DDV DD=3.0V to3.6V DC250 LVCMOS clock Inputf CLK MHzFrequency V=2.3V to2.7V DC180DDT A Operating free-air temperature–4085°CCopyright©2010,Texas Instruments Incorporated Submit Documentation Feedback3Product Folder Link(s):CDCLVC11xxCDCLVC11xxSCAS895–DEVICE CHARACTERISTICSover recommended operating free-air temperature range(unless otherwise noted)PARAMETER CONDITION MIN TYP(1)MAX UNIT OVERALL PARAMETERS FOR ALL VERSIONS1G=V DD;CLKIN=0V or V DD;I O=0mA;V DD=3.6V610mAI DD Static device current(2)1G=V DD;CLKIN=0V or V DD;I O=0mA;V DD=2.7V36mAI PD Power down current1G=0V;CLKIN=0V or V DD;I O=0mA;V DD=3.6V or2.7V60µAV DD=3.3V;f=10MHz6pF Power dissipation capacitanceC PDper output(3)V=2.5V;f=10MHz 4.5pFDDInput leakage current at1G±8I I V I=0V or V DD,V DD=3.6V or2.7VµAInput leakage current at CLKIN±25V DD=3.3V45ΩR OUT Output impedanceV DD=2.5V60ΩV DD=3.0V to3.6V DC250MHz f OUT Output frequencyV DD=2.3V to2.7V DC180MHz OUTPUT PARAMETERS FOR V DD=3.3V±0.3VV DD=3V,I OH=–0.1mA 2.9V OH High-level output voltage V DD=3V,I OH=–8mA 2.5VV DD=3V,I OH=–12mA 2.2V DD=3V,I OL=0.1mA0.1V OL Low-level output voltage V DD=3V,I OL=8mA0.5VV DD=3V,I OL=12mA0.8t PLH,Propagation delay CLKIN to Yn0.8 2.0nst PHLt sk(o)Output skew Equal load of each output50pst r/t f Rise and fall time20%–80%(V OH-V OL)0.30.8nst DIS Output disable time1G to Yn6nst EN Output enable time1G to Yn6nsPulse skew;t sk(p)To be measured with input duty cycle of50%180ps t PLH(Yn)–t PHL(Yn)(4)t sk(pp)Part-to-part skew Under equal operating conditions for two parts0.5nst jitter Additive jitter rms12kHz…20MHz,f OUT=250MHz100fs(1)All typical values are at respective nominal V DD.For switching characteristics,outputs are terminated to50Ωto V DD/2(see Figure1).(2)For dynamic I DD over frequency see Figure8and Figure9.(3)This is the formula for the power dissipation calculation(see Figure8and the Power Consideration section).P tot=P stat+P dyn+P Cload[W]P stat=V DD×I DD[W]P dyn=C PD×V DD2׃[W]P Cload=C load×V DD2׃×n[W]n=Number of switching output pins(4)t sk(p)depends on output rise-and fall-time(t r/t f).The output duty-cycle can be calculated:odc=(t w(OUT)±t sk(p))/t period;t w(OUT)ispulse-width of output waveform and tperiod is1/f OUT.4Submit Documentation Feedback Copyright©2010,Texas Instruments IncorporatedProduct Folder Link(s):CDCLVC11xxCDCLVC11xx SCAS895–MAY2010DEVICE CHARACTERISTICS(continued)over recommended operating free-air temperature range(unless otherwise noted)PARAMETER CONDITION MIN TYP(1)MAX UNIT OUTPUT PARAMETERS FOR V DD=2.5V±0.2VV DD=2.3V,I OH=–0.1mA 2.2V OH High-level output voltage VV DD=2.3V,I OH=–8mA 1.7V DD=2.3V,I OL=0.1mA0.1V OL Low-level output voltage VV DD=2.3V,I OL=8mA0.5t PLH,Propagation delay CLKIN to Yn 1.0 2.6nst PHLt sk(o)Output skew Equal load of each output50pst r/t f Rise and fall time20%–80%reference point0.3 1.2nst DIS Output disable time1G to Yn10nst EN Output enable time1G to Yn10nsPulse skew;t sk(p)To be measured with input duty cycle of50%220ps t PLH(Yn)–t PHL(Yn)(5)t sk(pp)Part-to-part skew Under equal operating conditions for two parts 1.2nst jitter Additive jitter rms12kHz…20MHz,f OUT=180MHz350fs (5)t sk(p)depends on output rise-and fall-time(t r/t f).The output duty-cycle can be calculated:odc=(t w(OUT)±t sk(p))/t period;t w(OUT)ispulse-width of output waveform and tperiod is1/f OUT.Copyright©2010,Texas Instruments Incorporated Submit Documentation Feedback5Product Folder Link(s):CDCLVC11xxR=50Wfrom Measurement EquipmentV /2DDV = 3.3 V or 2.5 V1GYnY n+1Y nCDCLVC11xxSCAS895–MAY 2010PARAMETERS MEASUREMENT INFORMATIONFigure 1.Test Load CircuitFigure 2.Application Load With 50ΩLine TerminationFigure 3.Application Load With Series Line TerminationFigure 4.t DIS and t EN for Disable Low Figure 5.Output Skew t sk(o)6Submit Documentation FeedbackCopyright ©2010,Texas Instruments IncorporatedProduct Folder Link(s):CDCLVC11xxY nOL CLKINOLVY nCLKINNote:sk (p)PLH PHL CDCLVC11xxSCAS895–MAY 2010PARAMETERS MEASUREMENT INFORMATION (continued)Figure 6.Pulse Skew t sk(p)and Propagation DelayFigure 7.Rise/Fall Times t r /t ft PLH /t PHLTYPICAL CHARACTERISTICSPower ConsiderationThe following power consideration refers to the device-consumed power consumption only.The device power consumption is the sum of static power and dynamic power.The dynamic power usage consists of two components:1.Power used by the device as it switches states.2.Power required to charge any output load.The output load can be capacitive only or capacitive and resistive.The following formula and the power graphs in Figure 8and Figure 9can be used to obtain the power consumption of the device:P dev =P stat +n (P dyn +P Cload )P stat =V DD x I DDP dyn +P Cload =see Figure 8and Figure 9where:V DD =Supply voltage (3.3V or 2.5V)I DD =Static device current (typ 6mA for V DD =3.3V;typ 3mA for V DD =2.5V)n =Number of switching output pinsExample for Device Power Consumption for CDCLVC1104:4outputs are switching,f =120MHz,V DD =3.3V and C load =2pF per output:P dev =P stat +n (P dyn +P Cload )=19.8mW +40mW =59.8mW P stat =V DD x I DD =6mA x 3.3V =19.8mW n (P dyn +P Cload )=4x 10mW =40mWNOTEFor dimensioning the power supply,the total power consumption needs to be considered.The total power consumption is the sum of the device power consumption and the power consumption of the load.Copyright ©2010,Texas Instruments Incorporated Submit Documentation Feedback7Product Folder Link(s):CDCLVC11xx051015f - Clock Frequency - MHzD e v i c e P o w e r C o n s u m p t i o n - mWf - Clock Frequency - MHzD e v i c e P o w e r C o n s u m p t i o n - m W0123f - Clock Frequency - MHzI - D y n a m i c S u p p l y C u r r e n t - m Ad yn 012345f - Clock Frequency - MHzI - D y n a m i c S u p p l y C u r r e n t - m Ad y n CDCLVC11xxSCAS895–MAY 2010TYPICAL CHARACTERISTICS (continued)Figure 8.Device Power Consumption vs Clock FrequencyFigure 9.Device Power Consumption vs Clock Frequency(Load 50Ωinto V DD /2.2pF,8pF;Per Output)(Load 50Ωinto V DD /2.2pF,8pF;Per Output)Figure 10.Dynamic Supply Current vs Clock FrequencyFigure 11.Dynamic Supply Current vs Clock Frequency(C PD =6pF,No Load;Per Output)(C PD =4.5pF,No Load;Per Output)8Submit Documentation FeedbackCopyright ©2010,Texas Instruments IncorporatedProduct Folder Link(s):CDCLVC11xxPACKAG PACKAGING INFORMATIONOrderable Device Status (1)Package Type PackageDrawing Pins Package Qty Eco Plan (2)Lead/Ball FinishMSL PeaCDCLVC1102PW ACTIVE TSSOP PW8150Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1102PWR ACTIVE TSSOP PW82000Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1103PW ACTIVE TSSOP PW8150Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1103PWR ACTIVE TSSOP PW82000Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1104PW ACTIVE TSSOP PW8150Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1104PWR ACTIVE TSSOP PW82000Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1106PW ACTIVE TSSOP PW1490Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1106PWR ACTIVE TSSOP PW142000Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1108PW ACTIVE TSSOP PW1690Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1108PWR ACTIVE TSSOP PW162000Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1110PW ACTIVE TSSOP PW2070Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1110PWR ACTIVE TSSOP PW202000Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1112PW ACTIVE TSSOP PW2460Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260CCDCLVC1112PWR ACTIVE TSSOP PW242000Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.//PACKAG Array (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.tinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for alllead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable foPb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package,the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardin homogeneous material)(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TIprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate infcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical an TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for releasIn no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Cu分销商库存信息: TICDCLVC1112PW。